1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2021 Marvell International Ltd.
5 */
6
7#ifndef _QED_HSI_H
8#define _QED_HSI_H
9
10#include <linux/types.h>
11#include <linux/io.h>
12#include <linux/bitops.h>
13#include <linux/delay.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/slab.h>
17#include <linux/qed/common_hsi.h>
18#include <linux/qed/storage_common.h>
19#include <linux/qed/tcp_common.h>
20#include <linux/qed/fcoe_common.h>
21#include <linux/qed/eth_common.h>
22#include <linux/qed/iscsi_common.h>
23#include <linux/qed/nvmetcp_common.h>
24#include <linux/qed/iwarp_common.h>
25#include <linux/qed/rdma_common.h>
26#include <linux/qed/roce_common.h>
27#include <linux/qed/qed_fcoe_if.h>
28
29struct qed_hwfn;
30struct qed_ptt;
31
32/* Opcodes for the event ring */
33enum common_event_opcode {
34 COMMON_EVENT_PF_START,
35 COMMON_EVENT_PF_STOP,
36 COMMON_EVENT_VF_START,
37 COMMON_EVENT_VF_STOP,
38 COMMON_EVENT_VF_PF_CHANNEL,
39 COMMON_EVENT_VF_FLR,
40 COMMON_EVENT_PF_UPDATE,
41 COMMON_EVENT_FW_ERROR,
42 COMMON_EVENT_RL_UPDATE,
43 COMMON_EVENT_EMPTY,
44 MAX_COMMON_EVENT_OPCODE
45};
46
47/* Common Ramrod Command IDs */
48enum common_ramrod_cmd_id {
49 COMMON_RAMROD_UNUSED,
50 COMMON_RAMROD_PF_START,
51 COMMON_RAMROD_PF_STOP,
52 COMMON_RAMROD_VF_START,
53 COMMON_RAMROD_VF_STOP,
54 COMMON_RAMROD_PF_UPDATE,
55 COMMON_RAMROD_RL_UPDATE,
56 COMMON_RAMROD_EMPTY,
57 MAX_COMMON_RAMROD_CMD_ID
58};
59
60/* How ll2 should deal with packet upon errors */
61enum core_error_handle {
62 LL2_DROP_PACKET,
63 LL2_DO_NOTHING,
64 LL2_ASSERT,
65 MAX_CORE_ERROR_HANDLE
66};
67
68/* Opcodes for the event ring */
69enum core_event_opcode {
70 CORE_EVENT_TX_QUEUE_START,
71 CORE_EVENT_TX_QUEUE_STOP,
72 CORE_EVENT_RX_QUEUE_START,
73 CORE_EVENT_RX_QUEUE_STOP,
74 CORE_EVENT_RX_QUEUE_FLUSH,
75 CORE_EVENT_TX_QUEUE_UPDATE,
76 CORE_EVENT_QUEUE_STATS_QUERY,
77 MAX_CORE_EVENT_OPCODE
78};
79
80/* The L4 pseudo checksum mode for Core */
81enum core_l4_pseudo_checksum_mode {
82 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
83 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
84 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
85};
86
87/* LL2 SP error code */
88enum core_ll2_error_code {
89 LL2_OK = 0,
90 LL2_ERROR,
91 MAX_CORE_LL2_ERROR_CODE
92};
93
94/* Light-L2 RX Producers in Tstorm RAM */
95struct core_ll2_port_stats {
96 struct regpair gsi_invalid_hdr;
97 struct regpair gsi_invalid_pkt_length;
98 struct regpair gsi_unsupported_pkt_typ;
99 struct regpair gsi_crcchksm_error;
100};
101
102/* LL2 TX Per Queue Stats */
103struct core_ll2_pstorm_per_queue_stat {
104 struct regpair sent_ucast_bytes;
105 struct regpair sent_mcast_bytes;
106 struct regpair sent_bcast_bytes;
107 struct regpair sent_ucast_pkts;
108 struct regpair sent_mcast_pkts;
109 struct regpair sent_bcast_pkts;
110 struct regpair error_drop_pkts;
111};
112
113/* Light-L2 RX Producers in Tstorm RAM */
114struct core_ll2_rx_prod {
115 __le16 bd_prod;
116 __le16 cqe_prod;
117};
118
119struct core_ll2_tstorm_per_queue_stat {
120 struct regpair packet_too_big_discard;
121 struct regpair no_buff_discard;
122};
123
124struct core_ll2_ustorm_per_queue_stat {
125 struct regpair rcv_ucast_bytes;
126 struct regpair rcv_mcast_bytes;
127 struct regpair rcv_bcast_bytes;
128 struct regpair rcv_ucast_pkts;
129 struct regpair rcv_mcast_pkts;
130 struct regpair rcv_bcast_pkts;
131};
132
133struct core_ll2_rx_per_queue_stat {
134 struct core_ll2_tstorm_per_queue_stat tstorm_stat;
135 struct core_ll2_ustorm_per_queue_stat ustorm_stat;
136};
137
138struct core_ll2_tx_per_queue_stat {
139 struct core_ll2_pstorm_per_queue_stat pstorm_stat;
140};
141
142/* Structure for doorbell data, in PWM mode, for RX producers update. */
143struct core_pwm_prod_update_data {
144 __le16 icid; /* internal CID */
145 u8 reserved0;
146 u8 params;
147#define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
148#define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
149#define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */
150#define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2
151 struct core_ll2_rx_prod prod; /* Producers */
152};
153
154/* Ramrod data for rx/tx queue statistics query ramrod */
155struct core_queue_stats_query_ramrod_data {
156 u8 rx_stat;
157 u8 tx_stat;
158 __le16 reserved[3];
159 struct regpair rx_stat_addr;
160 struct regpair tx_stat_addr;
161};
162
163/* Core Ramrod Command IDs (light L2) */
164enum core_ramrod_cmd_id {
165 CORE_RAMROD_UNUSED,
166 CORE_RAMROD_RX_QUEUE_START,
167 CORE_RAMROD_TX_QUEUE_START,
168 CORE_RAMROD_RX_QUEUE_STOP,
169 CORE_RAMROD_TX_QUEUE_STOP,
170 CORE_RAMROD_RX_QUEUE_FLUSH,
171 CORE_RAMROD_TX_QUEUE_UPDATE,
172 CORE_RAMROD_QUEUE_STATS_QUERY,
173 MAX_CORE_RAMROD_CMD_ID
174};
175
176/* Core RX CQE Type for Light L2 */
177enum core_roce_flavor_type {
178 CORE_ROCE,
179 CORE_RROCE,
180 MAX_CORE_ROCE_FLAVOR_TYPE
181};
182
183/* Specifies how ll2 should deal with packets errors: packet_too_big and
184 * no_buff.
185 */
186struct core_rx_action_on_error {
187 u8 error_type;
188#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
189#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
190#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
191#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
192#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
193#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
194};
195
196/* Core RX BD for Light L2 */
197struct core_rx_bd {
198 struct regpair addr;
199 __le16 reserved[4];
200};
201
202/* Core RX CM offload BD for Light L2 */
203struct core_rx_bd_with_buff_len {
204 struct regpair addr;
205 __le16 buff_length;
206 __le16 reserved[3];
207};
208
209/* Core RX CM offload BD for Light L2 */
210union core_rx_bd_union {
211 struct core_rx_bd rx_bd;
212 struct core_rx_bd_with_buff_len rx_bd_with_len;
213};
214
215/* Opaque Data for Light L2 RX CQE */
216struct core_rx_cqe_opaque_data {
217 __le32 data[2];
218};
219
220/* Core RX CQE Type for Light L2 */
221enum core_rx_cqe_type {
222 CORE_RX_CQE_ILLEGAL_TYPE,
223 CORE_RX_CQE_TYPE_REGULAR,
224 CORE_RX_CQE_TYPE_GSI_OFFLOAD,
225 CORE_RX_CQE_TYPE_SLOW_PATH,
226 MAX_CORE_RX_CQE_TYPE
227};
228
229/* Core RX CQE for Light L2 */
230struct core_rx_fast_path_cqe {
231 u8 type;
232 u8 placement_offset;
233 struct parsing_and_err_flags parse_flags;
234 __le16 packet_length;
235 __le16 vlan;
236 struct core_rx_cqe_opaque_data opaque_data;
237 struct parsing_err_flags err_flags;
238 u8 packet_source;
239 u8 reserved0;
240 __le32 reserved1[3];
241};
242
243/* Core Rx CM offload CQE */
244struct core_rx_gsi_offload_cqe {
245 u8 type;
246 u8 data_length_error;
247 struct parsing_and_err_flags parse_flags;
248 __le16 data_length;
249 __le16 vlan;
250 __le32 src_mac_addrhi;
251 __le16 src_mac_addrlo;
252 __le16 qp_id;
253 __le32 src_qp;
254 struct core_rx_cqe_opaque_data opaque_data;
255 u8 packet_source;
256 u8 reserved[3];
257};
258
259/* Core RX CQE for Light L2 */
260struct core_rx_slow_path_cqe {
261 u8 type;
262 u8 ramrod_cmd_id;
263 __le16 echo;
264 struct core_rx_cqe_opaque_data opaque_data;
265 __le32 reserved1[5];
266};
267
268/* Core RX CM offload BD for Light L2 */
269union core_rx_cqe_union {
270 struct core_rx_fast_path_cqe rx_cqe_fp;
271 struct core_rx_gsi_offload_cqe rx_cqe_gsi;
272 struct core_rx_slow_path_cqe rx_cqe_sp;
273};
274
275/* RX packet source. */
276enum core_rx_pkt_source {
277 CORE_RX_PKT_SOURCE_NETWORK = 0,
278 CORE_RX_PKT_SOURCE_LB,
279 CORE_RX_PKT_SOURCE_TX,
280 CORE_RX_PKT_SOURCE_LL2_TX,
281 MAX_CORE_RX_PKT_SOURCE
282};
283
284/* Ramrod data for rx queue start ramrod */
285struct core_rx_start_ramrod_data {
286 struct regpair bd_base;
287 struct regpair cqe_pbl_addr;
288 __le16 mtu;
289 __le16 sb_id;
290 u8 sb_index;
291 u8 complete_cqe_flg;
292 u8 complete_event_flg;
293 u8 drop_ttl0_flg;
294 __le16 num_of_pbl_pages;
295 u8 inner_vlan_stripping_en;
296 u8 report_outer_vlan;
297 u8 queue_id;
298 u8 main_func_queue;
299 u8 mf_si_bcast_accept_all;
300 u8 mf_si_mcast_accept_all;
301 struct core_rx_action_on_error action_on_error;
302 u8 gsi_offload_flag;
303 u8 vport_id_valid;
304 u8 vport_id;
305 u8 zero_prod_flg;
306 u8 wipe_inner_vlan_pri_en;
307 u8 reserved[2];
308};
309
310/* Ramrod data for rx queue stop ramrod */
311struct core_rx_stop_ramrod_data {
312 u8 complete_cqe_flg;
313 u8 complete_event_flg;
314 u8 queue_id;
315 u8 reserved1;
316 __le16 reserved2[2];
317};
318
319/* Flags for Core TX BD */
320struct core_tx_bd_data {
321 __le16 as_bitfield;
322#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
323#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
324#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
325#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
326#define CORE_TX_BD_DATA_START_BD_MASK 0x1
327#define CORE_TX_BD_DATA_START_BD_SHIFT 2
328#define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
329#define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
330#define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
331#define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
332#define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
333#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
334#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
335#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
336#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
337#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
338#define CORE_TX_BD_DATA_NBDS_MASK 0xF
339#define CORE_TX_BD_DATA_NBDS_SHIFT 8
340#define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
341#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
342#define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
343#define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
344#define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
345#define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14
346#define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
347#define CORE_TX_BD_DATA_RESERVED0_SHIFT 15
348};
349
350/* Core TX BD for Light L2 */
351struct core_tx_bd {
352 struct regpair addr;
353 __le16 nbytes;
354 __le16 nw_vlan_or_lb_echo;
355 struct core_tx_bd_data bd_data;
356 __le16 bitfield1;
357#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
358#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
359#define CORE_TX_BD_TX_DST_MASK 0x3
360#define CORE_TX_BD_TX_DST_SHIFT 14
361};
362
363/* Light L2 TX Destination */
364enum core_tx_dest {
365 CORE_TX_DEST_NW,
366 CORE_TX_DEST_LB,
367 CORE_TX_DEST_RESERVED,
368 CORE_TX_DEST_DROP,
369 MAX_CORE_TX_DEST
370};
371
372/* Ramrod data for tx queue start ramrod */
373struct core_tx_start_ramrod_data {
374 struct regpair pbl_base_addr;
375 __le16 mtu;
376 __le16 sb_id;
377 u8 sb_index;
378 u8 stats_en;
379 u8 stats_id;
380 u8 conn_type;
381 __le16 pbl_size;
382 __le16 qm_pq_id;
383 u8 gsi_offload_flag;
384 u8 ctx_stats_en;
385 u8 vport_id_valid;
386 u8 vport_id;
387 u8 enforce_security_flag;
388 u8 reserved[7];
389};
390
391/* Ramrod data for tx queue stop ramrod */
392struct core_tx_stop_ramrod_data {
393 __le32 reserved0[2];
394};
395
396/* Ramrod data for tx queue update ramrod */
397struct core_tx_update_ramrod_data {
398 u8 update_qm_pq_id_flg;
399 u8 reserved0;
400 __le16 qm_pq_id;
401 __le32 reserved1[1];
402};
403
404/* Enum flag for what type of dcb data to update */
405enum dcb_dscp_update_mode {
406 DONT_UPDATE_DCB_DSCP,
407 UPDATE_DCB,
408 UPDATE_DSCP,
409 UPDATE_DCB_DSCP,
410 MAX_DCB_DSCP_UPDATE_MODE
411};
412
413/* The core storm context for the Ystorm */
414struct ystorm_core_conn_st_ctx {
415 __le32 reserved[4];
416};
417
418/* The core storm context for the Pstorm */
419struct pstorm_core_conn_st_ctx {
420 __le32 reserved[20];
421};
422
423/* Core Slowpath Connection storm context of Xstorm */
424struct xstorm_core_conn_st_ctx {
425 struct regpair spq_base_addr;
426 __le32 reserved0[2];
427 __le16 spq_cons;
428 __le16 reserved1[111];
429};
430
431struct xstorm_core_conn_ag_ctx {
432 u8 reserved0;
433 u8 state;
434 u8 flags0;
435#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
436#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
437#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
438#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
439#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
440#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
441#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
442#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
443#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
444#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
445#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
446#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
447#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
448#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
449#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
450#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
451 u8 flags1;
452#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
453#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
454#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
455#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
456#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
457#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
458#define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
459#define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
460#define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
461#define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
462#define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
463#define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
464#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
465#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
466#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
467#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
468 u8 flags2;
469#define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
470#define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
471#define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
472#define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
473#define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
474#define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
475#define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
476#define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
477 u8 flags3;
478#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
479#define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
480#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
481#define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
482#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
483#define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
484#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
485#define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
486 u8 flags4;
487#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
488#define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
489#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
490#define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
491#define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
492#define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
493#define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
494#define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
495 u8 flags5;
496#define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
497#define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
498#define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
499#define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
500#define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
501#define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
502#define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
503#define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
504 u8 flags6;
505#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
506#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
507#define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
508#define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
509#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
510#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
511#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
512#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
513 u8 flags7;
514#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
515#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
516#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
517#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
518#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
519#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
520#define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
521#define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
522#define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
523#define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
524 u8 flags8;
525#define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
526#define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
527#define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
528#define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
529#define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
530#define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
531#define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
532#define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
533#define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
534#define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
535#define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
536#define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
537#define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
538#define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
539#define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
540#define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
541 u8 flags9;
542#define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
543#define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
544#define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
545#define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
546#define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
547#define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
548#define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
549#define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
550#define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
551#define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
552#define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
553#define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
554#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
555#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
556#define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
557#define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
558 u8 flags10;
559#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
560#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
561#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
562#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
563#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
564#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
565#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
566#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
567#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
568#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
569#define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
570#define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
571#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
572#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
573#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
574#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
575 u8 flags11;
576#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
577#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
578#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
579#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
580#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
581#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
582#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
583#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
584#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
585#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
586#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
587#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
588#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
589#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
590#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
591#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
592 u8 flags12;
593#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
594#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
595#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
596#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
597#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
598#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
599#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
600#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
601#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
602#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
603#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
604#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
605#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
606#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
607#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
608#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
609 u8 flags13;
610#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
611#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
612#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
613#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
614#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
615#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
616#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
617#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
618#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
619#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
620#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
621#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
622#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
623#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
624#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
625#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
626 u8 flags14;
627#define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
628#define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
629#define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
630#define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
631#define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
632#define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
633#define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
634#define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
635#define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
636#define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
637#define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
638#define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
639#define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
640#define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
641 u8 byte2;
642 __le16 physical_q0;
643 __le16 consolid_prod;
644 __le16 reserved16;
645 __le16 tx_bd_cons;
646 __le16 tx_bd_or_spq_prod;
647 __le16 updated_qm_pq_id;
648 __le16 conn_dpi;
649 u8 byte3;
650 u8 byte4;
651 u8 byte5;
652 u8 byte6;
653 __le32 reg0;
654 __le32 reg1;
655 __le32 reg2;
656 __le32 reg3;
657 __le32 reg4;
658 __le32 reg5;
659 __le32 reg6;
660 __le16 word7;
661 __le16 word8;
662 __le16 word9;
663 __le16 word10;
664 __le32 reg7;
665 __le32 reg8;
666 __le32 reg9;
667 u8 byte7;
668 u8 byte8;
669 u8 byte9;
670 u8 byte10;
671 u8 byte11;
672 u8 byte12;
673 u8 byte13;
674 u8 byte14;
675 u8 byte15;
676 u8 e5_reserved;
677 __le16 word11;
678 __le32 reg10;
679 __le32 reg11;
680 __le32 reg12;
681 __le32 reg13;
682 __le32 reg14;
683 __le32 reg15;
684 __le32 reg16;
685 __le32 reg17;
686 __le32 reg18;
687 __le32 reg19;
688 __le16 word12;
689 __le16 word13;
690 __le16 word14;
691 __le16 word15;
692};
693
694struct tstorm_core_conn_ag_ctx {
695 u8 byte0;
696 u8 byte1;
697 u8 flags0;
698#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
699#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
700#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
701#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
702#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
703#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
704#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
705#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
706#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
707#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
708#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
709#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
710#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
711#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
712 u8 flags1;
713#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
714#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
715#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
716#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
717#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
718#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
719#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
720#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
721 u8 flags2;
722#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
723#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
724#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
725#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
726#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
727#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
728#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
729#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
730 u8 flags3;
731#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
732#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
733#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
734#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
735#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
736#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
737#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
738#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
739#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
740#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
741#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
742#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
743 u8 flags4;
744#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
745#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
746#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
747#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
748#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
749#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
750#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
751#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
752#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
753#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
754#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
755#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
756#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
757#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
758#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
759#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
760 u8 flags5;
761#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
762#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
763#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
764#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
765#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
766#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
767#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
768#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
769#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
770#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
771#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
772#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
773#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
774#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
775#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
776#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
777 __le32 reg0;
778 __le32 reg1;
779 __le32 reg2;
780 __le32 reg3;
781 __le32 reg4;
782 __le32 reg5;
783 __le32 reg6;
784 __le32 reg7;
785 __le32 reg8;
786 u8 byte2;
787 u8 byte3;
788 __le16 word0;
789 u8 byte4;
790 u8 byte5;
791 __le16 word1;
792 __le16 word2;
793 __le16 word3;
794 __le32 ll2_rx_prod;
795 __le32 reg10;
796};
797
798struct ustorm_core_conn_ag_ctx {
799 u8 reserved;
800 u8 byte1;
801 u8 flags0;
802#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
803#define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
804#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
805#define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
806#define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
807#define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
808#define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
809#define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
810#define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
811#define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
812 u8 flags1;
813#define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
814#define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
815#define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
816#define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
817#define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
818#define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
819#define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
820#define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
821 u8 flags2;
822#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
823#define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
824#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
825#define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
826#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
827#define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
828#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
829#define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
830#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
831#define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
832#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
833#define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
834#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
835#define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
836#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
837#define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
838 u8 flags3;
839#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
840#define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
841#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
842#define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
843#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
844#define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
845#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
846#define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
847#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
848#define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
849#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
850#define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
851#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
852#define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
853#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
854#define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
855 u8 byte2;
856 u8 byte3;
857 __le16 word0;
858 __le16 word1;
859 __le32 rx_producers;
860 __le32 reg1;
861 __le32 reg2;
862 __le32 reg3;
863 __le16 word2;
864 __le16 word3;
865};
866
867/* The core storm context for the Mstorm */
868struct mstorm_core_conn_st_ctx {
869 __le32 reserved[40];
870};
871
872/* The core storm context for the Ustorm */
873struct ustorm_core_conn_st_ctx {
874 __le32 reserved[20];
875};
876
877/* The core storm context for the Tstorm */
878struct tstorm_core_conn_st_ctx {
879 __le32 reserved[4];
880};
881
882/* core connection context */
883struct core_conn_context {
884 struct ystorm_core_conn_st_ctx ystorm_st_context;
885 struct regpair ystorm_st_padding[2];
886 struct pstorm_core_conn_st_ctx pstorm_st_context;
887 struct regpair pstorm_st_padding[2];
888 struct xstorm_core_conn_st_ctx xstorm_st_context;
889 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
890 struct tstorm_core_conn_ag_ctx tstorm_ag_context;
891 struct ustorm_core_conn_ag_ctx ustorm_ag_context;
892 struct mstorm_core_conn_st_ctx mstorm_st_context;
893 struct ustorm_core_conn_st_ctx ustorm_st_context;
894 struct regpair ustorm_st_padding[2];
895 struct tstorm_core_conn_st_ctx tstorm_st_context;
896 struct regpair tstorm_st_padding[2];
897};
898
899struct eth_mstorm_per_pf_stat {
900 struct regpair gre_discard_pkts;
901 struct regpair vxlan_discard_pkts;
902 struct regpair geneve_discard_pkts;
903 struct regpair lb_discard_pkts;
904};
905
906struct eth_mstorm_per_queue_stat {
907 struct regpair ttl0_discard;
908 struct regpair packet_too_big_discard;
909 struct regpair no_buff_discard;
910 struct regpair not_active_discard;
911 struct regpair tpa_coalesced_pkts;
912 struct regpair tpa_coalesced_events;
913 struct regpair tpa_aborts_num;
914 struct regpair tpa_coalesced_bytes;
915};
916
917/* Ethernet TX Per PF */
918struct eth_pstorm_per_pf_stat {
919 struct regpair sent_lb_ucast_bytes;
920 struct regpair sent_lb_mcast_bytes;
921 struct regpair sent_lb_bcast_bytes;
922 struct regpair sent_lb_ucast_pkts;
923 struct regpair sent_lb_mcast_pkts;
924 struct regpair sent_lb_bcast_pkts;
925 struct regpair sent_gre_bytes;
926 struct regpair sent_vxlan_bytes;
927 struct regpair sent_geneve_bytes;
928 struct regpair sent_mpls_bytes;
929 struct regpair sent_gre_mpls_bytes;
930 struct regpair sent_udp_mpls_bytes;
931 struct regpair sent_gre_pkts;
932 struct regpair sent_vxlan_pkts;
933 struct regpair sent_geneve_pkts;
934 struct regpair sent_mpls_pkts;
935 struct regpair sent_gre_mpls_pkts;
936 struct regpair sent_udp_mpls_pkts;
937 struct regpair gre_drop_pkts;
938 struct regpair vxlan_drop_pkts;
939 struct regpair geneve_drop_pkts;
940 struct regpair mpls_drop_pkts;
941 struct regpair gre_mpls_drop_pkts;
942 struct regpair udp_mpls_drop_pkts;
943};
944
945/* Ethernet TX Per Queue Stats */
946struct eth_pstorm_per_queue_stat {
947 struct regpair sent_ucast_bytes;
948 struct regpair sent_mcast_bytes;
949 struct regpair sent_bcast_bytes;
950 struct regpair sent_ucast_pkts;
951 struct regpair sent_mcast_pkts;
952 struct regpair sent_bcast_pkts;
953 struct regpair error_drop_pkts;
954};
955
956/* ETH Rx producers data */
957struct eth_rx_rate_limit {
958 __le16 mult;
959 __le16 cnst;
960 u8 add_sub_cnst;
961 u8 reserved0;
962 __le16 reserved1;
963};
964
965/* Update RSS indirection table entry command */
966struct eth_tstorm_rss_update_data {
967 u8 vport_id;
968 u8 ind_table_index;
969 __le16 ind_table_value;
970 __le16 reserved1;
971 u8 reserved;
972 u8 valid;
973};
974
975struct eth_ustorm_per_pf_stat {
976 struct regpair rcv_lb_ucast_bytes;
977 struct regpair rcv_lb_mcast_bytes;
978 struct regpair rcv_lb_bcast_bytes;
979 struct regpair rcv_lb_ucast_pkts;
980 struct regpair rcv_lb_mcast_pkts;
981 struct regpair rcv_lb_bcast_pkts;
982 struct regpair rcv_gre_bytes;
983 struct regpair rcv_vxlan_bytes;
984 struct regpair rcv_geneve_bytes;
985 struct regpair rcv_gre_pkts;
986 struct regpair rcv_vxlan_pkts;
987 struct regpair rcv_geneve_pkts;
988};
989
990struct eth_ustorm_per_queue_stat {
991 struct regpair rcv_ucast_bytes;
992 struct regpair rcv_mcast_bytes;
993 struct regpair rcv_bcast_bytes;
994 struct regpair rcv_ucast_pkts;
995 struct regpair rcv_mcast_pkts;
996 struct regpair rcv_bcast_pkts;
997};
998
999/* Event Ring VF-PF Channel data */
1000struct vf_pf_channel_eqe_data {
1001 struct regpair msg_addr;
1002};
1003
1004/* Event Ring initial cleanup data */
1005struct initial_cleanup_eqe_data {
1006 u8 vf_id;
1007 u8 reserved[7];
1008};
1009
1010/* FW error data */
1011struct fw_err_data {
1012 u8 recovery_scope;
1013 u8 err_id;
1014 __le16 entity_id;
1015 u8 reserved[4];
1016};
1017
1018/* Event Data Union */
1019union event_ring_data {
1020 u8 bytes[8];
1021 struct vf_pf_channel_eqe_data vf_pf_channel;
1022 struct iscsi_eqe_data iscsi_info;
1023 struct iscsi_connect_done_results iscsi_conn_done_info;
1024 union rdma_eqe_data rdma_data;
1025 struct initial_cleanup_eqe_data vf_init_cleanup;
1026 struct fw_err_data err_data;
1027};
1028
1029/* Event Ring Entry */
1030struct event_ring_entry {
1031 u8 protocol_id;
1032 u8 opcode;
1033 u8 reserved0;
1034 u8 vf_id;
1035 __le16 echo;
1036 u8 fw_return_code;
1037 u8 flags;
1038#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
1039#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
1040#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
1041#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
1042 union event_ring_data data;
1043};
1044
1045/* Event Ring Next Page Address */
1046struct event_ring_next_addr {
1047 struct regpair addr;
1048 __le32 reserved[2];
1049};
1050
1051/* Event Ring Element */
1052union event_ring_element {
1053 struct event_ring_entry entry;
1054 struct event_ring_next_addr next_addr;
1055};
1056
1057/* Ports mode */
1058enum fw_flow_ctrl_mode {
1059 flow_ctrl_pause,
1060 flow_ctrl_pfc,
1061 MAX_FW_FLOW_CTRL_MODE
1062};
1063
1064/* GFT profile type */
1065enum gft_profile_type {
1066 GFT_PROFILE_TYPE_4_TUPLE,
1067 GFT_PROFILE_TYPE_L4_DST_PORT,
1068 GFT_PROFILE_TYPE_IP_DST_ADDR,
1069 GFT_PROFILE_TYPE_IP_SRC_ADDR,
1070 GFT_PROFILE_TYPE_TUNNEL_TYPE,
1071 MAX_GFT_PROFILE_TYPE
1072};
1073
1074/* Major and Minor hsi Versions */
1075struct hsi_fp_ver_struct {
1076 u8 minor_ver_arr[2];
1077 u8 major_ver_arr[2];
1078};
1079
1080/* Integration Phase */
1081enum integ_phase {
1082 INTEG_PHASE_BB_A0_LATEST = 3,
1083 INTEG_PHASE_BB_B0_NO_MCP = 10,
1084 INTEG_PHASE_BB_B0_WITH_MCP = 11,
1085 MAX_INTEG_PHASE
1086};
1087
1088/* Ports mode */
1089enum iwarp_ll2_tx_queues {
1090 IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1091 IWARP_LL2_ALIGNED_TX_QUEUE,
1092 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1093 IWARP_LL2_ERROR,
1094 MAX_IWARP_LL2_TX_QUEUES
1095};
1096
1097/* Function error ID */
1098enum func_err_id {
1099 FUNC_NO_ERROR,
1100 VF_PF_CHANNEL_NOT_READY,
1101 VF_ZONE_MSG_NOT_VALID,
1102 VF_ZONE_FUNC_NOT_ENABLED,
1103 ETH_PACKET_TOO_SMALL,
1104 ETH_ILLEGAL_VLAN_MODE,
1105 ETH_MTU_VIOLATION,
1106 ETH_ILLEGAL_INBAND_TAGS,
1107 ETH_VLAN_INSERT_AND_INBAND_VLAN,
1108 ETH_ILLEGAL_NBDS,
1109 ETH_FIRST_BD_WO_SOP,
1110 ETH_INSUFFICIENT_BDS,
1111 ETH_ILLEGAL_LSO_HDR_NBDS,
1112 ETH_ILLEGAL_LSO_MSS,
1113 ETH_ZERO_SIZE_BD,
1114 ETH_ILLEGAL_LSO_HDR_LEN,
1115 ETH_INSUFFICIENT_PAYLOAD,
1116 ETH_EDPM_OUT_OF_SYNC,
1117 ETH_TUNN_IPV6_EXT_NBD_ERR,
1118 ETH_CONTROL_PACKET_VIOLATION,
1119 ETH_ANTI_SPOOFING_ERR,
1120 ETH_PACKET_SIZE_TOO_LARGE,
1121 CORE_ILLEGAL_VLAN_MODE,
1122 CORE_ILLEGAL_NBDS,
1123 CORE_FIRST_BD_WO_SOP,
1124 CORE_INSUFFICIENT_BDS,
1125 CORE_PACKET_TOO_SMALL,
1126 CORE_ILLEGAL_INBAND_TAGS,
1127 CORE_VLAN_INSERT_AND_INBAND_VLAN,
1128 CORE_MTU_VIOLATION,
1129 CORE_CONTROL_PACKET_VIOLATION,
1130 CORE_ANTI_SPOOFING_ERR,
1131 CORE_PACKET_SIZE_TOO_LARGE,
1132 CORE_ILLEGAL_BD_FLAGS,
1133 CORE_GSI_PACKET_VIOLATION,
1134 MAX_FUNC_ERR_ID
1135};
1136
1137/* FW error handling mode */
1138enum fw_err_mode {
1139 FW_ERR_FATAL_ASSERT,
1140 FW_ERR_DRV_REPORT,
1141 MAX_FW_ERR_MODE
1142};
1143
1144/* FW error recovery scope */
1145enum fw_err_recovery_scope {
1146 ERR_SCOPE_INVALID,
1147 ERR_SCOPE_TX_Q,
1148 ERR_SCOPE_RX_Q,
1149 ERR_SCOPE_QP,
1150 ERR_SCOPE_VPORT,
1151 ERR_SCOPE_FUNC,
1152 ERR_SCOPE_PORT,
1153 ERR_SCOPE_ENGINE,
1154 MAX_FW_ERR_RECOVERY_SCOPE
1155};
1156
1157/* Mstorm non-triggering VF zone */
1158struct mstorm_non_trigger_vf_zone {
1159 struct eth_mstorm_per_queue_stat eth_queue_stat;
1160 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_RXQ_VF_QUAD];
1161};
1162
1163/* Mstorm VF zone */
1164struct mstorm_vf_zone {
1165 struct mstorm_non_trigger_vf_zone non_trigger;
1166};
1167
1168/* vlan header including TPID and TCI fields */
1169struct vlan_header {
1170 __le16 tpid;
1171 __le16 tci;
1172};
1173
1174/* outer tag configurations */
1175struct outer_tag_config_struct {
1176 u8 enable_stag_pri_change;
1177 u8 pri_map_valid;
1178 u8 reserved[2];
1179 struct vlan_header outer_tag;
1180 u8 inner_to_outer_pri_map[8];
1181};
1182
1183/* personality per PF */
1184enum personality_type {
1185 BAD_PERSONALITY_TYP,
1186 PERSONALITY_TCP_ULP,
1187 PERSONALITY_FCOE,
1188 PERSONALITY_RDMA_AND_ETH,
1189 PERSONALITY_RDMA,
1190 PERSONALITY_CORE,
1191 PERSONALITY_ETH,
1192 PERSONALITY_RESERVED,
1193 MAX_PERSONALITY_TYPE
1194};
1195
1196/* tunnel configuration */
1197struct pf_start_tunnel_config {
1198 u8 set_vxlan_udp_port_flg;
1199 u8 set_geneve_udp_port_flg;
1200 u8 set_no_inner_l2_vxlan_udp_port_flg;
1201 u8 tunnel_clss_vxlan;
1202 u8 tunnel_clss_l2geneve;
1203 u8 tunnel_clss_ipgeneve;
1204 u8 tunnel_clss_l2gre;
1205 u8 tunnel_clss_ipgre;
1206 __le16 vxlan_udp_port;
1207 __le16 geneve_udp_port;
1208 __le16 no_inner_l2_vxlan_udp_port;
1209 __le16 reserved[3];
1210};
1211
1212/* Ramrod data for PF start ramrod */
1213struct pf_start_ramrod_data {
1214 struct regpair event_ring_pbl_addr;
1215 struct regpair consolid_q_pbl_base_addr;
1216 struct pf_start_tunnel_config tunnel_config;
1217 __le16 event_ring_sb_id;
1218 u8 base_vf_id;
1219 u8 num_vfs;
1220 u8 event_ring_num_pages;
1221 u8 event_ring_sb_index;
1222 u8 path_id;
1223 u8 warning_as_error;
1224 u8 dont_log_ramrods;
1225 u8 personality;
1226 __le16 log_type_mask;
1227 u8 mf_mode;
1228 u8 integ_phase;
1229 u8 allow_npar_tx_switching;
1230 u8 reserved0;
1231 struct hsi_fp_ver_struct hsi_fp_ver;
1232 struct outer_tag_config_struct outer_tag_config;
1233 u8 pf_fp_err_mode;
1234 u8 consolid_q_num_pages;
1235 u8 reserved[6];
1236};
1237
1238/* Data for port update ramrod */
1239struct protocol_dcb_data {
1240 u8 dcb_enable_flag;
1241 u8 dscp_enable_flag;
1242 u8 dcb_priority;
1243 u8 dcb_tc;
1244 u8 dscp_val;
1245 u8 dcb_dont_add_vlan0;
1246};
1247
1248/* Update tunnel configuration */
1249struct pf_update_tunnel_config {
1250 u8 update_rx_pf_clss;
1251 u8 update_rx_def_ucast_clss;
1252 u8 update_rx_def_non_ucast_clss;
1253 u8 set_vxlan_udp_port_flg;
1254 u8 set_geneve_udp_port_flg;
1255 u8 set_no_inner_l2_vxlan_udp_port_flg;
1256 u8 tunnel_clss_vxlan;
1257 u8 tunnel_clss_l2geneve;
1258 u8 tunnel_clss_ipgeneve;
1259 u8 tunnel_clss_l2gre;
1260 u8 tunnel_clss_ipgre;
1261 u8 reserved;
1262 __le16 vxlan_udp_port;
1263 __le16 geneve_udp_port;
1264 __le16 no_inner_l2_vxlan_udp_port;
1265 __le16 reserved1[3];
1266};
1267
1268/* Data for port update ramrod */
1269struct pf_update_ramrod_data {
1270 u8 update_eth_dcb_data_mode;
1271 u8 update_fcoe_dcb_data_mode;
1272 u8 update_iscsi_dcb_data_mode;
1273 u8 update_roce_dcb_data_mode;
1274 u8 update_rroce_dcb_data_mode;
1275 u8 update_iwarp_dcb_data_mode;
1276 u8 update_mf_vlan_flag;
1277 u8 update_enable_stag_pri_change;
1278 struct protocol_dcb_data eth_dcb_data;
1279 struct protocol_dcb_data fcoe_dcb_data;
1280 struct protocol_dcb_data iscsi_dcb_data;
1281 struct protocol_dcb_data roce_dcb_data;
1282 struct protocol_dcb_data rroce_dcb_data;
1283 struct protocol_dcb_data iwarp_dcb_data;
1284 __le16 mf_vlan;
1285 u8 enable_stag_pri_change;
1286 u8 reserved;
1287 struct pf_update_tunnel_config tunnel_config;
1288};
1289
1290/* Ports mode */
1291enum ports_mode {
1292 ENGX2_PORTX1,
1293 ENGX2_PORTX2,
1294 ENGX1_PORTX1,
1295 ENGX1_PORTX2,
1296 ENGX1_PORTX4,
1297 MAX_PORTS_MODE
1298};
1299
1300/* Protocol-common error code */
1301enum protocol_common_error_code {
1302 COMMON_ERR_CODE_OK = 0,
1303 COMMON_ERR_CODE_ERROR,
1304 MAX_PROTOCOL_COMMON_ERROR_CODE
1305};
1306
1307/* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1308enum protocol_version_array_key {
1309 ETH_VER_KEY = 0,
1310 ROCE_VER_KEY,
1311 MAX_PROTOCOL_VERSION_ARRAY_KEY
1312};
1313
1314/* RDMA TX Stats */
1315struct rdma_sent_stats {
1316 struct regpair sent_bytes;
1317 struct regpair sent_pkts;
1318};
1319
1320/* Pstorm non-triggering VF zone */
1321struct pstorm_non_trigger_vf_zone {
1322 struct eth_pstorm_per_queue_stat eth_queue_stat;
1323 struct rdma_sent_stats rdma_stats;
1324};
1325
1326/* Pstorm VF zone */
1327struct pstorm_vf_zone {
1328 struct pstorm_non_trigger_vf_zone non_trigger;
1329 struct regpair reserved[7];
1330};
1331
1332/* Ramrod Header of SPQE */
1333struct ramrod_header {
1334 __le32 cid;
1335 u8 cmd_id;
1336 u8 protocol_id;
1337 __le16 echo;
1338};
1339
1340/* RDMA RX Stats */
1341struct rdma_rcv_stats {
1342 struct regpair rcv_bytes;
1343 struct regpair rcv_pkts;
1344};
1345
1346/* Data for update QCN/DCQCN RL ramrod */
1347struct rl_update_ramrod_data {
1348 u8 qcn_update_param_flg;
1349 u8 dcqcn_update_param_flg;
1350 u8 rl_init_flg;
1351 u8 rl_start_flg;
1352 u8 rl_stop_flg;
1353 u8 rl_id_first;
1354 u8 rl_id_last;
1355 u8 rl_dc_qcn_flg;
1356 u8 dcqcn_reset_alpha_on_idle;
1357 u8 rl_bc_stage_th;
1358 u8 rl_timer_stage_th;
1359 u8 reserved1;
1360 __le32 rl_bc_rate;
1361 __le16 rl_max_rate;
1362 __le16 rl_r_ai;
1363 __le16 rl_r_hai;
1364 __le16 dcqcn_g;
1365 __le32 dcqcn_k_us;
1366 __le32 dcqcn_timeuot_us;
1367 __le32 qcn_timeuot_us;
1368 __le32 reserved2;
1369};
1370
1371/* Slowpath Element (SPQE) */
1372struct slow_path_element {
1373 struct ramrod_header hdr;
1374 struct regpair data_ptr;
1375};
1376
1377/* Tstorm non-triggering VF zone */
1378struct tstorm_non_trigger_vf_zone {
1379 struct rdma_rcv_stats rdma_stats;
1380};
1381
1382struct tstorm_per_port_stat {
1383 struct regpair trunc_error_discard;
1384 struct regpair mac_error_discard;
1385 struct regpair mftag_filter_discard;
1386 struct regpair eth_mac_filter_discard;
1387 struct regpair ll2_mac_filter_discard;
1388 struct regpair ll2_conn_disabled_discard;
1389 struct regpair iscsi_irregular_pkt;
1390 struct regpair fcoe_irregular_pkt;
1391 struct regpair roce_irregular_pkt;
1392 struct regpair iwarp_irregular_pkt;
1393 struct regpair eth_irregular_pkt;
1394 struct regpair toe_irregular_pkt;
1395 struct regpair preroce_irregular_pkt;
1396 struct regpair eth_gre_tunn_filter_discard;
1397 struct regpair eth_vxlan_tunn_filter_discard;
1398 struct regpair eth_geneve_tunn_filter_discard;
1399 struct regpair eth_gft_drop_pkt;
1400};
1401
1402/* Tstorm VF zone */
1403struct tstorm_vf_zone {
1404 struct tstorm_non_trigger_vf_zone non_trigger;
1405};
1406
1407/* Tunnel classification scheme */
1408enum tunnel_clss {
1409 TUNNEL_CLSS_MAC_VLAN = 0,
1410 TUNNEL_CLSS_MAC_VNI,
1411 TUNNEL_CLSS_INNER_MAC_VLAN,
1412 TUNNEL_CLSS_INNER_MAC_VNI,
1413 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1414 MAX_TUNNEL_CLSS
1415};
1416
1417/* Ustorm non-triggering VF zone */
1418struct ustorm_non_trigger_vf_zone {
1419 struct eth_ustorm_per_queue_stat eth_queue_stat;
1420 struct regpair vf_pf_msg_addr;
1421};
1422
1423/* Ustorm triggering VF zone */
1424struct ustorm_trigger_vf_zone {
1425 u8 vf_pf_msg_valid;
1426 u8 reserved[7];
1427};
1428
1429/* Ustorm VF zone */
1430struct ustorm_vf_zone {
1431 struct ustorm_non_trigger_vf_zone non_trigger;
1432 struct ustorm_trigger_vf_zone trigger;
1433};
1434
1435/* VF-PF channel data */
1436struct vf_pf_channel_data {
1437 __le32 ready;
1438 u8 valid;
1439 u8 reserved0;
1440 __le16 reserved1;
1441};
1442
1443/* Ramrod data for VF start ramrod */
1444struct vf_start_ramrod_data {
1445 u8 vf_id;
1446 u8 enable_flr_ack;
1447 __le16 opaque_fid;
1448 u8 personality;
1449 u8 reserved[7];
1450 struct hsi_fp_ver_struct hsi_fp_ver;
1451
1452};
1453
1454/* Ramrod data for VF start ramrod */
1455struct vf_stop_ramrod_data {
1456 u8 vf_id;
1457 u8 reserved0;
1458 __le16 reserved1;
1459 __le32 reserved2;
1460};
1461
1462/* VF zone size mode */
1463enum vf_zone_size_mode {
1464 VF_ZONE_SIZE_MODE_DEFAULT,
1465 VF_ZONE_SIZE_MODE_DOUBLE,
1466 VF_ZONE_SIZE_MODE_QUAD,
1467 MAX_VF_ZONE_SIZE_MODE
1468};
1469
1470/* Xstorm non-triggering VF zone */
1471struct xstorm_non_trigger_vf_zone {
1472 struct regpair non_edpm_ack_pkts;
1473};
1474
1475/* Tstorm VF zone */
1476struct xstorm_vf_zone {
1477 struct xstorm_non_trigger_vf_zone non_trigger;
1478};
1479
1480/* Attentions status block */
1481struct atten_status_block {
1482 __le32 atten_bits;
1483 __le32 atten_ack;
1484 __le16 reserved0;
1485 __le16 sb_index;
1486 __le32 reserved1;
1487};
1488
1489/* DMAE command */
1490struct dmae_cmd {
1491 __le32 opcode;
1492#define DMAE_CMD_SRC_MASK 0x1
1493#define DMAE_CMD_SRC_SHIFT 0
1494#define DMAE_CMD_DST_MASK 0x3
1495#define DMAE_CMD_DST_SHIFT 1
1496#define DMAE_CMD_C_DST_MASK 0x1
1497#define DMAE_CMD_C_DST_SHIFT 3
1498#define DMAE_CMD_CRC_RESET_MASK 0x1
1499#define DMAE_CMD_CRC_RESET_SHIFT 4
1500#define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1501#define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1502#define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1503#define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1504#define DMAE_CMD_COMP_FUNC_MASK 0x1
1505#define DMAE_CMD_COMP_FUNC_SHIFT 7
1506#define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1507#define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1508#define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1509#define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1510#define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1511#define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1512#define DMAE_CMD_RESERVED1_MASK 0x1
1513#define DMAE_CMD_RESERVED1_SHIFT 13
1514#define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1515#define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1516#define DMAE_CMD_ERR_HANDLING_MASK 0x3
1517#define DMAE_CMD_ERR_HANDLING_SHIFT 16
1518#define DMAE_CMD_PORT_ID_MASK 0x3
1519#define DMAE_CMD_PORT_ID_SHIFT 18
1520#define DMAE_CMD_SRC_PF_ID_MASK 0xF
1521#define DMAE_CMD_SRC_PF_ID_SHIFT 20
1522#define DMAE_CMD_DST_PF_ID_MASK 0xF
1523#define DMAE_CMD_DST_PF_ID_SHIFT 24
1524#define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1525#define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1526#define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1527#define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1528#define DMAE_CMD_RESERVED2_MASK 0x3
1529#define DMAE_CMD_RESERVED2_SHIFT 30
1530 __le32 src_addr_lo;
1531 __le32 src_addr_hi;
1532 __le32 dst_addr_lo;
1533 __le32 dst_addr_hi;
1534 __le16 length_dw;
1535 __le16 opcode_b;
1536#define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1537#define DMAE_CMD_SRC_VF_ID_SHIFT 0
1538#define DMAE_CMD_DST_VF_ID_MASK 0xFF
1539#define DMAE_CMD_DST_VF_ID_SHIFT 8
1540 __le32 comp_addr_lo;
1541 __le32 comp_addr_hi;
1542 __le32 comp_val;
1543 __le32 crc32;
1544 __le32 crc_32_c;
1545 __le16 crc16;
1546 __le16 crc16_c;
1547 __le16 crc10;
1548 __le16 error_bit_reserved;
1549#define DMAE_CMD_ERROR_BIT_MASK 0x1
1550#define DMAE_CMD_ERROR_BIT_SHIFT 0
1551#define DMAE_CMD_RESERVED_MASK 0x7FFF
1552#define DMAE_CMD_RESERVED_SHIFT 1
1553 __le16 xsum16;
1554 __le16 xsum8;
1555};
1556
1557enum dmae_cmd_comp_crc_en_enum {
1558 dmae_cmd_comp_crc_disabled,
1559 dmae_cmd_comp_crc_enabled,
1560 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1561};
1562
1563enum dmae_cmd_comp_func_enum {
1564 dmae_cmd_comp_func_to_src,
1565 dmae_cmd_comp_func_to_dst,
1566 MAX_DMAE_CMD_COMP_FUNC_ENUM
1567};
1568
1569enum dmae_cmd_comp_word_en_enum {
1570 dmae_cmd_comp_word_disabled,
1571 dmae_cmd_comp_word_enabled,
1572 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1573};
1574
1575enum dmae_cmd_c_dst_enum {
1576 dmae_cmd_c_dst_pcie,
1577 dmae_cmd_c_dst_grc,
1578 MAX_DMAE_CMD_C_DST_ENUM
1579};
1580
1581enum dmae_cmd_dst_enum {
1582 dmae_cmd_dst_none_0,
1583 dmae_cmd_dst_pcie,
1584 dmae_cmd_dst_grc,
1585 dmae_cmd_dst_none_3,
1586 MAX_DMAE_CMD_DST_ENUM
1587};
1588
1589enum dmae_cmd_error_handling_enum {
1590 dmae_cmd_error_handling_send_regular_comp,
1591 dmae_cmd_error_handling_send_comp_with_err,
1592 dmae_cmd_error_handling_dont_send_comp,
1593 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1594};
1595
1596enum dmae_cmd_src_enum {
1597 dmae_cmd_src_pcie,
1598 dmae_cmd_src_grc,
1599 MAX_DMAE_CMD_SRC_ENUM
1600};
1601
1602struct mstorm_core_conn_ag_ctx {
1603 u8 byte0;
1604 u8 byte1;
1605 u8 flags0;
1606#define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1607#define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1608#define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1609#define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1610#define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1611#define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1612#define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1613#define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1614#define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1615#define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1616 u8 flags1;
1617#define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1618#define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1619#define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1620#define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1621#define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1622#define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1623#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1624#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1625#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1626#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1627#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1628#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1629#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1630#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1631#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1632#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1633 __le16 word0;
1634 __le16 word1;
1635 __le32 reg0;
1636 __le32 reg1;
1637};
1638
1639struct ystorm_core_conn_ag_ctx {
1640 u8 byte0;
1641 u8 byte1;
1642 u8 flags0;
1643#define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1644#define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1645#define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1646#define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1647#define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1648#define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1649#define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1650#define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1651#define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1652#define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1653 u8 flags1;
1654#define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1655#define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1656#define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1657#define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1658#define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1659#define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1660#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1661#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1662#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1663#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1664#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1665#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1666#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1667#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1668#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1669#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1670 u8 byte2;
1671 u8 byte3;
1672 __le16 word0;
1673 __le32 reg0;
1674 __le32 reg1;
1675 __le16 word1;
1676 __le16 word2;
1677 __le16 word3;
1678 __le16 word4;
1679 __le32 reg2;
1680 __le32 reg3;
1681};
1682
1683/* DMAE parameters */
1684struct qed_dmae_params {
1685 u32 flags;
1686/* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the
1687 * source is a block of length DMAE_MAX_RW_SIZE and the
1688 * destination is larger, the source block will be duplicated as
1689 * many times as required to fill the destination block. This is
1690 * used mostly to write a zeroed buffer to destination address
1691 * using DMA
1692 */
1693#define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
1694#define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0
1695#define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
1696#define QED_DMAE_PARAMS_SRC_VF_VALID_SHIFT 1
1697#define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1
1698#define QED_DMAE_PARAMS_DST_VF_VALID_SHIFT 2
1699#define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1
1700#define QED_DMAE_PARAMS_COMPLETION_DST_SHIFT 3
1701#define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1
1702#define QED_DMAE_PARAMS_PORT_VALID_SHIFT 4
1703#define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
1704#define QED_DMAE_PARAMS_SRC_PF_VALID_SHIFT 5
1705#define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1
1706#define QED_DMAE_PARAMS_DST_PF_VALID_SHIFT 6
1707#define QED_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF
1708#define QED_DMAE_PARAMS_RESERVED_SHIFT 7
1709 u8 src_vfid;
1710 u8 dst_vfid;
1711 u8 port_id;
1712 u8 src_pfid;
1713 u8 dst_pfid;
1714 u8 reserved1;
1715 __le16 reserved2;
1716};
1717
1718/* IGU cleanup command */
1719struct igu_cleanup {
1720 __le32 sb_id_and_flags;
1721#define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1722#define IGU_CLEANUP_RESERVED0_SHIFT 0
1723#define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1724#define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
1725#define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1726#define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
1727#define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1728#define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
1729 __le32 reserved1;
1730};
1731
1732/* IGU firmware driver command */
1733union igu_command {
1734 struct igu_prod_cons_update prod_cons_update;
1735 struct igu_cleanup cleanup;
1736};
1737
1738/* IGU firmware driver command */
1739struct igu_command_reg_ctrl {
1740 __le16 opaque_fid;
1741 __le16 igu_command_reg_ctrl_fields;
1742#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1743#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1744#define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1745#define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
1746#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1747#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1748};
1749
1750/* IGU mapping line structure */
1751struct igu_mapping_line {
1752 __le32 igu_mapping_line_fields;
1753#define IGU_MAPPING_LINE_VALID_MASK 0x1
1754#define IGU_MAPPING_LINE_VALID_SHIFT 0
1755#define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1756#define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
1757#define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1758#define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
1759#define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1760#define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
1761#define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1762#define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
1763#define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1764#define IGU_MAPPING_LINE_RESERVED_SHIFT 24
1765};
1766
1767/* IGU MSIX line structure */
1768struct igu_msix_vector {
1769 struct regpair address;
1770 __le32 data;
1771 __le32 msix_vector_fields;
1772#define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1773#define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1774#define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1775#define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
1776#define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1777#define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1778#define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1779#define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
1780};
1781
1782/* per encapsulation type enabling flags */
1783struct prs_reg_encapsulation_type_en {
1784 u8 flags;
1785#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1786#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1787#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1788#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1789#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1790#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1791#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1792#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1793#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1794#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1795#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1796#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1797#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1798#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1799};
1800
1801enum pxp_tph_st_hint {
1802 TPH_ST_HINT_BIDIR,
1803 TPH_ST_HINT_REQUESTER,
1804 TPH_ST_HINT_TARGET,
1805 TPH_ST_HINT_TARGET_PRIO,
1806 MAX_PXP_TPH_ST_HINT
1807};
1808
1809/* QM hardware structure of enable bypass credit mask */
1810struct qm_rf_bypass_mask {
1811 u8 flags;
1812#define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1813#define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1814#define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1815#define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1816#define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1817#define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1818#define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1819#define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1820#define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1821#define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1822#define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1823#define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1824#define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1825#define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1826#define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1827#define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1828};
1829
1830/* QM hardware structure of opportunistic credit mask */
1831struct qm_rf_opportunistic_mask {
1832 __le16 flags;
1833#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1834#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1835#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1836#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1837#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1838#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1839#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1840#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1841#define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1842#define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1843#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1844#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1845#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1846#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1847#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1848#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1849#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1850#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1851#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1852#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1853};
1854
1855/* QM hardware structure of QM map memory */
1856struct qm_rf_pq_map {
1857 __le32 reg;
1858#define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
1859#define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1860#define QM_RF_PQ_MAP_RL_ID_MASK 0xFF
1861#define QM_RF_PQ_MAP_RL_ID_SHIFT 1
1862#define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1863#define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
1864#define QM_RF_PQ_MAP_VOQ_MASK 0x1F
1865#define QM_RF_PQ_MAP_VOQ_SHIFT 18
1866#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
1867#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
1868#define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
1869#define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
1870#define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1871#define QM_RF_PQ_MAP_RESERVED_SHIFT 26
1872};
1873
1874/* Completion params for aggregated interrupt completion */
1875struct sdm_agg_int_comp_params {
1876 __le16 params;
1877#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1878#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1879#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1880#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1881#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1882#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1883};
1884
1885/* SDM operation gen command (generate aggregative interrupt) */
1886struct sdm_op_gen {
1887 __le32 command;
1888#define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1889#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1890#define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1891#define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1892#define SDM_OP_GEN_RESERVED_MASK 0xFFF
1893#define SDM_OP_GEN_RESERVED_SHIFT 20
1894};
1895
1896/* Physical memory descriptor */
1897struct phys_mem_desc {
1898 dma_addr_t phys_addr;
1899 void *virt_addr;
1900 u32 size; /* In bytes */
1901};
1902
1903/* Virtual memory descriptor */
1904struct virt_mem_desc {
1905 void *ptr;
1906 u32 size; /* In bytes */
1907};
1908
1909/********************************/
1910/* HSI Init Functions constants */
1911/********************************/
1912
1913/* Number of VLAN priorities */
1914#define NUM_OF_VLAN_PRIORITIES 8
1915
1916/* BRB RAM init requirements */
1917struct init_brb_ram_req {
1918 u32 guranteed_per_tc;
1919 u32 headroom_per_tc;
1920 u32 min_pkt_size;
1921 u32 max_ports_per_engine;
1922 u8 num_active_tcs[MAX_NUM_PORTS];
1923};
1924
1925/* ETS per-TC init requirements */
1926struct init_ets_tc_req {
1927 u8 use_sp;
1928 u8 use_wfq;
1929 u16 weight;
1930};
1931
1932/* ETS init requirements */
1933struct init_ets_req {
1934 u32 mtu;
1935 struct init_ets_tc_req tc_req[NUM_OF_TCS];
1936};
1937
1938/* NIG LB RL init requirements */
1939struct init_nig_lb_rl_req {
1940 u16 lb_mac_rate;
1941 u16 lb_rate;
1942 u32 mtu;
1943 u16 tc_rate[NUM_OF_PHYS_TCS];
1944};
1945
1946/* NIG TC mapping for each priority */
1947struct init_nig_pri_tc_map_entry {
1948 u8 tc_id;
1949 u8 valid;
1950};
1951
1952/* NIG priority to TC map init requirements */
1953struct init_nig_pri_tc_map_req {
1954 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
1955};
1956
1957/* QM per global RL init parameters */
1958struct init_qm_global_rl_params {
1959 u8 type;
1960 u8 reserved0;
1961 u16 reserved1;
1962 u32 rate_limit;
1963};
1964
1965/* QM per-port init parameters */
1966struct init_qm_port_params {
1967 u16 active_phys_tcs;
1968 u16 num_pbf_cmd_lines;
1969 u16 num_btb_blocks;
1970 u8 active;
1971 u8 reserved;
1972};
1973
1974/* QM per-PQ init parameters */
1975struct init_qm_pq_params {
1976 u16 vport_id;
1977 u16 rl_id;
1978 u8 rl_valid;
1979 u8 tc_id;
1980 u8 wrr_group;
1981 u8 port_id;
1982};
1983
1984/* QM per RL init parameters */
1985struct init_qm_rl_params {
1986 u32 vport_rl;
1987 u8 vport_rl_type;
1988 u8 reserved[3];
1989};
1990
1991/* QM Rate Limiter types */
1992enum init_qm_rl_type {
1993 QM_RL_TYPE_NORMAL,
1994 QM_RL_TYPE_QCN,
1995 MAX_INIT_QM_RL_TYPE
1996};
1997
1998/* QM per-vport init parameters */
1999struct init_qm_vport_params {
2000 u16 wfq;
2001 u16 reserved;
2002 u16 tc_wfq[NUM_OF_TCS];
2003 u16 first_tx_pq_id[NUM_OF_TCS];
2004};
2005
2006/**************************************/
2007/* Init Tool HSI constants and macros */
2008/**************************************/
2009
2010/* Width of GRC address in bits (addresses are specified in dwords) */
2011#define GRC_ADDR_BITS 23
2012#define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1)
2013
2014/* indicates an init that should be applied to any phase ID */
2015#define ANY_PHASE_ID 0xffff
2016
2017/* Max size in dwords of a zipped array */
2018#define MAX_ZIPPED_SIZE 8192
2019enum chip_ids {
2020 CHIP_BB,
2021 CHIP_K2,
2022 MAX_CHIP_IDS
2023};
2024
2025struct fw_asserts_ram_section {
2026 __le16 section_ram_line_offset;
2027 __le16 section_ram_line_size;
2028 u8 list_dword_offset;
2029 u8 list_element_dword_size;
2030 u8 list_num_elements;
2031 u8 list_next_index_dword_offset;
2032};
2033
2034struct fw_ver_num {
2035 u8 major;
2036 u8 minor;
2037 u8 rev;
2038 u8 eng;
2039};
2040
2041struct fw_ver_info {
2042 __le16 tools_ver;
2043 u8 image_id;
2044 u8 reserved1;
2045 struct fw_ver_num num;
2046 __le32 timestamp;
2047 __le32 reserved2;
2048};
2049
2050struct fw_info {
2051 struct fw_ver_info ver;
2052 struct fw_asserts_ram_section fw_asserts_section;
2053};
2054
2055struct fw_info_location {
2056 __le32 grc_addr;
2057 __le32 size;
2058};
2059
2060enum init_modes {
2061 MODE_BB_A0_DEPRECATED,
2062 MODE_BB,
2063 MODE_K2,
2064 MODE_ASIC,
2065 MODE_EMUL_REDUCED,
2066 MODE_EMUL_FULL,
2067 MODE_FPGA,
2068 MODE_CHIPSIM,
2069 MODE_SF,
2070 MODE_MF_SD,
2071 MODE_MF_SI,
2072 MODE_PORTS_PER_ENG_1,
2073 MODE_PORTS_PER_ENG_2,
2074 MODE_PORTS_PER_ENG_4,
2075 MODE_100G,
2076 MODE_SKIP_PRAM_INIT,
2077 MODE_EMUL_MAC,
2078 MAX_INIT_MODES
2079};
2080
2081enum init_phases {
2082 PHASE_ENGINE,
2083 PHASE_PORT,
2084 PHASE_PF,
2085 PHASE_VF,
2086 PHASE_QM_PF,
2087 MAX_INIT_PHASES
2088};
2089
2090enum init_split_types {
2091 SPLIT_TYPE_NONE,
2092 SPLIT_TYPE_PORT,
2093 SPLIT_TYPE_PF,
2094 SPLIT_TYPE_PORT_PF,
2095 SPLIT_TYPE_VF,
2096 MAX_INIT_SPLIT_TYPES
2097};
2098
2099/* Binary buffer header */
2100struct bin_buffer_hdr {
2101 u32 offset;
2102 u32 length;
2103};
2104
2105/* Binary init buffer types */
2106enum bin_init_buffer_type {
2107 BIN_BUF_INIT_FW_VER_INFO,
2108 BIN_BUF_INIT_CMD,
2109 BIN_BUF_INIT_VAL,
2110 BIN_BUF_INIT_MODE_TREE,
2111 BIN_BUF_INIT_IRO,
2112 BIN_BUF_INIT_OVERLAYS,
2113 MAX_BIN_INIT_BUFFER_TYPE
2114};
2115
2116/* FW overlay buffer header */
2117struct fw_overlay_buf_hdr {
2118 u32 data;
2119#define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF
2120#define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
2121#define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF
2122#define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8
2123};
2124
2125/* init array header: raw */
2126struct init_array_raw_hdr {
2127 __le32 data;
2128#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2129#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2130#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2131#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
2132};
2133
2134/* init array header: standard */
2135struct init_array_standard_hdr {
2136 __le32 data;
2137#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2138#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2139#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2140#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
2141};
2142
2143/* init array header: zipped */
2144struct init_array_zipped_hdr {
2145 __le32 data;
2146#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2147#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2148#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2149#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
2150};
2151
2152/* init array header: pattern */
2153struct init_array_pattern_hdr {
2154 __le32 data;
2155#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2156#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2157#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2158#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
2159#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2160#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
2161};
2162
2163/* init array header union */
2164union init_array_hdr {
2165 struct init_array_raw_hdr raw;
2166 struct init_array_standard_hdr standard;
2167 struct init_array_zipped_hdr zipped;
2168 struct init_array_pattern_hdr pattern;
2169};
2170
2171/* init array types */
2172enum init_array_types {
2173 INIT_ARR_STANDARD,
2174 INIT_ARR_ZIPPED,
2175 INIT_ARR_PATTERN,
2176 MAX_INIT_ARRAY_TYPES
2177};
2178
2179/* init operation: callback */
2180struct init_callback_op {
2181 __le32 op_data;
2182#define INIT_CALLBACK_OP_OP_MASK 0xF
2183#define INIT_CALLBACK_OP_OP_SHIFT 0
2184#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2185#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2186 __le16 callback_id;
2187 __le16 block_id;
2188};
2189
2190/* init operation: delay */
2191struct init_delay_op {
2192 __le32 op_data;
2193#define INIT_DELAY_OP_OP_MASK 0xF
2194#define INIT_DELAY_OP_OP_SHIFT 0
2195#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2196#define INIT_DELAY_OP_RESERVED_SHIFT 4
2197 __le32 delay;
2198};
2199
2200/* init operation: if_mode */
2201struct init_if_mode_op {
2202 __le32 op_data;
2203#define INIT_IF_MODE_OP_OP_MASK 0xF
2204#define INIT_IF_MODE_OP_OP_SHIFT 0
2205#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2206#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
2207#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2208#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
2209 __le16 reserved2;
2210 __le16 modes_buf_offset;
2211};
2212
2213/* init operation: if_phase */
2214struct init_if_phase_op {
2215 __le32 op_data;
2216#define INIT_IF_PHASE_OP_OP_MASK 0xF
2217#define INIT_IF_PHASE_OP_OP_SHIFT 0
2218#define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF
2219#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 4
2220#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2221#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
2222 __le32 phase_data;
2223#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2224#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2225#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2226#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
2227#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2228#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
2229};
2230
2231/* init mode operators */
2232enum init_mode_ops {
2233 INIT_MODE_OP_NOT,
2234 INIT_MODE_OP_OR,
2235 INIT_MODE_OP_AND,
2236 MAX_INIT_MODE_OPS
2237};
2238
2239/* init operation: raw */
2240struct init_raw_op {
2241 __le32 op_data;
2242#define INIT_RAW_OP_OP_MASK 0xF
2243#define INIT_RAW_OP_OP_SHIFT 0
2244#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2245#define INIT_RAW_OP_PARAM1_SHIFT 4
2246 __le32 param2;
2247};
2248
2249/* init array params */
2250struct init_op_array_params {
2251 __le16 size;
2252 __le16 offset;
2253};
2254
2255/* Write init operation arguments */
2256union init_write_args {
2257 __le32 inline_val;
2258 __le32 zeros_count;
2259 __le32 array_offset;
2260 struct init_op_array_params runtime;
2261};
2262
2263/* init operation: write */
2264struct init_write_op {
2265 __le32 data;
2266#define INIT_WRITE_OP_OP_MASK 0xF
2267#define INIT_WRITE_OP_OP_SHIFT 0
2268#define INIT_WRITE_OP_SOURCE_MASK 0x7
2269#define INIT_WRITE_OP_SOURCE_SHIFT 4
2270#define INIT_WRITE_OP_RESERVED_MASK 0x1
2271#define INIT_WRITE_OP_RESERVED_SHIFT 7
2272#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2273#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
2274#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2275#define INIT_WRITE_OP_ADDRESS_SHIFT 9
2276 union init_write_args args;
2277};
2278
2279/* init operation: read */
2280struct init_read_op {
2281 __le32 op_data;
2282#define INIT_READ_OP_OP_MASK 0xF
2283#define INIT_READ_OP_OP_SHIFT 0
2284#define INIT_READ_OP_POLL_TYPE_MASK 0xF
2285#define INIT_READ_OP_POLL_TYPE_SHIFT 4
2286#define INIT_READ_OP_RESERVED_MASK 0x1
2287#define INIT_READ_OP_RESERVED_SHIFT 8
2288#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
2289#define INIT_READ_OP_ADDRESS_SHIFT 9
2290 __le32 expected_val;
2291};
2292
2293/* Init operations union */
2294union init_op {
2295 struct init_raw_op raw;
2296 struct init_write_op write;
2297 struct init_read_op read;
2298 struct init_if_mode_op if_mode;
2299 struct init_if_phase_op if_phase;
2300 struct init_callback_op callback;
2301 struct init_delay_op delay;
2302};
2303
2304/* Init command operation types */
2305enum init_op_types {
2306 INIT_OP_READ,
2307 INIT_OP_WRITE,
2308 INIT_OP_IF_MODE,
2309 INIT_OP_IF_PHASE,
2310 INIT_OP_DELAY,
2311 INIT_OP_CALLBACK,
2312 MAX_INIT_OP_TYPES
2313};
2314
2315/* init polling types */
2316enum init_poll_types {
2317 INIT_POLL_NONE,
2318 INIT_POLL_EQ,
2319 INIT_POLL_OR,
2320 INIT_POLL_AND,
2321 MAX_INIT_POLL_TYPES
2322};
2323
2324/* init source types */
2325enum init_source_types {
2326 INIT_SRC_INLINE,
2327 INIT_SRC_ZEROS,
2328 INIT_SRC_ARRAY,
2329 INIT_SRC_RUNTIME,
2330 MAX_INIT_SOURCE_TYPES
2331};
2332
2333/* Internal RAM Offsets macro data */
2334struct iro {
2335 u32 base;
2336 u16 m1;
2337 u16 m2;
2338 u16 m3;
2339 u16 size;
2340};
2341
2342/* Win 2 */
2343#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
2344
2345/* Win 3 */
2346#define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
2347
2348/* Win 4 */
2349#define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
2350
2351/* Win 5 */
2352#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
2353
2354/* Win 6 */
2355#define GTT_BAR0_MAP_REG_MSDM_RAM_2048 0x013000UL
2356
2357/* Win 7 */
2358#define GTT_BAR0_MAP_REG_USDM_RAM 0x014000UL
2359
2360/* Win 8 */
2361#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x015000UL
2362
2363/* Win 9 */
2364#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x016000UL
2365
2366/* Win 10 */
2367#define GTT_BAR0_MAP_REG_XSDM_RAM 0x017000UL
2368
2369/* Win 11 */
2370#define GTT_BAR0_MAP_REG_XSDM_RAM_1024 0x018000UL
2371
2372/* Win 12 */
2373#define GTT_BAR0_MAP_REG_YSDM_RAM 0x019000UL
2374
2375/* Win 13 */
2376#define GTT_BAR0_MAP_REG_PSDM_RAM 0x01a000UL
2377
2378/* Returns the VOQ based on port and TC */
2379#define VOQ(port, tc, max_phys_tcs_per_port) ((tc) == \
2380 PURE_LB_TC ? NUM_OF_PHYS_TCS *\
2381 MAX_NUM_PORTS_BB + \
2382 (port) : (port) * \
2383 (max_phys_tcs_per_port) + (tc))
2384
2385struct init_qm_pq_params;
2386
2387/**
2388 * qed_qm_pf_mem_size(): Prepare QM ILT sizes.
2389 *
2390 * @num_pf_cids: Number of connections used by this PF.
2391 * @num_vf_cids: Number of connections used by VFs of this PF.
2392 * @num_tids: Number of tasks used by this PF.
2393 * @num_pf_pqs: Number of PQs used by this PF.
2394 * @num_vf_pqs: Number of PQs used by VFs of this PF.
2395 *
2396 * Return: The required host memory size in 4KB units.
2397 *
2398 * Returns the required host memory size in 4KB units.
2399 * Must be called before all QM init HSI functions.
2400 */
2401u32 qed_qm_pf_mem_size(u32 num_pf_cids,
2402 u32 num_vf_cids,
2403 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
2404
2405struct qed_qm_common_rt_init_params {
2406 u8 max_ports_per_engine;
2407 u8 max_phys_tcs_per_port;
2408 bool pf_rl_en;
2409 bool pf_wfq_en;
2410 bool global_rl_en;
2411 bool vport_wfq_en;
2412 struct init_qm_port_params *port_params;
2413 struct init_qm_global_rl_params
2414 global_rl_params[COMMON_MAX_QM_GLOBAL_RLS];
2415};
2416
2417/**
2418 * qed_qm_common_rt_init(): Prepare QM runtime init values for the
2419 * engine phase.
2420 *
2421 * @p_hwfn: HW device data.
2422 * @p_params: Parameters.
2423 *
2424 * Return: 0 on success, -1 on error.
2425 */
2426int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
2427 struct qed_qm_common_rt_init_params *p_params);
2428
2429struct qed_qm_pf_rt_init_params {
2430 u8 port_id;
2431 u8 pf_id;
2432 u8 max_phys_tcs_per_port;
2433 bool is_pf_loading;
2434 u32 num_pf_cids;
2435 u32 num_vf_cids;
2436 u32 num_tids;
2437 u16 start_pq;
2438 u16 num_pf_pqs;
2439 u16 num_vf_pqs;
2440 u16 start_vport;
2441 u16 num_vports;
2442 u16 start_rl;
2443 u16 num_rls;
2444 u16 pf_wfq;
2445 u32 pf_rl;
2446 u32 link_speed;
2447 struct init_qm_pq_params *pq_params;
2448 struct init_qm_vport_params *vport_params;
2449 struct init_qm_rl_params *rl_params;
2450};
2451
2452/**
2453 * qed_qm_pf_rt_init(): Prepare QM runtime init values for the PF phase.
2454 *
2455 * @p_hwfn: HW device data.
2456 * @p_ptt: Ptt window used for writing the registers
2457 * @p_params: Parameters.
2458 *
2459 * Return: 0 on success, -1 on error.
2460 */
2461int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
2462 struct qed_ptt *p_ptt,
2463 struct qed_qm_pf_rt_init_params *p_params);
2464
2465/**
2466 * qed_init_pf_wfq(): Initializes the WFQ weight of the specified PF.
2467 *
2468 * @p_hwfn: HW device data.
2469 * @p_ptt: Ptt window used for writing the registers
2470 * @pf_id: PF ID
2471 * @pf_wfq: WFQ weight. Must be non-zero.
2472 *
2473 * Return: 0 on success, -1 on error.
2474 */
2475int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
2476 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
2477
2478/**
2479 * qed_init_pf_rl(): Initializes the rate limit of the specified PF
2480 *
2481 * @p_hwfn: HW device data.
2482 * @p_ptt: Ptt window used for writing the registers.
2483 * @pf_id: PF ID.
2484 * @pf_rl: rate limit in Mb/sec units
2485 *
2486 * Return: 0 on success, -1 on error.
2487 */
2488int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
2489 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
2490
2491/**
2492 * qed_init_vport_wfq(): Initializes the WFQ weight of the specified VPORT
2493 *
2494 * @p_hwfn: HW device data.
2495 * @p_ptt: Ptt window used for writing the registers
2496 * @first_tx_pq_id: An array containing the first Tx PQ ID associated
2497 * with the VPORT for each TC. This array is filled by
2498 * qed_qm_pf_rt_init
2499 * @wfq: WFQ weight. Must be non-zero.
2500 *
2501 * Return: 0 on success, -1 on error.
2502 */
2503int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
2504 struct qed_ptt *p_ptt,
2505 u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq);
2506
2507/**
2508 * qed_init_vport_tc_wfq(): Initializes the WFQ weight of the specified
2509 * VPORT and TC.
2510 *
2511 * @p_hwfn: HW device data.
2512 * @p_ptt: Ptt window used for writing the registers.
2513 * @first_tx_pq_id: The first Tx PQ ID associated with the VPORT and TC.
2514 * (filled by qed_qm_pf_rt_init).
2515 * @weight: VPORT+TC WFQ weight.
2516 *
2517 * Return: 0 on success, -1 on error.
2518 */
2519int qed_init_vport_tc_wfq(struct qed_hwfn *p_hwfn,
2520 struct qed_ptt *p_ptt,
2521 u16 first_tx_pq_id, u16 weight);
2522
2523/**
2524 * qed_init_global_rl(): Initializes the rate limit of the specified
2525 * rate limiter.
2526 *
2527 * @p_hwfn: HW device data.
2528 * @p_ptt: Ptt window used for writing the registers.
2529 * @rl_id: RL ID.
2530 * @rate_limit: Rate limit in Mb/sec units
2531 * @vport_rl_type: Vport RL type.
2532 *
2533 * Return: 0 on success, -1 on error.
2534 */
2535int qed_init_global_rl(struct qed_hwfn *p_hwfn,
2536 struct qed_ptt *p_ptt,
2537 u16 rl_id, u32 rate_limit,
2538 enum init_qm_rl_type vport_rl_type);
2539
2540/**
2541 * qed_send_qm_stop_cmd(): Sends a stop command to the QM.
2542 *
2543 * @p_hwfn: HW device data.
2544 * @p_ptt: Ptt window used for writing the registers.
2545 * @is_release_cmd: true for release, false for stop.
2546 * @is_tx_pq: true for Tx PQs, false for Other PQs.
2547 * @start_pq: first PQ ID to stop
2548 * @num_pqs: Number of PQs to stop, starting from start_pq.
2549 *
2550 * Return: Bool, true if successful, false if timeout occurred while waiting
2551 * for QM command done.
2552 */
2553bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
2554 struct qed_ptt *p_ptt,
2555 bool is_release_cmd,
2556 bool is_tx_pq, u16 start_pq, u16 num_pqs);
2557
2558/**
2559 * qed_set_vxlan_dest_port(): Initializes vxlan tunnel destination udp port.
2560 *
2561 * @p_hwfn: HW device data.
2562 * @p_ptt: Ptt window used for writing the registers.
2563 * @dest_port: vxlan destination udp port.
2564 *
2565 * Return: Void.
2566 */
2567void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
2568 struct qed_ptt *p_ptt, u16 dest_port);
2569
2570/**
2571 * qed_set_vxlan_enable(): Enable or disable VXLAN tunnel in HW.
2572 *
2573 * @p_hwfn: HW device data.
2574 * @p_ptt: Ptt window used for writing the registers.
2575 * @vxlan_enable: vxlan enable flag.
2576 *
2577 * Return: Void.
2578 */
2579void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
2580 struct qed_ptt *p_ptt, bool vxlan_enable);
2581
2582/**
2583 * qed_set_gre_enable(): Enable or disable GRE tunnel in HW.
2584 *
2585 * @p_hwfn: HW device data.
2586 * @p_ptt: Ptt window used for writing the registers.
2587 * @eth_gre_enable: Eth GRE enable flag.
2588 * @ip_gre_enable: IP GRE enable flag.
2589 *
2590 * Return: Void.
2591 */
2592void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
2593 struct qed_ptt *p_ptt,
2594 bool eth_gre_enable, bool ip_gre_enable);
2595
2596/**
2597 * qed_set_geneve_dest_port(): Initializes geneve tunnel destination udp port
2598 *
2599 * @p_hwfn: HW device data.
2600 * @p_ptt: Ptt window used for writing the registers.
2601 * @dest_port: Geneve destination udp port.
2602 *
2603 * Retur: Void.
2604 */
2605void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
2606 struct qed_ptt *p_ptt, u16 dest_port);
2607
2608/**
2609 * qed_set_geneve_enable(): Enable or disable GRE tunnel in HW.
2610 *
2611 * @p_hwfn: HW device data.
2612 * @p_ptt: Ptt window used for writing the registers.
2613 * @eth_geneve_enable: Eth GENEVE enable flag.
2614 * @ip_geneve_enable: IP GENEVE enable flag.
2615 *
2616 * Return: Void.
2617 */
2618void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
2619 struct qed_ptt *p_ptt,
2620 bool eth_geneve_enable, bool ip_geneve_enable);
2621
2622void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
2623 struct qed_ptt *p_ptt, bool enable);
2624
2625/**
2626 * qed_gft_disable(): Disable GFT.
2627 *
2628 * @p_hwfn: HW device data.
2629 * @p_ptt: Ptt window used for writing the registers.
2630 * @pf_id: PF on which to disable GFT.
2631 *
2632 * Return: Void.
2633 */
2634void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id);
2635
2636/**
2637 * qed_gft_config(): Enable and configure HW for GFT.
2638 *
2639 * @p_hwfn: HW device data.
2640 * @p_ptt: Ptt window used for writing the registers.
2641 * @pf_id: PF on which to enable GFT.
2642 * @tcp: Set profile tcp packets.
2643 * @udp: Set profile udp packet.
2644 * @ipv4: Set profile ipv4 packet.
2645 * @ipv6: Set profile ipv6 packet.
2646 * @profile_type: Define packet same fields. Use enum gft_profile_type.
2647 *
2648 * Return: Void.
2649 */
2650void qed_gft_config(struct qed_hwfn *p_hwfn,
2651 struct qed_ptt *p_ptt,
2652 u16 pf_id,
2653 bool tcp,
2654 bool udp,
2655 bool ipv4, bool ipv6, enum gft_profile_type profile_type);
2656
2657/**
2658 * qed_enable_context_validation(): Enable and configure context
2659 * validation.
2660 *
2661 * @p_hwfn: HW device data.
2662 * @p_ptt: Ptt window used for writing the registers.
2663 *
2664 * Return: Void.
2665 */
2666void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
2667 struct qed_ptt *p_ptt);
2668
2669#define NUM_STORMS 6
2670
2671/**
2672 * qed_get_protocol_type_str(): Get a string for Protocol type.
2673 *
2674 * @protocol_type: Protocol type (using enum protocol_type).
2675 *
2676 * Return: String.
2677 */
2678const char *qed_get_protocol_type_str(u32 protocol_type);
2679
2680/**
2681 * qed_get_ramrod_cmd_id_str(): Get a string for Ramrod command ID.
2682 *
2683 * @protocol_type: Protocol type (using enum protocol_type).
2684 * @ramrod_cmd_id: Ramrod command ID (using per-protocol enum <protocol>_ramrod_cmd_id).
2685 *
2686 * Return: String.
2687 */
2688const char *qed_get_ramrod_cmd_id_str(u32 protocol_type, u32 ramrod_cmd_id);
2689
2690/**
2691 * qed_set_rdma_error_level(): Sets the RDMA assert level.
2692 * If the severity of the error will be
2693 * above the level, the FW will assert.
2694 * @p_hwfn: HW device data.
2695 * @p_ptt: Ptt window used for writing the registers.
2696 * @assert_level: An array of assert levels for each storm.
2697 *
2698 * Return: Void.
2699 */
2700void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
2701 struct qed_ptt *p_ptt,
2702 u8 assert_level[NUM_STORMS]);
2703/**
2704 * qed_fw_overlay_mem_alloc(): Allocates and fills the FW overlay memory.
2705 *
2706 * @p_hwfn: HW device data.
2707 * @fw_overlay_in_buf: The input FW overlay buffer.
2708 * @buf_size_in_bytes: The size of the input FW overlay buffer in bytes.
2709 * must be aligned to dwords.
2710 *
2711 * Return: A pointer to the allocated overlays memory,
2712 * or NULL in case of failures.
2713 */
2714struct phys_mem_desc *
2715qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
2716 const u32 *const fw_overlay_in_buf,
2717 u32 buf_size_in_bytes);
2718
2719/**
2720 * qed_fw_overlay_init_ram(): Initializes the FW overlay RAM.
2721 *
2722 * @p_hwfn: HW device data.
2723 * @p_ptt: Ptt window used for writing the registers.
2724 * @fw_overlay_mem: the allocated FW overlay memory.
2725 *
2726 * Return: Void.
2727 */
2728void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
2729 struct qed_ptt *p_ptt,
2730 struct phys_mem_desc *fw_overlay_mem);
2731
2732/**
2733 * qed_fw_overlay_mem_free(): Frees the FW overlay memory.
2734 *
2735 * @p_hwfn: HW device data.
2736 * @fw_overlay_mem: The allocated FW overlay memory to free.
2737 *
2738 * Return: Void.
2739 */
2740void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
2741 struct phys_mem_desc **fw_overlay_mem);
2742
2743#define PCICFG_OFFSET 0x2000
2744#define GRC_CONFIG_REG_PF_INIT_VF 0x624
2745
2746/* First VF_NUM for PF is encoded in this register.
2747 * The number of VFs assigned to a PF is assumed to be a multiple of 8.
2748 * Software should program these bits based on Total Number of VFs programmed
2749 * for each PF.
2750 * Since registers from 0x000-0x7ff are spilt across functions, each PF will
2751 * have the same location for the same 4 bits
2752 */
2753#define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xff
2754
2755/* Runtime array offsets */
2756#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
2757#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
2758#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
2759#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
2760#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
2761#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
2762#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
2763#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
2764#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
2765#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
2766#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
2767#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
2768#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
2769#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
2770#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
2771#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
2772#define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET 16
2773#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 17
2774#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 18
2775#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 19
2776#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 20
2777#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 21
2778#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 22
2779#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 23
2780#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 24
2781#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 25
2782#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 26
2783#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
2784#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 762
2785#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
2786#define CAU_REG_PI_MEMORY_RT_OFFSET 1498
2787#define CAU_REG_PI_MEMORY_RT_SIZE 4416
2788#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 5914
2789#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 5915
2790#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 5916
2791#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 5917
2792#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 5918
2793#define PRS_REG_SEARCH_TCP_RT_OFFSET 5919
2794#define PRS_REG_SEARCH_FCOE_RT_OFFSET 5920
2795#define PRS_REG_SEARCH_ROCE_RT_OFFSET 5921
2796#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 5922
2797#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 5923
2798#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 5924
2799#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 5925
2800#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 5926
2801#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 5927
2802#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 5928
2803#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 5929
2804#define SRC_REG_FIRSTFREE_RT_OFFSET 5930
2805#define SRC_REG_FIRSTFREE_RT_SIZE 2
2806#define SRC_REG_LASTFREE_RT_OFFSET 5932
2807#define SRC_REG_LASTFREE_RT_SIZE 2
2808#define SRC_REG_COUNTFREE_RT_OFFSET 5934
2809#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 5935
2810#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 5936
2811#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 5937
2812#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 5938
2813#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 5939
2814#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 5940
2815#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 5941
2816#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 5942
2817#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 5943
2818#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 5944
2819#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 5945
2820#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 5946
2821#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 5947
2822#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 5948
2823#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 5949
2824#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 5950
2825#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 5951
2826#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 5952
2827#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 5953
2828#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5954
2829#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5955
2830#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5956
2831#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 5957
2832#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 5958
2833#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 5959
2834#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 5960
2835#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 5961
2836#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 5962
2837#define PSWRQ2_REG_VF_BASE_RT_OFFSET 5963
2838#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 5964
2839#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 5965
2840#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 5966
2841#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 5967
2842#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
2843#define PGLUE_REG_B_VF_BASE_RT_OFFSET 27967
2844#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 27968
2845#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 27969
2846#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 27970
2847#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 27971
2848#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 27972
2849#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 27973
2850#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 27974
2851#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 27975
2852#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 27976
2853#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 27977
2854#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 27978
2855#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 27979
2856#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
2857#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 28395
2858#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
2859#define QM_REG_MAXPQSIZE_0_RT_OFFSET 28907
2860#define QM_REG_MAXPQSIZE_1_RT_OFFSET 28908
2861#define QM_REG_MAXPQSIZE_2_RT_OFFSET 28909
2862#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 28910
2863#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 28911
2864#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 28912
2865#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 28913
2866#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 28914
2867#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 28915
2868#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 28916
2869#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 28917
2870#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 28918
2871#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 28919
2872#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 28920
2873#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 28921
2874#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 28922
2875#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 28923
2876#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 28924
2877#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 28925
2878#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 28926
2879#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 28927
2880#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 28928
2881#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 28929
2882#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 28930
2883#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 28931
2884#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 28932
2885#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 28933
2886#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 28934
2887#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 28935
2888#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 28936
2889#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 28937
2890#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 28938
2891#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 28939
2892#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 28940
2893#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 28941
2894#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 28942
2895#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 28943
2896#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 28944
2897#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 28945
2898#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 28946
2899#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 28947
2900#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 28948
2901#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 28949
2902#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 28950
2903#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 28951
2904#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 28952
2905#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 28953
2906#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 28954
2907#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 28955
2908#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 28956
2909#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 28957
2910#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 28958
2911#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 28959
2912#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 28960
2913#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 28961
2914#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 28962
2915#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 28963
2916#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 28964
2917#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 28965
2918#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 28966
2919#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 28967
2920#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 28968
2921#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 28969
2922#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 28970
2923#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 28971
2924#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 28972
2925#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 28973
2926#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 28974
2927#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
2928#define QM_REG_PTRTBLOTHER_RT_OFFSET 29102
2929#define QM_REG_PTRTBLOTHER_RT_SIZE 256
2930#define QM_REG_VOQCRDLINE_RT_OFFSET 29358
2931#define QM_REG_VOQCRDLINE_RT_SIZE 20
2932#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29378
2933#define QM_REG_VOQINITCRDLINE_RT_SIZE 20
2934#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29398
2935#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29399
2936#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29400
2937#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29401
2938#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29402
2939#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29403
2940#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29404
2941#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29405
2942#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29406
2943#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29407
2944#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29408
2945#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29409
2946#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29410
2947#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29411
2948#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29412
2949#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29413
2950#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29414
2951#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29415
2952#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29416
2953#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29417
2954#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29418
2955#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29419
2956#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29420
2957#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29421
2958#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29422
2959#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29423
2960#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29424
2961#define QM_REG_PQTX2PF_0_RT_OFFSET 29425
2962#define QM_REG_PQTX2PF_1_RT_OFFSET 29426
2963#define QM_REG_PQTX2PF_2_RT_OFFSET 29427
2964#define QM_REG_PQTX2PF_3_RT_OFFSET 29428
2965#define QM_REG_PQTX2PF_4_RT_OFFSET 29429
2966#define QM_REG_PQTX2PF_5_RT_OFFSET 29430
2967#define QM_REG_PQTX2PF_6_RT_OFFSET 29431
2968#define QM_REG_PQTX2PF_7_RT_OFFSET 29432
2969#define QM_REG_PQTX2PF_8_RT_OFFSET 29433
2970#define QM_REG_PQTX2PF_9_RT_OFFSET 29434
2971#define QM_REG_PQTX2PF_10_RT_OFFSET 29435
2972#define QM_REG_PQTX2PF_11_RT_OFFSET 29436
2973#define QM_REG_PQTX2PF_12_RT_OFFSET 29437
2974#define QM_REG_PQTX2PF_13_RT_OFFSET 29438
2975#define QM_REG_PQTX2PF_14_RT_OFFSET 29439
2976#define QM_REG_PQTX2PF_15_RT_OFFSET 29440
2977#define QM_REG_PQTX2PF_16_RT_OFFSET 29441
2978#define QM_REG_PQTX2PF_17_RT_OFFSET 29442
2979#define QM_REG_PQTX2PF_18_RT_OFFSET 29443
2980#define QM_REG_PQTX2PF_19_RT_OFFSET 29444
2981#define QM_REG_PQTX2PF_20_RT_OFFSET 29445
2982#define QM_REG_PQTX2PF_21_RT_OFFSET 29446
2983#define QM_REG_PQTX2PF_22_RT_OFFSET 29447
2984#define QM_REG_PQTX2PF_23_RT_OFFSET 29448
2985#define QM_REG_PQTX2PF_24_RT_OFFSET 29449
2986#define QM_REG_PQTX2PF_25_RT_OFFSET 29450
2987#define QM_REG_PQTX2PF_26_RT_OFFSET 29451
2988#define QM_REG_PQTX2PF_27_RT_OFFSET 29452
2989#define QM_REG_PQTX2PF_28_RT_OFFSET 29453
2990#define QM_REG_PQTX2PF_29_RT_OFFSET 29454
2991#define QM_REG_PQTX2PF_30_RT_OFFSET 29455
2992#define QM_REG_PQTX2PF_31_RT_OFFSET 29456
2993#define QM_REG_PQTX2PF_32_RT_OFFSET 29457
2994#define QM_REG_PQTX2PF_33_RT_OFFSET 29458
2995#define QM_REG_PQTX2PF_34_RT_OFFSET 29459
2996#define QM_REG_PQTX2PF_35_RT_OFFSET 29460
2997#define QM_REG_PQTX2PF_36_RT_OFFSET 29461
2998#define QM_REG_PQTX2PF_37_RT_OFFSET 29462
2999#define QM_REG_PQTX2PF_38_RT_OFFSET 29463
3000#define QM_REG_PQTX2PF_39_RT_OFFSET 29464
3001#define QM_REG_PQTX2PF_40_RT_OFFSET 29465
3002#define QM_REG_PQTX2PF_41_RT_OFFSET 29466
3003#define QM_REG_PQTX2PF_42_RT_OFFSET 29467
3004#define QM_REG_PQTX2PF_43_RT_OFFSET 29468
3005#define QM_REG_PQTX2PF_44_RT_OFFSET 29469
3006#define QM_REG_PQTX2PF_45_RT_OFFSET 29470
3007#define QM_REG_PQTX2PF_46_RT_OFFSET 29471
3008#define QM_REG_PQTX2PF_47_RT_OFFSET 29472
3009#define QM_REG_PQTX2PF_48_RT_OFFSET 29473
3010#define QM_REG_PQTX2PF_49_RT_OFFSET 29474
3011#define QM_REG_PQTX2PF_50_RT_OFFSET 29475
3012#define QM_REG_PQTX2PF_51_RT_OFFSET 29476
3013#define QM_REG_PQTX2PF_52_RT_OFFSET 29477
3014#define QM_REG_PQTX2PF_53_RT_OFFSET 29478
3015#define QM_REG_PQTX2PF_54_RT_OFFSET 29479
3016#define QM_REG_PQTX2PF_55_RT_OFFSET 29480
3017#define QM_REG_PQTX2PF_56_RT_OFFSET 29481
3018#define QM_REG_PQTX2PF_57_RT_OFFSET 29482
3019#define QM_REG_PQTX2PF_58_RT_OFFSET 29483
3020#define QM_REG_PQTX2PF_59_RT_OFFSET 29484
3021#define QM_REG_PQTX2PF_60_RT_OFFSET 29485
3022#define QM_REG_PQTX2PF_61_RT_OFFSET 29486
3023#define QM_REG_PQTX2PF_62_RT_OFFSET 29487
3024#define QM_REG_PQTX2PF_63_RT_OFFSET 29488
3025#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29489
3026#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29490
3027#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29491
3028#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29492
3029#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29493
3030#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29494
3031#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29495
3032#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29496
3033#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29497
3034#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29498
3035#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29499
3036#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29500
3037#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29501
3038#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29502
3039#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29503
3040#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29504
3041#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29505
3042#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29506
3043#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29507
3044#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29508
3045#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29509
3046#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29510
3047#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29511
3048#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29512
3049#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29513
3050#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29514
3051#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29515
3052#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29516
3053#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29517
3054#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
3055#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 29773
3056#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
3057#define QM_REG_RLGLBLCRD_RT_OFFSET 30029
3058#define QM_REG_RLGLBLCRD_RT_SIZE 256
3059#define QM_REG_RLGLBLENABLE_RT_OFFSET 30285
3060#define QM_REG_RLPFPERIOD_RT_OFFSET 30286
3061#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30287
3062#define QM_REG_RLPFINCVAL_RT_OFFSET 30288
3063#define QM_REG_RLPFINCVAL_RT_SIZE 16
3064#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30304
3065#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
3066#define QM_REG_RLPFCRD_RT_OFFSET 30320
3067#define QM_REG_RLPFCRD_RT_SIZE 16
3068#define QM_REG_RLPFENABLE_RT_OFFSET 30336
3069#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30337
3070#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30338
3071#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
3072#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30354
3073#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
3074#define QM_REG_WFQPFCRD_RT_OFFSET 30370
3075#define QM_REG_WFQPFCRD_RT_SIZE 160
3076#define QM_REG_WFQPFENABLE_RT_OFFSET 30530
3077#define QM_REG_WFQVPENABLE_RT_OFFSET 30531
3078#define QM_REG_BASEADDRTXPQ_RT_OFFSET 30532
3079#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
3080#define QM_REG_TXPQMAP_RT_OFFSET 31044
3081#define QM_REG_TXPQMAP_RT_SIZE 512
3082#define QM_REG_WFQVPWEIGHT_RT_OFFSET 31556
3083#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
3084#define QM_REG_WFQVPUPPERBOUND_RT_OFFSET 32068
3085#define QM_REG_WFQVPUPPERBOUND_RT_SIZE 512
3086#define QM_REG_WFQVPCRD_RT_OFFSET 32580
3087#define QM_REG_WFQVPCRD_RT_SIZE 512
3088#define QM_REG_WFQVPMAP_RT_OFFSET 33092
3089#define QM_REG_WFQVPMAP_RT_SIZE 512
3090#define QM_REG_PTRTBLTX_RT_OFFSET 33604
3091#define QM_REG_PTRTBLTX_RT_SIZE 1024
3092#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34628
3093#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
3094#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34788
3095#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 34789
3096#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34790
3097#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34791
3098#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34792
3099#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34793
3100#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34794
3101#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34795
3102#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
3103#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34799
3104#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
3105#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34803
3106#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
3107#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34835
3108#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
3109#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34851
3110#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
3111#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34867
3112#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
3113#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34883
3114#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
3115#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34899
3116#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 34900
3117#define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8
3118#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34908
3119#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34909
3120#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34910
3121#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34911
3122#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34912
3123#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34913
3124#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34914
3125#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34915
3126#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34916
3127#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34917
3128#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34918
3129#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34919
3130#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34920
3131#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34921
3132#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34922
3133#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34923
3134#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34924
3135#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34925
3136#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34926
3137#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34927
3138#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34928
3139#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34929
3140#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34930
3141#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34931
3142#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34932
3143#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34933
3144#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34934
3145#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34935
3146#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34936
3147#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34937
3148#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34938
3149#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34939
3150#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34940
3151#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34941
3152#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34942
3153#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34943
3154#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34944
3155#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34945
3156#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34946
3157#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34947
3158#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34948
3159#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34949
3160#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34950
3161#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34951
3162#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34952
3163#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34953
3164#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34954
3165#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34955
3166#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34956
3167#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34957
3168#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34958
3169#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34959
3170#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34960
3171#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34961
3172#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34962
3173#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34963
3174#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34964
3175#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34965
3176#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34966
3177#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34967
3178#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34968
3179#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34969
3180#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34970
3181#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34971
3182#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34972
3183#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34973
3184#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34974
3185#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34975
3186#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34976
3187#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34977
3188#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34978
3189#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34979
3190#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34980
3191#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34981
3192#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34982
3193#define XCM_REG_CON_PHY_Q3_RT_OFFSET 34983
3194
3195#define RUNTIME_ARRAY_SIZE 34984
3196
3197/* Init Callbacks */
3198#define DMAE_READY_CB 0
3199
3200/* The eth storm context for the Tstorm */
3201struct tstorm_eth_conn_st_ctx {
3202 __le32 reserved[4];
3203};
3204
3205/* The eth storm context for the Pstorm */
3206struct pstorm_eth_conn_st_ctx {
3207 __le32 reserved[8];
3208};
3209
3210/* The eth storm context for the Xstorm */
3211struct xstorm_eth_conn_st_ctx {
3212 __le32 reserved[60];
3213};
3214
3215struct xstorm_eth_conn_ag_ctx {
3216 u8 reserved0;
3217 u8 state;
3218 u8 flags0;
3219#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
3220#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
3221#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
3222#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
3223#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
3224#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
3225#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
3226#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
3227#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
3228#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
3229#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
3230#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
3231#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
3232#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
3233#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
3234#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
3235 u8 flags1;
3236#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
3237#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
3238#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
3239#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
3240#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
3241#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
3242#define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
3243#define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
3244#define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
3245#define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
3246#define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
3247#define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
3248#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
3249#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
3250#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
3251#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
3252 u8 flags2;
3253#define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3254#define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
3255#define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
3256#define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
3257#define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3258#define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
3259#define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3260#define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
3261 u8 flags3;
3262#define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
3263#define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
3264#define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
3265#define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
3266#define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
3267#define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
3268#define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
3269#define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
3270 u8 flags4;
3271#define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
3272#define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
3273#define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
3274#define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
3275#define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
3276#define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
3277#define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
3278#define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
3279 u8 flags5;
3280#define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
3281#define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
3282#define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
3283#define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
3284#define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
3285#define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
3286#define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
3287#define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
3288 u8 flags6;
3289#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
3290#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
3291#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
3292#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
3293#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
3294#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
3295#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
3296#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
3297 u8 flags7;
3298#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
3299#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
3300#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
3301#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
3302#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
3303#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
3304#define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
3305#define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
3306#define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
3307#define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
3308 u8 flags8;
3309#define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3310#define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
3311#define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3312#define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
3313#define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
3314#define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
3315#define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
3316#define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
3317#define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
3318#define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
3319#define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
3320#define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
3321#define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
3322#define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
3323#define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
3324#define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
3325 u8 flags9;
3326#define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
3327#define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
3328#define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
3329#define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
3330#define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
3331#define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
3332#define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
3333#define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
3334#define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
3335#define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
3336#define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
3337#define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
3338#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
3339#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
3340#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
3341#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
3342 u8 flags10;
3343#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
3344#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
3345#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
3346#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
3347#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
3348#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
3349#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
3350#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
3351#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
3352#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
3353#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
3354#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
3355#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
3356#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
3357#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
3358#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
3359 u8 flags11;
3360#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
3361#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
3362#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
3363#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
3364#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
3365#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
3366#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3367#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
3368#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
3369#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
3370#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3371#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
3372#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
3373#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
3374#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
3375#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
3376 u8 flags12;
3377#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
3378#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
3379#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
3380#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
3381#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
3382#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
3383#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
3384#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
3385#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
3386#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
3387#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
3388#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
3389#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
3390#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
3391#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
3392#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
3393 u8 flags13;
3394#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
3395#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
3396#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
3397#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
3398#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
3399#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
3400#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
3401#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
3402#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
3403#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
3404#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
3405#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
3406#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
3407#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
3408#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
3409#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
3410 u8 flags14;
3411#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
3412#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
3413#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
3414#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
3415#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
3416#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
3417#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
3418#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
3419#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
3420#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
3421#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
3422#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
3423#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
3424#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
3425 u8 edpm_event_id;
3426 __le16 physical_q0;
3427 __le16 e5_reserved1;
3428 __le16 edpm_num_bds;
3429 __le16 tx_bd_cons;
3430 __le16 tx_bd_prod;
3431 __le16 updated_qm_pq_id;
3432 __le16 conn_dpi;
3433 u8 byte3;
3434 u8 byte4;
3435 u8 byte5;
3436 u8 byte6;
3437 __le32 reg0;
3438 __le32 reg1;
3439 __le32 reg2;
3440 __le32 reg3;
3441 __le32 reg4;
3442 __le32 reg5;
3443 __le32 reg6;
3444 __le16 word7;
3445 __le16 word8;
3446 __le16 word9;
3447 __le16 word10;
3448 __le32 reg7;
3449 __le32 reg8;
3450 __le32 reg9;
3451 u8 byte7;
3452 u8 byte8;
3453 u8 byte9;
3454 u8 byte10;
3455 u8 byte11;
3456 u8 byte12;
3457 u8 byte13;
3458 u8 byte14;
3459 u8 byte15;
3460 u8 e5_reserved;
3461 __le16 word11;
3462 __le32 reg10;
3463 __le32 reg11;
3464 __le32 reg12;
3465 __le32 reg13;
3466 __le32 reg14;
3467 __le32 reg15;
3468 __le32 reg16;
3469 __le32 reg17;
3470 __le32 reg18;
3471 __le32 reg19;
3472 __le16 word12;
3473 __le16 word13;
3474 __le16 word14;
3475 __le16 word15;
3476};
3477
3478/* The eth storm context for the Ystorm */
3479struct ystorm_eth_conn_st_ctx {
3480 __le32 reserved[8];
3481};
3482
3483struct ystorm_eth_conn_ag_ctx {
3484 u8 byte0;
3485 u8 state;
3486 u8 flags0;
3487#define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3488#define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
3489#define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3490#define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
3491#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
3492#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
3493#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
3494#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
3495#define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3496#define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
3497 u8 flags1;
3498#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
3499#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
3500#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
3501#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
3502#define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3503#define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
3504#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3505#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
3506#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3507#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
3508#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3509#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
3510#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3511#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
3512#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3513#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
3514 u8 tx_q0_int_coallecing_timeset;
3515 u8 byte3;
3516 __le16 word0;
3517 __le32 terminate_spqe;
3518 __le32 reg1;
3519 __le16 tx_bd_cons_upd;
3520 __le16 word2;
3521 __le16 word3;
3522 __le16 word4;
3523 __le32 reg2;
3524 __le32 reg3;
3525};
3526
3527struct tstorm_eth_conn_ag_ctx {
3528 u8 byte0;
3529 u8 byte1;
3530 u8 flags0;
3531#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3532#define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
3533#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3534#define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
3535#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
3536#define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
3537#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
3538#define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
3539#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
3540#define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
3541#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
3542#define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
3543#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3544#define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
3545 u8 flags1;
3546#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
3547#define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
3548#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3549#define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
3550#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3551#define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
3552#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
3553#define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
3554 u8 flags2;
3555#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
3556#define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
3557#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
3558#define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
3559#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
3560#define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
3561#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
3562#define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
3563 u8 flags3;
3564#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
3565#define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
3566#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
3567#define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
3568#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
3569#define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
3570#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
3571#define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
3572#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3573#define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
3574#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3575#define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
3576 u8 flags4;
3577#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
3578#define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
3579#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
3580#define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
3581#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
3582#define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
3583#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
3584#define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
3585#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
3586#define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
3587#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
3588#define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
3589#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
3590#define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
3591#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3592#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
3593 u8 flags5;
3594#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3595#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
3596#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3597#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
3598#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3599#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
3600#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3601#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
3602#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3603#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
3604#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
3605#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
3606#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3607#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
3608#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
3609#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
3610 __le32 reg0;
3611 __le32 reg1;
3612 __le32 reg2;
3613 __le32 reg3;
3614 __le32 reg4;
3615 __le32 reg5;
3616 __le32 reg6;
3617 __le32 reg7;
3618 __le32 reg8;
3619 u8 byte2;
3620 u8 byte3;
3621 __le16 rx_bd_cons;
3622 u8 byte4;
3623 u8 byte5;
3624 __le16 rx_bd_prod;
3625 __le16 word2;
3626 __le16 word3;
3627 __le32 reg9;
3628 __le32 reg10;
3629};
3630
3631struct ustorm_eth_conn_ag_ctx {
3632 u8 byte0;
3633 u8 byte1;
3634 u8 flags0;
3635#define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3636#define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
3637#define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3638#define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
3639#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
3640#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
3641#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
3642#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
3643#define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3644#define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
3645 u8 flags1;
3646#define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3647#define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
3648#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
3649#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
3650#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
3651#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
3652#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
3653#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
3654 u8 flags2;
3655#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
3656#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
3657#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
3658#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
3659#define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3660#define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
3661#define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3662#define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
3663#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
3664#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
3665#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
3666#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
3667#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
3668#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
3669#define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3670#define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
3671 u8 flags3;
3672#define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3673#define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
3674#define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3675#define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
3676#define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3677#define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
3678#define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3679#define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
3680#define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3681#define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
3682#define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
3683#define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
3684#define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3685#define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
3686#define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
3687#define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
3688 u8 byte2;
3689 u8 byte3;
3690 __le16 word0;
3691 __le16 tx_bd_cons;
3692 __le32 reg0;
3693 __le32 reg1;
3694 __le32 reg2;
3695 __le32 tx_int_coallecing_timeset;
3696 __le16 tx_drv_bd_cons;
3697 __le16 rx_drv_cqe_cons;
3698};
3699
3700/* The eth storm context for the Ustorm */
3701struct ustorm_eth_conn_st_ctx {
3702 __le32 reserved[40];
3703};
3704
3705/* The eth storm context for the Mstorm */
3706struct mstorm_eth_conn_st_ctx {
3707 __le32 reserved[8];
3708};
3709
3710/* eth connection context */
3711struct eth_conn_context {
3712 struct tstorm_eth_conn_st_ctx tstorm_st_context;
3713 struct regpair tstorm_st_padding[2];
3714 struct pstorm_eth_conn_st_ctx pstorm_st_context;
3715 struct xstorm_eth_conn_st_ctx xstorm_st_context;
3716 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
3717 struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
3718 struct ystorm_eth_conn_st_ctx ystorm_st_context;
3719 struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
3720 struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
3721 struct ustorm_eth_conn_st_ctx ustorm_st_context;
3722 struct mstorm_eth_conn_st_ctx mstorm_st_context;
3723};
3724
3725/* Ethernet filter types: mac/vlan/pair */
3726enum eth_error_code {
3727 ETH_OK = 0x00,
3728 ETH_FILTERS_MAC_ADD_FAIL_FULL,
3729 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
3730 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
3731 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
3732 ETH_FILTERS_MAC_DEL_FAIL_NOF,
3733 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
3734 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
3735 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
3736 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
3737 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
3738 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
3739 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
3740 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
3741 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
3742 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
3743 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
3744 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
3745 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
3746 ETH_FILTERS_VNI_ADD_FAIL_FULL,
3747 ETH_FILTERS_VNI_ADD_FAIL_DUP,
3748 ETH_FILTERS_GFT_UPDATE_FAIL,
3749 ETH_RX_QUEUE_FAIL_LOAD_VF_DATA,
3750 ETH_FILTERS_GFS_ADD_FILTER_FAIL_MAX_HOPS,
3751 ETH_FILTERS_GFS_ADD_FILTER_FAIL_NO_FREE_ENRTY,
3752 ETH_FILTERS_GFS_ADD_FILTER_FAIL_ALREADY_EXISTS,
3753 ETH_FILTERS_GFS_ADD_FILTER_FAIL_PCI_ERROR,
3754 ETH_FILTERS_GFS_ADD_FINLER_FAIL_MAGIC_NUM_ERROR,
3755 ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAX_HOPS,
3756 ETH_FILTERS_GFS_DEL_FILTER_FAIL_NO_MATCH_ENRTY,
3757 ETH_FILTERS_GFS_DEL_FILTER_FAIL_PCI_ERROR,
3758 ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAGIC_NUM_ERROR,
3759 MAX_ETH_ERROR_CODE
3760};
3761
3762/* Opcodes for the event ring */
3763enum eth_event_opcode {
3764 ETH_EVENT_UNUSED,
3765 ETH_EVENT_VPORT_START,
3766 ETH_EVENT_VPORT_UPDATE,
3767 ETH_EVENT_VPORT_STOP,
3768 ETH_EVENT_TX_QUEUE_START,
3769 ETH_EVENT_TX_QUEUE_STOP,
3770 ETH_EVENT_RX_QUEUE_START,
3771 ETH_EVENT_RX_QUEUE_UPDATE,
3772 ETH_EVENT_RX_QUEUE_STOP,
3773 ETH_EVENT_FILTERS_UPDATE,
3774 ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
3775 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
3776 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
3777 ETH_EVENT_RX_ADD_UDP_FILTER,
3778 ETH_EVENT_RX_DELETE_UDP_FILTER,
3779 ETH_EVENT_RX_CREATE_GFT_ACTION,
3780 ETH_EVENT_RX_GFT_UPDATE_FILTER,
3781 ETH_EVENT_TX_QUEUE_UPDATE,
3782 ETH_EVENT_RGFS_ADD_FILTER,
3783 ETH_EVENT_RGFS_DEL_FILTER,
3784 ETH_EVENT_TGFS_ADD_FILTER,
3785 ETH_EVENT_TGFS_DEL_FILTER,
3786 ETH_EVENT_GFS_COUNTERS_REPORT_REQUEST,
3787 MAX_ETH_EVENT_OPCODE
3788};
3789
3790/* Classify rule types in E2/E3 */
3791enum eth_filter_action {
3792 ETH_FILTER_ACTION_UNUSED,
3793 ETH_FILTER_ACTION_REMOVE,
3794 ETH_FILTER_ACTION_ADD,
3795 ETH_FILTER_ACTION_REMOVE_ALL,
3796 MAX_ETH_FILTER_ACTION
3797};
3798
3799/* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
3800struct eth_filter_cmd {
3801 u8 type;
3802 u8 vport_id;
3803 u8 action;
3804 u8 reserved0;
3805 __le32 vni;
3806 __le16 mac_lsb;
3807 __le16 mac_mid;
3808 __le16 mac_msb;
3809 __le16 vlan_id;
3810};
3811
3812/* $$KEEP_ENDIANNESS$$ */
3813struct eth_filter_cmd_header {
3814 u8 rx;
3815 u8 tx;
3816 u8 cmd_cnt;
3817 u8 assert_on_error;
3818 u8 reserved1[4];
3819};
3820
3821/* Ethernet filter types: mac/vlan/pair */
3822enum eth_filter_type {
3823 ETH_FILTER_TYPE_UNUSED,
3824 ETH_FILTER_TYPE_MAC,
3825 ETH_FILTER_TYPE_VLAN,
3826 ETH_FILTER_TYPE_PAIR,
3827 ETH_FILTER_TYPE_INNER_MAC,
3828 ETH_FILTER_TYPE_INNER_VLAN,
3829 ETH_FILTER_TYPE_INNER_PAIR,
3830 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
3831 ETH_FILTER_TYPE_MAC_VNI_PAIR,
3832 ETH_FILTER_TYPE_VNI,
3833 MAX_ETH_FILTER_TYPE
3834};
3835
3836/* inner to inner vlan priority translation configurations */
3837struct eth_in_to_in_pri_map_cfg {
3838 u8 inner_vlan_pri_remap_en;
3839 u8 reserved[7];
3840 u8 non_rdma_in_to_in_pri_map[8];
3841 u8 rdma_in_to_in_pri_map[8];
3842};
3843
3844/* Eth IPv4 Fragment Type */
3845enum eth_ipv4_frag_type {
3846 ETH_IPV4_NOT_FRAG,
3847 ETH_IPV4_FIRST_FRAG,
3848 ETH_IPV4_NON_FIRST_FRAG,
3849 MAX_ETH_IPV4_FRAG_TYPE
3850};
3851
3852/* eth IPv4 Fragment Type */
3853enum eth_ip_type {
3854 ETH_IPV4,
3855 ETH_IPV6,
3856 MAX_ETH_IP_TYPE
3857};
3858
3859/* Ethernet Ramrod Command IDs */
3860enum eth_ramrod_cmd_id {
3861 ETH_RAMROD_UNUSED,
3862 ETH_RAMROD_VPORT_START,
3863 ETH_RAMROD_VPORT_UPDATE,
3864 ETH_RAMROD_VPORT_STOP,
3865 ETH_RAMROD_RX_QUEUE_START,
3866 ETH_RAMROD_RX_QUEUE_STOP,
3867 ETH_RAMROD_TX_QUEUE_START,
3868 ETH_RAMROD_TX_QUEUE_STOP,
3869 ETH_RAMROD_FILTERS_UPDATE,
3870 ETH_RAMROD_RX_QUEUE_UPDATE,
3871 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
3872 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
3873 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
3874 ETH_RAMROD_RX_ADD_UDP_FILTER,
3875 ETH_RAMROD_RX_DELETE_UDP_FILTER,
3876 ETH_RAMROD_RX_CREATE_GFT_ACTION,
3877 ETH_RAMROD_RX_UPDATE_GFT_FILTER,
3878 ETH_RAMROD_TX_QUEUE_UPDATE,
3879 ETH_RAMROD_RGFS_FILTER_ADD,
3880 ETH_RAMROD_RGFS_FILTER_DEL,
3881 ETH_RAMROD_TGFS_FILTER_ADD,
3882 ETH_RAMROD_TGFS_FILTER_DEL,
3883 ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST,
3884 MAX_ETH_RAMROD_CMD_ID
3885};
3886
3887/* Return code from eth sp ramrods */
3888struct eth_return_code {
3889 u8 value;
3890#define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F
3891#define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
3892#define ETH_RETURN_CODE_RESERVED_MASK 0x1
3893#define ETH_RETURN_CODE_RESERVED_SHIFT 6
3894#define ETH_RETURN_CODE_RX_TX_MASK 0x1
3895#define ETH_RETURN_CODE_RX_TX_SHIFT 7
3896};
3897
3898/* tx destination enum */
3899enum eth_tx_dst_mode_config_enum {
3900 ETH_TX_DST_MODE_CONFIG_DISABLE,
3901 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD,
3902 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT,
3903 MAX_ETH_TX_DST_MODE_CONFIG_ENUM
3904};
3905
3906/* What to do in case an error occurs */
3907enum eth_tx_err {
3908 ETH_TX_ERR_DROP,
3909 ETH_TX_ERR_ASSERT_MALICIOUS,
3910 MAX_ETH_TX_ERR
3911};
3912
3913/* Array of the different error type behaviors */
3914struct eth_tx_err_vals {
3915 __le16 values;
3916#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
3917#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
3918#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
3919#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
3920#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
3921#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
3922#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
3923#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
3924#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
3925#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
3926#define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
3927#define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
3928#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
3929#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
3930#define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1
3931#define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_SHIFT 7
3932#define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF
3933#define ETH_TX_ERR_VALS_RESERVED_SHIFT 8
3934};
3935
3936/* vport rss configuration data */
3937struct eth_vport_rss_config {
3938 __le16 capabilities;
3939#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
3940#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
3941#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
3942#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
3943#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
3944#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
3945#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
3946#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
3947#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
3948#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
3949#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
3950#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
3951#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
3952#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
3953#define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
3954#define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
3955 u8 rss_id;
3956 u8 rss_mode;
3957 u8 update_rss_key;
3958 u8 update_rss_ind_table;
3959 u8 update_rss_capabilities;
3960 u8 tbl_size;
3961 u8 ind_table_mask_valid;
3962 u8 reserved2[3];
3963 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
3964 __le32 ind_table_mask[ETH_RSS_IND_TABLE_MASK_SIZE_REGS];
3965 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
3966 __le32 reserved3;
3967};
3968
3969/* eth vport RSS mode */
3970enum eth_vport_rss_mode {
3971 ETH_VPORT_RSS_MODE_DISABLED,
3972 ETH_VPORT_RSS_MODE_REGULAR,
3973 MAX_ETH_VPORT_RSS_MODE
3974};
3975
3976/* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
3977struct eth_vport_rx_mode {
3978 __le16 state;
3979#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
3980#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
3981#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
3982#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
3983#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
3984#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3985#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
3986#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
3987#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
3988#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
3989#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
3990#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
3991#define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1
3992#define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT 6
3993#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF
3994#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 7
3995};
3996
3997/* Command for setting tpa parameters */
3998struct eth_vport_tpa_param {
3999 u8 tpa_ipv4_en_flg;
4000 u8 tpa_ipv6_en_flg;
4001 u8 tpa_ipv4_tunn_en_flg;
4002 u8 tpa_ipv6_tunn_en_flg;
4003 u8 tpa_pkt_split_flg;
4004 u8 tpa_hdr_data_split_flg;
4005 u8 tpa_gro_consistent_flg;
4006
4007 u8 tpa_max_aggs_num;
4008
4009 __le16 tpa_max_size;
4010 __le16 tpa_min_size_to_start;
4011
4012 __le16 tpa_min_size_to_cont;
4013 u8 max_buff_num;
4014 u8 reserved;
4015};
4016
4017/* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
4018struct eth_vport_tx_mode {
4019 __le16 state;
4020#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
4021#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
4022#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4023#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
4024#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
4025#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
4026#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4027#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
4028#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4029#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
4030#define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
4031#define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
4032};
4033
4034/* GFT filter update action type */
4035enum gft_filter_update_action {
4036 GFT_ADD_FILTER,
4037 GFT_DELETE_FILTER,
4038 MAX_GFT_FILTER_UPDATE_ACTION
4039};
4040
4041/* Ramrod data for rx create gft action */
4042struct rx_create_gft_action_ramrod_data {
4043 u8 vport_id;
4044 u8 reserved[7];
4045};
4046
4047/* Ramrod data for rx create openflow action */
4048struct rx_create_openflow_action_ramrod_data {
4049 u8 vport_id;
4050 u8 reserved[7];
4051};
4052
4053/* Ramrod data for rx add openflow filter */
4054struct rx_openflow_filter_ramrod_data {
4055 __le16 action_icid;
4056 u8 priority;
4057 u8 reserved0;
4058 __le32 tenant_id;
4059 __le16 dst_mac_hi;
4060 __le16 dst_mac_mid;
4061 __le16 dst_mac_lo;
4062 __le16 src_mac_hi;
4063 __le16 src_mac_mid;
4064 __le16 src_mac_lo;
4065 __le16 vlan_id;
4066 __le16 l2_eth_type;
4067 u8 ipv4_dscp;
4068 u8 ipv4_frag_type;
4069 u8 ipv4_over_ip;
4070 u8 tenant_id_exists;
4071 __le32 ipv4_dst_addr;
4072 __le32 ipv4_src_addr;
4073 __le16 l4_dst_port;
4074 __le16 l4_src_port;
4075};
4076
4077/* Ramrod data for rx queue start ramrod */
4078struct rx_queue_start_ramrod_data {
4079 __le16 rx_queue_id;
4080 __le16 num_of_pbl_pages;
4081 __le16 bd_max_bytes;
4082 __le16 sb_id;
4083 u8 sb_index;
4084 u8 vport_id;
4085 u8 default_rss_queue_flg;
4086 u8 complete_cqe_flg;
4087 u8 complete_event_flg;
4088 u8 stats_counter_id;
4089 u8 pin_context;
4090 u8 pxp_tph_valid_bd;
4091 u8 pxp_tph_valid_pkt;
4092 u8 pxp_st_hint;
4093
4094 __le16 pxp_st_index;
4095 u8 pmd_mode;
4096
4097 u8 notify_en;
4098 u8 toggle_val;
4099
4100 u8 vf_rx_prod_index;
4101 u8 vf_rx_prod_use_zone_a;
4102 u8 reserved[5];
4103 __le16 reserved1;
4104 struct regpair cqe_pbl_addr;
4105 struct regpair bd_base;
4106 struct regpair reserved2;
4107};
4108
4109/* Ramrod data for rx queue stop ramrod */
4110struct rx_queue_stop_ramrod_data {
4111 __le16 rx_queue_id;
4112 u8 complete_cqe_flg;
4113 u8 complete_event_flg;
4114 u8 vport_id;
4115 u8 reserved[3];
4116};
4117
4118/* Ramrod data for rx queue update ramrod */
4119struct rx_queue_update_ramrod_data {
4120 __le16 rx_queue_id;
4121 u8 complete_cqe_flg;
4122 u8 complete_event_flg;
4123 u8 vport_id;
4124 u8 set_default_rss_queue;
4125 u8 reserved[3];
4126 u8 reserved1;
4127 u8 reserved2;
4128 u8 reserved3;
4129 __le16 reserved4;
4130 __le16 reserved5;
4131 struct regpair reserved6;
4132};
4133
4134/* Ramrod data for rx Add UDP Filter */
4135struct rx_udp_filter_ramrod_data {
4136 __le16 action_icid;
4137 __le16 vlan_id;
4138 u8 ip_type;
4139 u8 tenant_id_exists;
4140 __le16 reserved1;
4141 __le32 ip_dst_addr[4];
4142 __le32 ip_src_addr[4];
4143 __le16 udp_dst_port;
4144 __le16 udp_src_port;
4145 __le32 tenant_id;
4146};
4147
4148/* Add or delete GFT filter - filter is packet header of type of packet wished
4149 * to pass certain FW flow.
4150 */
4151struct rx_update_gft_filter_ramrod_data {
4152 struct regpair pkt_hdr_addr;
4153 __le16 pkt_hdr_length;
4154 __le16 action_icid;
4155 __le16 rx_qid;
4156 __le16 flow_id;
4157 __le16 vport_id;
4158 u8 action_icid_valid;
4159 u8 rx_qid_valid;
4160 u8 flow_id_valid;
4161 u8 filter_action;
4162 u8 assert_on_error;
4163 u8 inner_vlan_removal_en;
4164};
4165
4166/* Ramrod data for tx queue start ramrod */
4167struct tx_queue_start_ramrod_data {
4168 __le16 sb_id;
4169 u8 sb_index;
4170 u8 vport_id;
4171 u8 reserved0;
4172 u8 stats_counter_id;
4173 __le16 qm_pq_id;
4174 u8 flags;
4175#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
4176#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
4177#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
4178#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
4179#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
4180#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 2
4181#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
4182#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 3
4183#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
4184#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 4
4185#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7
4186#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 5
4187 u8 pxp_st_hint;
4188 u8 pxp_tph_valid_bd;
4189 u8 pxp_tph_valid_pkt;
4190 __le16 pxp_st_index;
4191 u8 comp_agg_size;
4192 u8 reserved3;
4193 __le16 queue_zone_id;
4194 __le16 reserved2;
4195 __le16 pbl_size;
4196 __le16 tx_queue_id;
4197 __le16 same_as_last_id;
4198 __le16 reserved[3];
4199 struct regpair pbl_base_addr;
4200 struct regpair bd_cons_address;
4201};
4202
4203/* Ramrod data for tx queue stop ramrod */
4204struct tx_queue_stop_ramrod_data {
4205 __le16 reserved[4];
4206};
4207
4208/* Ramrod data for tx queue update ramrod */
4209struct tx_queue_update_ramrod_data {
4210 __le16 update_qm_pq_id_flg;
4211 __le16 qm_pq_id;
4212 __le32 reserved0;
4213 struct regpair reserved1[5];
4214};
4215
4216/* Inner to Inner VLAN priority map update mode */
4217enum update_in_to_in_pri_map_mode_enum {
4218 ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED,
4219 ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL,
4220 ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL,
4221 MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM
4222};
4223
4224/* Ramrod data for vport update ramrod */
4225struct vport_filter_update_ramrod_data {
4226 struct eth_filter_cmd_header filter_cmd_hdr;
4227 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
4228};
4229
4230/* Ramrod data for vport start ramrod */
4231struct vport_start_ramrod_data {
4232 u8 vport_id;
4233 u8 sw_fid;
4234 __le16 mtu;
4235 u8 drop_ttl0_en;
4236 u8 inner_vlan_removal_en;
4237 struct eth_vport_rx_mode rx_mode;
4238 struct eth_vport_tx_mode tx_mode;
4239 struct eth_vport_tpa_param tpa_param;
4240 __le16 default_vlan;
4241 u8 tx_switching_en;
4242 u8 anti_spoofing_en;
4243 u8 default_vlan_en;
4244 u8 handle_ptp_pkts;
4245 u8 silent_vlan_removal_en;
4246 u8 untagged;
4247 struct eth_tx_err_vals tx_err_behav;
4248 u8 zero_placement_offset;
4249 u8 ctl_frame_mac_check_en;
4250 u8 ctl_frame_ethtype_check_en;
4251 u8 reserved0;
4252 u8 reserved1;
4253 u8 tx_dst_port_mode_config;
4254 u8 dst_vport_id;
4255 u8 tx_dst_port_mode;
4256 u8 dst_vport_id_valid;
4257 u8 wipe_inner_vlan_pri_en;
4258 u8 reserved2[2];
4259 struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg;
4260};
4261
4262/* Ramrod data for vport stop ramrod */
4263struct vport_stop_ramrod_data {
4264 u8 vport_id;
4265 u8 reserved[7];
4266};
4267
4268/* Ramrod data for vport update ramrod */
4269struct vport_update_ramrod_data_cmn {
4270 u8 vport_id;
4271 u8 update_rx_active_flg;
4272 u8 rx_active_flg;
4273 u8 update_tx_active_flg;
4274 u8 tx_active_flg;
4275 u8 update_rx_mode_flg;
4276 u8 update_tx_mode_flg;
4277 u8 update_approx_mcast_flg;
4278
4279 u8 update_rss_flg;
4280 u8 update_inner_vlan_removal_en_flg;
4281
4282 u8 inner_vlan_removal_en;
4283 u8 update_tpa_param_flg;
4284 u8 update_tpa_en_flg;
4285 u8 update_tx_switching_en_flg;
4286
4287 u8 tx_switching_en;
4288 u8 update_anti_spoofing_en_flg;
4289
4290 u8 anti_spoofing_en;
4291 u8 update_handle_ptp_pkts;
4292
4293 u8 handle_ptp_pkts;
4294 u8 update_default_vlan_en_flg;
4295
4296 u8 default_vlan_en;
4297
4298 u8 update_default_vlan_flg;
4299
4300 __le16 default_vlan;
4301 u8 update_accept_any_vlan_flg;
4302
4303 u8 accept_any_vlan;
4304 u8 silent_vlan_removal_en;
4305 u8 update_mtu_flg;
4306
4307 __le16 mtu;
4308 u8 update_ctl_frame_checks_en_flg;
4309 u8 ctl_frame_mac_check_en;
4310 u8 ctl_frame_ethtype_check_en;
4311 u8 update_in_to_in_pri_map_mode;
4312 u8 in_to_in_pri_map[8];
4313 u8 update_tx_dst_port_mode_flg;
4314 u8 tx_dst_port_mode_config;
4315 u8 dst_vport_id;
4316 u8 tx_dst_port_mode;
4317 u8 dst_vport_id_valid;
4318 u8 reserved[1];
4319};
4320
4321struct vport_update_ramrod_mcast {
4322 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
4323};
4324
4325/* Ramrod data for vport update ramrod */
4326struct vport_update_ramrod_data {
4327 struct vport_update_ramrod_data_cmn common;
4328
4329 struct eth_vport_rx_mode rx_mode;
4330 struct eth_vport_tx_mode tx_mode;
4331 __le32 reserved[3];
4332 struct eth_vport_tpa_param tpa_param;
4333 struct vport_update_ramrod_mcast approx_mcast;
4334 struct eth_vport_rss_config rss_config;
4335};
4336
4337struct xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
4338 u8 reserved0;
4339 u8 state;
4340 u8 flags0;
4341#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
4342#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
4343#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
4344#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
4345#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
4346#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
4347#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
4348#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
4349#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
4350#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
4351#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
4352#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
4353#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
4354#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
4355#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
4356#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
4357 u8 flags1;
4358#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
4359#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
4360#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
4361#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
4362#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
4363#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
4364#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
4365#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
4366#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1
4367#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4
4368#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1
4369#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5
4370#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
4371#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
4372#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
4373#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
4374 u8 flags2;
4375#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
4376#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
4377#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
4378#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
4379#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
4380#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
4381#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
4382#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
4383 u8 flags3;
4384#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
4385#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
4386#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
4387#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
4388#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
4389#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
4390#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
4391#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
4392 u8 flags4;
4393#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
4394#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
4395#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
4396#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
4397#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
4398#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
4399#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
4400#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
4401 u8 flags5;
4402#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
4403#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
4404#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
4405#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
4406#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
4407#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
4408#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
4409#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
4410 u8 flags6;
4411#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
4412#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
4413#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
4414#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
4415#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
4416#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
4417#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
4418#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
4419 u8 flags7;
4420#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
4421#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
4422#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
4423#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
4424#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
4425#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
4426#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
4427#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
4428#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
4429#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
4430 u8 flags8;
4431#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
4432#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
4433#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
4434#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
4435#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
4436#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
4437#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
4438#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
4439#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
4440#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
4441#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
4442#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
4443#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
4444#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
4445#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
4446#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
4447 u8 flags9;
4448#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
4449#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
4450#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
4451#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
4452#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
4453#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
4454#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
4455#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
4456#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
4457#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
4458#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
4459#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
4460#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
4461#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
4462#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
4463#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
4464 u8 flags10;
4465#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
4466#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
4467#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
4468#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
4469#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
4470#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
4471#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
4472#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
4473#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
4474#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
4475#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
4476#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
4477#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
4478#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
4479#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
4480#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
4481 u8 flags11;
4482#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
4483#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
4484#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
4485#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
4486#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
4487#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
4488#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
4489#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
4490#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
4491#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
4492#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
4493#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
4494#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
4495#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
4496#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
4497#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
4498 u8 flags12;
4499#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
4500#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
4501#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
4502#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
4503#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
4504#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
4505#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
4506#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
4507#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
4508#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
4509#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
4510#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
4511#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
4512#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
4513#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
4514#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
4515 u8 flags13;
4516#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
4517#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
4518#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
4519#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
4520#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
4521#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
4522#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
4523#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
4524#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
4525#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
4526#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
4527#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
4528#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
4529#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
4530#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
4531#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
4532 u8 flags14;
4533#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
4534#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
4535#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
4536#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
4537#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
4538#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
4539#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4540#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
4541#define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
4542#define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
4543#define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
4544#define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
4545#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
4546#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
4547 u8 edpm_event_id;
4548 __le16 physical_q0;
4549 __le16 e5_reserved1;
4550 __le16 edpm_num_bds;
4551 __le16 tx_bd_cons;
4552 __le16 tx_bd_prod;
4553 __le16 updated_qm_pq_id;
4554 __le16 conn_dpi;
4555 u8 byte3;
4556 u8 byte4;
4557 u8 byte5;
4558 u8 byte6;
4559 __le32 reg0;
4560 __le32 reg1;
4561 __le32 reg2;
4562 __le32 reg3;
4563 __le32 reg4;
4564};
4565
4566struct mstorm_eth_conn_ag_ctx {
4567 u8 byte0;
4568 u8 byte1;
4569 u8 flags0;
4570#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4571#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4572#define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4573#define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4574#define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4575#define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
4576#define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4577#define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
4578#define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4579#define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
4580 u8 flags1;
4581#define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4582#define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
4583#define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4584#define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
4585#define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4586#define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
4587#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4588#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
4589#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4590#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
4591#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4592#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
4593#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4594#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
4595#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4596#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
4597 __le16 word0;
4598 __le16 word1;
4599 __le32 reg0;
4600 __le32 reg1;
4601};
4602
4603struct xstorm_eth_hw_conn_ag_ctx {
4604 u8 reserved0;
4605 u8 state;
4606 u8 flags0;
4607#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4608#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4609#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
4610#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
4611#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
4612#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
4613#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
4614#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
4615#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
4616#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
4617#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
4618#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
4619#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
4620#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
4621#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
4622#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
4623 u8 flags1;
4624#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
4625#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
4626#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
4627#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
4628#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
4629#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
4630#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
4631#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
4632#define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
4633#define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
4634#define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
4635#define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
4636#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
4637#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
4638#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
4639#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
4640 u8 flags2;
4641#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
4642#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
4643#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
4644#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
4645#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
4646#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
4647#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
4648#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
4649 u8 flags3;
4650#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
4651#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
4652#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
4653#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
4654#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
4655#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
4656#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
4657#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
4658 u8 flags4;
4659#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
4660#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
4661#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
4662#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
4663#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
4664#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
4665#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
4666#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
4667 u8 flags5;
4668#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
4669#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
4670#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
4671#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
4672#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
4673#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
4674#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
4675#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
4676 u8 flags6;
4677#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4678#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
4679#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4680#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
4681#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
4682#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
4683#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4684#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
4685 u8 flags7;
4686#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4687#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
4688#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
4689#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
4690#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4691#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
4692#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
4693#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
4694#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
4695#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
4696 u8 flags8;
4697#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
4698#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
4699#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
4700#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
4701#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
4702#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
4703#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
4704#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
4705#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
4706#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
4707#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
4708#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
4709#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
4710#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
4711#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
4712#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
4713 u8 flags9;
4714#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
4715#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
4716#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
4717#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
4718#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
4719#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
4720#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
4721#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
4722#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
4723#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
4724#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
4725#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
4726#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4727#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
4728#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4729#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
4730 u8 flags10;
4731#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4732#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4733#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4734#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
4735#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4736#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
4737#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
4738#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
4739#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4740#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
4741#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4742#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
4743#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
4744#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
4745#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
4746#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
4747 u8 flags11;
4748#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
4749#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
4750#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
4751#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
4752#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
4753#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
4754#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
4755#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
4756#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
4757#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
4758#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
4759#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
4760#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
4761#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
4762#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
4763#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
4764 u8 flags12;
4765#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
4766#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
4767#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
4768#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
4769#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
4770#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
4771#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
4772#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
4773#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
4774#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
4775#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
4776#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
4777#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
4778#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
4779#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
4780#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
4781 u8 flags13;
4782#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
4783#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
4784#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
4785#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
4786#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
4787#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
4788#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
4789#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
4790#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
4791#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
4792#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
4793#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
4794#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
4795#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
4796#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
4797#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
4798 u8 flags14;
4799#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
4800#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
4801#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
4802#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
4803#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
4804#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
4805#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4806#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
4807#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
4808#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
4809#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
4810#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
4811#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4812#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
4813 u8 edpm_event_id;
4814 __le16 physical_q0;
4815 __le16 e5_reserved1;
4816 __le16 edpm_num_bds;
4817 __le16 tx_bd_cons;
4818 __le16 tx_bd_prod;
4819 __le16 updated_qm_pq_id;
4820 __le16 conn_dpi;
4821};
4822
4823/* GFT CAM line struct with fields breakout */
4824struct gft_cam_line_mapped {
4825 __le32 camline;
4826#define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
4827#define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
4828#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
4829#define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
4830#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
4831#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
4832#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
4833#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
4834#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
4835#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
4836#define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
4837#define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
4838#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
4839#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
4840#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
4841#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
4842#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
4843#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
4844#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
4845#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
4846#define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
4847#define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
4848#define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
4849#define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
4850};
4851
4852/* Used in gft_profile_key: Indication for ip version */
4853enum gft_profile_ip_version {
4854 GFT_PROFILE_IPV4 = 0,
4855 GFT_PROFILE_IPV6 = 1,
4856 MAX_GFT_PROFILE_IP_VERSION
4857};
4858
4859/* Profile key stucr fot GFT logic in Prs */
4860struct gft_profile_key {
4861 __le16 profile_key;
4862#define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
4863#define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
4864#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
4865#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
4866#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
4867#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
4868#define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
4869#define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
4870#define GFT_PROFILE_KEY_PF_ID_MASK 0xF
4871#define GFT_PROFILE_KEY_PF_ID_SHIFT 10
4872#define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
4873#define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
4874};
4875
4876/* Used in gft_profile_key: Indication for tunnel type */
4877enum gft_profile_tunnel_type {
4878 GFT_PROFILE_NO_TUNNEL = 0,
4879 GFT_PROFILE_VXLAN_TUNNEL = 1,
4880 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
4881 GFT_PROFILE_GRE_IP_TUNNEL = 3,
4882 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
4883 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
4884 MAX_GFT_PROFILE_TUNNEL_TYPE
4885};
4886
4887/* Used in gft_profile_key: Indication for protocol type */
4888enum gft_profile_upper_protocol_type {
4889 GFT_PROFILE_ROCE_PROTOCOL = 0,
4890 GFT_PROFILE_RROCE_PROTOCOL = 1,
4891 GFT_PROFILE_FCOE_PROTOCOL = 2,
4892 GFT_PROFILE_ICMP_PROTOCOL = 3,
4893 GFT_PROFILE_ARP_PROTOCOL = 4,
4894 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
4895 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
4896 GFT_PROFILE_TCP_PROTOCOL = 7,
4897 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
4898 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
4899 GFT_PROFILE_UDP_PROTOCOL = 10,
4900 GFT_PROFILE_USER_IP_1_INNER = 11,
4901 GFT_PROFILE_USER_IP_2_OUTER = 12,
4902 GFT_PROFILE_USER_ETH_1_INNER = 13,
4903 GFT_PROFILE_USER_ETH_2_OUTER = 14,
4904 GFT_PROFILE_RAW = 15,
4905 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
4906};
4907
4908/* GFT RAM line struct */
4909struct gft_ram_line {
4910 __le32 lo;
4911#define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
4912#define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
4913#define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
4914#define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
4915#define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
4916#define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
4917#define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
4918#define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
4919#define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
4920#define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
4921#define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
4922#define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
4923#define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
4924#define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
4925#define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
4926#define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
4927#define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
4928#define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
4929#define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
4930#define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
4931#define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
4932#define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
4933#define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
4934#define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
4935#define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
4936#define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
4937#define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
4938#define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
4939#define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
4940#define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
4941#define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
4942#define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
4943#define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
4944#define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
4945#define GFT_RAM_LINE_TTL_MASK 0x1
4946#define GFT_RAM_LINE_TTL_SHIFT 18
4947#define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
4948#define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
4949#define GFT_RAM_LINE_RESERVED0_MASK 0x1
4950#define GFT_RAM_LINE_RESERVED0_SHIFT 20
4951#define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
4952#define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
4953#define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
4954#define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
4955#define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
4956#define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
4957#define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
4958#define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
4959#define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
4960#define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
4961#define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
4962#define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
4963#define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
4964#define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
4965#define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
4966#define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
4967#define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
4968#define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
4969#define GFT_RAM_LINE_DST_PORT_MASK 0x1
4970#define GFT_RAM_LINE_DST_PORT_SHIFT 30
4971#define GFT_RAM_LINE_SRC_PORT_MASK 0x1
4972#define GFT_RAM_LINE_SRC_PORT_SHIFT 31
4973 __le32 hi;
4974#define GFT_RAM_LINE_DSCP_MASK 0x1
4975#define GFT_RAM_LINE_DSCP_SHIFT 0
4976#define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
4977#define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
4978#define GFT_RAM_LINE_DST_IP_MASK 0x1
4979#define GFT_RAM_LINE_DST_IP_SHIFT 2
4980#define GFT_RAM_LINE_SRC_IP_MASK 0x1
4981#define GFT_RAM_LINE_SRC_IP_SHIFT 3
4982#define GFT_RAM_LINE_PRIORITY_MASK 0x1
4983#define GFT_RAM_LINE_PRIORITY_SHIFT 4
4984#define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
4985#define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
4986#define GFT_RAM_LINE_VLAN_MASK 0x1
4987#define GFT_RAM_LINE_VLAN_SHIFT 6
4988#define GFT_RAM_LINE_DST_MAC_MASK 0x1
4989#define GFT_RAM_LINE_DST_MAC_SHIFT 7
4990#define GFT_RAM_LINE_SRC_MAC_MASK 0x1
4991#define GFT_RAM_LINE_SRC_MAC_SHIFT 8
4992#define GFT_RAM_LINE_TENANT_ID_MASK 0x1
4993#define GFT_RAM_LINE_TENANT_ID_SHIFT 9
4994#define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
4995#define GFT_RAM_LINE_RESERVED1_SHIFT 10
4996};
4997
4998/* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
4999enum gft_vlan_select {
5000 INNER_PROVIDER_VLAN = 0,
5001 INNER_VLAN = 1,
5002 OUTER_PROVIDER_VLAN = 2,
5003 OUTER_VLAN = 3,
5004 MAX_GFT_VLAN_SELECT
5005};
5006
5007/* The rdma task context of Mstorm */
5008struct ystorm_rdma_task_st_ctx {
5009 struct regpair temp[4];
5010};
5011
5012struct ystorm_rdma_task_ag_ctx {
5013 u8 reserved;
5014 u8 byte1;
5015 __le16 msem_ctx_upd_seq;
5016 u8 flags0;
5017#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5018#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5019#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5020#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
5021#define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5022#define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
5023#define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
5024#define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
5025#define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
5026#define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7
5027 u8 flags1;
5028#define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5029#define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5030#define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5031#define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
5032#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
5033#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
5034#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5035#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
5036#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5037#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
5038 u8 flags2;
5039#define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
5040#define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
5041#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5042#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
5043#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5044#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
5045#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5046#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
5047#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5048#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
5049#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5050#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
5051#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5052#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
5053#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5054#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
5055 u8 key;
5056 __le32 mw_cnt_or_qp_id;
5057 u8 ref_cnt_seq;
5058 u8 ctx_upd_seq;
5059 __le16 dif_flags;
5060 __le16 tx_ref_count;
5061 __le16 last_used_ltid;
5062 __le16 parent_mr_lo;
5063 __le16 parent_mr_hi;
5064 __le32 fbo_lo;
5065 __le32 fbo_hi;
5066};
5067
5068struct mstorm_rdma_task_ag_ctx {
5069 u8 reserved;
5070 u8 byte1;
5071 __le16 icid;
5072 u8 flags0;
5073#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5074#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5075#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5076#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
5077#define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5078#define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
5079#define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
5080#define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
5081#define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
5082#define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7
5083 u8 flags1;
5084#define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5085#define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5086#define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5087#define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
5088#define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
5089#define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
5090#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5091#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
5092#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5093#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
5094 u8 flags2;
5095#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
5096#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
5097#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5098#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
5099#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5100#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
5101#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5102#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
5103#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5104#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
5105#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5106#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
5107#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5108#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
5109#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5110#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
5111 u8 key;
5112 __le32 mw_cnt_or_qp_id;
5113 u8 ref_cnt_seq;
5114 u8 ctx_upd_seq;
5115 __le16 dif_flags;
5116 __le16 tx_ref_count;
5117 __le16 last_used_ltid;
5118 __le16 parent_mr_lo;
5119 __le16 parent_mr_hi;
5120 __le32 fbo_lo;
5121 __le32 fbo_hi;
5122};
5123
5124/* The roce task context of Mstorm */
5125struct mstorm_rdma_task_st_ctx {
5126 struct regpair temp[4];
5127};
5128
5129/* The roce task context of Ustorm */
5130struct ustorm_rdma_task_st_ctx {
5131 struct regpair temp[6];
5132};
5133
5134struct ustorm_rdma_task_ag_ctx {
5135 u8 reserved;
5136 u8 state;
5137 __le16 icid;
5138 u8 flags0;
5139#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5140#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5141#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5142#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
5143#define USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5144#define USTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
5145#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
5146#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
5147 u8 flags1;
5148#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
5149#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
5150#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
5151#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
5152#define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3
5153#define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT 4
5154#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
5155#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
5156 u8 flags2;
5157#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
5158#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
5159#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
5160#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
5161#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
5162#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
5163#define USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1
5164#define USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT 3
5165#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
5166#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
5167#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5168#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
5169#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5170#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
5171#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5172#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
5173 u8 flags3;
5174#define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1
5175#define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0
5176#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5177#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
5178#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1
5179#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_SHIFT 2
5180#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5181#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
5182#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
5183#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
5184 __le32 dif_err_intervals;
5185 __le32 dif_error_1st_interval;
5186 __le32 dif_rxmit_cons;
5187 __le32 dif_rxmit_prod;
5188 __le32 sge_index;
5189 __le32 sq_cons;
5190 u8 byte2;
5191 u8 byte3;
5192 __le16 dif_write_cons;
5193 __le16 dif_write_prod;
5194 __le16 word3;
5195 __le32 dif_error_buffer_address_lo;
5196 __le32 dif_error_buffer_address_hi;
5197};
5198
5199/* RDMA task context */
5200struct rdma_task_context {
5201 struct ystorm_rdma_task_st_ctx ystorm_st_context;
5202 struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
5203 struct tdif_task_context tdif_context;
5204 struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
5205 struct mstorm_rdma_task_st_ctx mstorm_st_context;
5206 struct rdif_task_context rdif_context;
5207 struct ustorm_rdma_task_st_ctx ustorm_st_context;
5208 struct regpair ustorm_st_padding[2];
5209 struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
5210};
5211
5212#define TOE_MAX_RAMROD_PER_PF 8
5213#define TOE_TX_PAGE_SIZE_BYTES 4096
5214#define TOE_GRQ_PAGE_SIZE_BYTES 4096
5215#define TOE_RX_CQ_PAGE_SIZE_BYTES 4096
5216
5217#define TOE_RX_MAX_RSS_CHAINS 64
5218#define TOE_TX_MAX_TSS_CHAINS 64
5219#define TOE_RSS_INDIRECTION_TABLE_SIZE 128
5220
5221/* The toe storm context of Mstorm */
5222struct mstorm_toe_conn_st_ctx {
5223 __le32 reserved[24];
5224};
5225
5226/* The toe storm context of Pstorm */
5227struct pstorm_toe_conn_st_ctx {
5228 __le32 reserved[36];
5229};
5230
5231/* The toe storm context of Ystorm */
5232struct ystorm_toe_conn_st_ctx {
5233 __le32 reserved[8];
5234};
5235
5236/* The toe storm context of Xstorm */
5237struct xstorm_toe_conn_st_ctx {
5238 __le32 reserved[44];
5239};
5240
5241struct ystorm_toe_conn_ag_ctx {
5242 u8 byte0;
5243 u8 byte1;
5244 u8 flags0;
5245#define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5246#define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5247#define YSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5248#define YSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT 1
5249#define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3
5250#define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT 2
5251#define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_MASK 0x3
5252#define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_SHIFT 4
5253#define YSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5254#define YSTORM_TOE_CONN_AG_CTX_CF2_SHIFT 6
5255 u8 flags1;
5256#define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1
5257#define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT 0
5258#define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK 0x1
5259#define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_SHIFT 1
5260#define YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5261#define YSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT 2
5262#define YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK 0x1
5263#define YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_SHIFT 3
5264#define YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5265#define YSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 4
5266#define YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5267#define YSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT 5
5268#define YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5269#define YSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 6
5270#define YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK 0x1
5271#define YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_SHIFT 7
5272 u8 completion_opcode;
5273 u8 byte3;
5274 __le16 word0;
5275 __le32 rel_seq;
5276 __le32 rel_seq_threshold;
5277 __le16 app_prod;
5278 __le16 app_cons;
5279 __le16 word3;
5280 __le16 word4;
5281 __le32 reg2;
5282 __le32 reg3;
5283};
5284
5285struct xstorm_toe_conn_ag_ctx {
5286 u8 reserved0;
5287 u8 state;
5288 u8 flags0;
5289#define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5290#define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5291#define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
5292#define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
5293#define XSTORM_TOE_CONN_AG_CTX_RESERVED1_MASK 0x1
5294#define XSTORM_TOE_CONN_AG_CTX_RESERVED1_SHIFT 2
5295#define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5296#define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
5297#define XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_MASK 0x1
5298#define XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_SHIFT 4
5299#define XSTORM_TOE_CONN_AG_CTX_RESERVED2_MASK 0x1
5300#define XSTORM_TOE_CONN_AG_CTX_RESERVED2_SHIFT 5
5301#define XSTORM_TOE_CONN_AG_CTX_BIT6_MASK 0x1
5302#define XSTORM_TOE_CONN_AG_CTX_BIT6_SHIFT 6
5303#define XSTORM_TOE_CONN_AG_CTX_BIT7_MASK 0x1
5304#define XSTORM_TOE_CONN_AG_CTX_BIT7_SHIFT 7
5305 u8 flags1;
5306#define XSTORM_TOE_CONN_AG_CTX_BIT8_MASK 0x1
5307#define XSTORM_TOE_CONN_AG_CTX_BIT8_SHIFT 0
5308#define XSTORM_TOE_CONN_AG_CTX_BIT9_MASK 0x1
5309#define XSTORM_TOE_CONN_AG_CTX_BIT9_SHIFT 1
5310#define XSTORM_TOE_CONN_AG_CTX_BIT10_MASK 0x1
5311#define XSTORM_TOE_CONN_AG_CTX_BIT10_SHIFT 2
5312#define XSTORM_TOE_CONN_AG_CTX_BIT11_MASK 0x1
5313#define XSTORM_TOE_CONN_AG_CTX_BIT11_SHIFT 3
5314#define XSTORM_TOE_CONN_AG_CTX_BIT12_MASK 0x1
5315#define XSTORM_TOE_CONN_AG_CTX_BIT12_SHIFT 4
5316#define XSTORM_TOE_CONN_AG_CTX_BIT13_MASK 0x1
5317#define XSTORM_TOE_CONN_AG_CTX_BIT13_SHIFT 5
5318#define XSTORM_TOE_CONN_AG_CTX_BIT14_MASK 0x1
5319#define XSTORM_TOE_CONN_AG_CTX_BIT14_SHIFT 6
5320#define XSTORM_TOE_CONN_AG_CTX_BIT15_MASK 0x1
5321#define XSTORM_TOE_CONN_AG_CTX_BIT15_SHIFT 7
5322 u8 flags2;
5323#define XSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
5324#define XSTORM_TOE_CONN_AG_CTX_CF0_SHIFT 0
5325#define XSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5326#define XSTORM_TOE_CONN_AG_CTX_CF1_SHIFT 2
5327#define XSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5328#define XSTORM_TOE_CONN_AG_CTX_CF2_SHIFT 4
5329#define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5330#define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
5331 u8 flags3;
5332#define XSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3
5333#define XSTORM_TOE_CONN_AG_CTX_CF4_SHIFT 0
5334#define XSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3
5335#define XSTORM_TOE_CONN_AG_CTX_CF5_SHIFT 2
5336#define XSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5337#define XSTORM_TOE_CONN_AG_CTX_CF6_SHIFT 4
5338#define XSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3
5339#define XSTORM_TOE_CONN_AG_CTX_CF7_SHIFT 6
5340 u8 flags4;
5341#define XSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3
5342#define XSTORM_TOE_CONN_AG_CTX_CF8_SHIFT 0
5343#define XSTORM_TOE_CONN_AG_CTX_CF9_MASK 0x3
5344#define XSTORM_TOE_CONN_AG_CTX_CF9_SHIFT 2
5345#define XSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3
5346#define XSTORM_TOE_CONN_AG_CTX_CF10_SHIFT 4
5347#define XSTORM_TOE_CONN_AG_CTX_CF11_MASK 0x3
5348#define XSTORM_TOE_CONN_AG_CTX_CF11_SHIFT 6
5349 u8 flags5;
5350#define XSTORM_TOE_CONN_AG_CTX_CF12_MASK 0x3
5351#define XSTORM_TOE_CONN_AG_CTX_CF12_SHIFT 0
5352#define XSTORM_TOE_CONN_AG_CTX_CF13_MASK 0x3
5353#define XSTORM_TOE_CONN_AG_CTX_CF13_SHIFT 2
5354#define XSTORM_TOE_CONN_AG_CTX_CF14_MASK 0x3
5355#define XSTORM_TOE_CONN_AG_CTX_CF14_SHIFT 4
5356#define XSTORM_TOE_CONN_AG_CTX_CF15_MASK 0x3
5357#define XSTORM_TOE_CONN_AG_CTX_CF15_SHIFT 6
5358 u8 flags6;
5359#define XSTORM_TOE_CONN_AG_CTX_CF16_MASK 0x3
5360#define XSTORM_TOE_CONN_AG_CTX_CF16_SHIFT 0
5361#define XSTORM_TOE_CONN_AG_CTX_CF17_MASK 0x3
5362#define XSTORM_TOE_CONN_AG_CTX_CF17_SHIFT 2
5363#define XSTORM_TOE_CONN_AG_CTX_CF18_MASK 0x3
5364#define XSTORM_TOE_CONN_AG_CTX_CF18_SHIFT 4
5365#define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
5366#define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
5367 u8 flags7;
5368#define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5369#define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5370#define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
5371#define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
5372#define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5373#define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
5374#define XSTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
5375#define XSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT 6
5376#define XSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5377#define XSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT 7
5378 u8 flags8;
5379#define XSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5380#define XSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT 0
5381#define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5382#define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
5383#define XSTORM_TOE_CONN_AG_CTX_CF4EN_MASK 0x1
5384#define XSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT 2
5385#define XSTORM_TOE_CONN_AG_CTX_CF5EN_MASK 0x1
5386#define XSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT 3
5387#define XSTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5388#define XSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT 4
5389#define XSTORM_TOE_CONN_AG_CTX_CF7EN_MASK 0x1
5390#define XSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT 5
5391#define XSTORM_TOE_CONN_AG_CTX_CF8EN_MASK 0x1
5392#define XSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT 6
5393#define XSTORM_TOE_CONN_AG_CTX_CF9EN_MASK 0x1
5394#define XSTORM_TOE_CONN_AG_CTX_CF9EN_SHIFT 7
5395 u8 flags9;
5396#define XSTORM_TOE_CONN_AG_CTX_CF10EN_MASK 0x1
5397#define XSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT 0
5398#define XSTORM_TOE_CONN_AG_CTX_CF11EN_MASK 0x1
5399#define XSTORM_TOE_CONN_AG_CTX_CF11EN_SHIFT 1
5400#define XSTORM_TOE_CONN_AG_CTX_CF12EN_MASK 0x1
5401#define XSTORM_TOE_CONN_AG_CTX_CF12EN_SHIFT 2
5402#define XSTORM_TOE_CONN_AG_CTX_CF13EN_MASK 0x1
5403#define XSTORM_TOE_CONN_AG_CTX_CF13EN_SHIFT 3
5404#define XSTORM_TOE_CONN_AG_CTX_CF14EN_MASK 0x1
5405#define XSTORM_TOE_CONN_AG_CTX_CF14EN_SHIFT 4
5406#define XSTORM_TOE_CONN_AG_CTX_CF15EN_MASK 0x1
5407#define XSTORM_TOE_CONN_AG_CTX_CF15EN_SHIFT 5
5408#define XSTORM_TOE_CONN_AG_CTX_CF16EN_MASK 0x1
5409#define XSTORM_TOE_CONN_AG_CTX_CF16EN_SHIFT 6
5410#define XSTORM_TOE_CONN_AG_CTX_CF17EN_MASK 0x1
5411#define XSTORM_TOE_CONN_AG_CTX_CF17EN_SHIFT 7
5412 u8 flags10;
5413#define XSTORM_TOE_CONN_AG_CTX_CF18EN_MASK 0x1
5414#define XSTORM_TOE_CONN_AG_CTX_CF18EN_SHIFT 0
5415#define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
5416#define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
5417#define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5418#define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
5419#define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
5420#define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
5421#define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
5422#define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
5423#define XSTORM_TOE_CONN_AG_CTX_CF23EN_MASK 0x1
5424#define XSTORM_TOE_CONN_AG_CTX_CF23EN_SHIFT 5
5425#define XSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5426#define XSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT 6
5427#define XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
5428#define XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
5429 u8 flags11;
5430#define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
5431#define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
5432#define XSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5433#define XSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 1
5434#define XSTORM_TOE_CONN_AG_CTX_RESERVED3_MASK 0x1
5435#define XSTORM_TOE_CONN_AG_CTX_RESERVED3_SHIFT 2
5436#define XSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5437#define XSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT 3
5438#define XSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5439#define XSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT 4
5440#define XSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5441#define XSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT 5
5442#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5443#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
5444#define XSTORM_TOE_CONN_AG_CTX_RULE9EN_MASK 0x1
5445#define XSTORM_TOE_CONN_AG_CTX_RULE9EN_SHIFT 7
5446 u8 flags12;
5447#define XSTORM_TOE_CONN_AG_CTX_RULE10EN_MASK 0x1
5448#define XSTORM_TOE_CONN_AG_CTX_RULE10EN_SHIFT 0
5449#define XSTORM_TOE_CONN_AG_CTX_RULE11EN_MASK 0x1
5450#define XSTORM_TOE_CONN_AG_CTX_RULE11EN_SHIFT 1
5451#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5452#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
5453#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5454#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
5455#define XSTORM_TOE_CONN_AG_CTX_RULE14EN_MASK 0x1
5456#define XSTORM_TOE_CONN_AG_CTX_RULE14EN_SHIFT 4
5457#define XSTORM_TOE_CONN_AG_CTX_RULE15EN_MASK 0x1
5458#define XSTORM_TOE_CONN_AG_CTX_RULE15EN_SHIFT 5
5459#define XSTORM_TOE_CONN_AG_CTX_RULE16EN_MASK 0x1
5460#define XSTORM_TOE_CONN_AG_CTX_RULE16EN_SHIFT 6
5461#define XSTORM_TOE_CONN_AG_CTX_RULE17EN_MASK 0x1
5462#define XSTORM_TOE_CONN_AG_CTX_RULE17EN_SHIFT 7
5463 u8 flags13;
5464#define XSTORM_TOE_CONN_AG_CTX_RULE18EN_MASK 0x1
5465#define XSTORM_TOE_CONN_AG_CTX_RULE18EN_SHIFT 0
5466#define XSTORM_TOE_CONN_AG_CTX_RULE19EN_MASK 0x1
5467#define XSTORM_TOE_CONN_AG_CTX_RULE19EN_SHIFT 1
5468#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5469#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
5470#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5471#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
5472#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5473#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
5474#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5475#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
5476#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5477#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
5478#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5479#define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
5480 u8 flags14;
5481#define XSTORM_TOE_CONN_AG_CTX_BIT16_MASK 0x1
5482#define XSTORM_TOE_CONN_AG_CTX_BIT16_SHIFT 0
5483#define XSTORM_TOE_CONN_AG_CTX_BIT17_MASK 0x1
5484#define XSTORM_TOE_CONN_AG_CTX_BIT17_SHIFT 1
5485#define XSTORM_TOE_CONN_AG_CTX_BIT18_MASK 0x1
5486#define XSTORM_TOE_CONN_AG_CTX_BIT18_SHIFT 2
5487#define XSTORM_TOE_CONN_AG_CTX_BIT19_MASK 0x1
5488#define XSTORM_TOE_CONN_AG_CTX_BIT19_SHIFT 3
5489#define XSTORM_TOE_CONN_AG_CTX_BIT20_MASK 0x1
5490#define XSTORM_TOE_CONN_AG_CTX_BIT20_SHIFT 4
5491#define XSTORM_TOE_CONN_AG_CTX_BIT21_MASK 0x1
5492#define XSTORM_TOE_CONN_AG_CTX_BIT21_SHIFT 5
5493#define XSTORM_TOE_CONN_AG_CTX_CF23_MASK 0x3
5494#define XSTORM_TOE_CONN_AG_CTX_CF23_SHIFT 6
5495 u8 byte2;
5496 __le16 physical_q0;
5497 __le16 physical_q1;
5498 __le16 word2;
5499 __le16 word3;
5500 __le16 bd_prod;
5501 __le16 word5;
5502 __le16 word6;
5503 u8 byte3;
5504 u8 byte4;
5505 u8 byte5;
5506 u8 byte6;
5507 __le32 reg0;
5508 __le32 reg1;
5509 __le32 reg2;
5510 __le32 more_to_send_seq;
5511 __le32 local_adv_wnd_seq;
5512 __le32 reg5;
5513 __le32 reg6;
5514 __le16 word7;
5515 __le16 word8;
5516 __le16 word9;
5517 __le16 word10;
5518 __le32 reg7;
5519 __le32 reg8;
5520 __le32 reg9;
5521 u8 byte7;
5522 u8 byte8;
5523 u8 byte9;
5524 u8 byte10;
5525 u8 byte11;
5526 u8 byte12;
5527 u8 byte13;
5528 u8 byte14;
5529 u8 byte15;
5530 u8 e5_reserved;
5531 __le16 word11;
5532 __le32 reg10;
5533 __le32 reg11;
5534 __le32 reg12;
5535 __le32 reg13;
5536 __le32 reg14;
5537 __le32 reg15;
5538 __le32 reg16;
5539 __le32 reg17;
5540};
5541
5542struct tstorm_toe_conn_ag_ctx {
5543 u8 reserved0;
5544 u8 byte1;
5545 u8 flags0;
5546#define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5547#define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5548#define TSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5549#define TSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT 1
5550#define TSTORM_TOE_CONN_AG_CTX_BIT2_MASK 0x1
5551#define TSTORM_TOE_CONN_AG_CTX_BIT2_SHIFT 2
5552#define TSTORM_TOE_CONN_AG_CTX_BIT3_MASK 0x1
5553#define TSTORM_TOE_CONN_AG_CTX_BIT3_SHIFT 3
5554#define TSTORM_TOE_CONN_AG_CTX_BIT4_MASK 0x1
5555#define TSTORM_TOE_CONN_AG_CTX_BIT4_SHIFT 4
5556#define TSTORM_TOE_CONN_AG_CTX_BIT5_MASK 0x1
5557#define TSTORM_TOE_CONN_AG_CTX_BIT5_SHIFT 5
5558#define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_MASK 0x3
5559#define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_SHIFT 6
5560 u8 flags1;
5561#define TSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5562#define TSTORM_TOE_CONN_AG_CTX_CF1_SHIFT 0
5563#define TSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5564#define TSTORM_TOE_CONN_AG_CTX_CF2_SHIFT 2
5565#define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5566#define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
5567#define TSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3
5568#define TSTORM_TOE_CONN_AG_CTX_CF4_SHIFT 6
5569 u8 flags2;
5570#define TSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3
5571#define TSTORM_TOE_CONN_AG_CTX_CF5_SHIFT 0
5572#define TSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5573#define TSTORM_TOE_CONN_AG_CTX_CF6_SHIFT 2
5574#define TSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3
5575#define TSTORM_TOE_CONN_AG_CTX_CF7_SHIFT 4
5576#define TSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3
5577#define TSTORM_TOE_CONN_AG_CTX_CF8_SHIFT 6
5578 u8 flags3;
5579#define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5580#define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5581#define TSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3
5582#define TSTORM_TOE_CONN_AG_CTX_CF10_SHIFT 2
5583#define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_MASK 0x1
5584#define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_SHIFT 4
5585#define TSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5586#define TSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT 5
5587#define TSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5588#define TSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT 6
5589#define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5590#define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
5591 u8 flags4;
5592#define TSTORM_TOE_CONN_AG_CTX_CF4EN_MASK 0x1
5593#define TSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT 0
5594#define TSTORM_TOE_CONN_AG_CTX_CF5EN_MASK 0x1
5595#define TSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT 1
5596#define TSTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5597#define TSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT 2
5598#define TSTORM_TOE_CONN_AG_CTX_CF7EN_MASK 0x1
5599#define TSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT 3
5600#define TSTORM_TOE_CONN_AG_CTX_CF8EN_MASK 0x1
5601#define TSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT 4
5602#define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5603#define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
5604#define TSTORM_TOE_CONN_AG_CTX_CF10EN_MASK 0x1
5605#define TSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT 6
5606#define TSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5607#define TSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT 7
5608 u8 flags5;
5609#define TSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5610#define TSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 0
5611#define TSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5612#define TSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT 1
5613#define TSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5614#define TSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 2
5615#define TSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
5616#define TSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT 3
5617#define TSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5618#define TSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT 4
5619#define TSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5620#define TSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT 5
5621#define TSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5622#define TSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT 6
5623#define TSTORM_TOE_CONN_AG_CTX_RULE8EN_MASK 0x1
5624#define TSTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT 7
5625 __le32 reg0;
5626 __le32 reg1;
5627 __le32 reg2;
5628 __le32 reg3;
5629 __le32 reg4;
5630 __le32 reg5;
5631 __le32 reg6;
5632 __le32 reg7;
5633 __le32 reg8;
5634 u8 byte2;
5635 u8 byte3;
5636 __le16 word0;
5637};
5638
5639struct ustorm_toe_conn_ag_ctx {
5640 u8 reserved;
5641 u8 byte1;
5642 u8 flags0;
5643#define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5644#define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5645#define USTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5646#define USTORM_TOE_CONN_AG_CTX_BIT1_SHIFT 1
5647#define USTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
5648#define USTORM_TOE_CONN_AG_CTX_CF0_SHIFT 2
5649#define USTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5650#define USTORM_TOE_CONN_AG_CTX_CF1_SHIFT 4
5651#define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_MASK 0x3
5652#define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_SHIFT 6
5653 u8 flags1;
5654#define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5655#define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 0
5656#define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3
5657#define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT 2
5658#define USTORM_TOE_CONN_AG_CTX_DQ_CF_MASK 0x3
5659#define USTORM_TOE_CONN_AG_CTX_DQ_CF_SHIFT 4
5660#define USTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5661#define USTORM_TOE_CONN_AG_CTX_CF6_SHIFT 6
5662 u8 flags2;
5663#define USTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
5664#define USTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT 0
5665#define USTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5666#define USTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT 1
5667#define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_MASK 0x1
5668#define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_SHIFT 2
5669#define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5670#define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 3
5671#define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1
5672#define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT 4
5673#define USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
5674#define USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 5
5675#define USTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5676#define USTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT 6
5677#define USTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5678#define USTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT 7
5679 u8 flags3;
5680#define USTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5681#define USTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 0
5682#define USTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5683#define USTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT 1
5684#define USTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5685#define USTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 2
5686#define USTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
5687#define USTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT 3
5688#define USTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5689#define USTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT 4
5690#define USTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5691#define USTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT 5
5692#define USTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5693#define USTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT 6
5694#define USTORM_TOE_CONN_AG_CTX_RULE8EN_MASK 0x1
5695#define USTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT 7
5696 u8 byte2;
5697 u8 byte3;
5698 __le16 word0;
5699 __le16 word1;
5700 __le32 reg0;
5701 __le32 reg1;
5702 __le32 reg2;
5703 __le32 reg3;
5704 __le16 word2;
5705 __le16 word3;
5706};
5707
5708/* The toe storm context of Tstorm */
5709struct tstorm_toe_conn_st_ctx {
5710 __le32 reserved[16];
5711};
5712
5713/* The toe storm context of Ustorm */
5714struct ustorm_toe_conn_st_ctx {
5715 __le32 reserved[52];
5716};
5717
5718/* toe connection context */
5719struct toe_conn_context {
5720 struct ystorm_toe_conn_st_ctx ystorm_st_context;
5721 struct pstorm_toe_conn_st_ctx pstorm_st_context;
5722 struct regpair pstorm_st_padding[2];
5723 struct xstorm_toe_conn_st_ctx xstorm_st_context;
5724 struct regpair xstorm_st_padding[2];
5725 struct ystorm_toe_conn_ag_ctx ystorm_ag_context;
5726 struct xstorm_toe_conn_ag_ctx xstorm_ag_context;
5727 struct tstorm_toe_conn_ag_ctx tstorm_ag_context;
5728 struct regpair tstorm_ag_padding[2];
5729 struct timers_context timer_context;
5730 struct ustorm_toe_conn_ag_ctx ustorm_ag_context;
5731 struct tstorm_toe_conn_st_ctx tstorm_st_context;
5732 struct mstorm_toe_conn_st_ctx mstorm_st_context;
5733 struct ustorm_toe_conn_st_ctx ustorm_st_context;
5734};
5735
5736/* toe init ramrod header */
5737struct toe_init_ramrod_header {
5738 u8 first_rss;
5739 u8 num_rss;
5740 u8 reserved[6];
5741};
5742
5743/* toe pf init parameters */
5744struct toe_pf_init_params {
5745 __le32 push_timeout;
5746 __le16 grq_buffer_size;
5747 __le16 grq_sb_id;
5748 u8 grq_sb_index;
5749 u8 max_seg_retransmit;
5750 u8 doubt_reachability;
5751 u8 ll2_rx_queue_id;
5752 __le16 grq_fetch_threshold;
5753 u8 reserved1[2];
5754 struct regpair grq_page_addr;
5755};
5756
5757/* toe tss parameters */
5758struct toe_tss_params {
5759 struct regpair curr_page_addr;
5760 struct regpair next_page_addr;
5761 u8 reserved0;
5762 u8 status_block_index;
5763 __le16 status_block_id;
5764 __le16 reserved1[2];
5765};
5766
5767/* toe rss parameters */
5768struct toe_rss_params {
5769 struct regpair curr_page_addr;
5770 struct regpair next_page_addr;
5771 u8 reserved0;
5772 u8 status_block_index;
5773 __le16 status_block_id;
5774 __le16 reserved1[2];
5775};
5776
5777/* toe init ramrod data */
5778struct toe_init_ramrod_data {
5779 struct toe_init_ramrod_header hdr;
5780 struct tcp_init_params tcp_params;
5781 struct toe_pf_init_params pf_params;
5782 struct toe_tss_params tss_params[TOE_TX_MAX_TSS_CHAINS];
5783 struct toe_rss_params rss_params[TOE_RX_MAX_RSS_CHAINS];
5784};
5785
5786/* toe offload parameters */
5787struct toe_offload_params {
5788 struct regpair tx_bd_page_addr;
5789 struct regpair tx_app_page_addr;
5790 __le32 more_to_send_seq;
5791 __le16 rcv_indication_size;
5792 u8 rss_tss_id;
5793 u8 ignore_grq_push;
5794 struct regpair rx_db_data_ptr;
5795};
5796
5797/* TOE offload ramrod data - DMAed by firmware */
5798struct toe_offload_ramrod_data {
5799 struct tcp_offload_params tcp_ofld_params;
5800 struct toe_offload_params toe_ofld_params;
5801};
5802
5803/* TOE ramrod command IDs */
5804enum toe_ramrod_cmd_id {
5805 TOE_RAMROD_UNUSED,
5806 TOE_RAMROD_FUNC_INIT,
5807 TOE_RAMROD_INITATE_OFFLOAD,
5808 TOE_RAMROD_FUNC_CLOSE,
5809 TOE_RAMROD_SEARCHER_DELETE,
5810 TOE_RAMROD_TERMINATE,
5811 TOE_RAMROD_QUERY,
5812 TOE_RAMROD_UPDATE,
5813 TOE_RAMROD_EMPTY,
5814 TOE_RAMROD_RESET_SEND,
5815 TOE_RAMROD_INVALIDATE,
5816 MAX_TOE_RAMROD_CMD_ID
5817};
5818
5819/* Toe RQ buffer descriptor */
5820struct toe_rx_bd {
5821 struct regpair addr;
5822 __le16 size;
5823 __le16 flags;
5824#define TOE_RX_BD_START_MASK 0x1
5825#define TOE_RX_BD_START_SHIFT 0
5826#define TOE_RX_BD_END_MASK 0x1
5827#define TOE_RX_BD_END_SHIFT 1
5828#define TOE_RX_BD_NO_PUSH_MASK 0x1
5829#define TOE_RX_BD_NO_PUSH_SHIFT 2
5830#define TOE_RX_BD_SPLIT_MASK 0x1
5831#define TOE_RX_BD_SPLIT_SHIFT 3
5832#define TOE_RX_BD_RESERVED0_MASK 0xFFF
5833#define TOE_RX_BD_RESERVED0_SHIFT 4
5834 __le32 reserved1;
5835};
5836
5837/* TOE RX completion queue opcodes (opcode 0 is illegal) */
5838enum toe_rx_cmp_opcode {
5839 TOE_RX_CMP_OPCODE_GA = 1,
5840 TOE_RX_CMP_OPCODE_GR = 2,
5841 TOE_RX_CMP_OPCODE_GNI = 3,
5842 TOE_RX_CMP_OPCODE_GAIR = 4,
5843 TOE_RX_CMP_OPCODE_GAIL = 5,
5844 TOE_RX_CMP_OPCODE_GRI = 6,
5845 TOE_RX_CMP_OPCODE_GJ = 7,
5846 TOE_RX_CMP_OPCODE_DGI = 8,
5847 TOE_RX_CMP_OPCODE_CMP = 9,
5848 TOE_RX_CMP_OPCODE_REL = 10,
5849 TOE_RX_CMP_OPCODE_SKP = 11,
5850 TOE_RX_CMP_OPCODE_URG = 12,
5851 TOE_RX_CMP_OPCODE_RT_TO = 13,
5852 TOE_RX_CMP_OPCODE_KA_TO = 14,
5853 TOE_RX_CMP_OPCODE_MAX_RT = 15,
5854 TOE_RX_CMP_OPCODE_DBT_RE = 16,
5855 TOE_RX_CMP_OPCODE_SYN = 17,
5856 TOE_RX_CMP_OPCODE_OPT_ERR = 18,
5857 TOE_RX_CMP_OPCODE_FW2_TO = 19,
5858 TOE_RX_CMP_OPCODE_2WY_CLS = 20,
5859 TOE_RX_CMP_OPCODE_RST_RCV = 21,
5860 TOE_RX_CMP_OPCODE_FIN_RCV = 22,
5861 TOE_RX_CMP_OPCODE_FIN_UPL = 23,
5862 TOE_RX_CMP_OPCODE_INIT = 32,
5863 TOE_RX_CMP_OPCODE_RSS_UPDATE = 33,
5864 TOE_RX_CMP_OPCODE_CLOSE = 34,
5865 TOE_RX_CMP_OPCODE_INITIATE_OFFLOAD = 80,
5866 TOE_RX_CMP_OPCODE_SEARCHER_DELETE = 81,
5867 TOE_RX_CMP_OPCODE_TERMINATE = 82,
5868 TOE_RX_CMP_OPCODE_QUERY = 83,
5869 TOE_RX_CMP_OPCODE_RESET_SEND = 84,
5870 TOE_RX_CMP_OPCODE_INVALIDATE = 85,
5871 TOE_RX_CMP_OPCODE_EMPTY = 86,
5872 TOE_RX_CMP_OPCODE_UPDATE = 87,
5873 MAX_TOE_RX_CMP_OPCODE
5874};
5875
5876/* TOE rx ooo completion data */
5877struct toe_rx_cqe_ooo_params {
5878 __le32 nbytes;
5879 __le16 grq_buff_id;
5880 u8 isle_num;
5881 u8 reserved0;
5882};
5883
5884/* TOE rx in order completion data */
5885struct toe_rx_cqe_in_order_params {
5886 __le32 nbytes;
5887 __le16 grq_buff_id;
5888 __le16 reserved1;
5889};
5890
5891/* Union for TOE rx completion data */
5892union toe_rx_cqe_data_union {
5893 struct toe_rx_cqe_ooo_params ooo_params;
5894 struct toe_rx_cqe_in_order_params in_order_params;
5895 struct regpair raw_data;
5896};
5897
5898/* TOE rx completion element */
5899struct toe_rx_cqe {
5900 __le16 icid;
5901 u8 completion_opcode;
5902 u8 reserved0;
5903 __le32 reserved1;
5904 union toe_rx_cqe_data_union data;
5905};
5906
5907/* toe RX doorbel data */
5908struct toe_rx_db_data {
5909 __le32 local_adv_wnd_seq;
5910 __le32 reserved[3];
5911};
5912
5913/* Toe GRQ buffer descriptor */
5914struct toe_rx_grq_bd {
5915 struct regpair addr;
5916 __le16 buff_id;
5917 __le16 reserved0;
5918 __le32 reserved1;
5919};
5920
5921/* Toe transmission application buffer descriptor */
5922struct toe_tx_app_buff_desc {
5923 __le32 next_buffer_start_seq;
5924 __le32 reserved;
5925};
5926
5927/* Toe transmission application buffer descriptor page pointer */
5928struct toe_tx_app_buff_page_pointer {
5929 struct regpair next_page_addr;
5930};
5931
5932/* Toe transmission buffer descriptor */
5933struct toe_tx_bd {
5934 struct regpair addr;
5935 __le16 size;
5936 __le16 flags;
5937#define TOE_TX_BD_PUSH_MASK 0x1
5938#define TOE_TX_BD_PUSH_SHIFT 0
5939#define TOE_TX_BD_NOTIFY_MASK 0x1
5940#define TOE_TX_BD_NOTIFY_SHIFT 1
5941#define TOE_TX_BD_LARGE_IO_MASK 0x1
5942#define TOE_TX_BD_LARGE_IO_SHIFT 2
5943#define TOE_TX_BD_BD_CONS_MASK 0x1FFF
5944#define TOE_TX_BD_BD_CONS_SHIFT 3
5945 __le32 next_bd_start_seq;
5946};
5947
5948/* TOE completion opcodes */
5949enum toe_tx_cmp_opcode {
5950 TOE_TX_CMP_OPCODE_DATA,
5951 TOE_TX_CMP_OPCODE_TERMINATE,
5952 TOE_TX_CMP_OPCODE_EMPTY,
5953 TOE_TX_CMP_OPCODE_RESET_SEND,
5954 TOE_TX_CMP_OPCODE_INVALIDATE,
5955 TOE_TX_CMP_OPCODE_RST_RCV,
5956 MAX_TOE_TX_CMP_OPCODE
5957};
5958
5959/* Toe transmission completion element */
5960struct toe_tx_cqe {
5961 __le16 icid;
5962 u8 opcode;
5963 u8 reserved;
5964 __le32 size;
5965};
5966
5967/* Toe transmission page pointer bd */
5968struct toe_tx_page_pointer_bd {
5969 struct regpair next_page_addr;
5970 struct regpair prev_page_addr;
5971};
5972
5973/* Toe transmission completion element page pointer */
5974struct toe_tx_page_pointer_cqe {
5975 struct regpair next_page_addr;
5976};
5977
5978/* toe update parameters */
5979struct toe_update_params {
5980 __le16 flags;
5981#define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_MASK 0x1
5982#define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT 0
5983#define TOE_UPDATE_PARAMS_RESERVED_MASK 0x7FFF
5984#define TOE_UPDATE_PARAMS_RESERVED_SHIFT 1
5985 __le16 rcv_indication_size;
5986 __le16 reserved1[2];
5987};
5988
5989/* TOE update ramrod data - DMAed by firmware */
5990struct toe_update_ramrod_data {
5991 struct tcp_update_params tcp_upd_params;
5992 struct toe_update_params toe_upd_params;
5993};
5994
5995struct mstorm_toe_conn_ag_ctx {
5996 u8 byte0;
5997 u8 byte1;
5998 u8 flags0;
5999#define MSTORM_TOE_CONN_AG_CTX_BIT0_MASK 0x1
6000#define MSTORM_TOE_CONN_AG_CTX_BIT0_SHIFT 0
6001#define MSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
6002#define MSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT 1
6003#define MSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
6004#define MSTORM_TOE_CONN_AG_CTX_CF0_SHIFT 2
6005#define MSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
6006#define MSTORM_TOE_CONN_AG_CTX_CF1_SHIFT 4
6007#define MSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
6008#define MSTORM_TOE_CONN_AG_CTX_CF2_SHIFT 6
6009 u8 flags1;
6010#define MSTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
6011#define MSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT 0
6012#define MSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
6013#define MSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT 1
6014#define MSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
6015#define MSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT 2
6016#define MSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
6017#define MSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT 3
6018#define MSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
6019#define MSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 4
6020#define MSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
6021#define MSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT 5
6022#define MSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
6023#define MSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 6
6024#define MSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
6025#define MSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT 7
6026 __le16 word0;
6027 __le16 word1;
6028 __le32 reg0;
6029 __le32 reg1;
6030};
6031
6032/* TOE doorbell data */
6033struct toe_db_data {
6034 u8 params;
6035#define TOE_DB_DATA_DEST_MASK 0x3
6036#define TOE_DB_DATA_DEST_SHIFT 0
6037#define TOE_DB_DATA_AGG_CMD_MASK 0x3
6038#define TOE_DB_DATA_AGG_CMD_SHIFT 2
6039#define TOE_DB_DATA_BYPASS_EN_MASK 0x1
6040#define TOE_DB_DATA_BYPASS_EN_SHIFT 4
6041#define TOE_DB_DATA_RESERVED_MASK 0x1
6042#define TOE_DB_DATA_RESERVED_SHIFT 5
6043#define TOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
6044#define TOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
6045 u8 agg_flags;
6046 __le16 bd_prod;
6047};
6048
6049/* rdma function init ramrod data */
6050struct rdma_close_func_ramrod_data {
6051 u8 cnq_start_offset;
6052 u8 num_cnqs;
6053 u8 vf_id;
6054 u8 vf_valid;
6055 u8 reserved[4];
6056};
6057
6058/* rdma function init CNQ parameters */
6059struct rdma_cnq_params {
6060 __le16 sb_num;
6061 u8 sb_index;
6062 u8 num_pbl_pages;
6063 __le32 reserved;
6064 struct regpair pbl_base_addr;
6065 __le16 queue_zone_num;
6066 u8 reserved1[6];
6067};
6068
6069/* rdma create cq ramrod data */
6070struct rdma_create_cq_ramrod_data {
6071 struct regpair cq_handle;
6072 struct regpair pbl_addr;
6073 __le32 max_cqes;
6074 __le16 pbl_num_pages;
6075 __le16 dpi;
6076 u8 is_two_level_pbl;
6077 u8 cnq_id;
6078 u8 pbl_log_page_size;
6079 u8 toggle_bit;
6080 __le16 int_timeout;
6081 u8 vf_id;
6082 u8 flags;
6083#define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6084#define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
6085#define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F
6086#define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_SHIFT 1
6087};
6088
6089/* rdma deregister tid ramrod data */
6090struct rdma_deregister_tid_ramrod_data {
6091 __le32 itid;
6092 __le32 reserved;
6093};
6094
6095/* rdma destroy cq output params */
6096struct rdma_destroy_cq_output_params {
6097 __le16 cnq_num;
6098 __le16 reserved0;
6099 __le32 reserved1;
6100};
6101
6102/* rdma destroy cq ramrod data */
6103struct rdma_destroy_cq_ramrod_data {
6104 struct regpair output_params_addr;
6105};
6106
6107/* RDMA slow path EQ cmd IDs */
6108enum rdma_event_opcode {
6109 RDMA_EVENT_UNUSED,
6110 RDMA_EVENT_FUNC_INIT,
6111 RDMA_EVENT_FUNC_CLOSE,
6112 RDMA_EVENT_REGISTER_MR,
6113 RDMA_EVENT_DEREGISTER_MR,
6114 RDMA_EVENT_CREATE_CQ,
6115 RDMA_EVENT_RESIZE_CQ,
6116 RDMA_EVENT_DESTROY_CQ,
6117 RDMA_EVENT_CREATE_SRQ,
6118 RDMA_EVENT_MODIFY_SRQ,
6119 RDMA_EVENT_DESTROY_SRQ,
6120 RDMA_EVENT_START_NAMESPACE_TRACKING,
6121 RDMA_EVENT_STOP_NAMESPACE_TRACKING,
6122 MAX_RDMA_EVENT_OPCODE
6123};
6124
6125/* RDMA FW return code for slow path ramrods */
6126enum rdma_fw_return_code {
6127 RDMA_RETURN_OK = 0,
6128 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
6129 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
6130 RDMA_RETURN_RESIZE_CQ_ERR,
6131 RDMA_RETURN_NIG_DRAIN_REQ,
6132 RDMA_RETURN_GENERAL_ERR,
6133 MAX_RDMA_FW_RETURN_CODE
6134};
6135
6136/* rdma function init header */
6137struct rdma_init_func_hdr {
6138 u8 cnq_start_offset;
6139 u8 num_cnqs;
6140 u8 cq_ring_mode;
6141 u8 vf_id;
6142 u8 vf_valid;
6143 u8 relaxed_ordering;
6144 __le16 first_reg_srq_id;
6145 __le32 reg_srq_base_addr;
6146 u8 flags;
6147#define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_MASK 0x1
6148#define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_SHIFT 0
6149#define RDMA_INIT_FUNC_HDR_PVRDMA_MODE_MASK 0x1
6150#define RDMA_INIT_FUNC_HDR_PVRDMA_MODE_SHIFT 1
6151#define RDMA_INIT_FUNC_HDR_DPT_MODE_MASK 0x1
6152#define RDMA_INIT_FUNC_HDR_DPT_MODE_SHIFT 2
6153#define RDMA_INIT_FUNC_HDR_RESERVED0_MASK 0x1F
6154#define RDMA_INIT_FUNC_HDR_RESERVED0_SHIFT 3
6155 u8 dpt_byte_threshold_log;
6156 u8 dpt_common_queue_id;
6157 u8 max_num_ns_log;
6158};
6159
6160/* rdma function init ramrod data */
6161struct rdma_init_func_ramrod_data {
6162 struct rdma_init_func_hdr params_header;
6163 struct rdma_cnq_params dptq_params;
6164 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
6165};
6166
6167/* rdma namespace tracking ramrod data */
6168struct rdma_namespace_tracking_ramrod_data {
6169 u8 name_space;
6170 u8 reserved[7];
6171};
6172
6173/* RDMA ramrod command IDs */
6174enum rdma_ramrod_cmd_id {
6175 RDMA_RAMROD_UNUSED,
6176 RDMA_RAMROD_FUNC_INIT,
6177 RDMA_RAMROD_FUNC_CLOSE,
6178 RDMA_RAMROD_REGISTER_MR,
6179 RDMA_RAMROD_DEREGISTER_MR,
6180 RDMA_RAMROD_CREATE_CQ,
6181 RDMA_RAMROD_RESIZE_CQ,
6182 RDMA_RAMROD_DESTROY_CQ,
6183 RDMA_RAMROD_CREATE_SRQ,
6184 RDMA_RAMROD_MODIFY_SRQ,
6185 RDMA_RAMROD_DESTROY_SRQ,
6186 RDMA_RAMROD_START_NS_TRACKING,
6187 RDMA_RAMROD_STOP_NS_TRACKING,
6188 MAX_RDMA_RAMROD_CMD_ID
6189};
6190
6191/* rdma register tid ramrod data */
6192struct rdma_register_tid_ramrod_data {
6193 __le16 flags;
6194#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
6195#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
6196#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
6197#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5
6198#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
6199#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6
6200#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
6201#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7
6202#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
6203#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8
6204#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
6205#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9
6206#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
6207#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10
6208#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
6209#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11
6210#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
6211#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12
6212#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
6213#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13
6214#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
6215#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14
6216 u8 flags1;
6217#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
6218#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
6219#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
6220#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
6221 u8 flags2;
6222#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
6223#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
6224#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
6225#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
6226#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
6227#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
6228 u8 key;
6229 u8 length_hi;
6230 u8 vf_id;
6231 u8 vf_valid;
6232 __le16 pd;
6233 __le16 reserved2;
6234 __le32 length_lo;
6235 __le32 itid;
6236 __le32 reserved3;
6237 struct regpair va;
6238 struct regpair pbl_base;
6239 struct regpair dif_error_addr;
6240 __le32 reserved4[4];
6241};
6242
6243/* rdma resize cq output params */
6244struct rdma_resize_cq_output_params {
6245 __le32 old_cq_cons;
6246 __le32 old_cq_prod;
6247};
6248
6249/* rdma resize cq ramrod data */
6250struct rdma_resize_cq_ramrod_data {
6251 u8 flags;
6252#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
6253#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
6254#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
6255#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
6256#define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6257#define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 2
6258#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F
6259#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 3
6260 u8 pbl_log_page_size;
6261 __le16 pbl_num_pages;
6262 __le32 max_cqes;
6263 struct regpair pbl_addr;
6264 struct regpair output_params_addr;
6265 u8 vf_id;
6266 u8 reserved1[7];
6267};
6268
6269/* The rdma SRQ context */
6270struct rdma_srq_context {
6271 struct regpair temp[8];
6272};
6273
6274/* rdma create qp requester ramrod data */
6275struct rdma_srq_create_ramrod_data {
6276 u8 flags;
6277#define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1
6278#define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0
6279#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
6280#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1
6281#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F
6282#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2
6283 u8 reserved2;
6284 __le16 xrc_domain;
6285 __le32 xrc_srq_cq_cid;
6286 struct regpair pbl_base_addr;
6287 __le16 pages_in_srq_pbl;
6288 __le16 pd_id;
6289 struct rdma_srq_id srq_id;
6290 __le16 page_size;
6291 __le16 reserved3;
6292 __le32 reserved4;
6293 struct regpair producers_addr;
6294};
6295
6296/* rdma create qp requester ramrod data */
6297struct rdma_srq_destroy_ramrod_data {
6298 struct rdma_srq_id srq_id;
6299 __le32 reserved;
6300};
6301
6302/* rdma create qp requester ramrod data */
6303struct rdma_srq_modify_ramrod_data {
6304 struct rdma_srq_id srq_id;
6305 __le32 wqe_limit;
6306};
6307
6308/* RDMA Tid type enumeration (for register_tid ramrod) */
6309enum rdma_tid_type {
6310 RDMA_TID_REGISTERED_MR,
6311 RDMA_TID_FMR,
6312 RDMA_TID_MW,
6313 MAX_RDMA_TID_TYPE
6314};
6315
6316/* The rdma XRC SRQ context */
6317struct rdma_xrc_srq_context {
6318 struct regpair temp[9];
6319};
6320
6321struct tstorm_rdma_task_ag_ctx {
6322 u8 byte0;
6323 u8 byte1;
6324 __le16 word0;
6325 u8 flags0;
6326#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
6327#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
6328#define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
6329#define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
6330#define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6331#define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6332#define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6333#define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6334#define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6335#define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6336 u8 flags1;
6337#define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6338#define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6339#define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
6340#define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
6341#define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6342#define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
6343#define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6344#define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
6345#define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6346#define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
6347 u8 flags2;
6348#define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6349#define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
6350#define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
6351#define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
6352#define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
6353#define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
6354#define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
6355#define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
6356 u8 flags3;
6357#define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
6358#define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
6359#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6360#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
6361#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6362#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
6363#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6364#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
6365#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6366#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
6367#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
6368#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
6369#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
6370#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
6371 u8 flags4;
6372#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
6373#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
6374#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
6375#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
6376#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6377#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
6378#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6379#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
6380#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6381#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
6382#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6383#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
6384#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6385#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
6386#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6387#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
6388 u8 byte2;
6389 __le16 word1;
6390 __le32 reg0;
6391 u8 byte3;
6392 u8 byte4;
6393 __le16 word2;
6394 __le16 word3;
6395 __le16 word4;
6396 __le32 reg1;
6397 __le32 reg2;
6398};
6399
6400struct ustorm_rdma_conn_ag_ctx {
6401 u8 reserved;
6402 u8 byte1;
6403 u8 flags0;
6404#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6405#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6406#define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1
6407#define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1
6408#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6409#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
6410#define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6411#define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
6412#define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6413#define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
6414 u8 flags1;
6415#define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
6416#define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
6417#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
6418#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
6419#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
6420#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
6421#define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6422#define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
6423 u8 flags2;
6424#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6425#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6426#define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6427#define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
6428#define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6429#define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
6430#define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
6431#define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
6432#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
6433#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
6434#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
6435#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
6436#define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6437#define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
6438#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
6439#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
6440 u8 flags3;
6441#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
6442#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
6443#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6444#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
6445#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6446#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
6447#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6448#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
6449#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6450#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
6451#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6452#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
6453#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6454#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
6455#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
6456#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
6457 u8 byte2;
6458 u8 nvmf_only;
6459 __le16 conn_dpi;
6460 __le16 word1;
6461 __le32 cq_cons;
6462 __le32 cq_se_prod;
6463 __le32 cq_prod;
6464 __le32 reg3;
6465 __le16 int_timeout;
6466 __le16 word3;
6467};
6468
6469struct xstorm_roce_conn_ag_ctx {
6470 u8 reserved0;
6471 u8 state;
6472 u8 flags0;
6473#define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6474#define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6475#define XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
6476#define XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
6477#define XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
6478#define XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2
6479#define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
6480#define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
6481#define XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
6482#define XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4
6483#define XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
6484#define XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5
6485#define XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1
6486#define XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT 6
6487#define XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1
6488#define XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT 7
6489 u8 flags1;
6490#define XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1
6491#define XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0
6492#define XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1
6493#define XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT 1
6494#define XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1
6495#define XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT 2
6496#define XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1
6497#define XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT 3
6498#define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
6499#define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
6500#define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
6501#define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
6502#define XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1
6503#define XSTORM_ROCE_CONN_AG_CTX_BIT14_SHIFT 6
6504#define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
6505#define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
6506 u8 flags2;
6507#define XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
6508#define XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0
6509#define XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
6510#define XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 2
6511#define XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
6512#define XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 4
6513#define XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3
6514#define XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT 6
6515 u8 flags3;
6516#define XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3
6517#define XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0
6518#define XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
6519#define XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 2
6520#define XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
6521#define XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 4
6522#define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6523#define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6524 u8 flags4;
6525#define XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
6526#define XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0
6527#define XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
6528#define XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 2
6529#define XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
6530#define XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 4
6531#define XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3
6532#define XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT 6
6533 u8 flags5;
6534#define XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3
6535#define XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0
6536#define XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3
6537#define XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT 2
6538#define XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3
6539#define XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT 4
6540#define XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3
6541#define XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT 6
6542 u8 flags6;
6543#define XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3
6544#define XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0
6545#define XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3
6546#define XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT 2
6547#define XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3
6548#define XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT 4
6549#define XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3
6550#define XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT 6
6551 u8 flags7;
6552#define XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3
6553#define XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0
6554#define XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3
6555#define XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT 2
6556#define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6557#define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
6558#define XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
6559#define XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 6
6560#define XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
6561#define XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 7
6562 u8 flags8;
6563#define XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
6564#define XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0
6565#define XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1
6566#define XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT 1
6567#define XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1
6568#define XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT 2
6569#define XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
6570#define XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 3
6571#define XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
6572#define XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 4
6573#define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6574#define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
6575#define XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
6576#define XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 6
6577#define XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
6578#define XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 7
6579 u8 flags9;
6580#define XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
6581#define XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0
6582#define XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1
6583#define XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT 1
6584#define XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1
6585#define XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT 2
6586#define XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1
6587#define XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT 3
6588#define XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1
6589#define XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT 4
6590#define XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1
6591#define XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT 5
6592#define XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1
6593#define XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT 6
6594#define XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1
6595#define XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT 7
6596 u8 flags10;
6597#define XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1
6598#define XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0
6599#define XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1
6600#define XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT 1
6601#define XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1
6602#define XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT 2
6603#define XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1
6604#define XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT 3
6605#define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6606#define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
6607#define XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1
6608#define XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT 5
6609#define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
6610#define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 6
6611#define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
6612#define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 7
6613 u8 flags11;
6614#define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
6615#define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0
6616#define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
6617#define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 1
6618#define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
6619#define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 2
6620#define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
6621#define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 3
6622#define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
6623#define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 4
6624#define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
6625#define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 5
6626#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6627#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
6628#define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1
6629#define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT 7
6630 u8 flags12;
6631#define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1
6632#define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0
6633#define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1
6634#define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT 1
6635#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6636#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
6637#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6638#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
6639#define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1
6640#define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT 4
6641#define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1
6642#define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT 5
6643#define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1
6644#define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT 6
6645#define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1
6646#define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT 7
6647 u8 flags13;
6648#define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1
6649#define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0
6650#define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1
6651#define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT 1
6652#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6653#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
6654#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6655#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
6656#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6657#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
6658#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6659#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
6660#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6661#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
6662#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6663#define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
6664 u8 flags14;
6665#define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1
6666#define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0
6667#define XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1
6668#define XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT 1
6669#define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
6670#define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
6671#define XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1
6672#define XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT 4
6673#define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6674#define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
6675#define XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3
6676#define XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT 6
6677 u8 byte2;
6678 __le16 physical_q0;
6679 __le16 word1;
6680 __le16 word2;
6681 __le16 word3;
6682 __le16 word4;
6683 __le16 word5;
6684 __le16 conn_dpi;
6685 u8 byte3;
6686 u8 byte4;
6687 u8 byte5;
6688 u8 byte6;
6689 __le32 reg0;
6690 __le32 reg1;
6691 __le32 reg2;
6692 __le32 snd_nxt_psn;
6693 __le32 reg4;
6694 __le32 reg5;
6695 __le32 reg6;
6696};
6697
6698struct tstorm_roce_conn_ag_ctx {
6699 u8 reserved0;
6700 u8 byte1;
6701 u8 flags0;
6702#define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6703#define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6704#define TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
6705#define TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
6706#define TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
6707#define TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2
6708#define TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1
6709#define TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT 3
6710#define TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
6711#define TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4
6712#define TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
6713#define TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5
6714#define TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
6715#define TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 6
6716 u8 flags1;
6717#define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6718#define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
6719#define TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
6720#define TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 2
6721#define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
6722#define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
6723#define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6724#define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6725 u8 flags2;
6726#define TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
6727#define TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0
6728#define TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
6729#define TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 2
6730#define TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3
6731#define TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT 4
6732#define TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
6733#define TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 6
6734 u8 flags3;
6735#define TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
6736#define TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0
6737#define TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
6738#define TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 2
6739#define TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
6740#define TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 4
6741#define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
6742#define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5
6743#define TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
6744#define TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 6
6745#define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
6746#define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
6747 u8 flags4;
6748#define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6749#define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6750#define TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
6751#define TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 1
6752#define TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
6753#define TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 2
6754#define TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1
6755#define TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT 3
6756#define TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
6757#define TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 4
6758#define TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
6759#define TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 5
6760#define TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
6761#define TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 6
6762#define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
6763#define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 7
6764 u8 flags5;
6765#define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
6766#define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0
6767#define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
6768#define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1
6769#define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
6770#define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2
6771#define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
6772#define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3
6773#define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
6774#define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4
6775#define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
6776#define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5
6777#define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
6778#define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6
6779#define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1
6780#define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7
6781 __le32 reg0;
6782 __le32 reg1;
6783 __le32 reg2;
6784 __le32 reg3;
6785 __le32 reg4;
6786 __le32 reg5;
6787 __le32 reg6;
6788 __le32 reg7;
6789 __le32 reg8;
6790 u8 byte2;
6791 u8 byte3;
6792 __le16 word0;
6793 u8 byte4;
6794 u8 byte5;
6795 __le16 word1;
6796 __le16 word2;
6797 __le16 word3;
6798 __le32 reg9;
6799 __le32 reg10;
6800};
6801
6802/* The roce storm context of Ystorm */
6803struct ystorm_roce_conn_st_ctx {
6804 struct regpair temp[2];
6805};
6806
6807/* The roce storm context of Mstorm */
6808struct pstorm_roce_conn_st_ctx {
6809 struct regpair temp[16];
6810};
6811
6812/* The roce storm context of Xstorm */
6813struct xstorm_roce_conn_st_ctx {
6814 struct regpair temp[24];
6815};
6816
6817/* The roce storm context of Tstorm */
6818struct tstorm_roce_conn_st_ctx {
6819 struct regpair temp[30];
6820};
6821
6822/* The roce storm context of Mstorm */
6823struct mstorm_roce_conn_st_ctx {
6824 struct regpair temp[6];
6825};
6826
6827/* The roce storm context of Ustorm */
6828struct ustorm_roce_conn_st_ctx {
6829 struct regpair temp[14];
6830};
6831
6832/* roce connection context */
6833struct roce_conn_context {
6834 struct ystorm_roce_conn_st_ctx ystorm_st_context;
6835 struct regpair ystorm_st_padding[2];
6836 struct pstorm_roce_conn_st_ctx pstorm_st_context;
6837 struct xstorm_roce_conn_st_ctx xstorm_st_context;
6838 struct xstorm_roce_conn_ag_ctx xstorm_ag_context;
6839 struct tstorm_roce_conn_ag_ctx tstorm_ag_context;
6840 struct timers_context timer_context;
6841 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
6842 struct tstorm_roce_conn_st_ctx tstorm_st_context;
6843 struct regpair tstorm_st_padding[2];
6844 struct mstorm_roce_conn_st_ctx mstorm_st_context;
6845 struct regpair mstorm_st_padding[2];
6846 struct ustorm_roce_conn_st_ctx ustorm_st_context;
6847 struct regpair ustorm_st_padding[2];
6848};
6849
6850/* roce cqes statistics */
6851struct roce_cqe_stats {
6852 __le32 req_cqe_error;
6853 __le32 req_remote_access_errors;
6854 __le32 req_remote_invalid_request;
6855 __le32 resp_cqe_error;
6856 __le32 resp_local_length_error;
6857 __le32 reserved;
6858};
6859
6860/* roce create qp requester ramrod data */
6861struct roce_create_qp_req_ramrod_data {
6862 __le16 flags;
6863#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6864#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6865#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
6866#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
6867#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
6868#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
6869#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
6870#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
6871#define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1
6872#define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7
6873#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
6874#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
6875#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
6876#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
6877 u8 max_ord;
6878 u8 traffic_class;
6879 u8 hop_limit;
6880 u8 orq_num_pages;
6881 __le16 p_key;
6882 __le32 flow_label;
6883 __le32 dst_qp_id;
6884 __le32 ack_timeout_val;
6885 __le32 initial_psn;
6886 __le16 mtu;
6887 __le16 pd;
6888 __le16 sq_num_pages;
6889 __le16 low_latency_phy_queue;
6890 struct regpair sq_pbl_addr;
6891 struct regpair orq_pbl_addr;
6892 __le16 local_mac_addr[3];
6893 __le16 remote_mac_addr[3];
6894 __le16 vlan_id;
6895 __le16 udp_src_port;
6896 __le32 src_gid[4];
6897 __le32 dst_gid[4];
6898 __le32 cq_cid;
6899 struct regpair qp_handle_for_cqe;
6900 struct regpair qp_handle_for_async;
6901 u8 stats_counter_id;
6902 u8 vf_id;
6903 u8 vport_id;
6904 u8 flags2;
6905#define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1
6906#define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0
6907#define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6908#define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_SHIFT 1
6909#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FORCE_LB_MASK 0x1
6910#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FORCE_LB_SHIFT 2
6911#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1F
6912#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 3
6913 u8 name_space;
6914 u8 reserved3[3];
6915 __le16 regular_latency_phy_queue;
6916 __le16 dpi;
6917};
6918
6919/* roce create qp responder ramrod data */
6920struct roce_create_qp_resp_ramrod_data {
6921 __le32 flags;
6922#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6923#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6924#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
6925#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
6926#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
6927#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
6928#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
6929#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
6930#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
6931#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
6932#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
6933#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
6934#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
6935#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
6936#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
6937#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
6938#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
6939#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
6940#define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1
6941#define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16
6942#define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6943#define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_SHIFT 17
6944#define ROCE_CREATE_QP_RESP_RAMROD_DATA_FORCE_LB_MASK 0x1
6945#define ROCE_CREATE_QP_RESP_RAMROD_DATA_FORCE_LB_SHIFT 18
6946#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x1FFF
6947#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 19
6948 __le16 xrc_domain;
6949 u8 max_ird;
6950 u8 traffic_class;
6951 u8 hop_limit;
6952 u8 irq_num_pages;
6953 __le16 p_key;
6954 __le32 flow_label;
6955 __le32 dst_qp_id;
6956 u8 stats_counter_id;
6957 u8 reserved1;
6958 __le16 mtu;
6959 __le32 initial_psn;
6960 __le16 pd;
6961 __le16 rq_num_pages;
6962 struct rdma_srq_id srq_id;
6963 struct regpair rq_pbl_addr;
6964 struct regpair irq_pbl_addr;
6965 __le16 local_mac_addr[3];
6966 __le16 remote_mac_addr[3];
6967 __le16 vlan_id;
6968 __le16 udp_src_port;
6969 __le32 src_gid[4];
6970 __le32 dst_gid[4];
6971 struct regpair qp_handle_for_cqe;
6972 struct regpair qp_handle_for_async;
6973 __le16 low_latency_phy_queue;
6974 u8 vf_id;
6975 u8 vport_id;
6976 __le32 cq_cid;
6977 __le16 regular_latency_phy_queue;
6978 __le16 dpi;
6979 __le32 src_qp_id;
6980 u8 name_space;
6981 u8 reserved3[3];
6982};
6983
6984/* RoCE Create Suspended qp requester runtime ramrod data */
6985struct roce_create_suspended_qp_req_runtime_ramrod_data {
6986 __le32 flags;
6987#define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_MASK 0x1
6988#define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_SHIFT 0
6989#define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_RESERVED0_MASK \
6990 0x7FFFFFFF
6991#define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_RESERVED0_SHIFT 1
6992 __le32 send_msg_psn;
6993 __le32 inflight_sends;
6994 __le32 ssn;
6995};
6996
6997/* RoCE Create Suspended QP requester ramrod data */
6998struct roce_create_suspended_qp_req_ramrod_data {
6999 struct roce_create_qp_req_ramrod_data qp_params;
7000 struct roce_create_suspended_qp_req_runtime_ramrod_data
7001 qp_runtime_params;
7002};
7003
7004/* RoCE Create Suspended QP responder runtime params */
7005struct roce_create_suspended_qp_resp_runtime_params {
7006 __le32 flags;
7007#define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1
7008#define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_SHIFT 0
7009#define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1
7010#define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_SHIFT 1
7011#define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7012#define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_SHIFT 2
7013 __le32 receive_msg_psn;
7014 __le32 inflight_receives;
7015 __le32 rmsn;
7016 __le32 rdma_key;
7017 struct regpair rdma_va;
7018 __le32 rdma_length;
7019 __le32 num_rdb_entries;
7020 __le32 resreved;
7021};
7022
7023/* RoCE RDB array entry */
7024struct roce_resp_qp_rdb_entry {
7025 struct regpair atomic_data;
7026 struct regpair va;
7027 __le32 psn;
7028 __le32 rkey;
7029 __le32 byte_count;
7030 u8 op_type;
7031 u8 reserved[3];
7032};
7033
7034/* RoCE Create Suspended QP responder runtime ramrod data */
7035struct roce_create_suspended_qp_resp_runtime_ramrod_data {
7036 struct roce_create_suspended_qp_resp_runtime_params params;
7037 struct roce_resp_qp_rdb_entry
7038 rdb_array_entries[RDMA_MAX_IRQ_ELEMS_IN_PAGE];
7039};
7040
7041/* RoCE Create Suspended QP responder ramrod data */
7042struct roce_create_suspended_qp_resp_ramrod_data {
7043 struct roce_create_qp_resp_ramrod_data
7044 qp_params;
7045 struct roce_create_suspended_qp_resp_runtime_ramrod_data
7046 qp_runtime_params;
7047};
7048
7049/* RoCE create ud qp ramrod data */
7050struct roce_create_ud_qp_ramrod_data {
7051 __le16 local_mac_addr[3];
7052 __le16 vlan_id;
7053 __le32 src_qp_id;
7054 u8 name_space;
7055 u8 reserved[3];
7056};
7057
7058/* roce DCQCN received statistics */
7059struct roce_dcqcn_received_stats {
7060 struct regpair ecn_pkt_rcv;
7061 struct regpair cnp_pkt_rcv;
7062 struct regpair cnp_pkt_reject;
7063};
7064
7065/* roce DCQCN sent statistics */
7066struct roce_dcqcn_sent_stats {
7067 struct regpair cnp_pkt_sent;
7068};
7069
7070/* RoCE destroy qp requester output params */
7071struct roce_destroy_qp_req_output_params {
7072 __le32 cq_prod;
7073 __le32 reserved;
7074};
7075
7076/* RoCE destroy qp requester ramrod data */
7077struct roce_destroy_qp_req_ramrod_data {
7078 struct regpair output_params_addr;
7079};
7080
7081/* RoCE destroy qp responder output params */
7082struct roce_destroy_qp_resp_output_params {
7083 __le32 cq_prod;
7084 __le32 reserved;
7085};
7086
7087/* RoCE destroy qp responder ramrod data */
7088struct roce_destroy_qp_resp_ramrod_data {
7089 struct regpair output_params_addr;
7090 __le32 src_qp_id;
7091 __le32 reserved;
7092};
7093
7094/* RoCE destroy ud qp ramrod data */
7095struct roce_destroy_ud_qp_ramrod_data {
7096 __le32 src_qp_id;
7097 __le32 reserved;
7098};
7099
7100/* roce error statistics */
7101struct roce_error_stats {
7102 __le32 resp_remote_access_errors;
7103 __le32 reserved;
7104};
7105
7106/* roce special events statistics */
7107struct roce_events_stats {
7108 __le32 silent_drops;
7109 __le32 rnr_naks_sent;
7110 __le32 retransmit_count;
7111 __le32 icrc_error_count;
7112 __le32 implied_nak_seq_err;
7113 __le32 duplicate_request;
7114 __le32 local_ack_timeout_err;
7115 __le32 out_of_sequence;
7116 __le32 packet_seq_err;
7117 __le32 rnr_nak_retry_err;
7118};
7119
7120/* roce slow path EQ cmd IDs */
7121enum roce_event_opcode {
7122 ROCE_EVENT_CREATE_QP = 13,
7123 ROCE_EVENT_MODIFY_QP,
7124 ROCE_EVENT_QUERY_QP,
7125 ROCE_EVENT_DESTROY_QP,
7126 ROCE_EVENT_CREATE_UD_QP,
7127 ROCE_EVENT_DESTROY_UD_QP,
7128 ROCE_EVENT_FUNC_UPDATE,
7129 ROCE_EVENT_SUSPEND_QP,
7130 ROCE_EVENT_QUERY_SUSPENDED_QP,
7131 ROCE_EVENT_CREATE_SUSPENDED_QP,
7132 ROCE_EVENT_RESUME_QP,
7133 ROCE_EVENT_SUSPEND_UD_QP,
7134 ROCE_EVENT_RESUME_UD_QP,
7135 ROCE_EVENT_CREATE_SUSPENDED_UD_QP,
7136 ROCE_EVENT_FLUSH_DPT_QP,
7137 MAX_ROCE_EVENT_OPCODE
7138};
7139
7140/* roce func init ramrod data */
7141struct roce_init_func_params {
7142 u8 ll2_queue_id;
7143 u8 cnp_vlan_priority;
7144 u8 cnp_dscp;
7145 u8 flags;
7146#define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7147#define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
7148#define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7149#define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1
7150#define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK 0x3F
7151#define ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT 2
7152 __le32 cnp_send_timeout;
7153 __le16 rl_offset;
7154 u8 rl_count_log;
7155 u8 reserved1[5];
7156};
7157
7158/* roce func init ramrod data */
7159struct roce_init_func_ramrod_data {
7160 struct rdma_init_func_ramrod_data rdma;
7161 struct roce_init_func_params roce;
7162};
7163
7164/* roce_ll2_cqe_data */
7165struct roce_ll2_cqe_data {
7166 u8 name_space;
7167 u8 flags;
7168#define ROCE_LL2_CQE_DATA_QP_SUSPENDED_MASK 0x1
7169#define ROCE_LL2_CQE_DATA_QP_SUSPENDED_SHIFT 0
7170#define ROCE_LL2_CQE_DATA_RESERVED0_MASK 0x7F
7171#define ROCE_LL2_CQE_DATA_RESERVED0_SHIFT 1
7172 u8 reserved1[2];
7173 __le32 cid;
7174};
7175
7176/* roce modify qp requester ramrod data */
7177struct roce_modify_qp_req_ramrod_data {
7178 __le16 flags;
7179#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7180#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7181#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
7182#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
7183#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
7184#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
7185#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7186#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
7187#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7188#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
7189#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
7190#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
7191#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
7192#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
7193#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
7194#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
7195#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
7196#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
7197#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
7198#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
7199#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7200#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
7201#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7202#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 13
7203#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_FORCE_LB_MASK 0x1
7204#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_FORCE_LB_SHIFT 14
7205#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x1
7206#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 15
7207 u8 fields;
7208#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7209#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
7210#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7211#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
7212 u8 max_ord;
7213 u8 traffic_class;
7214 u8 hop_limit;
7215 __le16 p_key;
7216 __le32 flow_label;
7217 __le32 ack_timeout_val;
7218 __le16 mtu;
7219 __le16 reserved2;
7220 __le32 reserved3[2];
7221 __le16 low_latency_phy_queue;
7222 __le16 regular_latency_phy_queue;
7223 __le32 src_gid[4];
7224 __le32 dst_gid[4];
7225};
7226
7227/* roce modify qp responder ramrod data */
7228struct roce_modify_qp_resp_ramrod_data {
7229 __le16 flags;
7230#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7231#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7232#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7233#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
7234#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7235#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
7236#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7237#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
7238#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7239#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
7240#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7241#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
7242#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
7243#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
7244#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
7245#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
7246#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
7247#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
7248#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
7249#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
7250#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7251#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 10
7252#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_FORCE_LB_MASK 0x1
7253#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_FORCE_LB_SHIFT 11
7254#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0xF
7255#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 12
7256 u8 fields;
7257#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7258#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
7259#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7260#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
7261 u8 max_ird;
7262 u8 traffic_class;
7263 u8 hop_limit;
7264 __le16 p_key;
7265 __le32 flow_label;
7266 __le16 mtu;
7267 __le16 low_latency_phy_queue;
7268 __le16 regular_latency_phy_queue;
7269 u8 reserved2[6];
7270 __le32 src_gid[4];
7271 __le32 dst_gid[4];
7272};
7273
7274/* RoCE query qp requester output params */
7275struct roce_query_qp_req_output_params {
7276 __le32 psn;
7277 __le32 flags;
7278#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7279#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7280#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7281#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
7282#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7283#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
7284};
7285
7286/* RoCE query qp requester ramrod data */
7287struct roce_query_qp_req_ramrod_data {
7288 struct regpair output_params_addr;
7289};
7290
7291/* RoCE query qp responder output params */
7292struct roce_query_qp_resp_output_params {
7293 __le32 psn;
7294 __le32 flags;
7295#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
7296#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7297#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7298#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
7299};
7300
7301/* RoCE query qp responder ramrod data */
7302struct roce_query_qp_resp_ramrod_data {
7303 struct regpair output_params_addr;
7304};
7305
7306/* RoCE Query Suspended QP requester output params */
7307struct roce_query_suspended_qp_req_output_params {
7308 __le32 psn;
7309 __le32 flags;
7310#define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7311#define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7312#define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7313#define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 1
7314 __le32 send_msg_psn;
7315 __le32 inflight_sends;
7316 __le32 ssn;
7317 __le32 reserved;
7318};
7319
7320/* RoCE Query Suspended QP requester ramrod data */
7321struct roce_query_suspended_qp_req_ramrod_data {
7322 struct regpair output_params_addr;
7323};
7324
7325/* RoCE Query Suspended QP responder runtime params */
7326struct roce_query_suspended_qp_resp_runtime_params {
7327 __le32 psn;
7328 __le32 flags;
7329#define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1
7330#define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_SHIFT 0
7331#define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1
7332#define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_SHIFT 1
7333#define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7334#define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_SHIFT 2
7335 __le32 receive_msg_psn;
7336 __le32 inflight_receives;
7337 __le32 rmsn;
7338 __le32 rdma_key;
7339 struct regpair rdma_va;
7340 __le32 rdma_length;
7341 __le32 num_rdb_entries;
7342};
7343
7344/* RoCE Query Suspended QP responder output params */
7345struct roce_query_suspended_qp_resp_output_params {
7346 struct roce_query_suspended_qp_resp_runtime_params runtime_params;
7347 struct roce_resp_qp_rdb_entry
7348 rdb_array_entries[RDMA_MAX_IRQ_ELEMS_IN_PAGE];
7349};
7350
7351/* RoCE Query Suspended QP responder ramrod data */
7352struct roce_query_suspended_qp_resp_ramrod_data {
7353 struct regpair output_params_addr;
7354};
7355
7356/* ROCE ramrod command IDs */
7357enum roce_ramrod_cmd_id {
7358 ROCE_RAMROD_CREATE_QP = 13,
7359 ROCE_RAMROD_MODIFY_QP,
7360 ROCE_RAMROD_QUERY_QP,
7361 ROCE_RAMROD_DESTROY_QP,
7362 ROCE_RAMROD_CREATE_UD_QP,
7363 ROCE_RAMROD_DESTROY_UD_QP,
7364 ROCE_RAMROD_FUNC_UPDATE,
7365 ROCE_RAMROD_SUSPEND_QP,
7366 ROCE_RAMROD_QUERY_SUSPENDED_QP,
7367 ROCE_RAMROD_CREATE_SUSPENDED_QP,
7368 ROCE_RAMROD_RESUME_QP,
7369 ROCE_RAMROD_SUSPEND_UD_QP,
7370 ROCE_RAMROD_RESUME_UD_QP,
7371 ROCE_RAMROD_CREATE_SUSPENDED_UD_QP,
7372 ROCE_RAMROD_FLUSH_DPT_QP,
7373 MAX_ROCE_RAMROD_CMD_ID
7374};
7375
7376/* ROCE RDB array entry type */
7377enum roce_resp_qp_rdb_entry_type {
7378 ROCE_QP_RDB_ENTRY_RDMA_RESPONSE = 0,
7379 ROCE_QP_RDB_ENTRY_ATOMIC_RESPONSE = 1,
7380 ROCE_QP_RDB_ENTRY_INVALID = 2,
7381 MAX_ROCE_RESP_QP_RDB_ENTRY_TYPE
7382};
7383
7384/* RoCE func init ramrod data */
7385struct roce_update_func_params {
7386 u8 cnp_vlan_priority;
7387 u8 cnp_dscp;
7388 __le16 flags;
7389#define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7390#define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
7391#define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7392#define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1
7393#define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK 0x3FFF
7394#define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT 2
7395 __le32 cnp_send_timeout;
7396};
7397
7398struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
7399 u8 reserved0;
7400 u8 state;
7401 u8 flags0;
7402#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
7403#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
7404#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
7405#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
7406#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
7407#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
7408#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
7409#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
7410#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
7411#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
7412#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
7413#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
7414#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
7415#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
7416#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
7417#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
7418 u8 flags1;
7419#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
7420#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
7421#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
7422#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
7423#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
7424#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
7425#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
7426#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
7427#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
7428#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 4
7429#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
7430#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5
7431#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
7432#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
7433#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
7434#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
7435 u8 flags2;
7436#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
7437#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
7438#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
7439#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
7440#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
7441#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
7442#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
7443#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
7444 u8 flags3;
7445#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
7446#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
7447#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
7448#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
7449#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
7450#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
7451#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
7452#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
7453 u8 flags4;
7454#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
7455#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
7456#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
7457#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
7458#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
7459#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
7460#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
7461#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
7462 u8 flags5;
7463#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
7464#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
7465#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
7466#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
7467#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
7468#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
7469#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
7470#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
7471 u8 flags6;
7472#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
7473#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
7474#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
7475#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
7476#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
7477#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
7478#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
7479#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
7480 u8 flags7;
7481#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
7482#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
7483#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
7484#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
7485#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
7486#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
7487#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
7488#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
7489#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
7490#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
7491 u8 flags8;
7492#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
7493#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
7494#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
7495#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
7496#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
7497#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
7498#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
7499#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
7500#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
7501#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
7502#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
7503#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
7504#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
7505#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
7506#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
7507#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
7508 u8 flags9;
7509#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
7510#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
7511#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
7512#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
7513#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
7514#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
7515#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
7516#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
7517#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
7518#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
7519#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
7520#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
7521#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
7522#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
7523#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
7524#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
7525 u8 flags10;
7526#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
7527#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
7528#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
7529#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
7530#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
7531#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
7532#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
7533#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
7534#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
7535#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
7536#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
7537#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
7538#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
7539#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
7540#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
7541#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
7542 u8 flags11;
7543#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
7544#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
7545#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
7546#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
7547#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
7548#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
7549#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
7550#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
7551#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
7552#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
7553#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
7554#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
7555#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
7556#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
7557#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
7558#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
7559 u8 flags12;
7560#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
7561#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
7562#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
7563#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
7564#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
7565#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
7566#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
7567#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
7568#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
7569#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
7570#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
7571#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
7572#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
7573#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
7574#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
7575#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
7576 u8 flags13;
7577#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
7578#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
7579#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
7580#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
7581#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
7582#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
7583#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
7584#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
7585#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
7586#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
7587#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
7588#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
7589#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
7590#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
7591#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
7592#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
7593 u8 flags14;
7594#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
7595#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
7596#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
7597#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
7598#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
7599#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
7600#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
7601#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
7602#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
7603#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
7604#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
7605#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
7606 u8 byte2;
7607 __le16 physical_q0;
7608 __le16 word1;
7609 __le16 word2;
7610 __le16 word3;
7611 __le16 word4;
7612 __le16 word5;
7613 __le16 conn_dpi;
7614 u8 byte3;
7615 u8 byte4;
7616 u8 byte5;
7617 u8 byte6;
7618 __le32 reg0;
7619 __le32 reg1;
7620 __le32 reg2;
7621 __le32 snd_nxt_psn;
7622 __le32 reg4;
7623};
7624
7625struct mstorm_roce_conn_ag_ctx {
7626 u8 byte0;
7627 u8 byte1;
7628 u8 flags0;
7629#define MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
7630#define MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
7631#define MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
7632#define MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
7633#define MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7634#define MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2
7635#define MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
7636#define MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4
7637#define MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7638#define MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6
7639 u8 flags1;
7640#define MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
7641#define MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
7642#define MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
7643#define MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1
7644#define MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
7645#define MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2
7646#define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
7647#define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
7648#define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
7649#define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
7650#define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
7651#define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
7652#define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
7653#define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
7654#define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
7655#define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
7656 __le16 word0;
7657 __le16 word1;
7658 __le32 reg0;
7659 __le32 reg1;
7660};
7661
7662struct mstorm_roce_req_conn_ag_ctx {
7663 u8 byte0;
7664 u8 byte1;
7665 u8 flags0;
7666#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7667#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7668#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7669#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7670#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7671#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7672#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7673#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7674#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7675#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7676 u8 flags1;
7677#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7678#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7679#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7680#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7681#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7682#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7683#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7684#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
7685#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7686#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
7687#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7688#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
7689#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7690#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
7691#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7692#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
7693 __le16 word0;
7694 __le16 word1;
7695 __le32 reg0;
7696 __le32 reg1;
7697};
7698
7699struct mstorm_roce_resp_conn_ag_ctx {
7700 u8 byte0;
7701 u8 byte1;
7702 u8 flags0;
7703#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7704#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7705#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7706#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7707#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7708#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
7709#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7710#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
7711#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7712#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
7713 u8 flags1;
7714#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7715#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7716#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7717#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
7718#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7719#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
7720#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7721#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
7722#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7723#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
7724#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7725#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
7726#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7727#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
7728#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7729#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
7730 __le16 word0;
7731 __le16 word1;
7732 __le32 reg0;
7733 __le32 reg1;
7734};
7735
7736struct tstorm_roce_req_conn_ag_ctx {
7737 u8 reserved0;
7738 u8 state;
7739 u8 flags0;
7740#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7741#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7742#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
7743#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1
7744#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
7745#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2
7746#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
7747#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
7748#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7749#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7750#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
7751#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
7752#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
7753#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
7754 u8 flags1;
7755#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7756#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7757#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
7758#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
7759#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7760#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
7761#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7762#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7763 u8 flags2;
7764#define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3
7765#define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0
7766#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
7767#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
7768#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
7769#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
7770#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
7771#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
7772 u8 flags3;
7773#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
7774#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
7775#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
7776#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
7777#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
7778#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
7779#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7780#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5
7781#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
7782#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
7783#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7784#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
7785 u8 flags4;
7786#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7787#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7788#define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1
7789#define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT 1
7790#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
7791#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
7792#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
7793#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
7794#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
7795#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
7796#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
7797#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
7798#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
7799#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
7800#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7801#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
7802 u8 flags5;
7803#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7804#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7805#define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1
7806#define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_SHIFT 1
7807#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7808#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
7809#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7810#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
7811#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7812#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
7813#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
7814#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
7815#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7816#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
7817#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7818#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
7819 __le32 dif_rxmit_cnt;
7820 __le32 snd_nxt_psn;
7821 __le32 snd_max_psn;
7822 __le32 orq_prod;
7823 __le32 reg4;
7824 __le32 dif_acked_cnt;
7825 __le32 dif_cnt;
7826 __le32 reg7;
7827 __le32 reg8;
7828 u8 tx_cqe_error_type;
7829 u8 orq_cache_idx;
7830 __le16 snd_sq_cons_th;
7831 u8 byte4;
7832 u8 byte5;
7833 __le16 snd_sq_cons;
7834 __le16 conn_dpi;
7835 __le16 force_comp_cons;
7836 __le32 dif_rxmit_acked_cnt;
7837 __le32 reg10;
7838};
7839
7840struct tstorm_roce_resp_conn_ag_ctx {
7841 u8 byte0;
7842 u8 state;
7843 u8 flags0;
7844#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7845#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7846#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
7847#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
7848#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
7849#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
7850#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
7851#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
7852#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7853#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7854#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
7855#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
7856#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7857#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
7858 u8 flags1;
7859#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7860#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7861#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
7862#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
7863#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7864#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
7865#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7866#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7867 u8 flags2;
7868#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7869#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
7870#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7871#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
7872#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
7873#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
7874#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7875#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
7876 u8 flags3;
7877#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7878#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
7879#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7880#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
7881#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7882#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
7883#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7884#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5
7885#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
7886#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
7887#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7888#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
7889 u8 flags4;
7890#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7891#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7892#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7893#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 1
7894#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
7895#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
7896#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
7897#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
7898#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7899#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
7900#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7901#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
7902#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7903#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
7904#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7905#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
7906 u8 flags5;
7907#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7908#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
7909#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7910#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
7911#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7912#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
7913#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7914#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
7915#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7916#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
7917#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
7918#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
7919#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7920#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
7921#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
7922#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
7923 __le32 psn_and_rxmit_id_echo;
7924 __le32 reg1;
7925 __le32 reg2;
7926 __le32 reg3;
7927 __le32 reg4;
7928 __le32 reg5;
7929 __le32 reg6;
7930 __le32 reg7;
7931 __le32 reg8;
7932 u8 tx_async_error_type;
7933 u8 byte3;
7934 __le16 rq_cons;
7935 u8 byte4;
7936 u8 byte5;
7937 __le16 rq_prod;
7938 __le16 conn_dpi;
7939 __le16 irq_cons;
7940 __le32 reg9;
7941 __le32 reg10;
7942};
7943
7944struct ustorm_roce_req_conn_ag_ctx {
7945 u8 byte0;
7946 u8 byte1;
7947 u8 flags0;
7948#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7949#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7950#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7951#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7952#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7953#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7954#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7955#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7956#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7957#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7958 u8 flags1;
7959#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
7960#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
7961#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
7962#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
7963#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
7964#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
7965#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
7966#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
7967 u8 flags2;
7968#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7969#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7970#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7971#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7972#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7973#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7974#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
7975#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
7976#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
7977#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
7978#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
7979#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
7980#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
7981#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
7982#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7983#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
7984 u8 flags3;
7985#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7986#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7987#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7988#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
7989#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7990#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
7991#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7992#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
7993#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7994#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
7995#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
7996#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
7997#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7998#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
7999#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8000#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
8001 u8 byte2;
8002 u8 byte3;
8003 __le16 word0;
8004 __le16 word1;
8005 __le32 reg0;
8006 __le32 reg1;
8007 __le32 reg2;
8008 __le32 reg3;
8009 __le16 word2;
8010 __le16 word3;
8011};
8012
8013struct ustorm_roce_resp_conn_ag_ctx {
8014 u8 byte0;
8015 u8 byte1;
8016 u8 flags0;
8017#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8018#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8019#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8020#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8021#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8022#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8023#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8024#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8025#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8026#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
8027 u8 flags1;
8028#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8029#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
8030#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
8031#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
8032#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
8033#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
8034#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8035#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
8036 u8 flags2;
8037#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8038#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8039#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8040#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8041#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8042#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8043#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8044#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
8045#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
8046#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
8047#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
8048#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
8049#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8050#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
8051#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8052#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
8053 u8 flags3;
8054#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8055#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8056#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8057#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
8058#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8059#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
8060#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8061#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
8062#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8063#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
8064#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8065#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
8066#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8067#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
8068#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8069#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
8070 u8 byte2;
8071 u8 byte3;
8072 __le16 word0;
8073 __le16 word1;
8074 __le32 reg0;
8075 __le32 reg1;
8076 __le32 reg2;
8077 __le32 reg3;
8078 __le16 word2;
8079 __le16 word3;
8080};
8081
8082struct xstorm_roce_req_conn_ag_ctx {
8083 u8 reserved0;
8084 u8 state;
8085 u8 flags0;
8086#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8087#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8088#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
8089#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
8090#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
8091#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
8092#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8093#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8094#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
8095#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
8096#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
8097#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
8098#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
8099#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
8100#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
8101#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
8102 u8 flags1;
8103#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
8104#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
8105#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
8106#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
8107#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
8108#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
8109#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
8110#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
8111#define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8112#define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
8113#define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8114#define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
8115#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8116#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8117#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8118#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
8119 u8 flags2;
8120#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8121#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
8122#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8123#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
8124#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8125#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
8126#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8127#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
8128 u8 flags3;
8129#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8130#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
8131#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8132#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
8133#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
8134#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
8135#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8136#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8137 u8 flags4;
8138#define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3
8139#define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0
8140#define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3
8141#define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT 2
8142#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
8143#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
8144#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
8145#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
8146 u8 flags5;
8147#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
8148#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
8149#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
8150#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
8151#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
8152#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
8153#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
8154#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
8155 u8 flags6;
8156#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
8157#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
8158#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
8159#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
8160#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
8161#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
8162#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
8163#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
8164 u8 flags7;
8165#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
8166#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
8167#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
8168#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
8169#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8170#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8171#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8172#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
8173#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8174#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
8175 u8 flags8;
8176#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8177#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
8178#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8179#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
8180#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8181#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
8182#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8183#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
8184#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
8185#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
8186#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8187#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8188#define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
8189#define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT 6
8190#define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1
8191#define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7
8192 u8 flags9;
8193#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
8194#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
8195#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
8196#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
8197#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
8198#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
8199#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
8200#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
8201#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
8202#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
8203#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
8204#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
8205#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
8206#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
8207#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
8208#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
8209 u8 flags10;
8210#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
8211#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
8212#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
8213#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
8214#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
8215#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
8216#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
8217#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
8218#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8219#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8220#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
8221#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
8222#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8223#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
8224#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8225#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
8226 u8 flags11;
8227#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8228#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
8229#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8230#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
8231#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8232#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
8233#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8234#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
8235#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8236#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
8237#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
8238#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
8239#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8240#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8241#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
8242#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
8243 u8 flags12;
8244#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
8245#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
8246#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
8247#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
8248#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8249#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8250#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8251#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8252#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
8253#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
8254#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
8255#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
8256#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
8257#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
8258#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
8259#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
8260 u8 flags13;
8261#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
8262#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
8263#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
8264#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
8265#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8266#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8267#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8268#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8269#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8270#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8271#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8272#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8273#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8274#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8275#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8276#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8277 u8 flags14;
8278#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
8279#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
8280#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
8281#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
8282#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
8283#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
8284#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
8285#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
8286#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
8287#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
8288#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
8289#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
8290 u8 byte2;
8291 __le16 physical_q0;
8292 __le16 word1;
8293 __le16 sq_cmp_cons;
8294 __le16 sq_cons;
8295 __le16 sq_prod;
8296 __le16 dif_error_first_sq_cons;
8297 __le16 conn_dpi;
8298 u8 dif_error_sge_index;
8299 u8 byte4;
8300 u8 byte5;
8301 u8 byte6;
8302 __le32 lsn;
8303 __le32 ssn;
8304 __le32 snd_una_psn;
8305 __le32 snd_nxt_psn;
8306 __le32 dif_error_offset;
8307 __le32 orq_cons_th;
8308 __le32 orq_cons;
8309};
8310
8311struct xstorm_roce_resp_conn_ag_ctx {
8312 u8 reserved0;
8313 u8 state;
8314 u8 flags0;
8315#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8316#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8317#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
8318#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
8319#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
8320#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
8321#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8322#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8323#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
8324#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
8325#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
8326#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
8327#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
8328#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
8329#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
8330#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
8331 u8 flags1;
8332#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
8333#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
8334#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
8335#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
8336#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
8337#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
8338#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
8339#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
8340#define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8341#define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
8342#define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8343#define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
8344#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8345#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8346#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8347#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
8348 u8 flags2;
8349#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8350#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
8351#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8352#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
8353#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8354#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
8355#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8356#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
8357 u8 flags3;
8358#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
8359#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
8360#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8361#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
8362#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
8363#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
8364#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8365#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8366 u8 flags4;
8367#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8368#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
8369#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8370#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
8371#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8372#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
8373#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
8374#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
8375 u8 flags5;
8376#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
8377#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
8378#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
8379#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
8380#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
8381#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
8382#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
8383#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
8384 u8 flags6;
8385#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
8386#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
8387#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
8388#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
8389#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
8390#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
8391#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
8392#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
8393 u8 flags7;
8394#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
8395#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
8396#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
8397#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
8398#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8399#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8400#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8401#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
8402#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8403#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
8404 u8 flags8;
8405#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8406#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
8407#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8408#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
8409#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
8410#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
8411#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8412#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
8413#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
8414#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
8415#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8416#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8417#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8418#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
8419#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8420#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
8421 u8 flags9;
8422#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8423#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
8424#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
8425#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
8426#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
8427#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
8428#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
8429#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
8430#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
8431#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
8432#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
8433#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
8434#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
8435#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
8436#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
8437#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
8438 u8 flags10;
8439#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
8440#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
8441#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
8442#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
8443#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
8444#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
8445#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
8446#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
8447#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8448#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8449#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
8450#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
8451#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8452#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
8453#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8454#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
8455 u8 flags11;
8456#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8457#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
8458#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8459#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
8460#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8461#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
8462#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8463#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
8464#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8465#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
8466#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8467#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
8468#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8469#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8470#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
8471#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
8472 u8 flags12;
8473#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
8474#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
8475#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
8476#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1
8477#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8478#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8479#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8480#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8481#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
8482#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
8483#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
8484#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
8485#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
8486#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
8487#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
8488#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
8489 u8 flags13;
8490#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
8491#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
8492#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
8493#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
8494#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8495#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8496#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8497#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8498#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8499#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8500#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8501#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8502#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8503#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8504#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8505#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8506 u8 flags14;
8507#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
8508#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
8509#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
8510#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
8511#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
8512#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
8513#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
8514#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
8515#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
8516#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
8517#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
8518#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
8519#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
8520#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
8521 u8 byte2;
8522 __le16 physical_q0;
8523 __le16 irq_prod_shadow;
8524 __le16 word2;
8525 __le16 irq_cons;
8526 __le16 irq_prod;
8527 __le16 e5_reserved1;
8528 __le16 conn_dpi;
8529 u8 rxmit_opcode;
8530 u8 byte4;
8531 u8 byte5;
8532 u8 byte6;
8533 __le32 rxmit_psn_and_id;
8534 __le32 rxmit_bytes_length;
8535 __le32 psn;
8536 __le32 reg3;
8537 __le32 reg4;
8538 __le32 reg5;
8539 __le32 msn_and_syndrome;
8540};
8541
8542struct ystorm_roce_conn_ag_ctx {
8543 u8 byte0;
8544 u8 byte1;
8545 u8 flags0;
8546#define YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
8547#define YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
8548#define YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
8549#define YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
8550#define YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
8551#define YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2
8552#define YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
8553#define YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4
8554#define YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
8555#define YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6
8556 u8 flags1;
8557#define YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
8558#define YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
8559#define YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
8560#define YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1
8561#define YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
8562#define YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2
8563#define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
8564#define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
8565#define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
8566#define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
8567#define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
8568#define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
8569#define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
8570#define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
8571#define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
8572#define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
8573 u8 byte2;
8574 u8 byte3;
8575 __le16 word0;
8576 __le32 reg0;
8577 __le32 reg1;
8578 __le16 word1;
8579 __le16 word2;
8580 __le16 word3;
8581 __le16 word4;
8582 __le32 reg2;
8583 __le32 reg3;
8584};
8585
8586struct ystorm_roce_req_conn_ag_ctx {
8587 u8 byte0;
8588 u8 byte1;
8589 u8 flags0;
8590#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8591#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8592#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8593#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
8594#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8595#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
8596#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8597#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
8598#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8599#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
8600 u8 flags1;
8601#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8602#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8603#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8604#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
8605#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8606#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
8607#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8608#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
8609#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8610#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
8611#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8612#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
8613#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8614#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
8615#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8616#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
8617 u8 byte2;
8618 u8 byte3;
8619 __le16 word0;
8620 __le32 reg0;
8621 __le32 reg1;
8622 __le16 word1;
8623 __le16 word2;
8624 __le16 word3;
8625 __le16 word4;
8626 __le32 reg2;
8627 __le32 reg3;
8628};
8629
8630struct ystorm_roce_resp_conn_ag_ctx {
8631 u8 byte0;
8632 u8 byte1;
8633 u8 flags0;
8634#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8635#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8636#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8637#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8638#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8639#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8640#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8641#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8642#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8643#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
8644 u8 flags1;
8645#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8646#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8647#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8648#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8649#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8650#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8651#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8652#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
8653#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8654#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
8655#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8656#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
8657#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8658#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
8659#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8660#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
8661 u8 byte2;
8662 u8 byte3;
8663 __le16 word0;
8664 __le32 reg0;
8665 __le32 reg1;
8666 __le16 word1;
8667 __le16 word2;
8668 __le16 word3;
8669 __le16 word4;
8670 __le32 reg2;
8671 __le32 reg3;
8672};
8673
8674/* Roce doorbell data */
8675enum roce_flavor {
8676 PLAIN_ROCE,
8677 RROCE_IPV4,
8678 RROCE_IPV6,
8679 MAX_ROCE_FLAVOR
8680};
8681
8682/* The iwarp storm context of Ystorm */
8683struct ystorm_iwarp_conn_st_ctx {
8684 __le32 reserved[4];
8685};
8686
8687/* The iwarp storm context of Pstorm */
8688struct pstorm_iwarp_conn_st_ctx {
8689 __le32 reserved[36];
8690};
8691
8692/* The iwarp storm context of Xstorm */
8693struct xstorm_iwarp_conn_st_ctx {
8694 __le32 reserved[48];
8695};
8696
8697struct xstorm_iwarp_conn_ag_ctx {
8698 u8 reserved0;
8699 u8 state;
8700 u8 flags0;
8701#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8702#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8703#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
8704#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
8705#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
8706#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
8707#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8708#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8709#define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8710#define XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
8711#define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
8712#define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
8713#define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
8714#define XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
8715#define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
8716#define XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
8717 u8 flags1;
8718#define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
8719#define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
8720#define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
8721#define XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
8722#define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
8723#define XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
8724#define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
8725#define XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
8726#define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
8727#define XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
8728#define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
8729#define XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
8730#define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
8731#define XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
8732#define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
8733#define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
8734 u8 flags2;
8735#define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8736#define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
8737#define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
8738#define XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
8739#define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
8740#define XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
8741#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8742#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
8743 u8 flags3;
8744#define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8745#define XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
8746#define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8747#define XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
8748#define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8749#define XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
8750#define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8751#define XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
8752 u8 flags4;
8753#define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8754#define XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
8755#define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
8756#define XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
8757#define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
8758#define XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
8759#define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
8760#define XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
8761 u8 flags5;
8762#define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
8763#define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
8764#define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
8765#define XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
8766#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8767#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
8768#define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
8769#define XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
8770 u8 flags6;
8771#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
8772#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
8773#define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
8774#define XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
8775#define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
8776#define XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
8777#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
8778#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
8779 u8 flags7;
8780#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8781#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
8782#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
8783#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
8784#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8785#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8786#define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8787#define XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
8788#define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
8789#define XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
8790 u8 flags8;
8791#define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
8792#define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
8793#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
8794#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
8795#define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
8796#define XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
8797#define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
8798#define XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
8799#define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
8800#define XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
8801#define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
8802#define XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
8803#define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
8804#define XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
8805#define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
8806#define XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
8807 u8 flags9;
8808#define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
8809#define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
8810#define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
8811#define XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
8812#define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
8813#define XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
8814#define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
8815#define XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
8816#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8817#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
8818#define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
8819#define XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
8820#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
8821#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
8822#define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
8823#define XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
8824 u8 flags10;
8825#define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
8826#define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
8827#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
8828#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
8829#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
8830#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
8831#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
8832#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
8833#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8834#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8835#define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1
8836#define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT 5
8837#define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
8838#define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
8839#define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
8840#define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
8841 u8 flags11;
8842#define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
8843#define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
8844#define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
8845#define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
8846#define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
8847#define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
8848#define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
8849#define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
8850#define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
8851#define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
8852#define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
8853#define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
8854#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8855#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8856#define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
8857#define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
8858 u8 flags12;
8859#define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
8860#define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
8861#define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
8862#define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
8863#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8864#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8865#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8866#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8867#define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
8868#define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
8869#define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
8870#define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
8871#define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
8872#define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
8873#define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
8874#define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
8875 u8 flags13;
8876#define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
8877#define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
8878#define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
8879#define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
8880#define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
8881#define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
8882#define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
8883#define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
8884#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8885#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8886#define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
8887#define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
8888#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8889#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8890#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8891#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8892 u8 flags14;
8893#define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
8894#define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
8895#define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
8896#define XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
8897#define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
8898#define XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
8899#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
8900#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
8901#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
8902#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
8903#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
8904#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
8905#define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3
8906#define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT 6
8907 u8 byte2;
8908 __le16 physical_q0;
8909 __le16 physical_q1;
8910 __le16 sq_comp_cons;
8911 __le16 sq_tx_cons;
8912 __le16 sq_prod;
8913 __le16 word5;
8914 __le16 conn_dpi;
8915 u8 byte3;
8916 u8 byte4;
8917 u8 byte5;
8918 u8 byte6;
8919 __le32 reg0;
8920 __le32 reg1;
8921 __le32 reg2;
8922 __le32 more_to_send_seq;
8923 __le32 reg4;
8924 __le32 rewinded_snd_max_or_term_opcode;
8925 __le32 rd_msn;
8926 __le16 irq_prod_via_msdm;
8927 __le16 irq_cons;
8928 __le16 hq_cons_th_or_mpa_data;
8929 __le16 hq_cons;
8930 __le32 atom_msn;
8931 __le32 orq_cons;
8932 __le32 orq_cons_th;
8933 u8 byte7;
8934 u8 wqe_data_pad_bytes;
8935 u8 max_ord;
8936 u8 former_hq_prod;
8937 u8 irq_prod_via_msem;
8938 u8 byte12;
8939 u8 max_pkt_pdu_size_lo;
8940 u8 max_pkt_pdu_size_hi;
8941 u8 byte15;
8942 u8 e5_reserved;
8943 __le16 e5_reserved4;
8944 __le32 reg10;
8945 __le32 reg11;
8946 __le32 shared_queue_page_addr_lo;
8947 __le32 shared_queue_page_addr_hi;
8948 __le32 reg14;
8949 __le32 reg15;
8950 __le32 reg16;
8951 __le32 reg17;
8952};
8953
8954struct tstorm_iwarp_conn_ag_ctx {
8955 u8 reserved0;
8956 u8 state;
8957 u8 flags0;
8958#define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8959#define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8960#define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
8961#define TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
8962#define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
8963#define TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
8964#define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1
8965#define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3
8966#define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8967#define TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
8968#define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
8969#define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
8970#define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8971#define TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
8972 u8 flags1;
8973#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
8974#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
8975#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
8976#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2
8977#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8978#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
8979#define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8980#define TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
8981 u8 flags2;
8982#define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8983#define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
8984#define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8985#define TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
8986#define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8987#define TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
8988#define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8989#define TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
8990 u8 flags3;
8991#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
8992#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
8993#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
8994#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
8995#define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8996#define TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
8997#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
8998#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
8999#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
9000#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6
9001#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9002#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
9003 u8 flags4;
9004#define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
9005#define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
9006#define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
9007#define TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
9008#define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9009#define TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
9010#define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
9011#define TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
9012#define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
9013#define TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
9014#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9015#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5
9016#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
9017#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
9018#define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9019#define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
9020 u8 flags5;
9021#define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9022#define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
9023#define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9024#define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
9025#define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9026#define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
9027#define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9028#define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
9029#define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9030#define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
9031#define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
9032#define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
9033#define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9034#define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
9035#define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9036#define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
9037 __le32 reg0;
9038 __le32 reg1;
9039 __le32 unaligned_nxt_seq;
9040 __le32 reg3;
9041 __le32 reg4;
9042 __le32 reg5;
9043 __le32 reg6;
9044 __le32 reg7;
9045 __le32 reg8;
9046 u8 orq_cache_idx;
9047 u8 hq_prod;
9048 __le16 sq_tx_cons_th;
9049 u8 orq_prod;
9050 u8 irq_cons;
9051 __le16 sq_tx_cons;
9052 __le16 conn_dpi;
9053 __le16 rq_prod;
9054 __le32 snd_seq;
9055 __le32 last_hq_sequence;
9056};
9057
9058/* The iwarp storm context of Tstorm */
9059struct tstorm_iwarp_conn_st_ctx {
9060 __le32 reserved[60];
9061};
9062
9063/* The iwarp storm context of Mstorm */
9064struct mstorm_iwarp_conn_st_ctx {
9065 __le32 reserved[32];
9066};
9067
9068/* The iwarp storm context of Ustorm */
9069struct ustorm_iwarp_conn_st_ctx {
9070 struct regpair reserved[14];
9071};
9072
9073/* iwarp connection context */
9074struct iwarp_conn_context {
9075 struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
9076 struct regpair ystorm_st_padding[2];
9077 struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
9078 struct regpair pstorm_st_padding[2];
9079 struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
9080 struct xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
9081 struct tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
9082 struct timers_context timer_context;
9083 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
9084 struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
9085 struct regpair tstorm_st_padding[2];
9086 struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
9087 struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
9088 struct regpair ustorm_st_padding[2];
9089};
9090
9091/* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
9092struct iwarp_create_qp_ramrod_data {
9093 u8 flags;
9094#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
9095#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
9096#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
9097#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1
9098#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9099#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
9100#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9101#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
9102#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9103#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
9104#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
9105#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5
9106#define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1
9107#define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT 6
9108#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1
9109#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 7
9110 u8 reserved1;
9111 __le16 pd;
9112 __le16 sq_num_pages;
9113 __le16 rq_num_pages;
9114 __le32 reserved3[2];
9115 struct regpair qp_handle_for_cqe;
9116 struct rdma_srq_id srq_id;
9117 __le32 cq_cid_for_sq;
9118 __le32 cq_cid_for_rq;
9119 __le16 dpi;
9120 __le16 physical_q0;
9121 __le16 physical_q1;
9122 u8 reserved2[6];
9123};
9124
9125/* iWARP completion queue types */
9126enum iwarp_eqe_async_opcode {
9127 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
9128 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
9129 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE,
9130 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED,
9131 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED,
9132 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE,
9133 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW,
9134 IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT,
9135 IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY,
9136 MAX_IWARP_EQE_ASYNC_OPCODE
9137};
9138
9139struct iwarp_eqe_data_mpa_async_completion {
9140 __le16 ulp_data_len;
9141 u8 rtr_type_sent;
9142 u8 reserved[5];
9143};
9144
9145struct iwarp_eqe_data_tcp_async_completion {
9146 __le16 ulp_data_len;
9147 u8 mpa_handshake_mode;
9148 u8 reserved[5];
9149};
9150
9151/* iWARP completion queue types */
9152enum iwarp_eqe_sync_opcode {
9153 IWARP_EVENT_TYPE_TCP_OFFLOAD = 13,
9154 IWARP_EVENT_TYPE_MPA_OFFLOAD,
9155 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
9156 IWARP_EVENT_TYPE_CREATE_QP,
9157 IWARP_EVENT_TYPE_QUERY_QP,
9158 IWARP_EVENT_TYPE_MODIFY_QP,
9159 IWARP_EVENT_TYPE_DESTROY_QP,
9160 IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD,
9161 MAX_IWARP_EQE_SYNC_OPCODE
9162};
9163
9164/* iWARP EQE completion status */
9165enum iwarp_fw_return_code {
9166 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 6,
9167 IWARP_CONN_ERROR_TCP_CONNECTION_RST,
9168 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
9169 IWARP_CONN_ERROR_MPA_ERROR_REJECT,
9170 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER,
9171 IWARP_CONN_ERROR_MPA_RST,
9172 IWARP_CONN_ERROR_MPA_FIN,
9173 IWARP_CONN_ERROR_MPA_RTR_MISMATCH,
9174 IWARP_CONN_ERROR_MPA_INSUF_IRD,
9175 IWARP_CONN_ERROR_MPA_INVALID_PACKET,
9176 IWARP_CONN_ERROR_MPA_LOCAL_ERROR,
9177 IWARP_CONN_ERROR_MPA_TIMEOUT,
9178 IWARP_CONN_ERROR_MPA_TERMINATE,
9179 IWARP_QP_IN_ERROR_GOOD_CLOSE,
9180 IWARP_QP_IN_ERROR_BAD_CLOSE,
9181 IWARP_EXCEPTION_DETECTED_LLP_CLOSED,
9182 IWARP_EXCEPTION_DETECTED_LLP_RESET,
9183 IWARP_EXCEPTION_DETECTED_IRQ_FULL,
9184 IWARP_EXCEPTION_DETECTED_RQ_EMPTY,
9185 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT,
9186 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR,
9187 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW,
9188 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC,
9189 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR,
9190 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR,
9191 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED,
9192 MAX_IWARP_FW_RETURN_CODE
9193};
9194
9195/* unaligned opaque data received from LL2 */
9196struct iwarp_init_func_params {
9197 u8 ll2_ooo_q_index;
9198 u8 reserved1[7];
9199};
9200
9201/* iwarp func init ramrod data */
9202struct iwarp_init_func_ramrod_data {
9203 struct rdma_init_func_ramrod_data rdma;
9204 struct tcp_init_params tcp;
9205 struct iwarp_init_func_params iwarp;
9206};
9207
9208/* iWARP QP - possible states to transition to */
9209enum iwarp_modify_qp_new_state_type {
9210 IWARP_MODIFY_QP_STATE_CLOSING = 1,
9211 IWARP_MODIFY_QP_STATE_ERROR = 2,
9212 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
9213};
9214
9215/* iwarp modify qp responder ramrod data */
9216struct iwarp_modify_qp_ramrod_data {
9217 __le16 transition_to_state;
9218 __le16 flags;
9219#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9220#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
9221#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9222#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1
9223#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9224#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2
9225#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
9226#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3
9227#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
9228#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4
9229#define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
9230#define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 5
9231#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF
9232#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 6
9233 __le16 physical_q0;
9234 __le16 physical_q1;
9235 __le32 reserved1[10];
9236};
9237
9238/* MPA params for Enhanced mode */
9239struct mpa_rq_params {
9240 __le32 ird;
9241 __le32 ord;
9242};
9243
9244/* MPA host Address-Len for private data */
9245struct mpa_ulp_buffer {
9246 struct regpair addr;
9247 __le16 len;
9248 __le16 reserved[3];
9249};
9250
9251/* iWARP MPA offload params common to Basic and Enhanced modes */
9252struct mpa_outgoing_params {
9253 u8 crc_needed;
9254 u8 reject;
9255 u8 reserved[6];
9256 struct mpa_rq_params out_rq;
9257 struct mpa_ulp_buffer outgoing_ulp_buffer;
9258};
9259
9260/* iWARP MPA offload params passed by driver to FW in MPA Offload Request
9261 * Ramrod.
9262 */
9263struct iwarp_mpa_offload_ramrod_data {
9264 struct mpa_outgoing_params common;
9265 __le32 tcp_cid;
9266 u8 mode;
9267 u8 tcp_connect_side;
9268 u8 rtr_pref;
9269#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7
9270#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
9271#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
9272#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3
9273 u8 reserved2;
9274 struct mpa_ulp_buffer incoming_ulp_buffer;
9275 struct regpair async_eqe_output_buf;
9276 struct regpair handle_for_async;
9277 struct regpair shared_queue_addr;
9278 __le32 additional_setup_time;
9279 __le16 rcv_wnd;
9280 u8 stats_counter_id;
9281 u8 reserved3[9];
9282};
9283
9284/* iWARP TCP connection offload params passed by driver to FW */
9285struct iwarp_offload_params {
9286 struct mpa_ulp_buffer incoming_ulp_buffer;
9287 struct regpair async_eqe_output_buf;
9288 struct regpair handle_for_async;
9289 __le32 additional_setup_time;
9290 __le16 physical_q0;
9291 __le16 physical_q1;
9292 u8 stats_counter_id;
9293 u8 mpa_mode;
9294 u8 src_vport_id;
9295 u8 reserved[5];
9296};
9297
9298/* iWARP query QP output params */
9299struct iwarp_query_qp_output_params {
9300 __le32 flags;
9301#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
9302#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
9303#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
9304#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
9305 u8 reserved1[4];
9306};
9307
9308/* iWARP query QP ramrod data */
9309struct iwarp_query_qp_ramrod_data {
9310 struct regpair output_params_addr;
9311};
9312
9313/* iWARP Ramrod Command IDs */
9314enum iwarp_ramrod_cmd_id {
9315 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 13,
9316 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
9317 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
9318 IWARP_RAMROD_CMD_ID_CREATE_QP,
9319 IWARP_RAMROD_CMD_ID_QUERY_QP,
9320 IWARP_RAMROD_CMD_ID_MODIFY_QP,
9321 IWARP_RAMROD_CMD_ID_DESTROY_QP,
9322 IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD,
9323 MAX_IWARP_RAMROD_CMD_ID
9324};
9325
9326/* Per PF iWARP retransmit path statistics */
9327struct iwarp_rxmit_stats_drv {
9328 struct regpair tx_go_to_slow_start_event_cnt;
9329 struct regpair tx_fast_retransmit_event_cnt;
9330};
9331
9332/* iWARP and TCP connection offload params passed by driver to FW in iWARP
9333 * offload ramrod.
9334 */
9335struct iwarp_tcp_offload_ramrod_data {
9336 struct tcp_offload_params_opt2 tcp;
9337 struct iwarp_offload_params iwarp;
9338};
9339
9340/* iWARP MPA negotiation types */
9341enum mpa_negotiation_mode {
9342 MPA_NEGOTIATION_TYPE_BASIC = 1,
9343 MPA_NEGOTIATION_TYPE_ENHANCED = 2,
9344 MAX_MPA_NEGOTIATION_MODE
9345};
9346
9347/* iWARP MPA Enhanced mode RTR types */
9348enum mpa_rtr_type {
9349 MPA_RTR_TYPE_NONE = 0,
9350 MPA_RTR_TYPE_ZERO_SEND = 1,
9351 MPA_RTR_TYPE_ZERO_WRITE = 2,
9352 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3,
9353 MPA_RTR_TYPE_ZERO_READ = 4,
9354 MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5,
9355 MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6,
9356 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7,
9357 MAX_MPA_RTR_TYPE
9358};
9359
9360/* unaligned opaque data received from LL2 */
9361struct unaligned_opaque_data {
9362 __le16 first_mpa_offset;
9363 u8 tcp_payload_offset;
9364 u8 flags;
9365#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
9366#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
9367#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
9368#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1
9369#define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
9370#define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2
9371 __le32 cid;
9372};
9373
9374struct mstorm_iwarp_conn_ag_ctx {
9375 u8 reserved;
9376 u8 state;
9377 u8 flags0;
9378#define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9379#define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9380#define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9381#define MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9382#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
9383#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
9384#define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9385#define MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9386#define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9387#define MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
9388 u8 flags1;
9389#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
9390#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
9391#define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9392#define MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9393#define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9394#define MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9395#define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9396#define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
9397#define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9398#define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
9399#define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9400#define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
9401#define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
9402#define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
9403#define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9404#define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
9405 __le16 rcq_cons;
9406 __le16 rcq_cons_th;
9407 __le32 reg0;
9408 __le32 reg1;
9409};
9410
9411struct ustorm_iwarp_conn_ag_ctx {
9412 u8 reserved;
9413 u8 byte1;
9414 u8 flags0;
9415#define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9416#define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9417#define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9418#define USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9419#define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9420#define USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
9421#define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9422#define USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9423#define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9424#define USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
9425 u8 flags1;
9426#define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
9427#define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
9428#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
9429#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
9430#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
9431#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
9432#define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9433#define USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
9434 u8 flags2;
9435#define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9436#define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9437#define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9438#define USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9439#define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9440#define USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9441#define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
9442#define USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
9443#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
9444#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
9445#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
9446#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
9447#define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9448#define USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
9449#define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
9450#define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
9451 u8 flags3;
9452#define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
9453#define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
9454#define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9455#define USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
9456#define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9457#define USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
9458#define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9459#define USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
9460#define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9461#define USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
9462#define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
9463#define USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
9464#define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9465#define USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
9466#define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9467#define USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
9468 u8 byte2;
9469 u8 byte3;
9470 __le16 word0;
9471 __le16 word1;
9472 __le32 cq_cons;
9473 __le32 cq_se_prod;
9474 __le32 cq_prod;
9475 __le32 reg3;
9476 __le16 word2;
9477 __le16 word3;
9478};
9479
9480struct ystorm_iwarp_conn_ag_ctx {
9481 u8 byte0;
9482 u8 byte1;
9483 u8 flags0;
9484#define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
9485#define YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
9486#define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9487#define YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9488#define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9489#define YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
9490#define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9491#define YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9492#define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9493#define YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
9494 u8 flags1;
9495#define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9496#define YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9497#define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9498#define YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9499#define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9500#define YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9501#define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9502#define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
9503#define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9504#define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
9505#define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9506#define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
9507#define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9508#define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
9509#define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9510#define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
9511 u8 byte2;
9512 u8 byte3;
9513 __le16 word0;
9514 __le32 reg0;
9515 __le32 reg1;
9516 __le16 word1;
9517 __le16 word2;
9518 __le16 word3;
9519 __le16 word4;
9520 __le32 reg2;
9521 __le32 reg3;
9522};
9523
9524/* The fcoe storm context of Ystorm */
9525struct ystorm_fcoe_conn_st_ctx {
9526 u8 func_mode;
9527 u8 cos;
9528 u8 conf_version;
9529 u8 eth_hdr_size;
9530 __le16 stat_ram_addr;
9531 __le16 mtu;
9532 __le16 max_fc_payload_len;
9533 __le16 tx_max_fc_pay_len;
9534 u8 fcp_cmd_size;
9535 u8 fcp_rsp_size;
9536 __le16 mss;
9537 struct regpair reserved;
9538 __le16 min_frame_size;
9539 u8 protection_info_flags;
9540#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9541#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
9542#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9543#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
9544#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
9545#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
9546 u8 dst_protection_per_mss;
9547 u8 src_protection_per_mss;
9548 u8 ptu_log_page_size;
9549 u8 flags;
9550#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9551#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
9552#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9553#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
9554#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
9555#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
9556 u8 fcp_xfer_size;
9557};
9558
9559/* FCoE 16-bits vlan structure */
9560struct fcoe_vlan_fields {
9561 __le16 fields;
9562#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
9563#define FCOE_VLAN_FIELDS_VID_SHIFT 0
9564#define FCOE_VLAN_FIELDS_CLI_MASK 0x1
9565#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
9566#define FCOE_VLAN_FIELDS_PRI_MASK 0x7
9567#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
9568};
9569
9570/* FCoE 16-bits vlan union */
9571union fcoe_vlan_field_union {
9572 struct fcoe_vlan_fields fields;
9573 __le16 val;
9574};
9575
9576/* FCoE 16-bits vlan, vif union */
9577union fcoe_vlan_vif_field_union {
9578 union fcoe_vlan_field_union vlan;
9579 __le16 vif;
9580};
9581
9582/* Ethernet context section */
9583struct pstorm_fcoe_eth_context_section {
9584 u8 remote_addr_3;
9585 u8 remote_addr_2;
9586 u8 remote_addr_1;
9587 u8 remote_addr_0;
9588 u8 local_addr_1;
9589 u8 local_addr_0;
9590 u8 remote_addr_5;
9591 u8 remote_addr_4;
9592 u8 local_addr_5;
9593 u8 local_addr_4;
9594 u8 local_addr_3;
9595 u8 local_addr_2;
9596 union fcoe_vlan_vif_field_union vif_outer_vlan;
9597 __le16 vif_outer_eth_type;
9598 union fcoe_vlan_vif_field_union inner_vlan;
9599 __le16 inner_eth_type;
9600};
9601
9602/* The fcoe storm context of Pstorm */
9603struct pstorm_fcoe_conn_st_ctx {
9604 u8 func_mode;
9605 u8 cos;
9606 u8 conf_version;
9607 u8 rsrv;
9608 __le16 stat_ram_addr;
9609 __le16 mss;
9610 struct regpair abts_cleanup_addr;
9611 struct pstorm_fcoe_eth_context_section eth;
9612 u8 sid_2;
9613 u8 sid_1;
9614 u8 sid_0;
9615 u8 flags;
9616#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
9617#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
9618#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
9619#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
9620#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9621#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
9622#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9623#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
9624#define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1
9625#define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4
9626#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7
9627#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5
9628 u8 did_2;
9629 u8 did_1;
9630 u8 did_0;
9631 u8 src_mac_index;
9632 __le16 rec_rr_tov_val;
9633 u8 q_relative_offset;
9634 u8 reserved1;
9635};
9636
9637/* The fcoe storm context of Xstorm */
9638struct xstorm_fcoe_conn_st_ctx {
9639 u8 func_mode;
9640 u8 src_mac_index;
9641 u8 conf_version;
9642 u8 cached_wqes_avail;
9643 __le16 stat_ram_addr;
9644 u8 flags;
9645#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
9646#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
9647#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9648#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
9649#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
9650#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
9651#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
9652#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
9653#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
9654#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
9655 u8 cached_wqes_offset;
9656 u8 reserved2;
9657 u8 eth_hdr_size;
9658 u8 seq_id;
9659 u8 max_conc_seqs;
9660 __le16 num_pages_in_pbl;
9661 __le16 reserved;
9662 struct regpair sq_pbl_addr;
9663 struct regpair sq_curr_page_addr;
9664 struct regpair sq_next_page_addr;
9665 struct regpair xferq_pbl_addr;
9666 struct regpair xferq_curr_page_addr;
9667 struct regpair xferq_next_page_addr;
9668 struct regpair respq_pbl_addr;
9669 struct regpair respq_curr_page_addr;
9670 struct regpair respq_next_page_addr;
9671 __le16 mtu;
9672 __le16 tx_max_fc_pay_len;
9673 __le16 max_fc_payload_len;
9674 __le16 min_frame_size;
9675 __le16 sq_pbl_next_index;
9676 __le16 respq_pbl_next_index;
9677 u8 fcp_cmd_byte_credit;
9678 u8 fcp_rsp_byte_credit;
9679 __le16 protection_info;
9680#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
9681#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
9682#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9683#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
9684#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9685#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
9686#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
9687#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
9688#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
9689#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
9690#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
9691#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
9692 __le16 xferq_pbl_next_index;
9693 __le16 page_size;
9694 u8 mid_seq;
9695 u8 fcp_xfer_byte_credit;
9696 u8 reserved1[2];
9697 struct fcoe_wqe cached_wqes[16];
9698};
9699
9700struct xstorm_fcoe_conn_ag_ctx {
9701 u8 reserved0;
9702 u8 state;
9703 u8 flags0;
9704#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9705#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9706#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
9707#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
9708#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
9709#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
9710#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9711#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
9712#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
9713#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
9714#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
9715#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
9716#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
9717#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
9718#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
9719#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
9720 u8 flags1;
9721#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
9722#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
9723#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
9724#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
9725#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
9726#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
9727#define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
9728#define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
9729#define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
9730#define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
9731#define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
9732#define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
9733#define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
9734#define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
9735#define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
9736#define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
9737 u8 flags2;
9738#define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
9739#define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
9740#define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
9741#define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
9742#define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9743#define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
9744#define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
9745#define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
9746 u8 flags3;
9747#define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9748#define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
9749#define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9750#define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
9751#define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9752#define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
9753#define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9754#define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
9755 u8 flags4;
9756#define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9757#define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
9758#define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9759#define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
9760#define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9761#define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
9762#define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
9763#define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
9764 u8 flags5;
9765#define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
9766#define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
9767#define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
9768#define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
9769#define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
9770#define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
9771#define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
9772#define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
9773 u8 flags6;
9774#define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
9775#define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
9776#define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
9777#define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
9778#define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
9779#define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
9780#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
9781#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
9782 u8 flags7;
9783#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9784#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9785#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
9786#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
9787#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9788#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
9789#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
9790#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
9791#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
9792#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
9793 u8 flags8;
9794#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9795#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
9796#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
9797#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
9798#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9799#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
9800#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9801#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
9802#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9803#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
9804#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
9805#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
9806#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
9807#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
9808#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
9809#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
9810 u8 flags9;
9811#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
9812#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
9813#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
9814#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
9815#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
9816#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
9817#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
9818#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
9819#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
9820#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
9821#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
9822#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
9823#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
9824#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
9825#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
9826#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
9827 u8 flags10;
9828#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
9829#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
9830#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
9831#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
9832#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9833#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
9834#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
9835#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
9836#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9837#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
9838#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
9839#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
9840#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
9841#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
9842#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
9843#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
9844 u8 flags11;
9845#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
9846#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
9847#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
9848#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
9849#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
9850#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
9851#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
9852#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
9853#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
9854#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
9855#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
9856#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
9857#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9858#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
9859#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
9860#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
9861 u8 flags12;
9862#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
9863#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
9864#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
9865#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
9866#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9867#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
9868#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9869#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
9870#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
9871#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
9872#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
9873#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
9874#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
9875#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
9876#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
9877#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
9878 u8 flags13;
9879#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
9880#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
9881#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
9882#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
9883#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9884#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
9885#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9886#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
9887#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9888#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
9889#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9890#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
9891#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9892#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
9893#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9894#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
9895 u8 flags14;
9896#define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
9897#define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
9898#define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
9899#define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
9900#define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
9901#define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
9902#define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
9903#define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
9904#define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
9905#define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
9906#define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
9907#define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
9908#define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
9909#define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
9910 u8 byte2;
9911 __le16 physical_q0;
9912 __le16 word1;
9913 __le16 word2;
9914 __le16 sq_cons;
9915 __le16 sq_prod;
9916 __le16 xferq_prod;
9917 __le16 xferq_cons;
9918 u8 byte3;
9919 u8 byte4;
9920 u8 byte5;
9921 u8 byte6;
9922 __le32 remain_io;
9923 __le32 reg1;
9924 __le32 reg2;
9925 __le32 reg3;
9926 __le32 reg4;
9927 __le32 reg5;
9928 __le32 reg6;
9929 __le16 respq_prod;
9930 __le16 respq_cons;
9931 __le16 word9;
9932 __le16 word10;
9933 __le32 reg7;
9934 __le32 reg8;
9935};
9936
9937/* The fcoe storm context of Ustorm */
9938struct ustorm_fcoe_conn_st_ctx {
9939 struct regpair respq_pbl_addr;
9940 __le16 num_pages_in_pbl;
9941 u8 ptu_log_page_size;
9942 u8 log_page_size;
9943 __le16 respq_prod;
9944 u8 reserved[2];
9945};
9946
9947struct tstorm_fcoe_conn_ag_ctx {
9948 u8 reserved0;
9949 u8 state;
9950 u8 flags0;
9951#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9952#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9953#define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
9954#define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
9955#define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
9956#define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
9957#define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
9958#define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
9959#define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
9960#define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
9961#define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
9962#define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
9963#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
9964#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
9965 u8 flags1;
9966#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
9967#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
9968#define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9969#define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
9970#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
9971#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
9972#define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9973#define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
9974 u8 flags2;
9975#define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9976#define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
9977#define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9978#define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
9979#define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9980#define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
9981#define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9982#define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
9983 u8 flags3;
9984#define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9985#define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
9986#define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9987#define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
9988#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
9989#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
9990#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
9991#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
9992#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9993#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
9994#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
9995#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
9996 u8 flags4;
9997#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9998#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
9999#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10000#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
10001#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10002#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
10003#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
10004#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
10005#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
10006#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
10007#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
10008#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
10009#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
10010#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
10011#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10012#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
10013 u8 flags5;
10014#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10015#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10016#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10017#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
10018#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10019#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
10020#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10021#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
10022#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10023#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
10024#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10025#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
10026#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10027#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
10028#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10029#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
10030 __le32 reg0;
10031 __le32 reg1;
10032};
10033
10034struct ustorm_fcoe_conn_ag_ctx {
10035 u8 byte0;
10036 u8 byte1;
10037 u8 flags0;
10038#define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10039#define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10040#define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10041#define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10042#define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10043#define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10044#define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10045#define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10046#define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10047#define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
10048 u8 flags1;
10049#define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10050#define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
10051#define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10052#define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
10053#define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10054#define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
10055#define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10056#define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
10057 u8 flags2;
10058#define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10059#define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10060#define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10061#define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10062#define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10063#define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10064#define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
10065#define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
10066#define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10067#define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
10068#define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10069#define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
10070#define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10071#define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
10072#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10073#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
10074 u8 flags3;
10075#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10076#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10077#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10078#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
10079#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10080#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
10081#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10082#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
10083#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10084#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
10085#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10086#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
10087#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10088#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
10089#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10090#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
10091 u8 byte2;
10092 u8 byte3;
10093 __le16 word0;
10094 __le16 word1;
10095 __le32 reg0;
10096 __le32 reg1;
10097 __le32 reg2;
10098 __le32 reg3;
10099 __le16 word2;
10100 __le16 word3;
10101};
10102
10103/* The fcoe storm context of Tstorm */
10104struct tstorm_fcoe_conn_st_ctx {
10105 __le16 stat_ram_addr;
10106 __le16 rx_max_fc_payload_len;
10107 __le16 e_d_tov_val;
10108 u8 flags;
10109#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
10110#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
10111#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
10112#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
10113#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
10114#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
10115 u8 timers_cleanup_invocation_cnt;
10116 __le32 reserved1[2];
10117 __le32 dst_mac_address_bytes_0_to_3;
10118 __le16 dst_mac_address_bytes_4_to_5;
10119 __le16 ramrod_echo;
10120 u8 flags1;
10121#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
10122#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
10123#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
10124#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
10125 u8 cq_relative_offset;
10126 u8 cmdq_relative_offset;
10127 u8 bdq_resource_id;
10128 u8 reserved0[4];
10129};
10130
10131struct mstorm_fcoe_conn_ag_ctx {
10132 u8 byte0;
10133 u8 byte1;
10134 u8 flags0;
10135#define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10136#define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10137#define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10138#define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10139#define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10140#define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10141#define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10142#define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10143#define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10144#define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
10145 u8 flags1;
10146#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10147#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10148#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10149#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10150#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10151#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10152#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10153#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
10154#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10155#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
10156#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10157#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
10158#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10159#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
10160#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10161#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
10162 __le16 word0;
10163 __le16 word1;
10164 __le32 reg0;
10165 __le32 reg1;
10166};
10167
10168/* Fast path part of the fcoe storm context of Mstorm */
10169struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
10170 __le16 xfer_prod;
10171 u8 num_cqs;
10172 u8 reserved1;
10173 u8 protection_info;
10174#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
10175#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10176#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
10177#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1
10178#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
10179#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2
10180 u8 q_relative_offset;
10181 u8 reserved2[2];
10182};
10183
10184/* Non fast path part of the fcoe storm context of Mstorm */
10185struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
10186 __le16 conn_id;
10187 __le16 stat_ram_addr;
10188 __le16 num_pages_in_pbl;
10189 u8 ptu_log_page_size;
10190 u8 log_page_size;
10191 __le16 unsolicited_cq_count;
10192 __le16 cmdq_count;
10193 u8 bdq_resource_id;
10194 u8 reserved0[3];
10195 struct regpair xferq_pbl_addr;
10196 struct regpair reserved1;
10197 struct regpair reserved2[3];
10198};
10199
10200/* The fcoe storm context of Mstorm */
10201struct mstorm_fcoe_conn_st_ctx {
10202 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
10203 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
10204};
10205
10206/* fcoe connection context */
10207struct fcoe_conn_context {
10208 struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
10209 struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
10210 struct regpair pstorm_st_padding[2];
10211 struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
10212 struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
10213 struct regpair xstorm_ag_padding[6];
10214 struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
10215 struct regpair ustorm_st_padding[2];
10216 struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
10217 struct regpair tstorm_ag_padding[2];
10218 struct timers_context timer_context;
10219 struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
10220 struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
10221 struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
10222 struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
10223};
10224
10225/* FCoE connection offload params passed by driver to FW in FCoE offload
10226 * ramrod.
10227 */
10228struct fcoe_conn_offload_ramrod_params {
10229 struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
10230};
10231
10232/* FCoE connection terminate params passed by driver to FW in FCoE terminate
10233 * conn ramrod.
10234 */
10235struct fcoe_conn_terminate_ramrod_params {
10236 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
10237};
10238
10239/* FCoE event type */
10240enum fcoe_event_type {
10241 FCOE_EVENT_INIT_FUNC,
10242 FCOE_EVENT_DESTROY_FUNC,
10243 FCOE_EVENT_STAT_FUNC,
10244 FCOE_EVENT_OFFLOAD_CONN,
10245 FCOE_EVENT_TERMINATE_CONN,
10246 FCOE_EVENT_ERROR,
10247 MAX_FCOE_EVENT_TYPE
10248};
10249
10250/* FCoE init params passed by driver to FW in FCoE init ramrod */
10251struct fcoe_init_ramrod_params {
10252 struct fcoe_init_func_ramrod_data init_ramrod_data;
10253};
10254
10255/* FCoE ramrod Command IDs */
10256enum fcoe_ramrod_cmd_id {
10257 FCOE_RAMROD_CMD_ID_INIT_FUNC,
10258 FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
10259 FCOE_RAMROD_CMD_ID_STAT_FUNC,
10260 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
10261 FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
10262 MAX_FCOE_RAMROD_CMD_ID
10263};
10264
10265/* FCoE statistics params buffer passed by driver to FW in FCoE statistics
10266 * ramrod.
10267 */
10268struct fcoe_stat_ramrod_params {
10269 struct fcoe_stat_ramrod_data stat_ramrod_data;
10270};
10271
10272struct ystorm_fcoe_conn_ag_ctx {
10273 u8 byte0;
10274 u8 byte1;
10275 u8 flags0;
10276#define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10277#define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10278#define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10279#define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10280#define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10281#define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10282#define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10283#define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10284#define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10285#define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
10286 u8 flags1;
10287#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10288#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10289#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10290#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10291#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10292#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10293#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10294#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
10295#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10296#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
10297#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10298#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
10299#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10300#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
10301#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10302#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
10303 u8 byte2;
10304 u8 byte3;
10305 __le16 word0;
10306 __le32 reg0;
10307 __le32 reg1;
10308 __le16 word1;
10309 __le16 word2;
10310 __le16 word3;
10311 __le16 word4;
10312 __le32 reg2;
10313 __le32 reg3;
10314};
10315
10316/* The iscsi storm connection context of Ystorm */
10317struct ystorm_iscsi_conn_st_ctx {
10318 __le32 reserved[8];
10319};
10320
10321/* Combined iSCSI and TCP storm connection of Pstorm */
10322struct pstorm_iscsi_tcp_conn_st_ctx {
10323 __le32 tcp[32];
10324 __le32 iscsi[4];
10325};
10326
10327/* The combined tcp and iscsi storm context of Xstorm */
10328struct xstorm_iscsi_tcp_conn_st_ctx {
10329 __le32 reserved_tcp[4];
10330 __le32 reserved_iscsi[44];
10331};
10332
10333struct xstorm_iscsi_conn_ag_ctx {
10334 u8 cdu_validation;
10335 u8 state;
10336 u8 flags0;
10337#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10338#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10339#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
10340#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
10341#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
10342#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
10343#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10344#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
10345#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10346#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
10347#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
10348#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
10349#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
10350#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
10351#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
10352#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
10353 u8 flags1;
10354#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
10355#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
10356#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
10357#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
10358#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
10359#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
10360#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
10361#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
10362#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
10363#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
10364#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
10365#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
10366#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
10367#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
10368#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
10369#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
10370 u8 flags2;
10371#define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10372#define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
10373#define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10374#define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
10375#define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10376#define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
10377#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10378#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
10379 u8 flags3;
10380#define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10381#define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
10382#define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10383#define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
10384#define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10385#define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
10386#define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10387#define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
10388 u8 flags4;
10389#define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10390#define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
10391#define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
10392#define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
10393#define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10394#define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
10395#define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
10396#define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
10397 u8 flags5;
10398#define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
10399#define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
10400#define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
10401#define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
10402#define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
10403#define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
10404#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
10405#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
10406 u8 flags6;
10407#define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
10408#define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
10409#define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
10410#define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
10411#define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
10412#define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
10413#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
10414#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
10415 u8 flags7;
10416#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
10417#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
10418#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
10419#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
10420#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10421#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
10422#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10423#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
10424#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10425#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
10426 u8 flags8;
10427#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10428#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
10429#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10430#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
10431#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10432#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
10433#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10434#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
10435#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10436#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
10437#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10438#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
10439#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10440#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
10441#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
10442#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
10443 u8 flags9;
10444#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
10445#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
10446#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
10447#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
10448#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
10449#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
10450#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
10451#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
10452#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
10453#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
10454#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
10455#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
10456#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
10457#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
10458#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
10459#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
10460 u8 flags10;
10461#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
10462#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
10463#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
10464#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
10465#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
10466#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
10467#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
10468#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
10469#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10470#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
10471#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
10472#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
10473#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10474#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
10475#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
10476#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
10477 u8 flags11;
10478#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
10479#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
10480#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10481#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
10482#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
10483#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
10484#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10485#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
10486#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10487#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
10488#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10489#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
10490#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10491#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
10492#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
10493#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
10494 u8 flags12;
10495#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
10496#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
10497#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
10498#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
10499#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10500#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
10501#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10502#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
10503#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
10504#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
10505#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
10506#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
10507#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
10508#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
10509#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
10510#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
10511 u8 flags13;
10512#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
10513#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
10514#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
10515#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
10516#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10517#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
10518#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10519#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
10520#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10521#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
10522#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10523#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
10524#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10525#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
10526#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10527#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
10528 u8 flags14;
10529#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
10530#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
10531#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
10532#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
10533#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
10534#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
10535#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
10536#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
10537#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
10538#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
10539#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
10540#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
10541#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
10542#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
10543 u8 byte2;
10544 __le16 physical_q0;
10545 __le16 physical_q1;
10546 __le16 dummy_dorq_var;
10547 __le16 sq_cons;
10548 __le16 sq_prod;
10549 __le16 word5;
10550 __le16 slow_io_total_data_tx_update;
10551 u8 byte3;
10552 u8 byte4;
10553 u8 byte5;
10554 u8 byte6;
10555 __le32 reg0;
10556 __le32 reg1;
10557 __le32 reg2;
10558 __le32 more_to_send_seq;
10559 __le32 reg4;
10560 __le32 reg5;
10561 __le32 hq_scan_next_relevant_ack;
10562 __le16 r2tq_prod;
10563 __le16 r2tq_cons;
10564 __le16 hq_prod;
10565 __le16 hq_cons;
10566 __le32 remain_seq;
10567 __le32 bytes_to_next_pdu;
10568 __le32 hq_tcp_seq;
10569 u8 byte7;
10570 u8 byte8;
10571 u8 byte9;
10572 u8 byte10;
10573 u8 byte11;
10574 u8 byte12;
10575 u8 byte13;
10576 u8 byte14;
10577 u8 byte15;
10578 u8 e5_reserved;
10579 __le16 word11;
10580 __le32 reg10;
10581 __le32 reg11;
10582 __le32 exp_stat_sn;
10583 __le32 ongoing_fast_rxmit_seq;
10584 __le32 reg14;
10585 __le32 reg15;
10586 __le32 reg16;
10587 __le32 reg17;
10588};
10589
10590struct tstorm_iscsi_conn_ag_ctx {
10591 u8 reserved0;
10592 u8 state;
10593 u8 flags0;
10594#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10595#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10596#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10597#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10598#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
10599#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
10600#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
10601#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
10602#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10603#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
10604#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
10605#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
10606#define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10607#define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
10608 u8 flags1;
10609#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
10610#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
10611#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
10612#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
10613#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10614#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
10615#define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10616#define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
10617 u8 flags2;
10618#define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10619#define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
10620#define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10621#define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
10622#define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10623#define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
10624#define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10625#define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
10626 u8 flags3;
10627#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10628#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
10629#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3
10630#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_SHIFT 2
10631#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10632#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
10633#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
10634#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
10635#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
10636#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
10637#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10638#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
10639 u8 flags4;
10640#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10641#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
10642#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10643#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
10644#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10645#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
10646#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10647#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
10648#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10649#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
10650#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10651#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
10652#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1
10653#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_SHIFT 6
10654#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10655#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
10656 u8 flags5;
10657#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10658#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10659#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10660#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
10661#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10662#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
10663#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10664#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
10665#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10666#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
10667#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10668#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
10669#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10670#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
10671#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10672#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
10673 __le32 reg0;
10674 __le32 reg1;
10675 __le32 rx_tcp_checksum_err_cnt;
10676 __le32 reg3;
10677 __le32 reg4;
10678 __le32 reg5;
10679 __le32 reg6;
10680 __le32 reg7;
10681 __le32 reg8;
10682 u8 cid_offload_cnt;
10683 u8 byte3;
10684 __le16 word0;
10685};
10686
10687struct ustorm_iscsi_conn_ag_ctx {
10688 u8 byte0;
10689 u8 byte1;
10690 u8 flags0;
10691#define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10692#define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10693#define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10694#define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10695#define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10696#define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10697#define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10698#define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10699#define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10700#define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
10701 u8 flags1;
10702#define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
10703#define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
10704#define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10705#define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
10706#define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10707#define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
10708#define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10709#define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
10710 u8 flags2;
10711#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10712#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10713#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10714#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10715#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10716#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10717#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
10718#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
10719#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10720#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
10721#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10722#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
10723#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10724#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
10725#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10726#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
10727 u8 flags3;
10728#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10729#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10730#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10731#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
10732#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10733#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
10734#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10735#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
10736#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10737#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
10738#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10739#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
10740#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10741#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
10742#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10743#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
10744 u8 byte2;
10745 u8 byte3;
10746 __le16 word0;
10747 __le16 word1;
10748 __le32 reg0;
10749 __le32 reg1;
10750 __le32 reg2;
10751 __le32 reg3;
10752 __le16 word2;
10753 __le16 word3;
10754};
10755
10756/* The iscsi storm connection context of Tstorm */
10757struct tstorm_iscsi_conn_st_ctx {
10758 __le32 reserved[44];
10759};
10760
10761struct mstorm_iscsi_conn_ag_ctx {
10762 u8 reserved;
10763 u8 state;
10764 u8 flags0;
10765#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10766#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10767#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10768#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10769#define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10770#define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10771#define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10772#define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10773#define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10774#define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
10775 u8 flags1;
10776#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10777#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10778#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10779#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10780#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10781#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10782#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10783#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
10784#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10785#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
10786#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10787#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
10788#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10789#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
10790#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10791#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
10792 __le16 word0;
10793 __le16 word1;
10794 __le32 reg0;
10795 __le32 reg1;
10796};
10797
10798/* Combined iSCSI and TCP storm connection of Mstorm */
10799struct mstorm_iscsi_tcp_conn_st_ctx {
10800 __le32 reserved_tcp[20];
10801 __le32 reserved_iscsi[12];
10802};
10803
10804/* The iscsi storm context of Ustorm */
10805struct ustorm_iscsi_conn_st_ctx {
10806 __le32 reserved[52];
10807};
10808
10809/* iscsi connection context */
10810struct iscsi_conn_context {
10811 struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
10812 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
10813 struct regpair pstorm_st_padding[2];
10814 struct pb_context xpb2_context;
10815 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
10816 struct regpair xstorm_st_padding[2];
10817 struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
10818 struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
10819 struct regpair tstorm_ag_padding[2];
10820 struct timers_context timer_context;
10821 struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
10822 struct pb_context upb_context;
10823 struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
10824 struct regpair tstorm_st_padding[2];
10825 struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
10826 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
10827 struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
10828};
10829
10830/* iSCSI init params passed by driver to FW in iSCSI init ramrod */
10831struct iscsi_init_ramrod_params {
10832 struct iscsi_spe_func_init iscsi_init_spe;
10833 struct tcp_init_params tcp_init;
10834};
10835
10836struct ystorm_iscsi_conn_ag_ctx {
10837 u8 byte0;
10838 u8 byte1;
10839 u8 flags0;
10840#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10841#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10842#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10843#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10844#define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10845#define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10846#define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10847#define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10848#define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10849#define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
10850 u8 flags1;
10851#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10852#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10853#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10854#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10855#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10856#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10857#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10858#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
10859#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10860#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
10861#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10862#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
10863#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10864#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
10865#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10866#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
10867 u8 byte2;
10868 u8 byte3;
10869 __le16 word0;
10870 __le32 reg0;
10871 __le32 reg1;
10872 __le16 word1;
10873 __le16 word2;
10874 __le16 word3;
10875 __le16 word4;
10876 __le32 reg2;
10877 __le32 reg3;
10878};
10879
10880#endif
10881

source code of linux/drivers/net/ethernet/qlogic/qed/qed_hsi.h