| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Microchip KSZ9477 register definitions |
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| 4 | * |
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| 5 | * Copyright (C) 2017-2025 Microchip Technology Inc. |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __KSZ9477_REGS_H |
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| 9 | #define __KSZ9477_REGS_H |
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| 10 | |
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| 11 | #define KS_PRIO_M 0x7 |
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| 12 | #define KS_PRIO_S 4 |
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| 13 | |
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| 14 | /* 0 - Operation */ |
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| 15 | #define REG_CHIP_ID0__1 0x0000 |
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| 16 | |
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| 17 | #define REG_CHIP_ID1__1 0x0001 |
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| 18 | |
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| 19 | #define FAMILY_ID 0x95 |
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| 20 | #define FAMILY_ID_94 0x94 |
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| 21 | #define FAMILY_ID_95 0x95 |
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| 22 | #define FAMILY_ID_85 0x85 |
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| 23 | #define FAMILY_ID_98 0x98 |
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| 24 | #define FAMILY_ID_88 0x88 |
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| 25 | |
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| 26 | #define REG_CHIP_ID2__1 0x0002 |
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| 27 | |
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| 28 | #define CHIP_ID_66 0x66 |
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| 29 | #define CHIP_ID_67 0x67 |
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| 30 | #define CHIP_ID_77 0x77 |
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| 31 | #define CHIP_ID_93 0x93 |
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| 32 | #define CHIP_ID_96 0x96 |
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| 33 | #define CHIP_ID_97 0x97 |
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| 34 | |
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| 35 | #define REG_CHIP_ID3__1 0x0003 |
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| 36 | |
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| 37 | #define SWITCH_REVISION_M 0x0F |
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| 38 | #define SWITCH_REVISION_S 4 |
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| 39 | #define SWITCH_RESET 0x01 |
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| 40 | |
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| 41 | #define REG_GLOBAL_OPTIONS 0x000F |
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| 42 | |
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| 43 | #define SW_GIGABIT_ABLE BIT(6) |
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| 44 | #define SW_REDUNDANCY_ABLE BIT(5) |
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| 45 | #define SW_AVB_ABLE BIT(4) |
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| 46 | #define SW_9567_RL_5_2 0xC |
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| 47 | #define SW_9477_SL_5_2 0xD |
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| 48 | |
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| 49 | #define SW_9896_GL_5_1 0xB |
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| 50 | #define SW_9896_RL_5_1 0x8 |
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| 51 | #define SW_9896_SL_5_1 0x9 |
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| 52 | |
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| 53 | #define SW_9895_GL_4_1 0x7 |
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| 54 | #define SW_9895_RL_4_1 0x4 |
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| 55 | #define SW_9895_SL_4_1 0x5 |
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| 56 | |
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| 57 | #define SW_9896_RL_4_2 0x6 |
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| 58 | |
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| 59 | #define SW_9893_RL_2_1 0x0 |
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| 60 | #define SW_9893_SL_2_1 0x1 |
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| 61 | #define SW_9893_GL_2_1 0x3 |
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| 62 | |
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| 63 | #define SW_QW_ABLE BIT(5) |
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| 64 | #define SW_9893_RN_2_1 0xC |
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| 65 | |
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| 66 | #define REG_SW_INT_STATUS__4 0x0010 |
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| 67 | #define REG_SW_INT_MASK__4 0x0014 |
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| 68 | |
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| 69 | #define LUE_INT BIT(31) |
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| 70 | #define TRIG_TS_INT BIT(30) |
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| 71 | #define APB_TIMEOUT_INT BIT(29) |
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| 72 | |
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| 73 | #define SWITCH_INT_MASK (TRIG_TS_INT | APB_TIMEOUT_INT) |
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| 74 | |
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| 75 | #define REG_SW_PORT_INT_STATUS__4 0x0018 |
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| 76 | #define REG_SW_PORT_INT_MASK__4 0x001C |
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| 77 | #define REG_SW_PHY_INT_STATUS 0x0020 |
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| 78 | #define REG_SW_PHY_INT_ENABLE 0x0024 |
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| 79 | |
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| 80 | /* 1 - Global */ |
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| 81 | #define REG_SW_GLOBAL_SERIAL_CTRL_0 0x0100 |
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| 82 | #define SW_SPARE_REG_2 BIT(7) |
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| 83 | #define SW_SPARE_REG_1 BIT(6) |
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| 84 | #define SW_SPARE_REG_0 BIT(5) |
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| 85 | #define SW_BIG_ENDIAN BIT(4) |
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| 86 | #define SPI_AUTO_EDGE_DETECTION BIT(1) |
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| 87 | #define SPI_CLOCK_OUT_RISING_EDGE BIT(0) |
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| 88 | |
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| 89 | #define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103 |
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| 90 | #define SW_ENABLE_REFCLKO BIT(1) |
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| 91 | #define SW_REFCLKO_IS_125MHZ BIT(0) |
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| 92 | |
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| 93 | #define REG_SW_IBA__4 0x0104 |
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| 94 | |
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| 95 | #define SW_IBA_ENABLE BIT(31) |
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| 96 | #define SW_IBA_DA_MATCH BIT(30) |
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| 97 | #define SW_IBA_INIT BIT(29) |
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| 98 | #define SW_IBA_QID_M 0xF |
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| 99 | #define SW_IBA_QID_S 22 |
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| 100 | #define SW_IBA_PORT_M 0x2F |
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| 101 | #define SW_IBA_PORT_S 16 |
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| 102 | #define SW_IBA_FRAME_TPID_M 0xFFFF |
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| 103 | |
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| 104 | #define REG_SW_APB_TIMEOUT_ADDR__4 0x0108 |
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| 105 | |
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| 106 | #define APB_TIMEOUT_ACKNOWLEDGE BIT(31) |
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| 107 | |
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| 108 | #define REG_SW_IBA_SYNC__1 0x010C |
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| 109 | |
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| 110 | #define REG_SW_IBA_STATUS__4 0x0110 |
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| 111 | |
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| 112 | #define SW_IBA_REQ BIT(31) |
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| 113 | #define SW_IBA_RESP BIT(30) |
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| 114 | #define SW_IBA_DA_MISMATCH BIT(14) |
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| 115 | #define SW_IBA_FMT_MISMATCH BIT(13) |
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| 116 | #define SW_IBA_CODE_ERROR BIT(12) |
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| 117 | #define SW_IBA_CMD_ERROR BIT(11) |
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| 118 | #define SW_IBA_CMD_LOC_M (BIT(6) - 1) |
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| 119 | |
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| 120 | #define REG_SW_IBA_STATES__4 0x0114 |
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| 121 | |
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| 122 | #define SW_IBA_BUF_STATE_S 30 |
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| 123 | #define SW_IBA_CMD_STATE_S 28 |
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| 124 | #define SW_IBA_RESP_STATE_S 26 |
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| 125 | #define SW_IBA_STATE_M 0x3 |
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| 126 | #define SW_IBA_PACKET_SIZE_M 0x7F |
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| 127 | #define SW_IBA_PACKET_SIZE_S 16 |
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| 128 | #define SW_IBA_FMT_ID_M 0xFFFF |
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| 129 | |
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| 130 | #define REG_SW_IBA_RESULT__4 0x0118 |
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| 131 | |
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| 132 | #define SW_IBA_SIZE_S 24 |
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| 133 | |
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| 134 | #define SW_IBA_RETRY_CNT_M (BIT(5) - 1) |
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| 135 | |
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| 136 | /* 2 - PHY */ |
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| 137 | #define REG_SW_POWER_MANAGEMENT_CTRL 0x0201 |
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| 138 | |
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| 139 | #define SW_PLL_POWER_DOWN BIT(5) |
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| 140 | #define SW_POWER_DOWN_MODE 0x3 |
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| 141 | #define SW_ENERGY_DETECTION 1 |
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| 142 | #define SW_SOFT_POWER_DOWN 2 |
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| 143 | #define SW_POWER_SAVING 3 |
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| 144 | |
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| 145 | /* 3 - Operation Control */ |
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| 146 | #define REG_SW_OPERATION 0x0300 |
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| 147 | |
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| 148 | #define SW_DOUBLE_TAG BIT(7) |
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| 149 | #define SW_RESET BIT(1) |
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| 150 | |
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| 151 | #define REG_SW_MTU__2 0x0308 |
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| 152 | #define REG_SW_MTU_MASK GENMASK(13, 0) |
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| 153 | |
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| 154 | #define REG_SW_ISP_TPID__2 0x030A |
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| 155 | |
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| 156 | #define REG_SW_HSR_TPID__2 0x030C |
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| 157 | |
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| 158 | #define REG_AVB_STRATEGY__2 0x030E |
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| 159 | |
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| 160 | #define SW_SHAPING_CREDIT_ACCT BIT(1) |
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| 161 | #define SW_POLICING_CREDIT_ACCT BIT(0) |
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| 162 | |
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| 163 | #define REG_SW_LUE_CTRL_0 0x0310 |
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| 164 | |
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| 165 | #define SW_VLAN_ENABLE BIT(7) |
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| 166 | #define SW_DROP_INVALID_VID BIT(6) |
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| 167 | #define SW_AGE_CNT_M GENMASK(5, 3) |
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| 168 | #define SW_RESV_MCAST_ENABLE BIT(2) |
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| 169 | #define SW_HASH_OPTION_M 0x03 |
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| 170 | #define SW_HASH_OPTION_CRC 1 |
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| 171 | #define SW_HASH_OPTION_XOR 2 |
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| 172 | #define SW_HASH_OPTION_DIRECT 3 |
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| 173 | |
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| 174 | #define REG_SW_LUE_CTRL_1 0x0311 |
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| 175 | |
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| 176 | #define UNICAST_LEARN_DISABLE BIT(7) |
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| 177 | #define SW_SRC_ADDR_FILTER BIT(6) |
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| 178 | #define SW_FLUSH_STP_TABLE BIT(5) |
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| 179 | #define SW_FLUSH_MSTP_TABLE BIT(4) |
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| 180 | #define SW_FWD_MCAST_SRC_ADDR BIT(3) |
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| 181 | #define SW_AGING_ENABLE BIT(2) |
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| 182 | #define SW_FAST_AGING BIT(1) |
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| 183 | #define SW_LINK_AUTO_AGING BIT(0) |
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| 184 | |
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| 185 | #define REG_SW_LUE_CTRL_2 0x0312 |
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| 186 | |
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| 187 | #define SW_TRAP_DOUBLE_TAG BIT(6) |
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| 188 | #define SW_EGRESS_VLAN_FILTER_DYN BIT(5) |
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| 189 | #define SW_EGRESS_VLAN_FILTER_STA BIT(4) |
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| 190 | #define SW_FLUSH_OPTION_M 0x3 |
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| 191 | #define SW_FLUSH_OPTION_S 2 |
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| 192 | #define SW_FLUSH_OPTION_DYN_MAC 1 |
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| 193 | #define SW_FLUSH_OPTION_STA_MAC 2 |
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| 194 | #define SW_FLUSH_OPTION_BOTH 3 |
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| 195 | #define SW_PRIO_M 0x3 |
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| 196 | #define SW_PRIO_DA 0 |
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| 197 | #define SW_PRIO_SA 1 |
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| 198 | #define SW_PRIO_HIGHEST_DA_SA 2 |
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| 199 | #define SW_PRIO_LOWEST_DA_SA 3 |
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| 200 | |
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| 201 | #define REG_SW_LUE_CTRL_3 0x0313 |
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| 202 | #define SW_AGE_PERIOD_7_0_M GENMASK(7, 0) |
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| 203 | |
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| 204 | #define REG_SW_LUE_INT_STATUS 0x0314 |
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| 205 | #define REG_SW_LUE_INT_ENABLE 0x0315 |
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| 206 | |
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| 207 | #define LEARN_FAIL_INT BIT(2) |
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| 208 | #define ALMOST_FULL_INT BIT(1) |
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| 209 | #define WRITE_FAIL_INT BIT(0) |
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| 210 | |
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| 211 | #define REG_SW_LUE_INDEX_0__2 0x0316 |
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| 212 | |
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| 213 | #define ENTRY_INDEX_M 0x0FFF |
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| 214 | |
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| 215 | #define REG_SW_LUE_INDEX_1__2 0x0318 |
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| 216 | |
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| 217 | #define FAIL_INDEX_M 0x03FF |
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| 218 | |
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| 219 | #define REG_SW_LUE_INDEX_2__2 0x031A |
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| 220 | |
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| 221 | #define REG_SW_LUE_UNK_UCAST_CTRL__4 0x0320 |
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| 222 | |
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| 223 | #define SW_UNK_UCAST_ENABLE BIT(31) |
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| 224 | |
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| 225 | #define REG_SW_LUE_UNK_MCAST_CTRL__4 0x0324 |
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| 226 | |
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| 227 | #define SW_UNK_MCAST_ENABLE BIT(31) |
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| 228 | |
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| 229 | #define REG_SW_LUE_UNK_VID_CTRL__4 0x0328 |
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| 230 | |
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| 231 | #define SW_UNK_VID_ENABLE BIT(31) |
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| 232 | |
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| 233 | #define REG_SW_MAC_CTRL_0 0x0330 |
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| 234 | |
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| 235 | #define SW_NEW_BACKOFF BIT(7) |
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| 236 | #define SW_CHECK_LENGTH BIT(3) |
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| 237 | #define SW_PAUSE_UNH_MODE BIT(1) |
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| 238 | #define SW_AGGR_BACKOFF BIT(0) |
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| 239 | |
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| 240 | #define REG_SW_MAC_CTRL_1 0x0331 |
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| 241 | |
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| 242 | #define SW_BACK_PRESSURE BIT(5) |
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| 243 | #define SW_BACK_PRESSURE_COLLISION 0 |
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| 244 | #define FAIR_FLOW_CTRL BIT(4) |
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| 245 | #define NO_EXC_COLLISION_DROP BIT(3) |
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| 246 | #define SW_JUMBO_PACKET BIT(2) |
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| 247 | #define SW_LEGAL_PACKET_DISABLE BIT(1) |
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| 248 | #define SW_PASS_SHORT_FRAME BIT(0) |
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| 249 | |
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| 250 | #define REG_SW_MAC_CTRL_2 0x0332 |
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| 251 | |
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| 252 | #define SW_REPLACE_VID BIT(3) |
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| 253 | |
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| 254 | #define REG_SW_MAC_CTRL_3 0x0333 |
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| 255 | |
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| 256 | #define REG_SW_MAC_CTRL_4 0x0334 |
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| 257 | |
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| 258 | #define SW_PASS_PAUSE BIT(3) |
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| 259 | |
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| 260 | #define REG_SW_MAC_CTRL_5 0x0335 |
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| 261 | |
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| 262 | #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3) |
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| 263 | |
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| 264 | #define REG_SW_MAC_CTRL_6 0x0336 |
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| 265 | |
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| 266 | #define SW_MIB_COUNTER_FLUSH BIT(7) |
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| 267 | #define SW_MIB_COUNTER_FREEZE BIT(6) |
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| 268 | |
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| 269 | #define REG_SW_MAC_802_1P_MAP_0 0x0338 |
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| 270 | #define REG_SW_MAC_802_1P_MAP_1 0x0339 |
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| 271 | #define REG_SW_MAC_802_1P_MAP_2 0x033A |
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| 272 | #define REG_SW_MAC_802_1P_MAP_3 0x033B |
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| 273 | |
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| 274 | #define SW_802_1P_MAP_M KS_PRIO_M |
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| 275 | #define SW_802_1P_MAP_S KS_PRIO_S |
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| 276 | |
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| 277 | #define REG_SW_MAC_ISP_CTRL 0x033C |
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| 278 | |
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| 279 | #define REG_SW_MAC_TOS_CTRL 0x033E |
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| 280 | |
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| 281 | #define BIT(1) |
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| 282 | #define SW_TOS_DSCP_REMAP BIT(0) |
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| 283 | |
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| 284 | #define REG_SW_MAC_TOS_PRIO_0 0x0340 |
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| 285 | #define REG_SW_MAC_TOS_PRIO_1 0x0341 |
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| 286 | #define REG_SW_MAC_TOS_PRIO_2 0x0342 |
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| 287 | #define REG_SW_MAC_TOS_PRIO_3 0x0343 |
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| 288 | #define REG_SW_MAC_TOS_PRIO_4 0x0344 |
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| 289 | #define REG_SW_MAC_TOS_PRIO_5 0x0345 |
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| 290 | #define REG_SW_MAC_TOS_PRIO_6 0x0346 |
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| 291 | #define REG_SW_MAC_TOS_PRIO_7 0x0347 |
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| 292 | #define REG_SW_MAC_TOS_PRIO_8 0x0348 |
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| 293 | #define REG_SW_MAC_TOS_PRIO_9 0x0349 |
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| 294 | #define REG_SW_MAC_TOS_PRIO_10 0x034A |
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| 295 | #define REG_SW_MAC_TOS_PRIO_11 0x034B |
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| 296 | #define REG_SW_MAC_TOS_PRIO_12 0x034C |
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| 297 | #define REG_SW_MAC_TOS_PRIO_13 0x034D |
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| 298 | #define REG_SW_MAC_TOS_PRIO_14 0x034E |
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| 299 | #define REG_SW_MAC_TOS_PRIO_15 0x034F |
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| 300 | #define REG_SW_MAC_TOS_PRIO_16 0x0350 |
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| 301 | #define REG_SW_MAC_TOS_PRIO_17 0x0351 |
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| 302 | #define REG_SW_MAC_TOS_PRIO_18 0x0352 |
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| 303 | #define REG_SW_MAC_TOS_PRIO_19 0x0353 |
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| 304 | #define REG_SW_MAC_TOS_PRIO_20 0x0354 |
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| 305 | #define REG_SW_MAC_TOS_PRIO_21 0x0355 |
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| 306 | #define REG_SW_MAC_TOS_PRIO_22 0x0356 |
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| 307 | #define REG_SW_MAC_TOS_PRIO_23 0x0357 |
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| 308 | #define REG_SW_MAC_TOS_PRIO_24 0x0358 |
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| 309 | #define REG_SW_MAC_TOS_PRIO_25 0x0359 |
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| 310 | #define REG_SW_MAC_TOS_PRIO_26 0x035A |
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| 311 | #define REG_SW_MAC_TOS_PRIO_27 0x035B |
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| 312 | #define REG_SW_MAC_TOS_PRIO_28 0x035C |
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| 313 | #define REG_SW_MAC_TOS_PRIO_29 0x035D |
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| 314 | #define REG_SW_MAC_TOS_PRIO_30 0x035E |
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| 315 | #define REG_SW_MAC_TOS_PRIO_31 0x035F |
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| 316 | |
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| 317 | #define REG_SW_MRI_CTRL_0 0x0370 |
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| 318 | |
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| 319 | #define SW_IGMP_SNOOP BIT(6) |
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| 320 | #define SW_IPV6_MLD_OPTION BIT(3) |
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| 321 | #define SW_IPV6_MLD_SNOOP BIT(2) |
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| 322 | #define SW_MIRROR_RX_TX BIT(0) |
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| 323 | |
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| 324 | #define REG_SW_CLASS_D_IP_CTRL__4 0x0374 |
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| 325 | |
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| 326 | #define SW_CLASS_D_IP_ENABLE BIT(31) |
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| 327 | |
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| 328 | #define REG_SW_MRI_CTRL_8 0x0378 |
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| 329 | |
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| 330 | #define SW_NO_COLOR_S 6 |
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| 331 | #define SW_RED_COLOR_S 4 |
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| 332 | #define SW_YELLOW_COLOR_S 2 |
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| 333 | #define SW_GREEN_COLOR_S 0 |
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| 334 | #define SW_COLOR_M 0x3 |
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| 335 | |
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| 336 | #define REG_SW_QM_CTRL__4 0x0390 |
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| 337 | |
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| 338 | #define PRIO_SCHEME_SELECT_M KS_PRIO_M |
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| 339 | #define PRIO_SCHEME_SELECT_S 6 |
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| 340 | #define PRIO_MAP_3_HI 0 |
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| 341 | #define PRIO_MAP_2_HI 2 |
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| 342 | #define PRIO_MAP_0_LO 3 |
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| 343 | #define UNICAST_VLAN_BOUNDARY BIT(1) |
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| 344 | |
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| 345 | #define REG_SW_EEE_QM_CTRL__2 0x03C0 |
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| 346 | |
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| 347 | #define REG_SW_EEE_TXQ_WAIT_TIME__2 0x03C2 |
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| 348 | |
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| 349 | /* 4 - */ |
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| 350 | #define REG_SW_VLAN_ENTRY__4 0x0400 |
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| 351 | |
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| 352 | #define VLAN_VALID BIT(31) |
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| 353 | #define VLAN_FORWARD_OPTION BIT(27) |
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| 354 | #define VLAN_PRIO_M KS_PRIO_M |
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| 355 | #define VLAN_PRIO_S 24 |
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| 356 | #define VLAN_MSTP_M 0x7 |
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| 357 | #define VLAN_MSTP_S 12 |
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| 358 | #define VLAN_FID_M 0x7F |
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| 359 | |
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| 360 | #define REG_SW_VLAN_ENTRY_UNTAG__4 0x0404 |
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| 361 | #define REG_SW_VLAN_ENTRY_PORTS__4 0x0408 |
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| 362 | |
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| 363 | #define REG_SW_VLAN_ENTRY_INDEX__2 0x040C |
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| 364 | |
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| 365 | #define VLAN_INDEX_M 0x0FFF |
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| 366 | |
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| 367 | #define REG_SW_VLAN_CTRL 0x040E |
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| 368 | |
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| 369 | #define VLAN_START BIT(7) |
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| 370 | #define VLAN_ACTION 0x3 |
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| 371 | #define VLAN_WRITE 1 |
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| 372 | #define VLAN_READ 2 |
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| 373 | #define VLAN_CLEAR 3 |
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| 374 | |
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| 375 | #define REG_SW_ALU_INDEX_0 0x0410 |
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| 376 | |
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| 377 | #define ALU_FID_INDEX_S 16 |
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| 378 | #define ALU_MAC_ADDR_HI 0xFFFF |
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| 379 | |
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| 380 | #define REG_SW_ALU_INDEX_1 0x0414 |
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| 381 | |
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| 382 | #define ALU_DIRECT_INDEX_M (BIT(12) - 1) |
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| 383 | |
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| 384 | #define REG_SW_ALU_CTRL__4 0x0418 |
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| 385 | |
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| 386 | #define ALU_VALID_CNT_M (BIT(14) - 1) |
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| 387 | #define ALU_VALID_CNT_S 16 |
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| 388 | #define ALU_START BIT(7) |
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| 389 | #define ALU_VALID BIT(6) |
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| 390 | #define ALU_DIRECT BIT(2) |
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| 391 | #define ALU_ACTION 0x3 |
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| 392 | #define ALU_WRITE 1 |
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| 393 | #define ALU_READ 2 |
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| 394 | #define ALU_SEARCH 3 |
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| 395 | |
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| 396 | #define REG_SW_ALU_STAT_CTRL__4 0x041C |
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| 397 | |
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| 398 | #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1) |
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| 399 | #define ALU_STAT_START BIT(7) |
|---|
| 400 | |
|---|
| 401 | #define REG_SW_ALU_VAL_A 0x0420 |
|---|
| 402 | |
|---|
| 403 | #define ALU_V_STATIC_VALID BIT(31) |
|---|
| 404 | #define ALU_V_SRC_FILTER BIT(30) |
|---|
| 405 | #define ALU_V_DST_FILTER BIT(29) |
|---|
| 406 | #define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1) |
|---|
| 407 | #define ALU_V_PRIO_AGE_CNT_S 26 |
|---|
| 408 | #define ALU_V_MSTP_M 0x7 |
|---|
| 409 | |
|---|
| 410 | #define REG_SW_ALU_VAL_B 0x0424 |
|---|
| 411 | |
|---|
| 412 | #define ALU_V_OVERRIDE BIT(31) |
|---|
| 413 | #define ALU_V_USE_FID BIT(30) |
|---|
| 414 | #define ALU_V_PORT_MAP (BIT(24) - 1) |
|---|
| 415 | |
|---|
| 416 | #define REG_SW_ALU_VAL_C 0x0428 |
|---|
| 417 | |
|---|
| 418 | #define ALU_V_FID_M (BIT(16) - 1) |
|---|
| 419 | #define ALU_V_FID_S 16 |
|---|
| 420 | #define ALU_V_MAC_ADDR_HI 0xFFFF |
|---|
| 421 | |
|---|
| 422 | #define REG_SW_ALU_VAL_D 0x042C |
|---|
| 423 | |
|---|
| 424 | #define REG_HSR_ALU_INDEX_0 0x0440 |
|---|
| 425 | |
|---|
| 426 | #define REG_HSR_ALU_INDEX_1 0x0444 |
|---|
| 427 | |
|---|
| 428 | #define HSR_DST_MAC_INDEX_LO_S 16 |
|---|
| 429 | #define HSR_SRC_MAC_INDEX_HI 0xFFFF |
|---|
| 430 | |
|---|
| 431 | #define REG_HSR_ALU_INDEX_2 0x0448 |
|---|
| 432 | |
|---|
| 433 | #define HSR_INDEX_MAX BIT(9) |
|---|
| 434 | #define HSR_DIRECT_INDEX_M (HSR_INDEX_MAX - 1) |
|---|
| 435 | |
|---|
| 436 | #define REG_HSR_ALU_INDEX_3 0x044C |
|---|
| 437 | |
|---|
| 438 | #define HSR_PATH_INDEX_M (BIT(4) - 1) |
|---|
| 439 | |
|---|
| 440 | #define REG_HSR_ALU_CTRL__4 0x0450 |
|---|
| 441 | |
|---|
| 442 | #define HSR_VALID_CNT_M (BIT(14) - 1) |
|---|
| 443 | #define HSR_VALID_CNT_S 16 |
|---|
| 444 | #define HSR_START BIT(7) |
|---|
| 445 | #define HSR_VALID BIT(6) |
|---|
| 446 | #define HSR_SEARCH_END BIT(5) |
|---|
| 447 | #define HSR_DIRECT BIT(2) |
|---|
| 448 | #define HSR_ACTION 0x3 |
|---|
| 449 | #define HSR_WRITE 1 |
|---|
| 450 | #define HSR_READ 2 |
|---|
| 451 | #define HSR_SEARCH 3 |
|---|
| 452 | |
|---|
| 453 | #define REG_HSR_ALU_VAL_A 0x0454 |
|---|
| 454 | |
|---|
| 455 | #define HSR_V_STATIC_VALID BIT(31) |
|---|
| 456 | #define HSR_V_AGE_CNT_M (BIT(3) - 1) |
|---|
| 457 | #define HSR_V_AGE_CNT_S 26 |
|---|
| 458 | #define HSR_V_PATH_ID_M (BIT(4) - 1) |
|---|
| 459 | |
|---|
| 460 | #define REG_HSR_ALU_VAL_B 0x0458 |
|---|
| 461 | |
|---|
| 462 | #define REG_HSR_ALU_VAL_C 0x045C |
|---|
| 463 | |
|---|
| 464 | #define HSR_V_DST_MAC_ADDR_LO_S 16 |
|---|
| 465 | #define HSR_V_SRC_MAC_ADDR_HI 0xFFFF |
|---|
| 466 | |
|---|
| 467 | #define REG_HSR_ALU_VAL_D 0x0460 |
|---|
| 468 | |
|---|
| 469 | #define REG_HSR_ALU_VAL_E 0x0464 |
|---|
| 470 | |
|---|
| 471 | #define HSR_V_START_SEQ_1_S 16 |
|---|
| 472 | #define HSR_V_START_SEQ_2_S 0 |
|---|
| 473 | |
|---|
| 474 | #define REG_HSR_ALU_VAL_F 0x0468 |
|---|
| 475 | |
|---|
| 476 | #define HSR_V_EXP_SEQ_1_S 16 |
|---|
| 477 | #define HSR_V_EXP_SEQ_2_S 0 |
|---|
| 478 | |
|---|
| 479 | #define REG_HSR_ALU_VAL_G 0x046C |
|---|
| 480 | |
|---|
| 481 | #define HSR_V_SEQ_CNT_1_S 16 |
|---|
| 482 | #define HSR_V_SEQ_CNT_2_S 0 |
|---|
| 483 | |
|---|
| 484 | #define HSR_V_SEQ_M (BIT(16) - 1) |
|---|
| 485 | |
|---|
| 486 | /* 5 - PTP Clock */ |
|---|
| 487 | #define REG_PTP_CLK_CTRL 0x0500 |
|---|
| 488 | |
|---|
| 489 | #define PTP_STEP_ADJ BIT(6) |
|---|
| 490 | #define PTP_STEP_DIR BIT(5) |
|---|
| 491 | #define PTP_READ_TIME BIT(4) |
|---|
| 492 | #define PTP_LOAD_TIME BIT(3) |
|---|
| 493 | #define PTP_CLK_ADJ_ENABLE BIT(2) |
|---|
| 494 | #define PTP_CLK_ENABLE BIT(1) |
|---|
| 495 | #define PTP_CLK_RESET BIT(0) |
|---|
| 496 | |
|---|
| 497 | #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502 |
|---|
| 498 | |
|---|
| 499 | #define PTP_RTC_SUB_NANOSEC_M 0x0007 |
|---|
| 500 | |
|---|
| 501 | #define REG_PTP_RTC_NANOSEC 0x0504 |
|---|
| 502 | #define REG_PTP_RTC_NANOSEC_H 0x0504 |
|---|
| 503 | #define REG_PTP_RTC_NANOSEC_L 0x0506 |
|---|
| 504 | |
|---|
| 505 | #define REG_PTP_RTC_SEC 0x0508 |
|---|
| 506 | #define REG_PTP_RTC_SEC_H 0x0508 |
|---|
| 507 | #define REG_PTP_RTC_SEC_L 0x050A |
|---|
| 508 | |
|---|
| 509 | #define REG_PTP_SUBNANOSEC_RATE 0x050C |
|---|
| 510 | #define REG_PTP_SUBNANOSEC_RATE_H 0x050C |
|---|
| 511 | |
|---|
| 512 | #define PTP_RATE_DIR BIT(31) |
|---|
| 513 | #define PTP_TMP_RATE_ENABLE BIT(30) |
|---|
| 514 | |
|---|
| 515 | #define REG_PTP_SUBNANOSEC_RATE_L 0x050E |
|---|
| 516 | |
|---|
| 517 | #define REG_PTP_RATE_DURATION 0x0510 |
|---|
| 518 | #define REG_PTP_RATE_DURATION_H 0x0510 |
|---|
| 519 | #define REG_PTP_RATE_DURATION_L 0x0512 |
|---|
| 520 | |
|---|
| 521 | #define REG_PTP_MSG_CONF1 0x0514 |
|---|
| 522 | |
|---|
| 523 | #define PTP_802_1AS BIT(7) |
|---|
| 524 | #define PTP_ENABLE BIT(6) |
|---|
| 525 | #define PTP_ETH_ENABLE BIT(5) |
|---|
| 526 | #define PTP_IPV4_UDP_ENABLE BIT(4) |
|---|
| 527 | #define PTP_IPV6_UDP_ENABLE BIT(3) |
|---|
| 528 | #define PTP_TC_P2P BIT(2) |
|---|
| 529 | #define PTP_MASTER BIT(1) |
|---|
| 530 | #define PTP_1STEP BIT(0) |
|---|
| 531 | |
|---|
| 532 | #define REG_PTP_MSG_CONF2 0x0516 |
|---|
| 533 | |
|---|
| 534 | #define PTP_UNICAST_ENABLE BIT(12) |
|---|
| 535 | #define PTP_ALTERNATE_MASTER BIT(11) |
|---|
| 536 | #define PTP_ALL_HIGH_PRIO BIT(10) |
|---|
| 537 | #define PTP_SYNC_CHECK BIT(9) |
|---|
| 538 | #define PTP_DELAY_CHECK BIT(8) |
|---|
| 539 | #define PTP_PDELAY_CHECK BIT(7) |
|---|
| 540 | #define PTP_DROP_SYNC_DELAY_REQ BIT(5) |
|---|
| 541 | #define PTP_DOMAIN_CHECK BIT(4) |
|---|
| 542 | #define PTP_UDP_CHECKSUM BIT(2) |
|---|
| 543 | |
|---|
| 544 | #define REG_PTP_DOMAIN_VERSION 0x0518 |
|---|
| 545 | #define PTP_VERSION_M 0xFF00 |
|---|
| 546 | #define PTP_DOMAIN_M 0x00FF |
|---|
| 547 | |
|---|
| 548 | #define REG_PTP_UNIT_INDEX__4 0x0520 |
|---|
| 549 | |
|---|
| 550 | #define PTP_UNIT_M 0xF |
|---|
| 551 | |
|---|
| 552 | #define PTP_GPIO_INDEX_S 16 |
|---|
| 553 | #define PTP_TSI_INDEX_S 8 |
|---|
| 554 | #define PTP_TOU_INDEX_S 0 |
|---|
| 555 | |
|---|
| 556 | #define REG_PTP_TRIG_STATUS__4 0x0524 |
|---|
| 557 | |
|---|
| 558 | #define TRIG_ERROR_S 16 |
|---|
| 559 | #define TRIG_DONE_S 0 |
|---|
| 560 | |
|---|
| 561 | #define REG_PTP_INT_STATUS__4 0x0528 |
|---|
| 562 | |
|---|
| 563 | #define TRIG_INT_S 16 |
|---|
| 564 | #define TS_INT_S 0 |
|---|
| 565 | |
|---|
| 566 | #define TRIG_UNIT_M 0x7 |
|---|
| 567 | #define TS_UNIT_M 0x3 |
|---|
| 568 | |
|---|
| 569 | #define REG_PTP_CTRL_STAT__4 0x052C |
|---|
| 570 | |
|---|
| 571 | #define GPIO_IN BIT(7) |
|---|
| 572 | #define GPIO_OUT BIT(6) |
|---|
| 573 | #define TS_INT_ENABLE BIT(5) |
|---|
| 574 | #define TRIG_ACTIVE BIT(4) |
|---|
| 575 | #define TRIG_ENABLE BIT(3) |
|---|
| 576 | #define TRIG_RESET BIT(2) |
|---|
| 577 | #define TS_ENABLE BIT(1) |
|---|
| 578 | #define TS_RESET BIT(0) |
|---|
| 579 | |
|---|
| 580 | #define GPIO_CTRL_M (GPIO_IN | GPIO_OUT) |
|---|
| 581 | |
|---|
| 582 | #define TRIG_CTRL_M \ |
|---|
| 583 | (TRIG_ACTIVE | TRIG_ENABLE | TRIG_RESET) |
|---|
| 584 | |
|---|
| 585 | #define TS_CTRL_M \ |
|---|
| 586 | (TS_INT_ENABLE | TS_ENABLE | TS_RESET) |
|---|
| 587 | |
|---|
| 588 | #define REG_TRIG_TARGET_NANOSEC 0x0530 |
|---|
| 589 | #define REG_TRIG_TARGET_SEC 0x0534 |
|---|
| 590 | |
|---|
| 591 | #define REG_TRIG_CTRL__4 0x0538 |
|---|
| 592 | |
|---|
| 593 | #define TRIG_CASCADE_ENABLE BIT(31) |
|---|
| 594 | #define TRIG_CASCADE_TAIL BIT(30) |
|---|
| 595 | #define TRIG_CASCADE_UPS_M 0xF |
|---|
| 596 | #define TRIG_CASCADE_UPS_S 26 |
|---|
| 597 | #define TRIG_NOW BIT(25) |
|---|
| 598 | #define TRIG_NOTIFY BIT(24) |
|---|
| 599 | #define TRIG_EDGE BIT(23) |
|---|
| 600 | #define TRIG_PATTERN_S 20 |
|---|
| 601 | #define TRIG_PATTERN_M 0x7 |
|---|
| 602 | #define TRIG_NEG_EDGE 0 |
|---|
| 603 | #define TRIG_POS_EDGE 1 |
|---|
| 604 | #define TRIG_NEG_PULSE 2 |
|---|
| 605 | #define TRIG_POS_PULSE 3 |
|---|
| 606 | #define TRIG_NEG_PERIOD 4 |
|---|
| 607 | #define TRIG_POS_PERIOD 5 |
|---|
| 608 | #define TRIG_REG_OUTPUT 6 |
|---|
| 609 | #define TRIG_GPO_S 16 |
|---|
| 610 | #define TRIG_GPO_M 0xF |
|---|
| 611 | #define TRIG_CASCADE_ITERATE_CNT_M 0xFFFF |
|---|
| 612 | |
|---|
| 613 | #define REG_TRIG_CYCLE_WIDTH 0x053C |
|---|
| 614 | |
|---|
| 615 | #define REG_TRIG_CYCLE_CNT 0x0540 |
|---|
| 616 | |
|---|
| 617 | #define TRIG_CYCLE_CNT_M 0xFFFF |
|---|
| 618 | #define TRIG_CYCLE_CNT_S 16 |
|---|
| 619 | #define TRIG_BIT_PATTERN_M 0xFFFF |
|---|
| 620 | |
|---|
| 621 | #define REG_TRIG_ITERATE_TIME 0x0544 |
|---|
| 622 | |
|---|
| 623 | #define REG_TRIG_PULSE_WIDTH__4 0x0548 |
|---|
| 624 | |
|---|
| 625 | #define TRIG_PULSE_WIDTH_M 0x00FFFFFF |
|---|
| 626 | |
|---|
| 627 | #define REG_TS_CTRL_STAT__4 0x0550 |
|---|
| 628 | |
|---|
| 629 | #define TS_EVENT_DETECT_M 0xF |
|---|
| 630 | #define TS_EVENT_DETECT_S 17 |
|---|
| 631 | #define TS_EVENT_OVERFLOW BIT(16) |
|---|
| 632 | #define TS_GPI_M 0xF |
|---|
| 633 | #define TS_GPI_S 8 |
|---|
| 634 | #define TS_DETECT_RISE BIT(7) |
|---|
| 635 | #define TS_DETECT_FALL BIT(6) |
|---|
| 636 | #define TS_DETECT_S 6 |
|---|
| 637 | #define TS_CASCADE_TAIL BIT(5) |
|---|
| 638 | #define TS_CASCADE_UPS_M 0xF |
|---|
| 639 | #define TS_CASCADE_UPS_S 1 |
|---|
| 640 | #define TS_CASCADE_ENABLE BIT(0) |
|---|
| 641 | |
|---|
| 642 | #define DETECT_RISE (TS_DETECT_RISE >> TS_DETECT_S) |
|---|
| 643 | #define DETECT_FALL (TS_DETECT_FALL >> TS_DETECT_S) |
|---|
| 644 | |
|---|
| 645 | #define REG_TS_EVENT_0_NANOSEC 0x0554 |
|---|
| 646 | #define REG_TS_EVENT_0_SEC 0x0558 |
|---|
| 647 | #define REG_TS_EVENT_0_SUB_NANOSEC 0x055C |
|---|
| 648 | |
|---|
| 649 | #define REG_TS_EVENT_1_NANOSEC 0x0560 |
|---|
| 650 | #define REG_TS_EVENT_1_SEC 0x0564 |
|---|
| 651 | #define REG_TS_EVENT_1_SUB_NANOSEC 0x0568 |
|---|
| 652 | |
|---|
| 653 | #define REG_TS_EVENT_2_NANOSEC 0x056C |
|---|
| 654 | #define REG_TS_EVENT_2_SEC 0x0570 |
|---|
| 655 | #define REG_TS_EVENT_2_SUB_NANOSEC 0x0574 |
|---|
| 656 | |
|---|
| 657 | #define REG_TS_EVENT_3_NANOSEC 0x0578 |
|---|
| 658 | #define REG_TS_EVENT_3_SEC 0x057C |
|---|
| 659 | #define REG_TS_EVENT_3_SUB_NANOSEC 0x0580 |
|---|
| 660 | |
|---|
| 661 | #define REG_TS_EVENT_4_NANOSEC 0x0584 |
|---|
| 662 | #define REG_TS_EVENT_4_SEC 0x0588 |
|---|
| 663 | #define REG_TS_EVENT_4_SUB_NANOSEC 0x058C |
|---|
| 664 | |
|---|
| 665 | #define REG_TS_EVENT_5_NANOSEC 0x0590 |
|---|
| 666 | #define REG_TS_EVENT_5_SEC 0x0594 |
|---|
| 667 | #define REG_TS_EVENT_5_SUB_NANOSEC 0x0598 |
|---|
| 668 | |
|---|
| 669 | #define REG_TS_EVENT_6_NANOSEC 0x059C |
|---|
| 670 | #define REG_TS_EVENT_6_SEC 0x05A0 |
|---|
| 671 | #define REG_TS_EVENT_6_SUB_NANOSEC 0x05A4 |
|---|
| 672 | |
|---|
| 673 | #define REG_TS_EVENT_7_NANOSEC 0x05A8 |
|---|
| 674 | #define REG_TS_EVENT_7_SEC 0x05AC |
|---|
| 675 | #define REG_TS_EVENT_7_SUB_NANOSEC 0x05B0 |
|---|
| 676 | |
|---|
| 677 | #define TS_EVENT_EDGE_M 0x1 |
|---|
| 678 | #define TS_EVENT_EDGE_S 30 |
|---|
| 679 | #define TS_EVENT_NANOSEC_M (BIT(30) - 1) |
|---|
| 680 | |
|---|
| 681 | #define TS_EVENT_SUB_NANOSEC_M 0x7 |
|---|
| 682 | |
|---|
| 683 | #define TS_EVENT_SAMPLE \ |
|---|
| 684 | (REG_TS_EVENT_1_NANOSEC - REG_TS_EVENT_0_NANOSEC) |
|---|
| 685 | |
|---|
| 686 | #define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12)) |
|---|
| 687 | |
|---|
| 688 | #define REG_GLOBAL_RR_INDEX__1 0x0600 |
|---|
| 689 | |
|---|
| 690 | /* DLR */ |
|---|
| 691 | #define REG_DLR_SRC_PORT__4 0x0604 |
|---|
| 692 | |
|---|
| 693 | #define DLR_SRC_PORT_UNICAST BIT(31) |
|---|
| 694 | #define DLR_SRC_PORT_M 0x3 |
|---|
| 695 | #define DLR_SRC_PORT_BOTH 0 |
|---|
| 696 | #define DLR_SRC_PORT_EACH 1 |
|---|
| 697 | |
|---|
| 698 | #define REG_DLR_IP_ADDR__4 0x0608 |
|---|
| 699 | |
|---|
| 700 | #define REG_DLR_CTRL__1 0x0610 |
|---|
| 701 | |
|---|
| 702 | #define DLR_RESET_SEQ_ID BIT(3) |
|---|
| 703 | #define DLR_BACKUP_AUTO_ON BIT(2) |
|---|
| 704 | #define DLR_BEACON_TX_ENABLE BIT(1) |
|---|
| 705 | #define DLR_ASSIST_ENABLE BIT(0) |
|---|
| 706 | |
|---|
| 707 | #define REG_DLR_STATE__1 0x0611 |
|---|
| 708 | |
|---|
| 709 | #define DLR_NODE_STATE_M 0x3 |
|---|
| 710 | #define DLR_NODE_STATE_S 1 |
|---|
| 711 | #define DLR_NODE_STATE_IDLE 0 |
|---|
| 712 | #define DLR_NODE_STATE_FAULT 1 |
|---|
| 713 | #define DLR_NODE_STATE_NORMAL 2 |
|---|
| 714 | #define DLR_RING_STATE_FAULT 0 |
|---|
| 715 | #define DLR_RING_STATE_NORMAL 1 |
|---|
| 716 | |
|---|
| 717 | #define REG_DLR_PRECEDENCE__1 0x0612 |
|---|
| 718 | |
|---|
| 719 | #define REG_DLR_BEACON_INTERVAL__4 0x0614 |
|---|
| 720 | |
|---|
| 721 | #define REG_DLR_BEACON_TIMEOUT__4 0x0618 |
|---|
| 722 | |
|---|
| 723 | #define REG_DLR_TIMEOUT_WINDOW__4 0x061C |
|---|
| 724 | |
|---|
| 725 | #define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1) |
|---|
| 726 | |
|---|
| 727 | #define REG_DLR_VLAN_ID__2 0x0620 |
|---|
| 728 | |
|---|
| 729 | #define DLR_VLAN_ID_M (BIT(12) - 1) |
|---|
| 730 | |
|---|
| 731 | #define REG_DLR_DEST_ADDR_0 0x0622 |
|---|
| 732 | #define REG_DLR_DEST_ADDR_1 0x0623 |
|---|
| 733 | #define REG_DLR_DEST_ADDR_2 0x0624 |
|---|
| 734 | #define REG_DLR_DEST_ADDR_3 0x0625 |
|---|
| 735 | #define REG_DLR_DEST_ADDR_4 0x0626 |
|---|
| 736 | #define REG_DLR_DEST_ADDR_5 0x0627 |
|---|
| 737 | |
|---|
| 738 | #define REG_DLR_PORT_MAP__4 0x0628 |
|---|
| 739 | |
|---|
| 740 | #define REG_DLR_CLASS__1 0x062C |
|---|
| 741 | |
|---|
| 742 | #define DLR_FRAME_QID_M 0x3 |
|---|
| 743 | |
|---|
| 744 | /* HSR */ |
|---|
| 745 | #define REG_HSR_PORT_MAP__4 0x0640 |
|---|
| 746 | |
|---|
| 747 | #define REG_HSR_ALU_CTRL_0__1 0x0644 |
|---|
| 748 | |
|---|
| 749 | #define HSR_DUPLICATE_DISCARD BIT(7) |
|---|
| 750 | #define HSR_NODE_UNICAST BIT(6) |
|---|
| 751 | #define HSR_AGE_CNT_DEFAULT_M 0x7 |
|---|
| 752 | #define HSR_AGE_CNT_DEFAULT_S 3 |
|---|
| 753 | #define HSR_LEARN_MCAST_DISABLE BIT(2) |
|---|
| 754 | #define HSR_HASH_OPTION_M 0x3 |
|---|
| 755 | #define HSR_HASH_DISABLE 0 |
|---|
| 756 | #define HSR_HASH_UPPER_BITS 1 |
|---|
| 757 | #define HSR_HASH_LOWER_BITS 2 |
|---|
| 758 | #define HSR_HASH_XOR_BOTH_BITS 3 |
|---|
| 759 | |
|---|
| 760 | #define REG_HSR_ALU_CTRL_1__1 0x0645 |
|---|
| 761 | |
|---|
| 762 | #define HSR_LEARN_UCAST_DISABLE BIT(7) |
|---|
| 763 | #define HSR_FLUSH_TABLE BIT(5) |
|---|
| 764 | #define HSR_PROC_MCAST_SRC BIT(3) |
|---|
| 765 | #define HSR_AGING_ENABLE BIT(2) |
|---|
| 766 | |
|---|
| 767 | #define REG_HSR_ALU_CTRL_2__2 0x0646 |
|---|
| 768 | |
|---|
| 769 | #define REG_HSR_ALU_AGE_PERIOD__4 0x0648 |
|---|
| 770 | |
|---|
| 771 | #define REG_HSR_ALU_INT_STATUS__1 0x064C |
|---|
| 772 | #define REG_HSR_ALU_INT_MASK__1 0x064D |
|---|
| 773 | |
|---|
| 774 | #define HSR_WINDOW_OVERFLOW_INT BIT(3) |
|---|
| 775 | #define HSR_LEARN_FAIL_INT BIT(2) |
|---|
| 776 | #define HSR_ALMOST_FULL_INT BIT(1) |
|---|
| 777 | #define HSR_WRITE_FAIL_INT BIT(0) |
|---|
| 778 | |
|---|
| 779 | #define REG_HSR_ALU_ENTRY_0__2 0x0650 |
|---|
| 780 | |
|---|
| 781 | #define HSR_ENTRY_INDEX_M (BIT(10) - 1) |
|---|
| 782 | #define HSR_FAIL_INDEX_M (BIT(8) - 1) |
|---|
| 783 | |
|---|
| 784 | #define REG_HSR_ALU_ENTRY_1__2 0x0652 |
|---|
| 785 | |
|---|
| 786 | #define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1) |
|---|
| 787 | |
|---|
| 788 | #define REG_HSR_ALU_ENTRY_3__2 0x0654 |
|---|
| 789 | |
|---|
| 790 | #define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1) |
|---|
| 791 | |
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| 792 | /* 0 - Operation */ |
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| 793 | #define REG_PORT_DEFAULT_VID 0x0000 |
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| 794 | |
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| 795 | #define REG_PORT_CUSTOM_VID 0x0002 |
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| 796 | #define REG_PORT_AVB_SR_1_VID 0x0004 |
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| 797 | #define REG_PORT_AVB_SR_2_VID 0x0006 |
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| 798 | |
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| 799 | #define REG_PORT_AVB_SR_1_TYPE 0x0008 |
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| 800 | #define REG_PORT_AVB_SR_2_TYPE 0x000A |
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| 801 | |
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| 802 | #define REG_PORT_INT_STATUS 0x001B |
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| 803 | #define REG_PORT_INT_MASK 0x001F |
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| 804 | |
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| 805 | #define PORT_SGMII_INT BIT(3) |
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| 806 | #define PORT_PTP_INT BIT(2) |
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| 807 | #define PORT_PHY_INT BIT(1) |
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| 808 | #define PORT_ACL_INT BIT(0) |
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| 809 | |
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| 810 | #define PORT_INT_MASK \ |
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| 811 | (PORT_SGMII_INT | PORT_PTP_INT | PORT_PHY_INT | PORT_ACL_INT) |
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| 812 | |
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| 813 | #define REG_PORT_CTRL_0 0x0020 |
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| 814 | |
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| 815 | #define PORT_MAC_LOOPBACK BIT(7) |
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| 816 | #define PORT_FORCE_TX_FLOW_CTRL BIT(4) |
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| 817 | #define PORT_FORCE_RX_FLOW_CTRL BIT(3) |
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| 818 | #define PORT_TAIL_TAG_ENABLE BIT(2) |
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| 819 | #define PORT_QUEUE_SPLIT_MASK GENMASK(1, 0) |
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| 820 | #define PORT_EIGHT_QUEUE 0x3 |
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| 821 | #define PORT_FOUR_QUEUE 0x2 |
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| 822 | #define PORT_TWO_QUEUE 0x1 |
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| 823 | #define PORT_SINGLE_QUEUE 0x0 |
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| 824 | |
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| 825 | #define REG_PORT_CTRL_1 0x0021 |
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| 826 | |
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| 827 | #define PORT_SRP_ENABLE 0x3 |
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| 828 | |
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| 829 | #define REG_PORT_STATUS_0 0x0030 |
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| 830 | |
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| 831 | #define PORT_INTF_SPEED_MASK GENMASK(4, 3) |
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| 832 | #define PORT_INTF_SPEED_NONE GENMASK(1, 0) |
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| 833 | #define PORT_INTF_FULL_DUPLEX BIT(2) |
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| 834 | #define PORT_TX_FLOW_CTRL BIT(1) |
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| 835 | #define PORT_RX_FLOW_CTRL BIT(0) |
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| 836 | |
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| 837 | #define REG_PORT_STATUS_1 0x0034 |
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| 838 | |
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| 839 | /* 1 - PHY */ |
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| 840 | #define REG_PORT_PHY_CTRL 0x0100 |
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| 841 | |
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| 842 | #define PORT_PHY_RESET BIT(15) |
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| 843 | #define PORT_PHY_LOOPBACK BIT(14) |
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| 844 | #define PORT_SPEED_100MBIT BIT(13) |
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| 845 | #define PORT_AUTO_NEG_ENABLE BIT(12) |
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| 846 | #define PORT_POWER_DOWN BIT(11) |
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| 847 | #define PORT_ISOLATE BIT(10) |
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| 848 | #define PORT_AUTO_NEG_RESTART BIT(9) |
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| 849 | #define PORT_FULL_DUPLEX BIT(8) |
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| 850 | #define PORT_COLLISION_TEST BIT(7) |
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| 851 | #define PORT_SPEED_1000MBIT BIT(6) |
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| 852 | |
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| 853 | #define REG_PORT_PHY_STATUS 0x0102 |
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| 854 | |
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| 855 | #define PORT_100BT4_CAPABLE BIT(15) |
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| 856 | #define PORT_100BTX_FD_CAPABLE BIT(14) |
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| 857 | #define PORT_100BTX_CAPABLE BIT(13) |
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| 858 | #define PORT_10BT_FD_CAPABLE BIT(12) |
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| 859 | #define PORT_10BT_CAPABLE BIT(11) |
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| 860 | #define PORT_EXTENDED_STATUS BIT(8) |
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| 861 | #define PORT_MII_SUPPRESS_CAPABLE BIT(6) |
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| 862 | #define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5) |
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| 863 | #define PORT_REMOTE_FAULT BIT(4) |
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| 864 | #define PORT_AUTO_NEG_CAPABLE BIT(3) |
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| 865 | #define PORT_LINK_STATUS BIT(2) |
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| 866 | #define PORT_JABBER_DETECT BIT(1) |
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| 867 | #define PORT_EXTENDED_CAPABILITY BIT(0) |
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| 868 | |
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| 869 | #define REG_PORT_PHY_ID_HI 0x0104 |
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| 870 | #define REG_PORT_PHY_ID_LO 0x0106 |
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| 871 | |
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| 872 | #define KSZ9477_ID_HI 0x0022 |
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| 873 | #define KSZ9477_ID_LO 0x1622 |
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| 874 | |
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| 875 | #define REG_PORT_PHY_AUTO_NEGOTIATION 0x0108 |
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| 876 | |
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| 877 | #define PORT_AUTO_NEG_NEXT_PAGE BIT(15) |
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| 878 | #define PORT_AUTO_NEG_REMOTE_FAULT BIT(13) |
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| 879 | #define PORT_AUTO_NEG_ASYM_PAUSE BIT(11) |
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| 880 | #define PORT_AUTO_NEG_SYM_PAUSE BIT(10) |
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| 881 | #define PORT_AUTO_NEG_100BT4 BIT(9) |
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| 882 | #define PORT_AUTO_NEG_100BTX_FD BIT(8) |
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| 883 | #define PORT_AUTO_NEG_100BTX BIT(7) |
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| 884 | #define PORT_AUTO_NEG_10BT_FD BIT(6) |
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| 885 | #define PORT_AUTO_NEG_10BT BIT(5) |
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| 886 | #define PORT_AUTO_NEG_SELECTOR 0x001F |
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| 887 | #define PORT_AUTO_NEG_802_3 0x0001 |
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| 888 | |
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| 889 | #define PORT_AUTO_NEG_PAUSE \ |
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| 890 | (PORT_AUTO_NEG_ASYM_PAUSE | PORT_AUTO_NEG_SYM_PAUSE) |
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| 891 | |
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| 892 | #define REG_PORT_PHY_REMOTE_CAPABILITY 0x010A |
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| 893 | |
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| 894 | #define PORT_REMOTE_NEXT_PAGE BIT(15) |
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| 895 | #define PORT_REMOTE_ACKNOWLEDGE BIT(14) |
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| 896 | #define PORT_REMOTE_REMOTE_FAULT BIT(13) |
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| 897 | #define PORT_REMOTE_ASYM_PAUSE BIT(11) |
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| 898 | #define PORT_REMOTE_SYM_PAUSE BIT(10) |
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| 899 | #define PORT_REMOTE_100BTX_FD BIT(8) |
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| 900 | #define PORT_REMOTE_100BTX BIT(7) |
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| 901 | #define PORT_REMOTE_10BT_FD BIT(6) |
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| 902 | #define PORT_REMOTE_10BT BIT(5) |
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| 903 | |
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| 904 | #define REG_PORT_PHY_1000_CTRL 0x0112 |
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| 905 | |
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| 906 | #define PORT_AUTO_NEG_MANUAL BIT(12) |
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| 907 | #define PORT_AUTO_NEG_MASTER BIT(11) |
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| 908 | #define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10) |
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| 909 | #define PORT_AUTO_NEG_1000BT_FD BIT(9) |
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| 910 | #define PORT_AUTO_NEG_1000BT BIT(8) |
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| 911 | |
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| 912 | #define REG_PORT_PHY_1000_STATUS 0x0114 |
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| 913 | |
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| 914 | #define PORT_MASTER_FAULT BIT(15) |
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| 915 | #define PORT_LOCAL_MASTER BIT(14) |
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| 916 | #define PORT_LOCAL_RX_OK BIT(13) |
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| 917 | #define PORT_REMOTE_RX_OK BIT(12) |
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| 918 | #define PORT_REMOTE_1000BT_FD BIT(11) |
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| 919 | #define PORT_REMOTE_1000BT BIT(10) |
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| 920 | #define PORT_REMOTE_IDLE_CNT_M 0x0F |
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| 921 | |
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| 922 | #define PORT_PHY_1000_STATIC_STATUS \ |
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| 923 | (PORT_LOCAL_RX_OK | \ |
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| 924 | PORT_REMOTE_RX_OK | \ |
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| 925 | PORT_REMOTE_1000BT_FD | \ |
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| 926 | PORT_REMOTE_1000BT) |
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| 927 | |
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| 928 | #define REG_PORT_PHY_MMD_SETUP 0x011A |
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| 929 | |
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| 930 | #define PORT_MMD_OP_MODE_M 0x3 |
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| 931 | #define PORT_MMD_OP_MODE_S 14 |
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| 932 | #define PORT_MMD_OP_INDEX 0 |
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| 933 | #define PORT_MMD_OP_DATA_NO_INCR 1 |
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| 934 | #define PORT_MMD_OP_DATA_INCR_RW 2 |
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| 935 | #define PORT_MMD_OP_DATA_INCR_W 3 |
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| 936 | #define PORT_MMD_DEVICE_ID_M 0x1F |
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| 937 | |
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| 938 | #define MMD_SETUP(mode, dev) \ |
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| 939 | (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev)) |
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| 940 | |
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| 941 | #define REG_PORT_PHY_MMD_INDEX_DATA 0x011C |
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| 942 | |
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| 943 | #define MMD_DEVICE_ID_DSP 1 |
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| 944 | |
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| 945 | #define MMD_DSP_SQI_CHAN_A 0xAC |
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| 946 | #define MMD_DSP_SQI_CHAN_B 0xAD |
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| 947 | #define MMD_DSP_SQI_CHAN_C 0xAE |
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| 948 | #define MMD_DSP_SQI_CHAN_D 0xAF |
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| 949 | |
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| 950 | #define DSP_SQI_ERR_DETECTED BIT(15) |
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| 951 | #define DSP_SQI_AVG_ERR 0x7FFF |
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| 952 | |
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| 953 | #define MMD_DEVICE_ID_COMMON 2 |
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| 954 | |
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| 955 | #define MMD_DEVICE_ID_EEE_ADV 7 |
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| 956 | |
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| 957 | #define MMD_EEE_ADV 0x3C |
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| 958 | #define EEE_ADV_100MBIT BIT(1) |
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| 959 | #define EEE_ADV_1GBIT BIT(2) |
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| 960 | |
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| 961 | #define MMD_EEE_LP_ADV 0x3D |
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| 962 | #define MMD_EEE_MSG_CODE 0x3F |
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| 963 | |
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| 964 | #define MMD_DEVICE_ID_AFED 0x1C |
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| 965 | |
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| 966 | #define REG_PORT_PHY_EXTENDED_STATUS 0x011E |
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| 967 | |
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| 968 | #define PORT_100BTX_FD_ABLE BIT(15) |
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| 969 | #define PORT_100BTX_ABLE BIT(14) |
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| 970 | #define PORT_10BT_FD_ABLE BIT(13) |
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| 971 | #define PORT_10BT_ABLE BIT(12) |
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| 972 | |
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| 973 | #define REG_PORT_SGMII_ADDR__4 0x0200 |
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| 974 | #define PORT_SGMII_AUTO_INCR BIT(23) |
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| 975 | #define PORT_SGMII_DEVICE_ID_M 0x1F |
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| 976 | #define PORT_SGMII_DEVICE_ID_S 16 |
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| 977 | #define PORT_SGMII_ADDR_M (BIT(21) - 1) |
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| 978 | |
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| 979 | #define REG_PORT_SGMII_DATA__4 0x0204 |
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| 980 | #define PORT_SGMII_DATA_M (BIT(16) - 1) |
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| 981 | |
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| 982 | #define MMD_DEVICE_ID_PMA 0x01 |
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| 983 | #define MMD_DEVICE_ID_PCS 0x03 |
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| 984 | #define MMD_DEVICE_ID_PHY_XS 0x04 |
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| 985 | #define MMD_DEVICE_ID_DTE_XS 0x05 |
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| 986 | #define MMD_DEVICE_ID_AN 0x07 |
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| 987 | #define MMD_DEVICE_ID_VENDOR_CTRL 0x1E |
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| 988 | #define MMD_DEVICE_ID_VENDOR_MII 0x1F |
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| 989 | |
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| 990 | #define SR_MII MMD_DEVICE_ID_VENDOR_MII |
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| 991 | |
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| 992 | #define MMD_SR_MII_CTRL 0x0000 |
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| 993 | |
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| 994 | #define SR_MII_RESET BIT(15) |
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| 995 | #define SR_MII_LOOPBACK BIT(14) |
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| 996 | #define SR_MII_SPEED_100MBIT BIT(13) |
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| 997 | #define SR_MII_AUTO_NEG_ENABLE BIT(12) |
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| 998 | #define SR_MII_POWER_DOWN BIT(11) |
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| 999 | #define SR_MII_AUTO_NEG_RESTART BIT(9) |
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| 1000 | #define SR_MII_FULL_DUPLEX BIT(8) |
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| 1001 | #define SR_MII_SPEED_1000MBIT BIT(6) |
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| 1002 | |
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| 1003 | #define MMD_SR_MII_STATUS 0x0001 |
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| 1004 | #define MMD_SR_MII_ID_1 0x0002 |
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| 1005 | #define MMD_SR_MII_ID_2 0x0003 |
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| 1006 | #define MMD_SR_MII_AUTO_NEGOTIATION 0x0004 |
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| 1007 | |
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| 1008 | #define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15) |
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| 1009 | #define SR_MII_AUTO_NEG_REMOTE_FAULT_M 0x3 |
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| 1010 | #define SR_MII_AUTO_NEG_REMOTE_FAULT_S 12 |
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| 1011 | #define SR_MII_AUTO_NEG_NO_ERROR 0 |
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| 1012 | #define SR_MII_AUTO_NEG_OFFLINE 1 |
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| 1013 | #define SR_MII_AUTO_NEG_LINK_FAILURE 2 |
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| 1014 | #define SR_MII_AUTO_NEG_ERROR 3 |
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| 1015 | #define SR_MII_AUTO_NEG_PAUSE_M 0x3 |
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| 1016 | #define SR_MII_AUTO_NEG_PAUSE_S 7 |
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| 1017 | #define SR_MII_AUTO_NEG_NO_PAUSE 0 |
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| 1018 | #define SR_MII_AUTO_NEG_ASYM_PAUSE_TX 1 |
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| 1019 | #define SR_MII_AUTO_NEG_SYM_PAUSE 2 |
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| 1020 | #define SR_MII_AUTO_NEG_ASYM_PAUSE_RX 3 |
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| 1021 | #define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6) |
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| 1022 | #define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5) |
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| 1023 | |
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| 1024 | #define MMD_SR_MII_REMOTE_CAPABILITY 0x0005 |
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| 1025 | #define MMD_SR_MII_AUTO_NEG_EXP 0x0006 |
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| 1026 | #define MMD_SR_MII_AUTO_NEG_EXT 0x000F |
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| 1027 | |
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| 1028 | #define MMD_SR_MII_DIGITAL_CTRL_1 0x8000 |
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| 1029 | |
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| 1030 | #define MMD_SR_MII_AUTO_NEG_CTRL 0x8001 |
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| 1031 | |
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| 1032 | #define SR_MII_8_BIT BIT(8) |
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| 1033 | #define SR_MII_SGMII_LINK_UP BIT(4) |
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| 1034 | #define SR_MII_TX_CFG_PHY_MASTER BIT(3) |
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| 1035 | #define SR_MII_PCS_MODE_M 0x3 |
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| 1036 | #define SR_MII_PCS_MODE_S 1 |
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| 1037 | #define SR_MII_PCS_SGMII 2 |
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| 1038 | #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0) |
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| 1039 | |
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| 1040 | #define MMD_SR_MII_AUTO_NEG_STATUS 0x8002 |
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| 1041 | |
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| 1042 | #define SR_MII_STAT_LINK_UP BIT(4) |
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| 1043 | #define SR_MII_STAT_M 0x3 |
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| 1044 | #define SR_MII_STAT_S 2 |
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| 1045 | #define SR_MII_STAT_10_MBPS 0 |
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| 1046 | #define SR_MII_STAT_100_MBPS 1 |
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| 1047 | #define SR_MII_STAT_1000_MBPS 2 |
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| 1048 | #define SR_MII_STAT_FULL_DUPLEX BIT(1) |
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| 1049 | |
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| 1050 | #define MMD_SR_MII_PHY_CTRL 0x80A0 |
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| 1051 | |
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| 1052 | #define SR_MII_PHY_LANE_SEL_M 0xF |
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| 1053 | #define SR_MII_PHY_LANE_SEL_S 8 |
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| 1054 | #define SR_MII_PHY_WRITE BIT(1) |
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| 1055 | #define SR_MII_PHY_START_BUSY BIT(0) |
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| 1056 | |
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| 1057 | #define MMD_SR_MII_PHY_ADDR 0x80A1 |
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| 1058 | |
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| 1059 | #define SR_MII_PHY_ADDR_M (BIT(16) - 1) |
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| 1060 | |
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| 1061 | #define MMD_SR_MII_PHY_DATA 0x80A2 |
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| 1062 | |
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| 1063 | #define SR_MII_PHY_DATA_M (BIT(16) - 1) |
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| 1064 | |
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| 1065 | #define SR_MII_PHY_JTAG_CHIP_ID_HI 0x000C |
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| 1066 | #define SR_MII_PHY_JTAG_CHIP_ID_LO 0x000D |
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| 1067 | |
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| 1068 | #define REG_PORT_PHY_REMOTE_LB_LED 0x0122 |
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| 1069 | |
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| 1070 | #define PORT_REMOTE_LOOPBACK BIT(8) |
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| 1071 | #define PORT_LED_SELECT (3 << 6) |
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| 1072 | #define PORT_LED_CTRL (3 << 4) |
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| 1073 | #define PORT_LED_CTRL_TEST BIT(3) |
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| 1074 | #define PORT_10BT_PREAMBLE BIT(2) |
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| 1075 | #define PORT_LINK_MD_10BT_ENABLE BIT(1) |
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| 1076 | #define PORT_LINK_MD_PASS BIT(0) |
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| 1077 | |
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| 1078 | #define REG_PORT_PHY_LINK_MD 0x0124 |
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| 1079 | |
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| 1080 | #define PORT_START_CABLE_DIAG BIT(15) |
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| 1081 | #define PORT_TX_DISABLE BIT(14) |
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| 1082 | #define PORT_CABLE_DIAG_PAIR_M 0x3 |
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| 1083 | #define PORT_CABLE_DIAG_PAIR_S 12 |
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| 1084 | #define PORT_CABLE_DIAG_SELECT_M 0x3 |
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| 1085 | #define PORT_CABLE_DIAG_SELECT_S 10 |
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| 1086 | #define PORT_CABLE_DIAG_RESULT_M 0x3 |
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| 1087 | #define PORT_CABLE_DIAG_RESULT_S 8 |
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| 1088 | #define PORT_CABLE_STAT_NORMAL 0 |
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| 1089 | #define PORT_CABLE_STAT_OPEN 1 |
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| 1090 | #define PORT_CABLE_STAT_SHORT 2 |
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| 1091 | #define PORT_CABLE_STAT_FAILED 3 |
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| 1092 | #define PORT_CABLE_FAULT_COUNTER 0x00FF |
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| 1093 | |
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| 1094 | #define REG_PORT_PHY_PMA_STATUS 0x0126 |
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| 1095 | |
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| 1096 | #define PORT_1000_LINK_GOOD BIT(1) |
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| 1097 | #define PORT_100_LINK_GOOD BIT(0) |
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| 1098 | |
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| 1099 | #define REG_PORT_PHY_DIGITAL_STATUS 0x0128 |
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| 1100 | |
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| 1101 | #define PORT_LINK_DETECT BIT(14) |
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| 1102 | #define PORT_SIGNAL_DETECT BIT(13) |
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| 1103 | #define PORT_PHY_STAT_MDI BIT(12) |
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| 1104 | #define PORT_PHY_STAT_MASTER BIT(11) |
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| 1105 | |
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| 1106 | #define REG_PORT_PHY_RXER_COUNTER 0x012A |
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| 1107 | |
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| 1108 | #define REG_PORT_PHY_INT_ENABLE 0x0136 |
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| 1109 | #define REG_PORT_PHY_INT_STATUS 0x0137 |
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| 1110 | |
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| 1111 | #define JABBER_INT BIT(7) |
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| 1112 | #define RX_ERR_INT BIT(6) |
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| 1113 | #define PAGE_RX_INT BIT(5) |
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| 1114 | #define PARALLEL_DETECT_FAULT_INT BIT(4) |
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| 1115 | #define LINK_PARTNER_ACK_INT BIT(3) |
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| 1116 | #define LINK_DOWN_INT BIT(2) |
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| 1117 | #define REMOTE_FAULT_INT BIT(1) |
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| 1118 | #define LINK_UP_INT BIT(0) |
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| 1119 | |
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| 1120 | #define REG_PORT_PHY_DIGITAL_DEBUG_1 0x0138 |
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| 1121 | |
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| 1122 | #define PORT_REG_CLK_SPEED_25_MHZ BIT(14) |
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| 1123 | #define PORT_PHY_FORCE_MDI BIT(7) |
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| 1124 | #define PORT_PHY_AUTO_MDIX_DISABLE BIT(6) |
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| 1125 | |
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| 1126 | /* Same as PORT_PHY_LOOPBACK */ |
|---|
| 1127 | #define PORT_PHY_PCS_LOOPBACK BIT(0) |
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| 1128 | |
|---|
| 1129 | #define REG_PORT_PHY_DIGITAL_DEBUG_2 0x013A |
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| 1130 | |
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| 1131 | #define REG_PORT_PHY_DIGITAL_DEBUG_3 0x013C |
|---|
| 1132 | |
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| 1133 | #define PORT_100BT_FIXED_LATENCY BIT(15) |
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| 1134 | |
|---|
| 1135 | #define REG_PORT_PHY_PHY_CTRL 0x013E |
|---|
| 1136 | |
|---|
| 1137 | #define PORT_INT_PIN_HIGH BIT(14) |
|---|
| 1138 | #define PORT_ENABLE_JABBER BIT(9) |
|---|
| 1139 | #define PORT_STAT_SPEED_1000MBIT BIT(6) |
|---|
| 1140 | #define PORT_STAT_SPEED_100MBIT BIT(5) |
|---|
| 1141 | #define PORT_STAT_SPEED_10MBIT BIT(4) |
|---|
| 1142 | #define PORT_STAT_FULL_DUPLEX BIT(3) |
|---|
| 1143 | |
|---|
| 1144 | /* Same as PORT_PHY_STAT_MASTER */ |
|---|
| 1145 | #define PORT_STAT_MASTER BIT(2) |
|---|
| 1146 | #define PORT_RESET BIT(1) |
|---|
| 1147 | #define PORT_LINK_STATUS_FAIL BIT(0) |
|---|
| 1148 | |
|---|
| 1149 | /* 3 - xMII */ |
|---|
| 1150 | #define PORT_SGMII_SEL BIT(7) |
|---|
| 1151 | #define PORT_GRXC_ENABLE BIT(0) |
|---|
| 1152 | |
|---|
| 1153 | #define PORT_RMII_CLK_SEL BIT(7) |
|---|
| 1154 | #define PORT_MII_SEL_EDGE BIT(5) |
|---|
| 1155 | |
|---|
| 1156 | #define REG_PMAVBC 0x03AC |
|---|
| 1157 | |
|---|
| 1158 | #define PMAVBC_MASK GENMASK(26, 16) |
|---|
| 1159 | #define PMAVBC_MIN 0x580 |
|---|
| 1160 | |
|---|
| 1161 | /* 4 - MAC */ |
|---|
| 1162 | #define REG_PORT_MAC_CTRL_0 0x0400 |
|---|
| 1163 | |
|---|
| 1164 | #define PORT_BROADCAST_STORM BIT(1) |
|---|
| 1165 | #define PORT_JUMBO_FRAME BIT(0) |
|---|
| 1166 | |
|---|
| 1167 | #define REG_PORT_MAC_CTRL_1 0x0401 |
|---|
| 1168 | |
|---|
| 1169 | #define PORT_BACK_PRESSURE BIT(3) |
|---|
| 1170 | #define PORT_PASS_ALL BIT(0) |
|---|
| 1171 | |
|---|
| 1172 | #define REG_PORT_MAC_CTRL_2 0x0402 |
|---|
| 1173 | |
|---|
| 1174 | #define PORT_100BT_EEE_DISABLE BIT(7) |
|---|
| 1175 | #define PORT_1000BT_EEE_DISABLE BIT(6) |
|---|
| 1176 | |
|---|
| 1177 | #define REG_PORT_MAC_IN_RATE_LIMIT 0x0403 |
|---|
| 1178 | |
|---|
| 1179 | #define PORT_IN_PORT_BASED_S 6 |
|---|
| 1180 | #define PORT_RATE_PACKET_BASED_S 5 |
|---|
| 1181 | #define PORT_IN_FLOW_CTRL_S 4 |
|---|
| 1182 | #define PORT_COUNT_IFG_S 1 |
|---|
| 1183 | #define PORT_COUNT_PREAMBLE_S 0 |
|---|
| 1184 | #define PORT_IN_PORT_BASED BIT(6) |
|---|
| 1185 | #define PORT_IN_PACKET_BASED BIT(5) |
|---|
| 1186 | #define PORT_IN_FLOW_CTRL BIT(4) |
|---|
| 1187 | #define PORT_IN_LIMIT_MODE_M 0x3 |
|---|
| 1188 | #define PORT_IN_LIMIT_MODE_S 2 |
|---|
| 1189 | #define PORT_IN_ALL 0 |
|---|
| 1190 | #define PORT_IN_UNICAST 1 |
|---|
| 1191 | #define PORT_IN_MULTICAST 2 |
|---|
| 1192 | #define PORT_IN_BROADCAST 3 |
|---|
| 1193 | #define PORT_COUNT_IFG BIT(1) |
|---|
| 1194 | #define PORT_COUNT_PREAMBLE BIT(0) |
|---|
| 1195 | |
|---|
| 1196 | #define REG_PORT_IN_RATE_0 0x0410 |
|---|
| 1197 | #define REG_PORT_IN_RATE_1 0x0411 |
|---|
| 1198 | #define REG_PORT_IN_RATE_2 0x0412 |
|---|
| 1199 | #define REG_PORT_IN_RATE_3 0x0413 |
|---|
| 1200 | #define REG_PORT_IN_RATE_4 0x0414 |
|---|
| 1201 | #define REG_PORT_IN_RATE_5 0x0415 |
|---|
| 1202 | #define REG_PORT_IN_RATE_6 0x0416 |
|---|
| 1203 | #define REG_PORT_IN_RATE_7 0x0417 |
|---|
| 1204 | |
|---|
| 1205 | #define REG_PORT_OUT_RATE_0 0x0420 |
|---|
| 1206 | #define REG_PORT_OUT_RATE_1 0x0421 |
|---|
| 1207 | #define REG_PORT_OUT_RATE_2 0x0422 |
|---|
| 1208 | #define REG_PORT_OUT_RATE_3 0x0423 |
|---|
| 1209 | |
|---|
| 1210 | #define PORT_RATE_LIMIT_M (BIT(7) - 1) |
|---|
| 1211 | |
|---|
| 1212 | /* 5 - MIB Counters */ |
|---|
| 1213 | #define REG_PORT_MIB_CTRL_STAT__4 0x0500 |
|---|
| 1214 | |
|---|
| 1215 | #define MIB_COUNTER_READ BIT(25) |
|---|
| 1216 | #define MIB_COUNTER_FLUSH_FREEZE BIT(24) |
|---|
| 1217 | #define MIB_COUNTER_INDEX_M (BIT(8) - 1) |
|---|
| 1218 | #define MIB_COUNTER_INDEX_S 16 |
|---|
| 1219 | #define MIB_COUNTER_DATA_HI_M 0xF |
|---|
| 1220 | |
|---|
| 1221 | #define REG_PORT_MIB_DATA 0x0504 |
|---|
| 1222 | |
|---|
| 1223 | /* 6 - ACL */ |
|---|
| 1224 | #define REG_PORT_ACL_0 0x0600 |
|---|
| 1225 | |
|---|
| 1226 | #define ACL_FIRST_RULE_M 0xF |
|---|
| 1227 | |
|---|
| 1228 | #define REG_PORT_ACL_1 0x0601 |
|---|
| 1229 | |
|---|
| 1230 | #define ACL_MODE_M 0x3 |
|---|
| 1231 | #define ACL_MODE_S 4 |
|---|
| 1232 | #define ACL_MODE_DISABLE 0 |
|---|
| 1233 | #define ACL_MODE_LAYER_2 1 |
|---|
| 1234 | #define ACL_MODE_LAYER_3 2 |
|---|
| 1235 | #define ACL_MODE_LAYER_4 3 |
|---|
| 1236 | #define ACL_ENABLE_M 0x3 |
|---|
| 1237 | #define ACL_ENABLE_S 2 |
|---|
| 1238 | #define ACL_ENABLE_2_COUNT 0 |
|---|
| 1239 | #define ACL_ENABLE_2_TYPE 1 |
|---|
| 1240 | #define ACL_ENABLE_2_MAC 2 |
|---|
| 1241 | #define ACL_ENABLE_2_BOTH 3 |
|---|
| 1242 | #define ACL_ENABLE_3_IP 1 |
|---|
| 1243 | #define ACL_ENABLE_3_SRC_DST_COMP 2 |
|---|
| 1244 | #define ACL_ENABLE_4_PROTOCOL 0 |
|---|
| 1245 | #define ACL_ENABLE_4_TCP_PORT_COMP 1 |
|---|
| 1246 | #define ACL_ENABLE_4_UDP_PORT_COMP 2 |
|---|
| 1247 | #define ACL_ENABLE_4_TCP_SEQN_COMP 3 |
|---|
| 1248 | #define ACL_SRC BIT(1) |
|---|
| 1249 | #define ACL_EQUAL BIT(0) |
|---|
| 1250 | |
|---|
| 1251 | #define REG_PORT_ACL_2 0x0602 |
|---|
| 1252 | #define REG_PORT_ACL_3 0x0603 |
|---|
| 1253 | |
|---|
| 1254 | #define ACL_MAX_PORT 0xFFFF |
|---|
| 1255 | |
|---|
| 1256 | #define REG_PORT_ACL_4 0x0604 |
|---|
| 1257 | #define REG_PORT_ACL_5 0x0605 |
|---|
| 1258 | |
|---|
| 1259 | #define ACL_MIN_PORT 0xFFFF |
|---|
| 1260 | #define ACL_IP_ADDR 0xFFFFFFFF |
|---|
| 1261 | #define ACL_TCP_SEQNUM 0xFFFFFFFF |
|---|
| 1262 | |
|---|
| 1263 | #define REG_PORT_ACL_6 0x0606 |
|---|
| 1264 | |
|---|
| 1265 | #define ACL_RESERVED 0xF8 |
|---|
| 1266 | #define ACL_PORT_MODE_M 0x3 |
|---|
| 1267 | #define ACL_PORT_MODE_S 1 |
|---|
| 1268 | #define ACL_PORT_MODE_DISABLE 0 |
|---|
| 1269 | #define ACL_PORT_MODE_EITHER 1 |
|---|
| 1270 | #define ACL_PORT_MODE_IN_RANGE 2 |
|---|
| 1271 | #define ACL_PORT_MODE_OUT_OF_RANGE 3 |
|---|
| 1272 | |
|---|
| 1273 | #define REG_PORT_ACL_7 0x0607 |
|---|
| 1274 | |
|---|
| 1275 | #define ACL_TCP_FLAG_ENABLE BIT(0) |
|---|
| 1276 | |
|---|
| 1277 | #define REG_PORT_ACL_8 0x0608 |
|---|
| 1278 | |
|---|
| 1279 | #define ACL_TCP_FLAG_M 0xFF |
|---|
| 1280 | |
|---|
| 1281 | #define REG_PORT_ACL_9 0x0609 |
|---|
| 1282 | |
|---|
| 1283 | #define ACL_TCP_FLAG 0xFF |
|---|
| 1284 | #define ACL_ETH_TYPE 0xFFFF |
|---|
| 1285 | #define ACL_IP_M 0xFFFFFFFF |
|---|
| 1286 | |
|---|
| 1287 | #define REG_PORT_ACL_A 0x060A |
|---|
| 1288 | |
|---|
| 1289 | #define ACL_PRIO_MODE_M 0x3 |
|---|
| 1290 | #define ACL_PRIO_MODE_S 6 |
|---|
| 1291 | #define ACL_PRIO_MODE_DISABLE 0 |
|---|
| 1292 | #define ACL_PRIO_MODE_HIGHER 1 |
|---|
| 1293 | #define ACL_PRIO_MODE_LOWER 2 |
|---|
| 1294 | #define ACL_PRIO_MODE_REPLACE 3 |
|---|
| 1295 | #define ACL_PRIO_M KS_PRIO_M |
|---|
| 1296 | #define ACL_PRIO_S 3 |
|---|
| 1297 | #define ACL_VLAN_PRIO_REPLACE BIT(2) |
|---|
| 1298 | #define ACL_VLAN_PRIO_M KS_PRIO_M |
|---|
| 1299 | #define ACL_VLAN_PRIO_HI_M 0x3 |
|---|
| 1300 | |
|---|
| 1301 | #define REG_PORT_ACL_B 0x060B |
|---|
| 1302 | |
|---|
| 1303 | #define ACL_VLAN_PRIO_LO_M 0x8 |
|---|
| 1304 | #define ACL_VLAN_PRIO_S 7 |
|---|
| 1305 | #define ACL_MAP_MODE_M 0x3 |
|---|
| 1306 | #define ACL_MAP_MODE_S 5 |
|---|
| 1307 | #define ACL_MAP_MODE_DISABLE 0 |
|---|
| 1308 | #define ACL_MAP_MODE_OR 1 |
|---|
| 1309 | #define ACL_MAP_MODE_AND 2 |
|---|
| 1310 | #define ACL_MAP_MODE_REPLACE 3 |
|---|
| 1311 | |
|---|
| 1312 | #define ACL_CNT_M (BIT(11) - 1) |
|---|
| 1313 | #define ACL_CNT_S 5 |
|---|
| 1314 | |
|---|
| 1315 | #define REG_PORT_ACL_C 0x060C |
|---|
| 1316 | |
|---|
| 1317 | #define REG_PORT_ACL_D 0x060D |
|---|
| 1318 | #define ACL_MSEC_UNIT BIT(6) |
|---|
| 1319 | #define ACL_INTR_MODE BIT(5) |
|---|
| 1320 | #define ACL_PORT_MAP 0x7F |
|---|
| 1321 | |
|---|
| 1322 | #define REG_PORT_ACL_E 0x060E |
|---|
| 1323 | #define REG_PORT_ACL_F 0x060F |
|---|
| 1324 | |
|---|
| 1325 | #define REG_PORT_ACL_BYTE_EN_MSB 0x0610 |
|---|
| 1326 | #define REG_PORT_ACL_BYTE_EN_LSB 0x0611 |
|---|
| 1327 | |
|---|
| 1328 | #define ACL_ACTION_START 0xA |
|---|
| 1329 | #define ACL_ACTION_LEN 4 |
|---|
| 1330 | #define ACL_INTR_CNT_START 0xD |
|---|
| 1331 | #define ACL_RULESET_START 0xE |
|---|
| 1332 | #define ACL_RULESET_LEN 2 |
|---|
| 1333 | #define ACL_TABLE_LEN 16 |
|---|
| 1334 | |
|---|
| 1335 | #define ACL_ACTION_ENABLE 0x003C |
|---|
| 1336 | #define ACL_MATCH_ENABLE 0x7FC3 |
|---|
| 1337 | #define ACL_RULESET_ENABLE 0x8003 |
|---|
| 1338 | #define ACL_BYTE_ENABLE 0xFFFF |
|---|
| 1339 | |
|---|
| 1340 | #define REG_PORT_ACL_CTRL_0 0x0612 |
|---|
| 1341 | |
|---|
| 1342 | #define PORT_ACL_WRITE_DONE BIT(6) |
|---|
| 1343 | #define PORT_ACL_READ_DONE BIT(5) |
|---|
| 1344 | #define PORT_ACL_WRITE BIT(4) |
|---|
| 1345 | #define PORT_ACL_INDEX_M 0xF |
|---|
| 1346 | |
|---|
| 1347 | #define REG_PORT_ACL_CTRL_1 0x0613 |
|---|
| 1348 | |
|---|
| 1349 | /* 8 - Classification and Policing */ |
|---|
| 1350 | #define REG_PORT_MRI_MIRROR_CTRL 0x0800 |
|---|
| 1351 | |
|---|
| 1352 | #define PORT_MIRROR_RX BIT(6) |
|---|
| 1353 | #define PORT_MIRROR_TX BIT(5) |
|---|
| 1354 | #define PORT_MIRROR_SNIFFER BIT(1) |
|---|
| 1355 | |
|---|
| 1356 | #define REG_PORT_MRI_PRIO_CTRL 0x0801 |
|---|
| 1357 | |
|---|
| 1358 | #define PORT_HIGHEST_PRIO BIT(7) |
|---|
| 1359 | #define PORT_OR_PRIO BIT(6) |
|---|
| 1360 | #define PORT_MAC_PRIO_ENABLE BIT(4) |
|---|
| 1361 | #define PORT_VLAN_PRIO_ENABLE BIT(3) |
|---|
| 1362 | #define PORT_802_1P_PRIO_ENABLE BIT(2) |
|---|
| 1363 | #define PORT_DIFFSERV_PRIO_ENABLE BIT(1) |
|---|
| 1364 | #define PORT_ACL_PRIO_ENABLE BIT(0) |
|---|
| 1365 | |
|---|
| 1366 | #define REG_PORT_MRI_MAC_CTRL 0x0802 |
|---|
| 1367 | |
|---|
| 1368 | #define PORT_USER_PRIO_CEILING BIT(7) |
|---|
| 1369 | #define PORT_DROP_NON_VLAN BIT(4) |
|---|
| 1370 | #define PORT_DROP_TAG BIT(3) |
|---|
| 1371 | #define PORT_BASED_PRIO_M KS_PRIO_M |
|---|
| 1372 | #define PORT_BASED_PRIO_S 0 |
|---|
| 1373 | |
|---|
| 1374 | #define REG_PORT_MRI_AUTHEN_CTRL 0x0803 |
|---|
| 1375 | |
|---|
| 1376 | #define PORT_ACL_ENABLE BIT(2) |
|---|
| 1377 | #define PORT_AUTHEN_MODE 0x3 |
|---|
| 1378 | #define PORT_AUTHEN_PASS 0 |
|---|
| 1379 | #define PORT_AUTHEN_BLOCK 1 |
|---|
| 1380 | #define PORT_AUTHEN_TRAP 2 |
|---|
| 1381 | |
|---|
| 1382 | #define REG_PORT_MRI_INDEX__4 0x0804 |
|---|
| 1383 | |
|---|
| 1384 | #define MRI_INDEX_P_M 0x7 |
|---|
| 1385 | #define MRI_INDEX_P_S 16 |
|---|
| 1386 | #define MRI_INDEX_Q_M 0x3 |
|---|
| 1387 | #define MRI_INDEX_Q_S 0 |
|---|
| 1388 | |
|---|
| 1389 | #define REG_PORT_MRI_TC_MAP__4 0x0808 |
|---|
| 1390 | |
|---|
| 1391 | #define PORT_TC_MAP_M 0xf |
|---|
| 1392 | #define PORT_TC_MAP_S 4 |
|---|
| 1393 | |
|---|
| 1394 | #define REG_PORT_MRI_POLICE_CTRL__4 0x080C |
|---|
| 1395 | |
|---|
| 1396 | #define POLICE_DROP_ALL BIT(10) |
|---|
| 1397 | #define POLICE_PACKET_TYPE_M 0x3 |
|---|
| 1398 | #define POLICE_PACKET_TYPE_S 8 |
|---|
| 1399 | #define POLICE_PACKET_DROPPED 0 |
|---|
| 1400 | #define POLICE_PACKET_GREEN 1 |
|---|
| 1401 | #define POLICE_PACKET_YELLOW 2 |
|---|
| 1402 | #define POLICE_PACKET_RED 3 |
|---|
| 1403 | #define PORT_BASED_POLICING BIT(7) |
|---|
| 1404 | #define NON_DSCP_COLOR_M 0x3 |
|---|
| 1405 | #define NON_DSCP_COLOR_S 5 |
|---|
| 1406 | #define COLOR_MARK_ENABLE BIT(4) |
|---|
| 1407 | #define COLOR_REMAP_ENABLE BIT(3) |
|---|
| 1408 | #define POLICE_DROP_SRP BIT(2) |
|---|
| 1409 | #define POLICE_COLOR_NOT_AWARE BIT(1) |
|---|
| 1410 | #define POLICE_ENABLE BIT(0) |
|---|
| 1411 | |
|---|
| 1412 | #define REG_PORT_POLICE_COLOR_0__4 0x0810 |
|---|
| 1413 | #define REG_PORT_POLICE_COLOR_1__4 0x0814 |
|---|
| 1414 | #define REG_PORT_POLICE_COLOR_2__4 0x0818 |
|---|
| 1415 | #define REG_PORT_POLICE_COLOR_3__4 0x081C |
|---|
| 1416 | |
|---|
| 1417 | #define POLICE_COLOR_MAP_S 2 |
|---|
| 1418 | #define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1) |
|---|
| 1419 | |
|---|
| 1420 | #define REG_PORT_POLICE_RATE__4 0x0820 |
|---|
| 1421 | |
|---|
| 1422 | #define POLICE_CIR_S 16 |
|---|
| 1423 | #define POLICE_PIR_S 0 |
|---|
| 1424 | |
|---|
| 1425 | #define REG_PORT_POLICE_BURST_SIZE__4 0x0824 |
|---|
| 1426 | |
|---|
| 1427 | #define POLICE_BURST_SIZE_M 0x3FFF |
|---|
| 1428 | #define POLICE_CBS_S 16 |
|---|
| 1429 | #define POLICE_PBS_S 0 |
|---|
| 1430 | |
|---|
| 1431 | #define REG_PORT_WRED_PM_CTRL_0__4 0x0830 |
|---|
| 1432 | |
|---|
| 1433 | #define WRED_PM_CTRL_M (BIT(11) - 1) |
|---|
| 1434 | |
|---|
| 1435 | #define WRED_PM_MAX_THRESHOLD_S 16 |
|---|
| 1436 | #define WRED_PM_MIN_THRESHOLD_S 0 |
|---|
| 1437 | |
|---|
| 1438 | #define REG_PORT_WRED_PM_CTRL_1__4 0x0834 |
|---|
| 1439 | |
|---|
| 1440 | #define WRED_PM_MULTIPLIER_S 16 |
|---|
| 1441 | #define WRED_PM_AVG_QUEUE_SIZE_S 0 |
|---|
| 1442 | |
|---|
| 1443 | #define REG_PORT_WRED_QUEUE_CTRL_0__4 0x0840 |
|---|
| 1444 | #define REG_PORT_WRED_QUEUE_CTRL_1__4 0x0844 |
|---|
| 1445 | |
|---|
| 1446 | #define REG_PORT_WRED_QUEUE_PMON__4 0x0848 |
|---|
| 1447 | |
|---|
| 1448 | #define WRED_RANDOM_DROP_ENABLE BIT(31) |
|---|
| 1449 | #define WRED_PMON_FLUSH BIT(30) |
|---|
| 1450 | #define WRED_DROP_GYR_DISABLE BIT(29) |
|---|
| 1451 | #define WRED_DROP_YR_DISABLE BIT(28) |
|---|
| 1452 | #define WRED_DROP_R_DISABLE BIT(27) |
|---|
| 1453 | #define WRED_DROP_ALL BIT(26) |
|---|
| 1454 | #define WRED_PMON_M (BIT(24) - 1) |
|---|
| 1455 | |
|---|
| 1456 | /* 9 - Shaping */ |
|---|
| 1457 | |
|---|
| 1458 | #define REG_PORT_MTI_QUEUE_CTRL_0__4 0x0904 |
|---|
| 1459 | |
|---|
| 1460 | #define MTI_PVID_REPLACE BIT(0) |
|---|
| 1461 | |
|---|
| 1462 | #define REG_PORT_MTI_CREDIT_INCREMENT 0x091A |
|---|
| 1463 | |
|---|
| 1464 | /* A - QM */ |
|---|
| 1465 | |
|---|
| 1466 | #define REG_PORT_QM_CTRL__4 0x0A00 |
|---|
| 1467 | |
|---|
| 1468 | #define PORT_QM_DROP_PRIO_M 0x3 |
|---|
| 1469 | |
|---|
| 1470 | #define REG_PORT_VLAN_MEMBERSHIP__4 0x0A04 |
|---|
| 1471 | |
|---|
| 1472 | #define REG_PORT_QM_QUEUE_INDEX__4 0x0A08 |
|---|
| 1473 | |
|---|
| 1474 | #define PORT_QM_QUEUE_INDEX_S 24 |
|---|
| 1475 | #define PORT_QM_BURST_SIZE_S 16 |
|---|
| 1476 | #define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1) |
|---|
| 1477 | |
|---|
| 1478 | #define REG_PORT_QM_WATER_MARK__4 0x0A0C |
|---|
| 1479 | |
|---|
| 1480 | #define PORT_QM_HI_WATER_MARK_S 16 |
|---|
| 1481 | #define PORT_QM_LO_WATER_MARK_S 0 |
|---|
| 1482 | #define PORT_QM_WATER_MARK_M (BIT(11) - 1) |
|---|
| 1483 | |
|---|
| 1484 | #define REG_PORT_QM_TX_CNT_0__4 0x0A10 |
|---|
| 1485 | |
|---|
| 1486 | #define PORT_QM_TX_CNT_USED_S 0 |
|---|
| 1487 | #define PORT_QM_TX_CNT_M (BIT(11) - 1) |
|---|
| 1488 | #define PORT_QM_TX_CNT_MAX 0x200 |
|---|
| 1489 | |
|---|
| 1490 | #define REG_PORT_QM_TX_CNT_1__4 0x0A14 |
|---|
| 1491 | |
|---|
| 1492 | #define PORT_QM_TX_CNT_CALCULATED_S 16 |
|---|
| 1493 | #define PORT_QM_TX_CNT_AVAIL_S 0 |
|---|
| 1494 | |
|---|
| 1495 | /* B - LUE */ |
|---|
| 1496 | #define REG_PORT_LUE_CTRL 0x0B00 |
|---|
| 1497 | |
|---|
| 1498 | #define PORT_VLAN_LOOKUP_VID_0 BIT(7) |
|---|
| 1499 | #define PORT_INGRESS_FILTER BIT(6) |
|---|
| 1500 | #define PORT_DISCARD_NON_VID BIT(5) |
|---|
| 1501 | #define PORT_MAC_BASED_802_1X BIT(4) |
|---|
| 1502 | #define PORT_SRC_ADDR_FILTER BIT(3) |
|---|
| 1503 | |
|---|
| 1504 | #define REG_PORT_LUE_MSTP_INDEX 0x0B01 |
|---|
| 1505 | |
|---|
| 1506 | #define REG_PORT_LUE_MSTP_STATE 0x0B04 |
|---|
| 1507 | |
|---|
| 1508 | /* C - PTP */ |
|---|
| 1509 | |
|---|
| 1510 | #define REG_PTP_PORT_RX_DELAY__2 0x0C00 |
|---|
| 1511 | #define REG_PTP_PORT_TX_DELAY__2 0x0C02 |
|---|
| 1512 | #define REG_PTP_PORT_ASYM_DELAY__2 0x0C04 |
|---|
| 1513 | |
|---|
| 1514 | #define REG_PTP_PORT_XDELAY_TS 0x0C08 |
|---|
| 1515 | #define REG_PTP_PORT_XDELAY_TS_H 0x0C08 |
|---|
| 1516 | #define REG_PTP_PORT_XDELAY_TS_L 0x0C0A |
|---|
| 1517 | |
|---|
| 1518 | #define REG_PTP_PORT_SYNC_TS 0x0C0C |
|---|
| 1519 | #define REG_PTP_PORT_SYNC_TS_H 0x0C0C |
|---|
| 1520 | #define REG_PTP_PORT_SYNC_TS_L 0x0C0E |
|---|
| 1521 | |
|---|
| 1522 | #define REG_PTP_PORT_PDRESP_TS 0x0C10 |
|---|
| 1523 | #define REG_PTP_PORT_PDRESP_TS_H 0x0C10 |
|---|
| 1524 | #define REG_PTP_PORT_PDRESP_TS_L 0x0C12 |
|---|
| 1525 | |
|---|
| 1526 | #define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14 |
|---|
| 1527 | #define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16 |
|---|
| 1528 | |
|---|
| 1529 | #define PTP_PORT_SYNC_INT BIT(15) |
|---|
| 1530 | #define PTP_PORT_XDELAY_REQ_INT BIT(14) |
|---|
| 1531 | #define PTP_PORT_PDELAY_RESP_INT BIT(13) |
|---|
| 1532 | |
|---|
| 1533 | #define REG_PTP_PORT_LINK_DELAY__4 0x0C18 |
|---|
| 1534 | |
|---|
| 1535 | #define PRIO_QUEUES 4 |
|---|
| 1536 | #define RX_PRIO_QUEUES 8 |
|---|
| 1537 | |
|---|
| 1538 | #define KS_PRIO_IN_REG 2 |
|---|
| 1539 | |
|---|
| 1540 | #define TOTAL_PORT_NUM 7 |
|---|
| 1541 | |
|---|
| 1542 | #define KSZ9477_COUNTER_NUM 0x20 |
|---|
| 1543 | #define TOTAL_KSZ9477_COUNTER_NUM (KSZ9477_COUNTER_NUM + 2 + 2) |
|---|
| 1544 | |
|---|
| 1545 | #define SWITCH_COUNTER_NUM KSZ9477_COUNTER_NUM |
|---|
| 1546 | #define TOTAL_SWITCH_COUNTER_NUM TOTAL_KSZ9477_COUNTER_NUM |
|---|
| 1547 | |
|---|
| 1548 | #define P_BCAST_STORM_CTRL REG_PORT_MAC_CTRL_0 |
|---|
| 1549 | #define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL |
|---|
| 1550 | #define P_MIRROR_CTRL REG_PORT_MRI_MIRROR_CTRL |
|---|
| 1551 | #define P_PHY_CTRL REG_PORT_PHY_CTRL |
|---|
| 1552 | #define P_RATE_LIMIT_CTRL REG_PORT_MAC_IN_RATE_LIMIT |
|---|
| 1553 | |
|---|
| 1554 | #define S_LINK_AGING_CTRL REG_SW_LUE_CTRL_1 |
|---|
| 1555 | #define S_MIRROR_CTRL REG_SW_MRI_CTRL_0 |
|---|
| 1556 | #define S_REPLACE_VID_CTRL REG_SW_MAC_CTRL_2 |
|---|
| 1557 | #define S_802_1P_PRIO_CTRL REG_SW_MAC_802_1P_MAP_0 |
|---|
| 1558 | #define S_TOS_PRIO_CTRL REG_SW_MAC_TOS_PRIO_0 |
|---|
| 1559 | #define S_FLUSH_TABLE_CTRL REG_SW_LUE_CTRL_1 |
|---|
| 1560 | |
|---|
| 1561 | #define SW_FLUSH_DYN_MAC_TABLE SW_FLUSH_MSTP_TABLE |
|---|
| 1562 | |
|---|
| 1563 | #define MAX_TIMESTAMP_UNIT 2 |
|---|
| 1564 | #define MAX_TRIG_UNIT 3 |
|---|
| 1565 | #define MAX_TIMESTAMP_EVENT_UNIT 8 |
|---|
| 1566 | #define MAX_GPIO 4 |
|---|
| 1567 | |
|---|
| 1568 | #define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1) |
|---|
| 1569 | #define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1) |
|---|
| 1570 | |
|---|
| 1571 | #endif /* KSZ9477_REGS_H */ |
|---|
| 1572 | |
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