1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Overview:
4	* This is the generic MTD driver for NAND flash devices. It should be
5	* capable of working with almost all NAND chips currently available.
6	*
7	* Additional technical information is available on
8	* http://www.linux-mtd.infradead.org/doc/nand.html
9	*
10	* Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
11	* 2002-2006 Thomas Gleixner (tglx@kernel.org)
12	*
13	* Credits:
14	* David Woodhouse for adding multichip support
15	*
16	* Aleph One Ltd. and Toby Churchill Ltd. for supporting the
17	* rework for 2K page size chips
18	*
19	* TODO:
20	* Enable cached programming for 2k page size chips
21	* Check, if mtd->ecctype should be set to MTD_ECC_HW
22	* if we have HW ECC support.
23	* BBT table is not serialized, has to be fixed
24	*/
25
26	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
28	#include <linux/module.h>
29	#include <linux/delay.h>
30	#include <linux/errno.h>
31	#include <linux/err.h>
32	#include <linux/sched.h>
33	#include <linux/slab.h>
34	#include <linux/mm.h>
35	#include <linux/types.h>
36	#include <linux/mtd/mtd.h>
37	#include <linux/mtd/nand.h>
38	#include <linux/mtd/nand-ecc-sw-hamming.h>
39	#include <linux/mtd/nand-ecc-sw-bch.h>
40	#include <linux/interrupt.h>
41	#include <linux/bitops.h>
42	#include <linux/io.h>
43	#include <linux/mtd/partitions.h>
44	#include <linux/of.h>
45	#include <linux/gpio/consumer.h>
46
47	#include "internals.h"
48
49	static int nand_pairing_dist3_get_info(struct mtd_info *mtd, int page,
50	struct mtd_pairing_info *info)
51	{
52	int lastpage = (mtd->erasesize / mtd->writesize) - 1;
53	int dist = 3;
54
55	if (page == lastpage)
56	dist = 2;
57
58	if (!page || (page & 1)) {
59	info->group = 0;
60	info->pair = (page + 1) / 2;
61	} else {
62	info->group = 1;
63	info->pair = (page + 1 - dist) / 2;
64	}
65
66	return 0;
67	}
68
69	static int nand_pairing_dist3_get_wunit(struct mtd_info *mtd,
70	const struct mtd_pairing_info *info)
71	{
72	int lastpair = ((mtd->erasesize / mtd->writesize) - 1) / 2;
73	int page = info->pair * 2;
74	int dist = 3;
75
76	if (!info->group && !info->pair)
77	return 0;
78
79	if (info->pair == lastpair && info->group)
80	dist = 2;
81
82	if (!info->group)
83	page--;
84	else if (info->pair)
85	page += dist - 1;
86
87	if (page >= mtd->erasesize / mtd->writesize)
88	return -EINVAL;
89
90	return page;
91	}
92
93	const struct mtd_pairing_scheme dist3_pairing_scheme = {
94	.ngroups = 2,
95	.get_info = nand_pairing_dist3_get_info,
96	.get_wunit = nand_pairing_dist3_get_wunit,
97	};
98
99	static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len)
100	{
101	int ret = 0;
102
103	/* Start address must align on block boundary */
104	if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
105	pr_debug("%s: unaligned address\n", __func__);
106	ret = -EINVAL;
107	}
108
109	/* Length must align on block boundary */
110	if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
111	pr_debug("%s: length not block aligned\n", __func__);
112	ret = -EINVAL;
113	}
114
115	return ret;
116	}
117
118	/**
119	* nand_extract_bits - Copy unaligned bits from one buffer to another one
120	* @dst: destination buffer
121	* @dst_off: bit offset at which the writing starts
122	* @src: source buffer
123	* @src_off: bit offset at which the reading starts
124	* @nbits: number of bits to copy from @src to @dst
125	*
126	* Copy bits from one memory region to another (overlap authorized).
127	*/
128	void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
129	unsigned int src_off, unsigned int nbits)
130	{
131	unsigned int tmp, n;
132
133	dst += dst_off / 8;
134	dst_off %= 8;
135	src += src_off / 8;
136	src_off %= 8;
137
138	while (nbits) {
139	n = min3(8 - dst_off, 8 - src_off, nbits);
140
141	tmp = (*src >> src_off) & GENMASK(n - 1, 0);
142	*dst &= ~GENMASK(n - 1 + dst_off, dst_off);
143	*dst |= tmp << dst_off;
144
145	dst_off += n;
146	if (dst_off >= 8) {
147	dst++;
148	dst_off -= 8;
149	}
150
151	src_off += n;
152	if (src_off >= 8) {
153	src++;
154	src_off -= 8;
155	}
156
157	nbits -= n;
158	}
159	}
160	EXPORT_SYMBOL_GPL(nand_extract_bits);
161
162	/**
163	* nand_select_target() - Select a NAND target (A.K.A. die)
164	* @chip: NAND chip object
165	* @cs: the CS line to select. Note that this CS id is always from the chip
166	* PoV, not the controller one
167	*
168	* Select a NAND target so that further operations executed on @chip go to the
169	* selected NAND target.
170	*/
171	void nand_select_target(struct nand_chip *chip, unsigned int cs)
172	{
173	/*
174	* cs should always lie between 0 and nanddev_ntargets(), when that's
175	* not the case it's a bug and the caller should be fixed.
176	*/
177	if (WARN_ON(cs > nanddev_ntargets(&chip->base)))
178	return;
179
180	chip->cur_cs = cs;
181
182	if (chip->legacy.select_chip)
183	chip->legacy.select_chip(chip, cs);
184	}
185	EXPORT_SYMBOL_GPL(nand_select_target);
186
187	/**
188	* nand_deselect_target() - Deselect the currently selected target
189	* @chip: NAND chip object
190	*
191	* Deselect the currently selected NAND target. The result of operations
192	* executed on @chip after the target has been deselected is undefined.
193	*/
194	void nand_deselect_target(struct nand_chip *chip)
195	{
196	if (chip->legacy.select_chip)
197	chip->legacy.select_chip(chip, -1);
198
199	chip->cur_cs = -1;
200	}
201	EXPORT_SYMBOL_GPL(nand_deselect_target);
202
203	/**
204	* nand_release_device - [GENERIC] release chip
205	* @chip: NAND chip object
206	*
207	* Release chip lock and wake up anyone waiting on the device.
208	*/
209	static void nand_release_device(struct nand_chip *chip)
210	{
211	/* Release the controller and the chip */
212	mutex_unlock(lock: &chip->controller->lock);
213	mutex_unlock(lock: &chip->lock);
214	}
215
216	/**
217	* nand_bbm_get_next_page - Get the next page for bad block markers
218	* @chip: NAND chip object
219	* @page: First page to start checking for bad block marker usage
220	*
221	* Returns an integer that corresponds to the page offset within a block, for
222	* a page that is used to store bad block markers. If no more pages are
223	* available, -EINVAL is returned.
224	*/
225	int nand_bbm_get_next_page(struct nand_chip *chip, int page)
226	{
227	struct mtd_info *mtd = nand_to_mtd(chip);
228	int last_page = ((mtd->erasesize - mtd->writesize) >>
229	chip->page_shift) & chip->pagemask;
230	unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE
231	| NAND_BBM_LASTPAGE;
232
233	if (page == 0 && !(chip->options & bbm_flags))
234	return 0;
235	if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
236	return 0;
237	if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
238	return 1;
239	if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
240	return last_page;
241
242	return -EINVAL;
243	}
244
245	/**
246	* nand_block_bad - [DEFAULT] Read bad block marker from the chip
247	* @chip: NAND chip object
248	* @ofs: offset from device start
249	*
250	* Check, if the block is bad.
251	*/
252	static int nand_block_bad(struct nand_chip *chip, loff_t ofs)
253	{
254	int first_page, page_offset;
255	int res;
256	u8 bad;
257
258	first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
259	page_offset = nand_bbm_get_next_page(chip, page: 0);
260
261	while (page_offset >= 0) {
262	res = chip->ecc.read_oob(chip, first_page + page_offset);
263	if (res < 0)
264	return res;
265
266	bad = chip->oob_poi[chip->badblockpos];
267
268	if (likely(chip->badblockbits == 8))
269	res = bad != 0xFF;
270	else
271	res = hweight8(bad) < chip->badblockbits;
272	if (res)
273	return res;
274
275	page_offset = nand_bbm_get_next_page(chip, page: page_offset + 1);
276	}
277
278	return 0;
279	}
280
281	/**
282	* nand_region_is_secured() - Check if the region is secured
283	* @chip: NAND chip object
284	* @offset: Offset of the region to check
285	* @size: Size of the region to check
286	*
287	* Checks if the region is secured by comparing the offset and size with the
288	* list of secure regions obtained from DT. Returns true if the region is
289	* secured else false.
290	*/
291	static bool nand_region_is_secured(struct nand_chip *chip, loff_t offset, u64 size)
292	{
293	int i;
294
295	/* Skip touching the secure regions if present */
296	for (i = 0; i < chip->nr_secure_regions; i++) {
297	const struct nand_secure_region *region = &chip->secure_regions[i];
298
299	if (offset + size <= region->offset ||
300	offset >= region->offset + region->size)
301	continue;
302
303	pr_debug("%s: Region 0x%llx - 0x%llx is secured!",
304	__func__, offset, offset + size);
305
306	return true;
307	}
308
309	return false;
310	}
311
312	static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs)
313	{
314	struct mtd_info *mtd = nand_to_mtd(chip);
315
316	if (chip->options & NAND_NO_BBM_QUIRK)
317	return 0;
318
319	/* Check if the region is secured */
320	if (nand_region_is_secured(chip, offset: ofs, size: mtd->erasesize))
321	return -EIO;
322
323	if (mtd_check_expert_analysis_mode())
324	return 0;
325
326	if (chip->legacy.block_bad)
327	return chip->legacy.block_bad(chip, ofs);
328
329	return nand_block_bad(chip, ofs);
330	}
331
332	/**
333	* nand_get_device - [GENERIC] Get chip for selected access
334	* @chip: NAND chip structure
335	*
336	* Lock the device and its controller for exclusive access
337	*/
338	static void nand_get_device(struct nand_chip *chip)
339	{
340	/* Wait until the device is resumed. */
341	while (1) {
342	mutex_lock(&chip->lock);
343	if (!chip->suspended) {
344	mutex_lock(&chip->controller->lock);
345	return;
346	}
347	mutex_unlock(lock: &chip->lock);
348
349	wait_event(chip->resume_wq, !chip->suspended);
350	}
351	}
352
353	/**
354	* nand_check_wp - [GENERIC] check if the chip is write protected
355	* @chip: NAND chip object
356	*
357	* Check, if the device is write protected. The function expects, that the
358	* device is already selected.
359	*/
360	static int nand_check_wp(struct nand_chip *chip)
361	{
362	u8 status;
363	int ret;
364
365	/* Broken xD cards report WP despite being writable */
366	if (chip->options & NAND_BROKEN_XD)
367	return 0;
368
369	/* controller responsible for NAND write protect */
370	if (chip->controller->controller_wp)
371	return 0;
372
373	/* Check the WP bit */
374	ret = nand_status_op(chip, status: &status);
375	if (ret)
376	return ret;
377
378	return status & NAND_STATUS_WP ? 0 : 1;
379	}
380
381	/**
382	* nand_fill_oob - [INTERN] Transfer client buffer to oob
383	* @chip: NAND chip object
384	* @oob: oob data buffer
385	* @len: oob data write length
386	* @ops: oob ops structure
387	*/
388	static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
389	struct mtd_oob_ops *ops)
390	{
391	struct mtd_info *mtd = nand_to_mtd(chip);
392	int ret;
393
394	/*
395	* Initialise to all 0xFF, to avoid the possibility of left over OOB
396	* data from a previous OOB read.
397	*/
398	memset(chip->oob_poi, 0xff, mtd->oobsize);
399
400	switch (ops->mode) {
401
402	case MTD_OPS_PLACE_OOB:
403	case MTD_OPS_RAW:
404	memcpy(chip->oob_poi + ops->ooboffs, oob, len);
405	return oob + len;
406
407	case MTD_OPS_AUTO_OOB:
408	ret = mtd_ooblayout_set_databytes(mtd, databuf: oob, oobbuf: chip->oob_poi,
409	start: ops->ooboffs, nbytes: len);
410	BUG_ON(ret);
411	return oob + len;
412
413	default:
414	BUG();
415	}
416	return NULL;
417	}
418
419	/**
420	* nand_do_write_oob - [MTD Interface] NAND write out-of-band
421	* @chip: NAND chip object
422	* @to: offset to write to
423	* @ops: oob operation description structure
424	*
425	* NAND write out-of-band.
426	*/
427	static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
428	struct mtd_oob_ops *ops)
429	{
430	struct mtd_info *mtd = nand_to_mtd(chip);
431	int chipnr, page, status, len, ret;
432
433	pr_debug("%s: to = 0x%08x, len = %i\n",
434	__func__, (unsigned int)to, (int)ops->ooblen);
435
436	len = mtd_oobavail(mtd, ops);
437
438	/* Do not allow write past end of page */
439	if ((ops->ooboffs + ops->ooblen) > len) {
440	pr_debug("%s: attempt to write past end of page\n",
441	__func__);
442	return -EINVAL;
443	}
444
445	/* Check if the region is secured */
446	if (nand_region_is_secured(chip, offset: to, size: ops->ooblen))
447	return -EIO;
448
449	chipnr = (int)(to >> chip->chip_shift);
450
451	/*
452	* Reset the chip. Some chips (like the Toshiba TC5832DC found in one
453	* of my DiskOnChip 2000 test units) will clear the whole data page too
454	* if we don't do this. I have no clue why, but I seem to have 'fixed'
455	* it in the doc2000 driver in August 1999. dwmw2.
456	*/
457	ret = nand_reset(chip, chipnr);
458	if (ret)
459	return ret;
460
461	nand_select_target(chip, chipnr);
462
463	/* Shift to get page */
464	page = (int)(to >> chip->page_shift);
465
466	/* Check, if it is write protected */
467	if (nand_check_wp(chip)) {
468	nand_deselect_target(chip);
469	return -EROFS;
470	}
471
472	/* Invalidate the page cache, if we write to the cached page */
473	if (page == chip->pagecache.page)
474	chip->pagecache.page = -1;
475
476	nand_fill_oob(chip, oob: ops->oobbuf, len: ops->ooblen, ops);
477
478	if (ops->mode == MTD_OPS_RAW)
479	status = chip->ecc.write_oob_raw(chip, page & chip->pagemask);
480	else
481	status = chip->ecc.write_oob(chip, page & chip->pagemask);
482
483	nand_deselect_target(chip);
484
485	if (status)
486	return status;
487
488	ops->oobretlen = ops->ooblen;
489
490	return 0;
491	}
492
493	/**
494	* nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
495	* @chip: NAND chip object
496	* @ofs: offset from device start
497	*
498	* This is the default implementation, which can be overridden by a hardware
499	* specific driver. It provides the details for writing a bad block marker to a
500	* block.
501	*/
502	static int nand_default_block_markbad(struct nand_chip *chip, loff_t ofs)
503	{
504	struct mtd_info *mtd = nand_to_mtd(chip);
505	struct mtd_oob_ops ops;
506	uint8_t buf[2] = { 0, 0 };
507	int ret = 0, res, page_offset;
508
509	memset(&ops, 0, sizeof(ops));
510	ops.oobbuf = buf;
511	ops.ooboffs = chip->badblockpos;
512	if (chip->options & NAND_BUSWIDTH_16) {
513	ops.ooboffs &= ~0x01;
514	ops.len = ops.ooblen = 2;
515	} else {
516	ops.len = ops.ooblen = 1;
517	}
518	ops.mode = MTD_OPS_PLACE_OOB;
519
520	page_offset = nand_bbm_get_next_page(chip, page: 0);
521
522	while (page_offset >= 0) {
523	res = nand_do_write_oob(chip,
524	to: ofs + (page_offset * mtd->writesize),
525	ops: &ops);
526
527	if (!ret)
528	ret = res;
529
530	page_offset = nand_bbm_get_next_page(chip, page: page_offset + 1);
531	}
532
533	return ret;
534	}
535
536	/**
537	* nand_markbad_bbm - mark a block by updating the BBM
538	* @chip: NAND chip object
539	* @ofs: offset of the block to mark bad
540	*/
541	int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs)
542	{
543	if (chip->legacy.block_markbad)
544	return chip->legacy.block_markbad(chip, ofs);
545
546	return nand_default_block_markbad(chip, ofs);
547	}
548
549	/**
550	* nand_block_markbad_lowlevel - mark a block bad
551	* @chip: NAND chip object
552	* @ofs: offset from device start
553	*
554	* This function performs the generic NAND bad block marking steps (i.e., bad
555	* block table(s) and/or marker(s)). We only allow the hardware driver to
556	* specify how to write bad block markers to OOB (chip->legacy.block_markbad).
557	*
558	* We try operations in the following order:
559	*
560	* (1) erase the affected block, to allow OOB marker to be written cleanly
561	* (2) write bad block marker to OOB area of affected block (unless flag
562	* NAND_BBT_NO_OOB_BBM is present)
563	* (3) update the BBT
564	*
565	* Note that we retain the first error encountered in (2) or (3), finish the
566	* procedures, and dump the error in the end.
567	*/
568	static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs)
569	{
570	struct mtd_info *mtd = nand_to_mtd(chip);
571	int res, ret = 0;
572
573	if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
574	struct erase_info einfo;
575
576	/* Attempt erase before marking OOB */
577	memset(&einfo, 0, sizeof(einfo));
578	einfo.addr = ofs;
579	einfo.len = 1ULL << chip->phys_erase_shift;
580	nand_erase_nand(chip, instr: &einfo, allowbbt: 0);
581
582	/* Write bad block marker to OOB */
583	nand_get_device(chip);
584
585	ret = nand_markbad_bbm(chip, ofs);
586	nand_release_device(chip);
587	}
588
589	/* Mark block bad in BBT */
590	if (chip->bbt) {
591	res = nand_markbad_bbt(chip, offs: ofs);
592	if (!ret)
593	ret = res;
594	}
595
596	if (!ret)
597	mtd->ecc_stats.badblocks++;
598
599	return ret;
600	}
601
602	/**
603	* nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
604	* @mtd: MTD device structure
605	* @ofs: offset from device start
606	*
607	* Check if the block is marked as reserved.
608	*/
609	static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
610	{
611	struct nand_chip *chip = mtd_to_nand(mtd);
612
613	if (!chip->bbt)
614	return 0;
615	/* Return info from the table */
616	return nand_isreserved_bbt(chip, offs: ofs);
617	}
618
619	/**
620	* nand_block_checkbad - [GENERIC] Check if a block is marked bad
621	* @chip: NAND chip object
622	* @ofs: offset from device start
623	* @allowbbt: 1, if its allowed to access the bbt area
624	*
625	* Check, if the block is bad. Either by reading the bad block table or
626	* calling of the scan function.
627	*/
628	static int nand_block_checkbad(struct nand_chip *chip, loff_t ofs, int allowbbt)
629	{
630	/* Return info from the table */
631	if (chip->bbt)
632	return nand_isbad_bbt(chip, offs: ofs, allowbbt);
633
634	return nand_isbad_bbm(chip, ofs);
635	}
636
637	/**
638	* nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1
639	* @chip: NAND chip structure
640	* @timeout_ms: Timeout in ms
641	*
642	* Poll the STATUS register using ->exec_op() until the RDY bit becomes 1.
643	* If that does not happen whitin the specified timeout, -ETIMEDOUT is
644	* returned.
645	*
646	* This helper is intended to be used when the controller does not have access
647	* to the NAND R/B pin.
648	*
649	* Be aware that calling this helper from an ->exec_op() implementation means
650	* ->exec_op() must be re-entrant.
651	*
652	* Return 0 if the NAND chip is ready, a negative error otherwise.
653	*/
654	int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
655	{
656	const struct nand_interface_config *conf;
657	u8 status = 0;
658	int ret;
659
660	if (!nand_has_exec_op(chip))
661	return -ENOTSUPP;
662
663	/* Wait tWB before polling the STATUS reg. */
664	conf = nand_get_interface_config(chip);
665	ndelay(NAND_COMMON_TIMING_NS(conf, tWB_max));
666
667	ret = nand_status_op(chip, NULL);
668	if (ret)
669	return ret;
670
671	/*
672	* +1 below is necessary because if we are now in the last fraction
673	* of jiffy and msecs_to_jiffies is 1 then we will wait only that
674	* small jiffy fraction - possibly leading to false timeout
675	*/
676	timeout_ms = jiffies + msecs_to_jiffies(m: timeout_ms) + 1;
677	do {
678	ret = nand_read_data_op(chip, buf: &status, len: sizeof(status), force_8bit: true,
679	check_only: false);
680	if (ret)
681	break;
682
683	if (status & NAND_STATUS_READY)
684	break;
685
686	/*
687	* Typical lowest execution time for a tR on most NANDs is 10us,
688	* use this as polling delay before doing something smarter (ie.
689	* deriving a delay from the timeout value, timeout_ms/ratio).
690	*/
691	udelay(usec: 10);
692	} while (time_before(jiffies, timeout_ms));
693
694	/*
695	* We have to exit READ_STATUS mode in order to read real data on the
696	* bus in case the WAITRDY instruction is preceding a DATA_IN
697	* instruction.
698	*/
699	nand_exit_status_op(chip);
700
701	if (ret)
702	return ret;
703
704	return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT;
705	};
706	EXPORT_SYMBOL_GPL(nand_soft_waitrdy);
707
708	/**
709	* nand_gpio_waitrdy - Poll R/B GPIO pin until ready
710	* @chip: NAND chip structure
711	* @gpiod: GPIO descriptor of R/B pin
712	* @timeout_ms: Timeout in ms
713	*
714	* Poll the R/B GPIO pin until it becomes ready. If that does not happen
715	* whitin the specified timeout, -ETIMEDOUT is returned.
716	*
717	* This helper is intended to be used when the controller has access to the
718	* NAND R/B pin over GPIO.
719	*
720	* Return 0 if the R/B pin indicates chip is ready, a negative error otherwise.
721	*/
722	int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
723	unsigned long timeout_ms)
724	{
725
726	/*
727	* Wait until R/B pin indicates chip is ready or timeout occurs.
728	* +1 below is necessary because if we are now in the last fraction
729	* of jiffy and msecs_to_jiffies is 1 then we will wait only that
730	* small jiffy fraction - possibly leading to false timeout.
731	*/
732	timeout_ms = jiffies + msecs_to_jiffies(m: timeout_ms) + 1;
733	do {
734	if (gpiod_get_value_cansleep(desc: gpiod))
735	return 0;
736
737	cond_resched();
738	} while (time_before(jiffies, timeout_ms));
739
740	return gpiod_get_value_cansleep(desc: gpiod) ? 0 : -ETIMEDOUT;
741	};
742	EXPORT_SYMBOL_GPL(nand_gpio_waitrdy);
743
744	/**
745	* panic_nand_wait - [GENERIC] wait until the command is done
746	* @chip: NAND chip structure
747	* @timeo: timeout
748	*
749	* Wait for command done. This is a helper function for nand_wait used when
750	* we are in interrupt context. May happen when in panic and trying to write
751	* an oops through mtdoops.
752	*/
753	void panic_nand_wait(struct nand_chip *chip, unsigned long timeo)
754	{
755	int i;
756	for (i = 0; i < timeo; i++) {
757	if (chip->legacy.dev_ready) {
758	if (chip->legacy.dev_ready(chip))
759	break;
760	} else {
761	int ret;
762	u8 status;
763
764	ret = nand_read_data_op(chip, buf: &status, len: sizeof(status),
765	force_8bit: true, check_only: false);
766	if (ret)
767	return;
768
769	if (status & NAND_STATUS_READY)
770	break;
771	}
772	mdelay(1);
773	}
774	}
775
776	static bool nand_supports_get_features(struct nand_chip *chip, int addr)
777	{
778	return (chip->parameters.supports_set_get_features &&
779	test_bit(addr, chip->parameters.get_feature_list));
780	}
781
782	static bool nand_supports_set_features(struct nand_chip *chip, int addr)
783	{
784	return (chip->parameters.supports_set_get_features &&
785	test_bit(addr, chip->parameters.set_feature_list));
786	}
787
788	/**
789	* nand_reset_interface - Reset data interface and timings
790	* @chip: The NAND chip
791	* @chipnr: Internal die id
792	*
793	* Reset the Data interface and timings to ONFI mode 0.
794	*
795	* Returns 0 for success or negative error code otherwise.
796	*/
797	static int nand_reset_interface(struct nand_chip *chip, int chipnr)
798	{
799	const struct nand_controller_ops *ops = chip->controller->ops;
800	int ret;
801
802	if (!nand_controller_can_setup_interface(chip))
803	return 0;
804
805	/*
806	* The ONFI specification says:
807	* "
808	* To transition from NV-DDR or NV-DDR2 to the SDR data
809	* interface, the host shall use the Reset (FFh) command
810	* using SDR timing mode 0. A device in any timing mode is
811	* required to recognize Reset (FFh) command issued in SDR
812	* timing mode 0.
813	* "
814	*
815	* Configure the data interface in SDR mode and set the
816	* timings to timing mode 0.
817	*/
818
819	chip->current_interface_config = nand_get_reset_interface_config();
820	ret = ops->setup_interface(chip, chipnr,
821	chip->current_interface_config);
822	if (ret)
823	pr_err("Failed to configure data interface to SDR timing mode 0\n");
824
825	return ret;
826	}
827
828	/**
829	* nand_setup_interface - Setup the best data interface and timings
830	* @chip: The NAND chip
831	* @chipnr: Internal die id
832	*
833	* Configure what has been reported to be the best data interface and NAND
834	* timings supported by the chip and the driver.
835	*
836	* Returns 0 for success or negative error code otherwise.
837	*/
838	static int nand_setup_interface(struct nand_chip *chip, int chipnr)
839	{
840	const struct nand_controller_ops *ops = chip->controller->ops;
841	u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { }, request;
842	int ret;
843
844	if (!nand_controller_can_setup_interface(chip))
845	return 0;
846
847	/*
848	* A nand_reset_interface() put both the NAND chip and the NAND
849	* controller in timings mode 0. If the default mode for this chip is
850	* also 0, no need to proceed to the change again. Plus, at probe time,
851	* nand_setup_interface() uses ->set/get_features() which would
852	* fail anyway as the parameter page is not available yet.
853	*/
854	if (!chip->best_interface_config)
855	return 0;
856
857	request = chip->best_interface_config->timings.mode;
858	if (nand_interface_is_sdr(conf: chip->best_interface_config))
859	request |= ONFI_DATA_INTERFACE_SDR;
860	else
861	request |= ONFI_DATA_INTERFACE_NVDDR;
862	tmode_param[0] = request;
863
864	/* Change the mode on the chip side (if supported by the NAND chip) */
865	if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) {
866	nand_select_target(chip, chipnr);
867	ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
868	subfeature_param: tmode_param);
869	nand_deselect_target(chip);
870	if (ret)
871	return ret;
872	}
873
874	/* Change the mode on the controller side */
875	ret = ops->setup_interface(chip, chipnr, chip->best_interface_config);
876	if (ret)
877	return ret;
878
879	/* Check the mode has been accepted by the chip, if supported */
880	if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE))
881	goto update_interface_config;
882
883	memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
884	nand_select_target(chip, chipnr);
885	ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
886	subfeature_param: tmode_param);
887	nand_deselect_target(chip);
888	if (ret)
889	goto err_reset_chip;
890
891	if (request != tmode_param[0]) {
892	pr_warn("%s timing mode %d not acknowledged by the NAND chip\n",
893	nand_interface_is_nvddr(chip->best_interface_config) ? "NV-DDR" : "SDR",
894	chip->best_interface_config->timings.mode);
895	pr_debug("NAND chip would work in %s timing mode %d\n",
896	tmode_param[0] & ONFI_DATA_INTERFACE_NVDDR ? "NV-DDR" : "SDR",
897	(unsigned int)ONFI_TIMING_MODE_PARAM(tmode_param[0]));
898	goto err_reset_chip;
899	}
900
901	update_interface_config:
902	chip->current_interface_config = chip->best_interface_config;
903
904	return 0;
905
906	err_reset_chip:
907	/*
908	* Fallback to mode 0 if the chip explicitly did not ack the chosen
909	* timing mode.
910	*/
911	nand_reset_interface(chip, chipnr);
912	nand_select_target(chip, chipnr);
913	nand_reset_op(chip);
914	nand_deselect_target(chip);
915
916	return ret;
917	}
918
919	/**
920	* nand_choose_best_sdr_timings - Pick up the best SDR timings that both the
921	* NAND controller and the NAND chip support
922	* @chip: the NAND chip
923	* @iface: the interface configuration (can eventually be updated)
924	* @spec_timings: specific timings, when not fitting the ONFI specification
925	*
926	* If specific timings are provided, use them. Otherwise, retrieve supported
927	* timing modes from ONFI information.
928	*/
929	int nand_choose_best_sdr_timings(struct nand_chip *chip,
930	struct nand_interface_config *iface,
931	struct nand_sdr_timings *spec_timings)
932	{
933	const struct nand_controller_ops *ops = chip->controller->ops;
934	int best_mode = 0, mode, ret = -EOPNOTSUPP;
935
936	iface->type = NAND_SDR_IFACE;
937
938	if (spec_timings) {
939	iface->timings.sdr = *spec_timings;
940	iface->timings.mode = onfi_find_closest_sdr_mode(spec_timings);
941
942	/* Verify the controller supports the requested interface */
943	ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
944	iface);
945	if (!ret) {
946	chip->best_interface_config = iface;
947	return ret;
948	}
949
950	/* Fallback to slower modes */
951	best_mode = iface->timings.mode;
952	} else if (chip->parameters.onfi) {
953	best_mode = fls(x: chip->parameters.onfi->sdr_timing_modes) - 1;
954	}
955
956	for (mode = best_mode; mode >= 0; mode--) {
957	onfi_fill_interface_config(chip, iface, type: NAND_SDR_IFACE, timing_mode: mode);
958
959	ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
960	iface);
961	if (!ret) {
962	chip->best_interface_config = iface;
963	break;
964	}
965	}
966
967	return ret;
968	}
969
970	/**
971	* nand_choose_best_nvddr_timings - Pick up the best NVDDR timings that both the
972	* NAND controller and the NAND chip support
973	* @chip: the NAND chip
974	* @iface: the interface configuration (can eventually be updated)
975	* @spec_timings: specific timings, when not fitting the ONFI specification
976	*
977	* If specific timings are provided, use them. Otherwise, retrieve supported
978	* timing modes from ONFI information.
979	*/
980	int nand_choose_best_nvddr_timings(struct nand_chip *chip,
981	struct nand_interface_config *iface,
982	struct nand_nvddr_timings *spec_timings)
983	{
984	const struct nand_controller_ops *ops = chip->controller->ops;
985	int best_mode = 0, mode, ret = -EOPNOTSUPP;
986
987	iface->type = NAND_NVDDR_IFACE;
988
989	if (spec_timings) {
990	iface->timings.nvddr = *spec_timings;
991	iface->timings.mode = onfi_find_closest_nvddr_mode(spec_timings);
992
993	/* Verify the controller supports the requested interface */
994	ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
995	iface);
996	if (!ret) {
997	chip->best_interface_config = iface;
998	return ret;
999	}
1000
1001	/* Fallback to slower modes */
1002	best_mode = iface->timings.mode;
1003	} else if (chip->parameters.onfi) {
1004	best_mode = fls(x: chip->parameters.onfi->nvddr_timing_modes) - 1;
1005	}
1006
1007	for (mode = best_mode; mode >= 0; mode--) {
1008	onfi_fill_interface_config(chip, iface, type: NAND_NVDDR_IFACE, timing_mode: mode);
1009
1010	ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
1011	iface);
1012	if (!ret) {
1013	chip->best_interface_config = iface;
1014	break;
1015	}
1016	}
1017
1018	return ret;
1019	}
1020
1021	/**
1022	* nand_choose_best_timings - Pick up the best NVDDR or SDR timings that both
1023	* NAND controller and the NAND chip support
1024	* @chip: the NAND chip
1025	* @iface: the interface configuration (can eventually be updated)
1026	*
1027	* If specific timings are provided, use them. Otherwise, retrieve supported
1028	* timing modes from ONFI information.
1029	*/
1030	static int nand_choose_best_timings(struct nand_chip *chip,
1031	struct nand_interface_config *iface)
1032	{
1033	int ret;
1034
1035	/* Try the fastest timings: NV-DDR */
1036	ret = nand_choose_best_nvddr_timings(chip, iface, NULL);
1037	if (!ret)
1038	return 0;
1039
1040	/* Fallback to SDR timings otherwise */
1041	return nand_choose_best_sdr_timings(chip, iface, NULL);
1042	}
1043
1044	/**
1045	* nand_choose_interface_config - find the best data interface and timings
1046	* @chip: The NAND chip
1047	*
1048	* Find the best data interface and NAND timings supported by the chip
1049	* and the driver. Eventually let the NAND manufacturer driver propose his own
1050	* set of timings.
1051	*
1052	* After this function nand_chip->interface_config is initialized with the best
1053	* timing mode available.
1054	*
1055	* Returns 0 for success or negative error code otherwise.
1056	*/
1057	static int nand_choose_interface_config(struct nand_chip *chip)
1058	{
1059	struct nand_interface_config *iface;
1060	int ret;
1061
1062	if (!nand_controller_can_setup_interface(chip))
1063	return 0;
1064
1065	iface = kzalloc(sizeof(*iface), GFP_KERNEL);
1066	if (!iface)
1067	return -ENOMEM;
1068
1069	if (chip->ops.choose_interface_config)
1070	ret = chip->ops.choose_interface_config(chip, iface);
1071	else
1072	ret = nand_choose_best_timings(chip, iface);
1073
1074	if (ret)
1075	kfree(objp: iface);
1076
1077	return ret;
1078	}
1079
1080	/**
1081	* nand_fill_column_cycles - fill the column cycles of an address
1082	* @chip: The NAND chip
1083	* @addrs: Array of address cycles to fill
1084	* @offset_in_page: The offset in the page
1085	*
1086	* Fills the first or the first two bytes of the @addrs field depending
1087	* on the NAND bus width and the page size.
1088	*
1089	* Returns the number of cycles needed to encode the column, or a negative
1090	* error code in case one of the arguments is invalid.
1091	*/
1092	static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs,
1093	unsigned int offset_in_page)
1094	{
1095	struct mtd_info *mtd = nand_to_mtd(chip);
1096	bool ident_stage = !mtd->writesize;
1097
1098	/* Bypass all checks during NAND identification */
1099	if (likely(!ident_stage)) {
1100	/* Make sure the offset is less than the actual page size. */
1101	if (offset_in_page > mtd->writesize + mtd->oobsize)
1102	return -EINVAL;
1103
1104	/*
1105	* On small page NANDs, there's a dedicated command to access the OOB
1106	* area, and the column address is relative to the start of the OOB
1107	* area, not the start of the page. Asjust the address accordingly.
1108	*/
1109	if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize)
1110	offset_in_page -= mtd->writesize;
1111
1112	/*
1113	* The offset in page is expressed in bytes, if the NAND bus is 16-bit
1114	* wide, then it must be divided by 2.
1115	*/
1116	if (chip->options & NAND_BUSWIDTH_16) {
1117	if (WARN_ON(offset_in_page % 2))
1118	return -EINVAL;
1119
1120	offset_in_page /= 2;
1121	}
1122	}
1123
1124	addrs[0] = offset_in_page;
1125
1126	/*
1127	* Small page NANDs use 1 cycle for the columns, while large page NANDs
1128	* need 2
1129	*/
1130	if (!ident_stage && mtd->writesize <= 512)
1131	return 1;
1132
1133	addrs[1] = offset_in_page >> 8;
1134
1135	return 2;
1136	}
1137
1138	static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
1139	unsigned int offset_in_page, void *buf,
1140	unsigned int len)
1141	{
1142	const struct nand_interface_config *conf =
1143	nand_get_interface_config(chip);
1144	struct mtd_info *mtd = nand_to_mtd(chip);
1145	u8 addrs[4];
1146	struct nand_op_instr instrs[] = {
1147	NAND_OP_CMD(NAND_CMD_READ0, 0),
1148	NAND_OP_ADDR(3, addrs, NAND_COMMON_TIMING_NS(conf, tWB_max)),
1149	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
1150	NAND_COMMON_TIMING_NS(conf, tRR_min)),
1151	NAND_OP_DATA_IN(len, buf, 0),
1152	};
1153	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1154	int ret;
1155
1156	/* Drop the DATA_IN instruction if len is set to 0. */
1157	if (!len)
1158	op.ninstrs--;
1159
1160	if (offset_in_page >= mtd->writesize)
1161	instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;
1162	else if (offset_in_page >= 256 &&
1163	!(chip->options & NAND_BUSWIDTH_16))
1164	instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;
1165
1166	ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1167	if (ret < 0)
1168	return ret;
1169
1170	addrs[1] = page;
1171	addrs[2] = page >> 8;
1172
1173	if (chip->options & NAND_ROW_ADDR_3) {
1174	addrs[3] = page >> 16;
1175	instrs[1].ctx.addr.naddrs++;
1176	}
1177
1178	return nand_exec_op(chip, op: &op);
1179	}
1180
1181	static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
1182	unsigned int offset_in_page, void *buf,
1183	unsigned int len)
1184	{
1185	const struct nand_interface_config *conf =
1186	nand_get_interface_config(chip);
1187	u8 addrs[5];
1188	struct nand_op_instr instrs[] = {
1189	NAND_OP_CMD(NAND_CMD_READ0, 0),
1190	NAND_OP_ADDR(4, addrs, 0),
1191	NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)),
1192	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
1193	NAND_COMMON_TIMING_NS(conf, tRR_min)),
1194	NAND_OP_DATA_IN(len, buf, 0),
1195	};
1196	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1197	int ret;
1198
1199	/* Drop the DATA_IN instruction if len is set to 0. */
1200	if (!len)
1201	op.ninstrs--;
1202
1203	ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1204	if (ret < 0)
1205	return ret;
1206
1207	addrs[2] = page;
1208	addrs[3] = page >> 8;
1209
1210	if (chip->options & NAND_ROW_ADDR_3) {
1211	addrs[4] = page >> 16;
1212	instrs[1].ctx.addr.naddrs++;
1213	}
1214
1215	return nand_exec_op(chip, op: &op);
1216	}
1217
1218	static unsigned int rawnand_last_page_of_lun(unsigned int pages_per_lun, unsigned int lun)
1219	{
1220	/* lun is expected to be very small */
1221	return (lun * pages_per_lun) + pages_per_lun - 1;
1222	}
1223
1224	static void rawnand_cap_cont_reads(struct nand_chip *chip)
1225	{
1226	struct nand_memory_organization *memorg;
1227	unsigned int ppl, first_lun, last_lun;
1228
1229	memorg = nanddev_get_memorg(nand: &chip->base);
1230	ppl = memorg->pages_per_eraseblock * memorg->eraseblocks_per_lun;
1231	first_lun = chip->cont_read.first_page / ppl;
1232	last_lun = chip->cont_read.last_page / ppl;
1233
1234	/* Prevent sequential cache reads across LUN boundaries */
1235	if (first_lun != last_lun)
1236	chip->cont_read.pause_page = rawnand_last_page_of_lun(pages_per_lun: ppl, lun: first_lun);
1237	else
1238	chip->cont_read.pause_page = chip->cont_read.last_page;
1239
1240	if (chip->cont_read.first_page == chip->cont_read.pause_page) {
1241	chip->cont_read.first_page++;
1242	chip->cont_read.pause_page = min(chip->cont_read.last_page,
1243	rawnand_last_page_of_lun(ppl, first_lun + 1));
1244	}
1245
1246	if (chip->cont_read.first_page >= chip->cont_read.last_page)
1247	chip->cont_read.ongoing = false;
1248	}
1249
1250	static int nand_lp_exec_cont_read_page_op(struct nand_chip *chip, unsigned int page,
1251	unsigned int offset_in_page, void *buf,
1252	unsigned int len, bool check_only)
1253	{
1254	const struct nand_interface_config *conf =
1255	nand_get_interface_config(chip);
1256	u8 addrs[5];
1257	struct nand_op_instr start_instrs[] = {
1258	NAND_OP_CMD(NAND_CMD_READ0, 0),
1259	NAND_OP_ADDR(4, addrs, 0),
1260	NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)),
1261	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 0),
1262	NAND_OP_CMD(NAND_CMD_READCACHESEQ, NAND_COMMON_TIMING_NS(conf, tWB_max)),
1263	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
1264	NAND_COMMON_TIMING_NS(conf, tRR_min)),
1265	NAND_OP_DATA_IN(len, buf, 0),
1266	};
1267	struct nand_op_instr cont_instrs[] = {
1268	NAND_OP_CMD(page == chip->cont_read.pause_page ?
1269	NAND_CMD_READCACHEEND : NAND_CMD_READCACHESEQ,
1270	NAND_COMMON_TIMING_NS(conf, tWB_max)),
1271	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
1272	NAND_COMMON_TIMING_NS(conf, tRR_min)),
1273	NAND_OP_DATA_IN(len, buf, 0),
1274	};
1275	struct nand_operation start_op = NAND_OPERATION(chip->cur_cs, start_instrs);
1276	struct nand_operation cont_op = NAND_OPERATION(chip->cur_cs, cont_instrs);
1277	int ret;
1278
1279	if (!len) {
1280	start_op.ninstrs--;
1281	cont_op.ninstrs--;
1282	}
1283
1284	ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1285	if (ret < 0)
1286	return ret;
1287
1288	addrs[2] = page;
1289	addrs[3] = page >> 8;
1290
1291	if (chip->options & NAND_ROW_ADDR_3) {
1292	addrs[4] = page >> 16;
1293	start_instrs[1].ctx.addr.naddrs++;
1294	}
1295
1296	/* Check if cache reads are supported */
1297	if (check_only) {
1298	if (nand_check_op(chip, op: &start_op) || nand_check_op(chip, op: &cont_op))
1299	return -EOPNOTSUPP;
1300
1301	return 0;
1302	}
1303
1304	if (page == chip->cont_read.first_page)
1305	ret = nand_exec_op(chip, op: &start_op);
1306	else
1307	ret = nand_exec_op(chip, op: &cont_op);
1308	if (ret)
1309	return ret;
1310
1311	if (!chip->cont_read.ongoing)
1312	return 0;
1313
1314	if (page == chip->cont_read.last_page) {
1315	chip->cont_read.ongoing = false;
1316	} else if (page == chip->cont_read.pause_page) {
1317	chip->cont_read.first_page++;
1318	rawnand_cap_cont_reads(chip);
1319	}
1320
1321	return 0;
1322	}
1323
1324	static bool rawnand_cont_read_ongoing(struct nand_chip *chip, unsigned int page)
1325	{
1326	return chip->cont_read.ongoing && page >= chip->cont_read.first_page;
1327	}
1328
1329	/**
1330	* nand_read_page_op - Do a READ PAGE operation
1331	* @chip: The NAND chip
1332	* @page: page to read
1333	* @offset_in_page: offset within the page
1334	* @buf: buffer used to store the data
1335	* @len: length of the buffer
1336	*
1337	* This function issues a READ PAGE operation.
1338	* This function does not select/unselect the CS line.
1339	*
1340	* Returns 0 on success, a negative error code otherwise.
1341	*/
1342	int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1343	unsigned int offset_in_page, void *buf, unsigned int len)
1344	{
1345	struct mtd_info *mtd = nand_to_mtd(chip);
1346
1347	if (len && !buf)
1348	return -EINVAL;
1349
1350	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1351	return -EINVAL;
1352
1353	if (nand_has_exec_op(chip)) {
1354	if (mtd->writesize > 512) {
1355	if (rawnand_cont_read_ongoing(chip, page))
1356	return nand_lp_exec_cont_read_page_op(chip, page,
1357	offset_in_page,
1358	buf, len, check_only: false);
1359	else
1360	return nand_lp_exec_read_page_op(chip, page,
1361	offset_in_page, buf,
1362	len);
1363	}
1364
1365	return nand_sp_exec_read_page_op(chip, page, offset_in_page,
1366	buf, len);
1367	}
1368
1369	chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page);
1370	if (len)
1371	chip->legacy.read_buf(chip, buf, len);
1372
1373	return 0;
1374	}
1375	EXPORT_SYMBOL_GPL(nand_read_page_op);
1376
1377	/**
1378	* nand_read_param_page_op - Do a READ PARAMETER PAGE operation
1379	* @chip: The NAND chip
1380	* @page: parameter page to read
1381	* @buf: buffer used to store the data
1382	* @len: length of the buffer
1383	*
1384	* This function issues a READ PARAMETER PAGE operation.
1385	* This function does not select/unselect the CS line.
1386	*
1387	* Returns 0 on success, a negative error code otherwise.
1388	*/
1389	int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
1390	unsigned int len)
1391	{
1392	unsigned int i;
1393	u8 *p = buf;
1394
1395	if (len && !buf)
1396	return -EINVAL;
1397
1398	if (nand_has_exec_op(chip)) {
1399	const struct nand_interface_config *conf =
1400	nand_get_interface_config(chip);
1401	struct nand_op_instr instrs[] = {
1402	NAND_OP_CMD(NAND_CMD_PARAM, 0),
1403	NAND_OP_ADDR(1, &page,
1404	NAND_COMMON_TIMING_NS(conf, tWB_max)),
1405	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
1406	NAND_COMMON_TIMING_NS(conf, tRR_min)),
1407	NAND_OP_8BIT_DATA_IN(len, buf, 0),
1408	};
1409	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1410
1411	/* Drop the DATA_IN instruction if len is set to 0. */
1412	if (!len)
1413	op.ninstrs--;
1414
1415	return nand_exec_op(chip, op: &op);
1416	}
1417
1418	chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1);
1419	for (i = 0; i < len; i++)
1420	p[i] = chip->legacy.read_byte(chip);
1421
1422	return 0;
1423	}
1424
1425	/**
1426	* nand_change_read_column_op - Do a CHANGE READ COLUMN operation
1427	* @chip: The NAND chip
1428	* @offset_in_page: offset within the page
1429	* @buf: buffer used to store the data
1430	* @len: length of the buffer
1431	* @force_8bit: force 8-bit bus access
1432	*
1433	* This function issues a CHANGE READ COLUMN operation.
1434	* This function does not select/unselect the CS line.
1435	*
1436	* Returns 0 on success, a negative error code otherwise.
1437	*/
1438	int nand_change_read_column_op(struct nand_chip *chip,
1439	unsigned int offset_in_page, void *buf,
1440	unsigned int len, bool force_8bit)
1441	{
1442	struct mtd_info *mtd = nand_to_mtd(chip);
1443	bool ident_stage = !mtd->writesize;
1444
1445	if (len && !buf)
1446	return -EINVAL;
1447
1448	if (!ident_stage) {
1449	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1450	return -EINVAL;
1451
1452	/* Small page NANDs do not support column change. */
1453	if (mtd->writesize <= 512)
1454	return -ENOTSUPP;
1455	}
1456
1457	if (nand_has_exec_op(chip)) {
1458	const struct nand_interface_config *conf =
1459	nand_get_interface_config(chip);
1460	u8 addrs[2] = {};
1461	struct nand_op_instr instrs[] = {
1462	NAND_OP_CMD(NAND_CMD_RNDOUT, 0),
1463	NAND_OP_ADDR(2, addrs, 0),
1464	NAND_OP_CMD(NAND_CMD_RNDOUTSTART,
1465	NAND_COMMON_TIMING_NS(conf, tCCS_min)),
1466	NAND_OP_DATA_IN(len, buf, 0),
1467	};
1468	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1469	int ret;
1470
1471	ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1472	if (ret < 0)
1473	return ret;
1474
1475	/* Drop the DATA_IN instruction if len is set to 0. */
1476	if (!len)
1477	op.ninstrs--;
1478
1479	instrs[3].ctx.data.force_8bit = force_8bit;
1480
1481	return nand_exec_op(chip, op: &op);
1482	}
1483
1484	chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1);
1485	if (len)
1486	chip->legacy.read_buf(chip, buf, len);
1487
1488	return 0;
1489	}
1490	EXPORT_SYMBOL_GPL(nand_change_read_column_op);
1491
1492	/**
1493	* nand_read_oob_op - Do a READ OOB operation
1494	* @chip: The NAND chip
1495	* @page: page to read
1496	* @offset_in_oob: offset within the OOB area
1497	* @buf: buffer used to store the data
1498	* @len: length of the buffer
1499	*
1500	* This function issues a READ OOB operation.
1501	* This function does not select/unselect the CS line.
1502	*
1503	* Returns 0 on success, a negative error code otherwise.
1504	*/
1505	int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1506	unsigned int offset_in_oob, void *buf, unsigned int len)
1507	{
1508	struct mtd_info *mtd = nand_to_mtd(chip);
1509
1510	if (len && !buf)
1511	return -EINVAL;
1512
1513	if (offset_in_oob + len > mtd->oobsize)
1514	return -EINVAL;
1515
1516	if (nand_has_exec_op(chip))
1517	return nand_read_page_op(chip, page,
1518	mtd->writesize + offset_in_oob,
1519	buf, len);
1520
1521	chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page);
1522	if (len)
1523	chip->legacy.read_buf(chip, buf, len);
1524
1525	return 0;
1526	}
1527	EXPORT_SYMBOL_GPL(nand_read_oob_op);
1528
1529	static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page,
1530	unsigned int offset_in_page, const void *buf,
1531	unsigned int len, bool prog)
1532	{
1533	const struct nand_interface_config *conf =
1534	nand_get_interface_config(chip);
1535	struct mtd_info *mtd = nand_to_mtd(chip);
1536	u8 addrs[5] = {};
1537	struct nand_op_instr instrs[] = {
1538	/*
1539	* The first instruction will be dropped if we're dealing
1540	* with a large page NAND and adjusted if we're dealing
1541	* with a small page NAND and the page offset is > 255.
1542	*/
1543	NAND_OP_CMD(NAND_CMD_READ0, 0),
1544	NAND_OP_CMD(NAND_CMD_SEQIN, 0),
1545	NAND_OP_ADDR(0, addrs, NAND_COMMON_TIMING_NS(conf, tADL_min)),
1546	NAND_OP_DATA_OUT(len, buf, 0),
1547	NAND_OP_CMD(NAND_CMD_PAGEPROG,
1548	NAND_COMMON_TIMING_NS(conf, tWB_max)),
1549	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max), 0),
1550	};
1551	struct nand_operation op = NAND_DESTRUCTIVE_OPERATION(chip->cur_cs,
1552	instrs);
1553	int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page);
1554
1555	if (naddrs < 0)
1556	return naddrs;
1557
1558	addrs[naddrs++] = page;
1559	addrs[naddrs++] = page >> 8;
1560	if (chip->options & NAND_ROW_ADDR_3)
1561	addrs[naddrs++] = page >> 16;
1562
1563	instrs[2].ctx.addr.naddrs = naddrs;
1564
1565	/* Drop the last two instructions if we're not programming the page. */
1566	if (!prog) {
1567	op.ninstrs -= 2;
1568	/* Also drop the DATA_OUT instruction if empty. */
1569	if (!len)
1570	op.ninstrs--;
1571	}
1572
1573	if (mtd->writesize <= 512) {
1574	/*
1575	* Small pages need some more tweaking: we have to adjust the
1576	* first instruction depending on the page offset we're trying
1577	* to access.
1578	*/
1579	if (offset_in_page >= mtd->writesize)
1580	instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;
1581	else if (offset_in_page >= 256 &&
1582	!(chip->options & NAND_BUSWIDTH_16))
1583	instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;
1584	} else {
1585	/*
1586	* Drop the first command if we're dealing with a large page
1587	* NAND.
1588	*/
1589	op.instrs++;
1590	op.ninstrs--;
1591	}
1592
1593	return nand_exec_op(chip, op: &op);
1594	}
1595
1596	/**
1597	* nand_prog_page_begin_op - starts a PROG PAGE operation
1598	* @chip: The NAND chip
1599	* @page: page to write
1600	* @offset_in_page: offset within the page
1601	* @buf: buffer containing the data to write to the page
1602	* @len: length of the buffer
1603	*
1604	* This function issues the first half of a PROG PAGE operation.
1605	* This function does not select/unselect the CS line.
1606	*
1607	* Returns 0 on success, a negative error code otherwise.
1608	*/
1609	int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1610	unsigned int offset_in_page, const void *buf,
1611	unsigned int len)
1612	{
1613	struct mtd_info *mtd = nand_to_mtd(chip);
1614
1615	if (len && !buf)
1616	return -EINVAL;
1617
1618	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1619	return -EINVAL;
1620
1621	if (nand_has_exec_op(chip))
1622	return nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1623	len, prog: false);
1624
1625	chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page);
1626
1627	if (buf)
1628	chip->legacy.write_buf(chip, buf, len);
1629
1630	return 0;
1631	}
1632	EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
1633
1634	/**
1635	* nand_prog_page_end_op - ends a PROG PAGE operation
1636	* @chip: The NAND chip
1637	*
1638	* This function issues the second half of a PROG PAGE operation.
1639	* This function does not select/unselect the CS line.
1640	*
1641	* Returns 0 on success, a negative error code otherwise.
1642	*/
1643	int nand_prog_page_end_op(struct nand_chip *chip)
1644	{
1645	int ret;
1646	u8 status;
1647
1648	if (nand_has_exec_op(chip)) {
1649	const struct nand_interface_config *conf =
1650	nand_get_interface_config(chip);
1651	struct nand_op_instr instrs[] = {
1652	NAND_OP_CMD(NAND_CMD_PAGEPROG,
1653	NAND_COMMON_TIMING_NS(conf, tWB_max)),
1654	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max),
1655	0),
1656	};
1657	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1658
1659	ret = nand_exec_op(chip, op: &op);
1660	if (ret)
1661	return ret;
1662
1663	ret = nand_status_op(chip, status: &status);
1664	if (ret)
1665	return ret;
1666	} else {
1667	chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1668	ret = chip->legacy.waitfunc(chip);
1669	if (ret < 0)
1670	return ret;
1671
1672	status = ret;
1673	}
1674
1675	if (status & NAND_STATUS_FAIL)
1676	return -EIO;
1677
1678	return 0;
1679	}
1680	EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
1681
1682	/**
1683	* nand_prog_page_op - Do a full PROG PAGE operation
1684	* @chip: The NAND chip
1685	* @page: page to write
1686	* @offset_in_page: offset within the page
1687	* @buf: buffer containing the data to write to the page
1688	* @len: length of the buffer
1689	*
1690	* This function issues a full PROG PAGE operation.
1691	* This function does not select/unselect the CS line.
1692	*
1693	* Returns 0 on success, a negative error code otherwise.
1694	*/
1695	int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1696	unsigned int offset_in_page, const void *buf,
1697	unsigned int len)
1698	{
1699	struct mtd_info *mtd = nand_to_mtd(chip);
1700	u8 status;
1701	int ret;
1702
1703	if (!len || !buf)
1704	return -EINVAL;
1705
1706	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1707	return -EINVAL;
1708
1709	if (nand_has_exec_op(chip)) {
1710	ret = nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1711	len, prog: true);
1712	if (ret)
1713	return ret;
1714
1715	ret = nand_status_op(chip, status: &status);
1716	if (ret)
1717	return ret;
1718	} else {
1719	chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page,
1720	page);
1721	chip->legacy.write_buf(chip, buf, len);
1722	chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1723	ret = chip->legacy.waitfunc(chip);
1724	if (ret < 0)
1725	return ret;
1726
1727	status = ret;
1728	}
1729
1730	if (status & NAND_STATUS_FAIL)
1731	return -EIO;
1732
1733	return 0;
1734	}
1735	EXPORT_SYMBOL_GPL(nand_prog_page_op);
1736
1737	/**
1738	* nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
1739	* @chip: The NAND chip
1740	* @offset_in_page: offset within the page
1741	* @buf: buffer containing the data to send to the NAND
1742	* @len: length of the buffer
1743	* @force_8bit: force 8-bit bus access
1744	*
1745	* This function issues a CHANGE WRITE COLUMN operation.
1746	* This function does not select/unselect the CS line.
1747	*
1748	* Returns 0 on success, a negative error code otherwise.
1749	*/
1750	int nand_change_write_column_op(struct nand_chip *chip,
1751	unsigned int offset_in_page,
1752	const void *buf, unsigned int len,
1753	bool force_8bit)
1754	{
1755	struct mtd_info *mtd = nand_to_mtd(chip);
1756
1757	if (len && !buf)
1758	return -EINVAL;
1759
1760	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1761	return -EINVAL;
1762
1763	/* Small page NANDs do not support column change. */
1764	if (mtd->writesize <= 512)
1765	return -ENOTSUPP;
1766
1767	if (nand_has_exec_op(chip)) {
1768	const struct nand_interface_config *conf =
1769	nand_get_interface_config(chip);
1770	u8 addrs[2];
1771	struct nand_op_instr instrs[] = {
1772	NAND_OP_CMD(NAND_CMD_RNDIN, 0),
1773	NAND_OP_ADDR(2, addrs, NAND_COMMON_TIMING_NS(conf, tCCS_min)),
1774	NAND_OP_DATA_OUT(len, buf, 0),
1775	};
1776	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1777	int ret;
1778
1779	ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1780	if (ret < 0)
1781	return ret;
1782
1783	instrs[2].ctx.data.force_8bit = force_8bit;
1784
1785	/* Drop the DATA_OUT instruction if len is set to 0. */
1786	if (!len)
1787	op.ninstrs--;
1788
1789	return nand_exec_op(chip, op: &op);
1790	}
1791
1792	chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1);
1793	if (len)
1794	chip->legacy.write_buf(chip, buf, len);
1795
1796	return 0;
1797	}
1798	EXPORT_SYMBOL_GPL(nand_change_write_column_op);
1799
1800	/**
1801	* nand_readid_op - Do a READID operation
1802	* @chip: The NAND chip
1803	* @addr: address cycle to pass after the READID command
1804	* @buf: buffer used to store the ID
1805	* @len: length of the buffer
1806	*
1807	* This function sends a READID command and reads back the ID returned by the
1808	* NAND.
1809	* This function does not select/unselect the CS line.
1810	*
1811	* Returns 0 on success, a negative error code otherwise.
1812	*/
1813	int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1814	unsigned int len)
1815	{
1816	unsigned int i;
1817	u8 *id = buf, *ddrbuf = NULL;
1818
1819	if (len && !buf)
1820	return -EINVAL;
1821
1822	if (nand_has_exec_op(chip)) {
1823	const struct nand_interface_config *conf =
1824	nand_get_interface_config(chip);
1825	struct nand_op_instr instrs[] = {
1826	NAND_OP_CMD(NAND_CMD_READID, 0),
1827	NAND_OP_ADDR(1, &addr,
1828	NAND_COMMON_TIMING_NS(conf, tADL_min)),
1829	NAND_OP_8BIT_DATA_IN(len, buf, 0),
1830	};
1831	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1832	int ret;
1833
1834	/* READ_ID data bytes are received twice in NV-DDR mode */
1835	if (len && nand_interface_is_nvddr(conf)) {
1836	ddrbuf = kcalloc(2, len, GFP_KERNEL);
1837	if (!ddrbuf)
1838	return -ENOMEM;
1839
1840	instrs[2].ctx.data.len *= 2;
1841	instrs[2].ctx.data.buf.in = ddrbuf;
1842	}
1843
1844	/* Drop the DATA_IN instruction if len is set to 0. */
1845	if (!len)
1846	op.ninstrs--;
1847
1848	ret = nand_exec_op(chip, op: &op);
1849	if (!ret && len && nand_interface_is_nvddr(conf)) {
1850	for (i = 0; i < len; i++)
1851	id[i] = ddrbuf[i * 2];
1852	}
1853
1854	kfree(objp: ddrbuf);
1855
1856	return ret;
1857	}
1858
1859	chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1);
1860
1861	for (i = 0; i < len; i++)
1862	id[i] = chip->legacy.read_byte(chip);
1863
1864	return 0;
1865	}
1866	EXPORT_SYMBOL_GPL(nand_readid_op);
1867
1868	/**
1869	* nand_status_op - Do a STATUS operation
1870	* @chip: The NAND chip
1871	* @status: out variable to store the NAND status
1872	*
1873	* This function sends a STATUS command and reads back the status returned by
1874	* the NAND.
1875	* This function does not select/unselect the CS line.
1876	*
1877	* Returns 0 on success, a negative error code otherwise.
1878	*/
1879	int nand_status_op(struct nand_chip *chip, u8 *status)
1880	{
1881	if (nand_has_exec_op(chip)) {
1882	const struct nand_interface_config *conf =
1883	nand_get_interface_config(chip);
1884	u8 ddrstatus[2];
1885	struct nand_op_instr instrs[] = {
1886	NAND_OP_CMD(NAND_CMD_STATUS,
1887	NAND_COMMON_TIMING_NS(conf, tADL_min)),
1888	NAND_OP_8BIT_DATA_IN(1, status, 0),
1889	};
1890	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1891	int ret;
1892
1893	/* The status data byte will be received twice in NV-DDR mode */
1894	if (status && nand_interface_is_nvddr(conf)) {
1895	instrs[1].ctx.data.len *= 2;
1896	instrs[1].ctx.data.buf.in = ddrstatus;
1897	}
1898
1899	if (!status)
1900	op.ninstrs--;
1901
1902	ret = nand_exec_op(chip, op: &op);
1903	if (!ret && status && nand_interface_is_nvddr(conf))
1904	*status = ddrstatus[0];
1905
1906	return ret;
1907	}
1908
1909	chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1);
1910	if (status)
1911	*status = chip->legacy.read_byte(chip);
1912
1913	return 0;
1914	}
1915	EXPORT_SYMBOL_GPL(nand_status_op);
1916
1917	/**
1918	* nand_exit_status_op - Exit a STATUS operation
1919	* @chip: The NAND chip
1920	*
1921	* This function sends a READ0 command to cancel the effect of the STATUS
1922	* command to avoid reading only the status until a new read command is sent.
1923	*
1924	* This function does not select/unselect the CS line.
1925	*
1926	* Returns 0 on success, a negative error code otherwise.
1927	*/
1928	int nand_exit_status_op(struct nand_chip *chip)
1929	{
1930	if (nand_has_exec_op(chip)) {
1931	struct nand_op_instr instrs[] = {
1932	NAND_OP_CMD(NAND_CMD_READ0, 0),
1933	};
1934	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1935
1936	return nand_exec_op(chip, op: &op);
1937	}
1938
1939	chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1);
1940
1941	return 0;
1942	}
1943	EXPORT_SYMBOL_GPL(nand_exit_status_op);
1944
1945	/**
1946	* nand_erase_op - Do an erase operation
1947	* @chip: The NAND chip
1948	* @eraseblock: block to erase
1949	*
1950	* This function sends an ERASE command and waits for the NAND to be ready
1951	* before returning.
1952	* This function does not select/unselect the CS line.
1953	*
1954	* Returns 0 on success, a negative error code otherwise.
1955	*/
1956	int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
1957	{
1958	unsigned int page = eraseblock <<
1959	(chip->phys_erase_shift - chip->page_shift);
1960	int ret;
1961	u8 status;
1962
1963	if (nand_has_exec_op(chip)) {
1964	const struct nand_interface_config *conf =
1965	nand_get_interface_config(chip);
1966	u8 addrs[3] = { page, page >> 8, page >> 16 };
1967	struct nand_op_instr instrs[] = {
1968	NAND_OP_CMD(NAND_CMD_ERASE1, 0),
1969	NAND_OP_ADDR(2, addrs, 0),
1970	NAND_OP_CMD(NAND_CMD_ERASE2,
1971	NAND_COMMON_TIMING_NS(conf, tWB_max)),
1972	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tBERS_max),
1973	0),
1974	};
1975	struct nand_operation op = NAND_DESTRUCTIVE_OPERATION(chip->cur_cs,
1976	instrs);
1977
1978	if (chip->options & NAND_ROW_ADDR_3)
1979	instrs[1].ctx.addr.naddrs++;
1980
1981	ret = nand_exec_op(chip, op: &op);
1982	if (ret)
1983	return ret;
1984
1985	ret = nand_status_op(chip, &status);
1986	if (ret)
1987	return ret;
1988	} else {
1989	chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page);
1990	chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1);
1991
1992	ret = chip->legacy.waitfunc(chip);
1993	if (ret < 0)
1994	return ret;
1995
1996	status = ret;
1997	}
1998
1999	if (status & NAND_STATUS_FAIL)
2000	return -EIO;
2001
2002	return 0;
2003	}
2004	EXPORT_SYMBOL_GPL(nand_erase_op);
2005
2006	/**
2007	* nand_set_features_op - Do a SET FEATURES operation
2008	* @chip: The NAND chip
2009	* @feature: feature id
2010	* @data: 4 bytes of data
2011	*
2012	* This function sends a SET FEATURES command and waits for the NAND to be
2013	* ready before returning.
2014	* This function does not select/unselect the CS line.
2015	*
2016	* Returns 0 on success, a negative error code otherwise.
2017	*/
2018	static int nand_set_features_op(struct nand_chip *chip, u8 feature,
2019	const void *data)
2020	{
2021	const u8 *params = data;
2022	int i, ret;
2023
2024	if (nand_has_exec_op(chip)) {
2025	const struct nand_interface_config *conf =
2026	nand_get_interface_config(chip);
2027	struct nand_op_instr instrs[] = {
2028	NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0),
2029	NAND_OP_ADDR(1, &feature, NAND_COMMON_TIMING_NS(conf,
2030	tADL_min)),
2031	NAND_OP_8BIT_DATA_OUT(ONFI_SUBFEATURE_PARAM_LEN, data,
2032	NAND_COMMON_TIMING_NS(conf,
2033	tWB_max)),
2034	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tFEAT_max),
2035	0),
2036	};
2037	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2038
2039	return nand_exec_op(chip, op: &op);
2040	}
2041
2042	chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1);
2043	for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2044	chip->legacy.write_byte(chip, params[i]);
2045
2046	ret = chip->legacy.waitfunc(chip);
2047	if (ret < 0)
2048	return ret;
2049
2050	if (ret & NAND_STATUS_FAIL)
2051	return -EIO;
2052
2053	return 0;
2054	}
2055
2056	/**
2057	* nand_get_features_op - Do a GET FEATURES operation
2058	* @chip: The NAND chip
2059	* @feature: feature id
2060	* @data: 4 bytes of data
2061	*
2062	* This function sends a GET FEATURES command and waits for the NAND to be
2063	* ready before returning.
2064	* This function does not select/unselect the CS line.
2065	*
2066	* Returns 0 on success, a negative error code otherwise.
2067	*/
2068	static int nand_get_features_op(struct nand_chip *chip, u8 feature,
2069	void *data)
2070	{
2071	u8 *params = data, ddrbuf[ONFI_SUBFEATURE_PARAM_LEN * 2];
2072	int i;
2073
2074	if (nand_has_exec_op(chip)) {
2075	const struct nand_interface_config *conf =
2076	nand_get_interface_config(chip);
2077	struct nand_op_instr instrs[] = {
2078	NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0),
2079	NAND_OP_ADDR(1, &feature,
2080	NAND_COMMON_TIMING_NS(conf, tWB_max)),
2081	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tFEAT_max),
2082	NAND_COMMON_TIMING_NS(conf, tRR_min)),
2083	NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN,
2084	data, 0),
2085	};
2086	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2087	int ret;
2088
2089	/* GET_FEATURE data bytes are received twice in NV-DDR mode */
2090	if (nand_interface_is_nvddr(conf)) {
2091	instrs[3].ctx.data.len *= 2;
2092	instrs[3].ctx.data.buf.in = ddrbuf;
2093	}
2094
2095	ret = nand_exec_op(chip, op: &op);
2096	if (nand_interface_is_nvddr(conf)) {
2097	for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; i++)
2098	params[i] = ddrbuf[i * 2];
2099	}
2100
2101	return ret;
2102	}
2103
2104	chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1);
2105	for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2106	params[i] = chip->legacy.read_byte(chip);
2107
2108	return 0;
2109	}
2110
2111	static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms,
2112	unsigned int delay_ns)
2113	{
2114	if (nand_has_exec_op(chip)) {
2115	struct nand_op_instr instrs[] = {
2116	NAND_OP_WAIT_RDY(PSEC_TO_MSEC(timeout_ms),
2117	PSEC_TO_NSEC(delay_ns)),
2118	};
2119	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2120
2121	return nand_exec_op(chip, op: &op);
2122	}
2123
2124	/* Apply delay or wait for ready/busy pin */
2125	if (!chip->legacy.dev_ready)
2126	udelay(usec: chip->legacy.chip_delay);
2127	else
2128	nand_wait_ready(chip);
2129
2130	return 0;
2131	}
2132
2133	/**
2134	* nand_reset_op - Do a reset operation
2135	* @chip: The NAND chip
2136	*
2137	* This function sends a RESET command and waits for the NAND to be ready
2138	* before returning.
2139	* This function does not select/unselect the CS line.
2140	*
2141	* Returns 0 on success, a negative error code otherwise.
2142	*/
2143	int nand_reset_op(struct nand_chip *chip)
2144	{
2145	if (nand_has_exec_op(chip)) {
2146	const struct nand_interface_config *conf =
2147	nand_get_interface_config(chip);
2148	struct nand_op_instr instrs[] = {
2149	NAND_OP_CMD(NAND_CMD_RESET,
2150	NAND_COMMON_TIMING_NS(conf, tWB_max)),
2151	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tRST_max),
2152	0),
2153	};
2154	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2155
2156	return nand_exec_op(chip, op: &op);
2157	}
2158
2159	chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1);
2160
2161	return 0;
2162	}
2163	EXPORT_SYMBOL_GPL(nand_reset_op);
2164
2165	/**
2166	* nand_read_data_op - Read data from the NAND
2167	* @chip: The NAND chip
2168	* @buf: buffer used to store the data
2169	* @len: length of the buffer
2170	* @force_8bit: force 8-bit bus access
2171	* @check_only: do not actually run the command, only checks if the
2172	* controller driver supports it
2173	*
2174	* This function does a raw data read on the bus. Usually used after launching
2175	* another NAND operation like nand_read_page_op().
2176	* This function does not select/unselect the CS line.
2177	*
2178	* Returns 0 on success, a negative error code otherwise.
2179	*/
2180	int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
2181	bool force_8bit, bool check_only)
2182	{
2183	if (!len || (!check_only && !buf))
2184	return -EINVAL;
2185
2186	if (nand_has_exec_op(chip)) {
2187	const struct nand_interface_config *conf =
2188	nand_get_interface_config(chip);
2189	struct nand_op_instr instrs[] = {
2190	NAND_OP_DATA_IN(len, buf, 0),
2191	};
2192	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2193	u8 *ddrbuf = NULL;
2194	int ret, i;
2195
2196	instrs[0].ctx.data.force_8bit = force_8bit;
2197
2198	/*
2199	* Parameter payloads (ID, status, features, etc) do not go
2200	* through the same pipeline as regular data, hence the
2201	* force_8bit flag must be set and this also indicates that in
2202	* case NV-DDR timings are being used the data will be received
2203	* twice.
2204	*/
2205	if (force_8bit && nand_interface_is_nvddr(conf)) {
2206	ddrbuf = kcalloc(2, len, GFP_KERNEL);
2207	if (!ddrbuf)
2208	return -ENOMEM;
2209
2210	instrs[0].ctx.data.len *= 2;
2211	instrs[0].ctx.data.buf.in = ddrbuf;
2212	}
2213
2214	if (check_only) {
2215	ret = nand_check_op(chip, op: &op);
2216	kfree(objp: ddrbuf);
2217	return ret;
2218	}
2219
2220	ret = nand_exec_op(chip, op: &op);
2221	if (!ret && force_8bit && nand_interface_is_nvddr(conf)) {
2222	u8 *dst = buf;
2223
2224	for (i = 0; i < len; i++)
2225	dst[i] = ddrbuf[i * 2];
2226	}
2227
2228	kfree(objp: ddrbuf);
2229
2230	return ret;
2231	}
2232
2233	if (check_only)
2234	return 0;
2235
2236	if (force_8bit) {
2237	u8 *p = buf;
2238	unsigned int i;
2239
2240	for (i = 0; i < len; i++)
2241	p[i] = chip->legacy.read_byte(chip);
2242	} else {
2243	chip->legacy.read_buf(chip, buf, len);
2244	}
2245
2246	return 0;
2247	}
2248	EXPORT_SYMBOL_GPL(nand_read_data_op);
2249
2250	/**
2251	* nand_write_data_op - Write data from the NAND
2252	* @chip: The NAND chip
2253	* @buf: buffer containing the data to send on the bus
2254	* @len: length of the buffer
2255	* @force_8bit: force 8-bit bus access
2256	*
2257	* This function does a raw data write on the bus. Usually used after launching
2258	* another NAND operation like nand_write_page_begin_op().
2259	* This function does not select/unselect the CS line.
2260	*
2261	* Returns 0 on success, a negative error code otherwise.
2262	*/
2263	int nand_write_data_op(struct nand_chip *chip, const void *buf,
2264	unsigned int len, bool force_8bit)
2265	{
2266	if (!len || !buf)
2267	return -EINVAL;
2268
2269	if (nand_has_exec_op(chip)) {
2270	struct nand_op_instr instrs[] = {
2271	NAND_OP_DATA_OUT(len, buf, 0),
2272	};
2273	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2274
2275	instrs[0].ctx.data.force_8bit = force_8bit;
2276
2277	return nand_exec_op(chip, op: &op);
2278	}
2279
2280	if (force_8bit) {
2281	const u8 *p = buf;
2282	unsigned int i;
2283
2284	for (i = 0; i < len; i++)
2285	chip->legacy.write_byte(chip, p[i]);
2286	} else {
2287	chip->legacy.write_buf(chip, buf, len);
2288	}
2289
2290	return 0;
2291	}
2292	EXPORT_SYMBOL_GPL(nand_write_data_op);
2293
2294	/**
2295	* struct nand_op_parser_ctx - Context used by the parser
2296	* @instrs: array of all the instructions that must be addressed
2297	* @ninstrs: length of the @instrs array
2298	* @subop: Sub-operation to be passed to the NAND controller
2299	*
2300	* This structure is used by the core to split NAND operations into
2301	* sub-operations that can be handled by the NAND controller.
2302	*/
2303	struct nand_op_parser_ctx {
2304	const struct nand_op_instr *instrs;
2305	unsigned int ninstrs;
2306	struct nand_subop subop;
2307	};
2308
2309	/**
2310	* nand_op_parser_must_split_instr - Checks if an instruction must be split
2311	* @pat: the parser pattern element that matches @instr
2312	* @instr: pointer to the instruction to check
2313	* @start_offset: this is an in/out parameter. If @instr has already been
2314	* split, then @start_offset is the offset from which to start
2315	* (either an address cycle or an offset in the data buffer).
2316	* Conversely, if the function returns true (ie. instr must be
2317	* split), this parameter is updated to point to the first
2318	* data/address cycle that has not been taken care of.
2319	*
2320	* Some NAND controllers are limited and cannot send X address cycles with a
2321	* unique operation, or cannot read/write more than Y bytes at the same time.
2322	* In this case, split the instruction that does not fit in a single
2323	* controller-operation into two or more chunks.
2324	*
2325	* Returns true if the instruction must be split, false otherwise.
2326	* The @start_offset parameter is also updated to the offset at which the next
2327	* bundle of instruction must start (if an address or a data instruction).
2328	*/
2329	static bool
2330	nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem *pat,
2331	const struct nand_op_instr *instr,
2332	unsigned int *start_offset)
2333	{
2334	switch (pat->type) {
2335	case NAND_OP_ADDR_INSTR:
2336	if (!pat->ctx.addr.maxcycles)
2337	break;
2338
2339	if (instr->ctx.addr.naddrs - *start_offset >
2340	pat->ctx.addr.maxcycles) {
2341	*start_offset += pat->ctx.addr.maxcycles;
2342	return true;
2343	}
2344	break;
2345
2346	case NAND_OP_DATA_IN_INSTR:
2347	case NAND_OP_DATA_OUT_INSTR:
2348	if (!pat->ctx.data.maxlen)
2349	break;
2350
2351	if (instr->ctx.data.len - *start_offset >
2352	pat->ctx.data.maxlen) {
2353	*start_offset += pat->ctx.data.maxlen;
2354	return true;
2355	}
2356	break;
2357
2358	default:
2359	break;
2360	}
2361
2362	return false;
2363	}
2364
2365	/**
2366	* nand_op_parser_match_pat - Checks if a pattern matches the instructions
2367	* remaining in the parser context
2368	* @pat: the pattern to test
2369	* @ctx: the parser context structure to match with the pattern @pat
2370	*
2371	* Check if @pat matches the set or a sub-set of instructions remaining in @ctx.
2372	* Returns true if this is the case, false ortherwise. When true is returned,
2373	* @ctx->subop is updated with the set of instructions to be passed to the
2374	* controller driver.
2375	*/
2376	static bool
2377	nand_op_parser_match_pat(const struct nand_op_parser_pattern *pat,
2378	struct nand_op_parser_ctx *ctx)
2379	{
2380	unsigned int instr_offset = ctx->subop.first_instr_start_off;
2381	const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs;
2382	const struct nand_op_instr *instr = ctx->subop.instrs;
2383	unsigned int i, ninstrs;
2384
2385	for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) {
2386	/*
2387	* The pattern instruction does not match the operation
2388	* instruction. If the instruction is marked optional in the
2389	* pattern definition, we skip the pattern element and continue
2390	* to the next one. If the element is mandatory, there's no
2391	* match and we can return false directly.
2392	*/
2393	if (instr->type != pat->elems[i].type) {
2394	if (!pat->elems[i].optional)
2395	return false;
2396
2397	continue;
2398	}
2399
2400	/*
2401	* Now check the pattern element constraints. If the pattern is
2402	* not able to handle the whole instruction in a single step,
2403	* we have to split it.
2404	* The last_instr_end_off value comes back updated to point to
2405	* the position where we have to split the instruction (the
2406	* start of the next subop chunk).
2407	*/
2408	if (nand_op_parser_must_split_instr(pat: &pat->elems[i], instr,
2409	start_offset: &instr_offset)) {
2410	ninstrs++;
2411	i++;
2412	break;
2413	}
2414
2415	instr++;
2416	ninstrs++;
2417	instr_offset = 0;
2418	}
2419
2420	/*
2421	* This can happen if all instructions of a pattern are optional.
2422	* Still, if there's not at least one instruction handled by this
2423	* pattern, this is not a match, and we should try the next one (if
2424	* any).
2425	*/
2426	if (!ninstrs)
2427	return false;
2428
2429	/*
2430	* We had a match on the pattern head, but the pattern may be longer
2431	* than the instructions we're asked to execute. We need to make sure
2432	* there's no mandatory elements in the pattern tail.
2433	*/
2434	for (; i < pat->nelems; i++) {
2435	if (!pat->elems[i].optional)
2436	return false;
2437	}
2438
2439	/*
2440	* We have a match: update the subop structure accordingly and return
2441	* true.
2442	*/
2443	ctx->subop.ninstrs = ninstrs;
2444	ctx->subop.last_instr_end_off = instr_offset;
2445
2446	return true;
2447	}
2448
2449	#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
2450	static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)
2451	{
2452	const struct nand_op_instr *instr;
2453	char *prefix = " ";
2454	unsigned int i;
2455
2456	pr_debug("executing subop (CS%d):\n", ctx->subop.cs);
2457
2458	for (i = 0; i < ctx->ninstrs; i++) {
2459	instr = &ctx->instrs[i];
2460
2461	if (instr == &ctx->subop.instrs[0])
2462	prefix = " ->";
2463
2464	nand_op_trace(prefix, instr);
2465
2466	if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1])
2467	prefix = " ";
2468	}
2469	}
2470	#else
2471	static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)
2472	{
2473	/* NOP */
2474	}
2475	#endif
2476
2477	static int nand_op_parser_cmp_ctx(const struct nand_op_parser_ctx *a,
2478	const struct nand_op_parser_ctx *b)
2479	{
2480	if (a->subop.ninstrs < b->subop.ninstrs)
2481	return -1;
2482	else if (a->subop.ninstrs > b->subop.ninstrs)
2483	return 1;
2484
2485	if (a->subop.last_instr_end_off < b->subop.last_instr_end_off)
2486	return -1;
2487	else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off)
2488	return 1;
2489
2490	return 0;
2491	}
2492
2493	/**
2494	* nand_op_parser_exec_op - exec_op parser
2495	* @chip: the NAND chip
2496	* @parser: patterns description provided by the controller driver
2497	* @op: the NAND operation to address
2498	* @check_only: when true, the function only checks if @op can be handled but
2499	* does not execute the operation
2500	*
2501	* Helper function designed to ease integration of NAND controller drivers that
2502	* only support a limited set of instruction sequences. The supported sequences
2503	* are described in @parser, and the framework takes care of splitting @op into
2504	* multiple sub-operations (if required) and pass them back to the ->exec()
2505	* callback of the matching pattern if @check_only is set to false.
2506	*
2507	* NAND controller drivers should call this function from their own ->exec_op()
2508	* implementation.
2509	*
2510	* Returns 0 on success, a negative error code otherwise. A failure can be
2511	* caused by an unsupported operation (none of the supported patterns is able
2512	* to handle the requested operation), or an error returned by one of the
2513	* matching pattern->exec() hook.
2514	*/
2515	int nand_op_parser_exec_op(struct nand_chip *chip,
2516	const struct nand_op_parser *parser,
2517	const struct nand_operation *op, bool check_only)
2518	{
2519	struct nand_op_parser_ctx ctx = {
2520	.subop.cs = op->cs,
2521	.subop.instrs = op->instrs,
2522	.instrs = op->instrs,
2523	.ninstrs = op->ninstrs,
2524	};
2525	unsigned int i;
2526
2527	while (ctx.subop.instrs < op->instrs + op->ninstrs) {
2528	const struct nand_op_parser_pattern *pattern;
2529	struct nand_op_parser_ctx best_ctx;
2530	int ret, best_pattern = -1;
2531
2532	for (i = 0; i < parser->npatterns; i++) {
2533	struct nand_op_parser_ctx test_ctx = ctx;
2534
2535	pattern = &parser->patterns[i];
2536	if (!nand_op_parser_match_pat(pat: pattern, ctx: &test_ctx))
2537	continue;
2538
2539	if (best_pattern >= 0 &&
2540	nand_op_parser_cmp_ctx(a: &test_ctx, b: &best_ctx) <= 0)
2541	continue;
2542
2543	best_pattern = i;
2544	best_ctx = test_ctx;
2545	}
2546
2547	if (best_pattern < 0) {
2548	pr_debug("->exec_op() parser: pattern not found!\n");
2549	return -ENOTSUPP;
2550	}
2551
2552	ctx = best_ctx;
2553	nand_op_parser_trace(ctx: &ctx);
2554
2555	if (!check_only) {
2556	pattern = &parser->patterns[best_pattern];
2557	ret = pattern->exec(chip, &ctx.subop);
2558	if (ret)
2559	return ret;
2560	}
2561
2562	/*
2563	* Update the context structure by pointing to the start of the
2564	* next subop.
2565	*/
2566	ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs;
2567	if (ctx.subop.last_instr_end_off)
2568	ctx.subop.instrs -= 1;
2569
2570	ctx.subop.first_instr_start_off = ctx.subop.last_instr_end_off;
2571	}
2572
2573	return 0;
2574	}
2575	EXPORT_SYMBOL_GPL(nand_op_parser_exec_op);
2576
2577	static bool nand_instr_is_data(const struct nand_op_instr *instr)
2578	{
2579	return instr && (instr->type == NAND_OP_DATA_IN_INSTR ||
2580	instr->type == NAND_OP_DATA_OUT_INSTR);
2581	}
2582
2583	static bool nand_subop_instr_is_valid(const struct nand_subop *subop,
2584	unsigned int instr_idx)
2585	{
2586	return subop && instr_idx < subop->ninstrs;
2587	}
2588
2589	static unsigned int nand_subop_get_start_off(const struct nand_subop *subop,
2590	unsigned int instr_idx)
2591	{
2592	if (instr_idx)
2593	return 0;
2594
2595	return subop->first_instr_start_off;
2596	}
2597
2598	/**
2599	* nand_subop_get_addr_start_off - Get the start offset in an address array
2600	* @subop: The entire sub-operation
2601	* @instr_idx: Index of the instruction inside the sub-operation
2602	*
2603	* During driver development, one could be tempted to directly use the
2604	* ->addr.addrs field of address instructions. This is wrong as address
2605	* instructions might be split.
2606	*
2607	* Given an address instruction, returns the offset of the first cycle to issue.
2608	*/
2609	unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
2610	unsigned int instr_idx)
2611	{
2612	if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2613	subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR))
2614	return 0;
2615
2616	return nand_subop_get_start_off(subop, instr_idx);
2617	}
2618	EXPORT_SYMBOL_GPL(nand_subop_get_addr_start_off);
2619
2620	/**
2621	* nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert
2622	* @subop: The entire sub-operation
2623	* @instr_idx: Index of the instruction inside the sub-operation
2624	*
2625	* During driver development, one could be tempted to directly use the
2626	* ->addr->naddrs field of a data instruction. This is wrong as instructions
2627	* might be split.
2628	*
2629	* Given an address instruction, returns the number of address cycle to issue.
2630	*/
2631	unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
2632	unsigned int instr_idx)
2633	{
2634	int start_off, end_off;
2635
2636	if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2637	subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR))
2638	return 0;
2639
2640	start_off = nand_subop_get_addr_start_off(subop, instr_idx);
2641
2642	if (instr_idx == subop->ninstrs - 1 &&
2643	subop->last_instr_end_off)
2644	end_off = subop->last_instr_end_off;
2645	else
2646	end_off = subop->instrs[instr_idx].ctx.addr.naddrs;
2647
2648	return end_off - start_off;
2649	}
2650	EXPORT_SYMBOL_GPL(nand_subop_get_num_addr_cyc);
2651
2652	/**
2653	* nand_subop_get_data_start_off - Get the start offset in a data array
2654	* @subop: The entire sub-operation
2655	* @instr_idx: Index of the instruction inside the sub-operation
2656	*
2657	* During driver development, one could be tempted to directly use the
2658	* ->data->buf.{in,out} field of data instructions. This is wrong as data
2659	* instructions might be split.
2660	*
2661	* Given a data instruction, returns the offset to start from.
2662	*/
2663	unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
2664	unsigned int instr_idx)
2665	{
2666	if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2667	!nand_instr_is_data(&subop->instrs[instr_idx])))
2668	return 0;
2669
2670	return nand_subop_get_start_off(subop, instr_idx);
2671	}
2672	EXPORT_SYMBOL_GPL(nand_subop_get_data_start_off);
2673
2674	/**
2675	* nand_subop_get_data_len - Get the number of bytes to retrieve
2676	* @subop: The entire sub-operation
2677	* @instr_idx: Index of the instruction inside the sub-operation
2678	*
2679	* During driver development, one could be tempted to directly use the
2680	* ->data->len field of a data instruction. This is wrong as data instructions
2681	* might be split.
2682	*
2683	* Returns the length of the chunk of data to send/receive.
2684	*/
2685	unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
2686	unsigned int instr_idx)
2687	{
2688	int start_off = 0, end_off;
2689
2690	if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2691	!nand_instr_is_data(&subop->instrs[instr_idx])))
2692	return 0;
2693
2694	start_off = nand_subop_get_data_start_off(subop, instr_idx);
2695
2696	if (instr_idx == subop->ninstrs - 1 &&
2697	subop->last_instr_end_off)
2698	end_off = subop->last_instr_end_off;
2699	else
2700	end_off = subop->instrs[instr_idx].ctx.data.len;
2701
2702	return end_off - start_off;
2703	}
2704	EXPORT_SYMBOL_GPL(nand_subop_get_data_len);
2705
2706	/**
2707	* nand_reset - Reset and initialize a NAND device
2708	* @chip: The NAND chip
2709	* @chipnr: Internal die id
2710	*
2711	* Save the timings data structure, then apply SDR timings mode 0 (see
2712	* nand_reset_interface for details), do the reset operation, and apply
2713	* back the previous timings.
2714	*
2715	* Returns 0 on success, a negative error code otherwise.
2716	*/
2717	int nand_reset(struct nand_chip *chip, int chipnr)
2718	{
2719	int ret;
2720
2721	ret = nand_reset_interface(chip, chipnr);
2722	if (ret)
2723	return ret;
2724
2725	/*
2726	* The CS line has to be released before we can apply the new NAND
2727	* interface settings, hence this weird nand_select_target()
2728	* nand_deselect_target() dance.
2729	*/
2730	nand_select_target(chip, chipnr);
2731	ret = nand_reset_op(chip);
2732	nand_deselect_target(chip);
2733	if (ret)
2734	return ret;
2735
2736	ret = nand_setup_interface(chip, chipnr);
2737	if (ret)
2738	return ret;
2739
2740	return 0;
2741	}
2742	EXPORT_SYMBOL_GPL(nand_reset);
2743
2744	/**
2745	* nand_get_features - wrapper to perform a GET_FEATURE
2746	* @chip: NAND chip info structure
2747	* @addr: feature address
2748	* @subfeature_param: the subfeature parameters, a four bytes array
2749	*
2750	* Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2751	* operation cannot be handled.
2752	*/
2753	int nand_get_features(struct nand_chip *chip, int addr,
2754	u8 *subfeature_param)
2755	{
2756	if (!nand_supports_get_features(chip, addr))
2757	return -ENOTSUPP;
2758
2759	if (chip->legacy.get_features)
2760	return chip->legacy.get_features(chip, addr, subfeature_param);
2761
2762	return nand_get_features_op(chip, feature: addr, data: subfeature_param);
2763	}
2764
2765	/**
2766	* nand_set_features - wrapper to perform a SET_FEATURE
2767	* @chip: NAND chip info structure
2768	* @addr: feature address
2769	* @subfeature_param: the subfeature parameters, a four bytes array
2770	*
2771	* Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2772	* operation cannot be handled.
2773	*/
2774	int nand_set_features(struct nand_chip *chip, int addr,
2775	u8 *subfeature_param)
2776	{
2777	if (!nand_supports_set_features(chip, addr))
2778	return -ENOTSUPP;
2779
2780	if (chip->legacy.set_features)
2781	return chip->legacy.set_features(chip, addr, subfeature_param);
2782
2783	return nand_set_features_op(chip, feature: addr, data: subfeature_param);
2784	}
2785
2786	/**
2787	* nand_read_page_raw_notsupp - dummy read raw page function
2788	* @chip: nand chip info structure
2789	* @buf: buffer to store read data
2790	* @oob_required: caller requires OOB data read to chip->oob_poi
2791	* @page: page number to read
2792	*
2793	* Returns -ENOTSUPP unconditionally.
2794	*/
2795	int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf,
2796	int oob_required, int page)
2797	{
2798	return -ENOTSUPP;
2799	}
2800
2801	/**
2802	* nand_read_page_raw - [INTERN] read raw page data without ecc
2803	* @chip: nand chip info structure
2804	* @buf: buffer to store read data
2805	* @oob_required: caller requires OOB data read to chip->oob_poi
2806	* @page: page number to read
2807	*
2808	* Not for syndrome calculating ECC controllers, which use a special oob layout.
2809	*/
2810	int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
2811	int page)
2812	{
2813	struct mtd_info *mtd = nand_to_mtd(chip);
2814	int ret;
2815
2816	ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
2817	if (ret)
2818	return ret;
2819
2820	if (oob_required) {
2821	ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
2822	false, false);
2823	if (ret)
2824	return ret;
2825	}
2826
2827	return 0;
2828	}
2829	EXPORT_SYMBOL(nand_read_page_raw);
2830
2831	/**
2832	* nand_monolithic_read_page_raw - Monolithic page read in raw mode
2833	* @chip: NAND chip info structure
2834	* @buf: buffer to store read data
2835	* @oob_required: caller requires OOB data read to chip->oob_poi
2836	* @page: page number to read
2837	*
2838	* This is a raw page read, ie. without any error detection/correction.
2839	* Monolithic means we are requesting all the relevant data (main plus
2840	* eventually OOB) to be loaded in the NAND cache and sent over the
2841	* bus (from the NAND chip to the NAND controller) in a single
2842	* operation. This is an alternative to nand_read_page_raw(), which
2843	* first reads the main data, and if the OOB data is requested too,
2844	* then reads more data on the bus.
2845	*/
2846	int nand_monolithic_read_page_raw(struct nand_chip *chip, u8 *buf,
2847	int oob_required, int page)
2848	{
2849	struct mtd_info *mtd = nand_to_mtd(chip);
2850	unsigned int size = mtd->writesize;
2851	u8 *read_buf = buf;
2852	int ret;
2853
2854	if (oob_required) {
2855	size += mtd->oobsize;
2856
2857	if (buf != chip->data_buf)
2858	read_buf = nand_get_data_buf(chip);
2859	}
2860
2861	ret = nand_read_page_op(chip, page, 0, read_buf, size);
2862	if (ret)
2863	return ret;
2864
2865	if (buf != chip->data_buf)
2866	memcpy(buf, read_buf, mtd->writesize);
2867
2868	return 0;
2869	}
2870	EXPORT_SYMBOL(nand_monolithic_read_page_raw);
2871
2872	/**
2873	* nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
2874	* @chip: nand chip info structure
2875	* @buf: buffer to store read data
2876	* @oob_required: caller requires OOB data read to chip->oob_poi
2877	* @page: page number to read
2878	*
2879	* We need a special oob layout and handling even when OOB isn't used.
2880	*/
2881	static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf,
2882	int oob_required, int page)
2883	{
2884	struct mtd_info *mtd = nand_to_mtd(chip);
2885	int eccsize = chip->ecc.size;
2886	int eccbytes = chip->ecc.bytes;
2887	uint8_t *oob = chip->oob_poi;
2888	int steps, size, ret;
2889
2890	ret = nand_read_page_op(chip, page, 0, NULL, 0);
2891	if (ret)
2892	return ret;
2893
2894	for (steps = chip->ecc.steps; steps > 0; steps--) {
2895	ret = nand_read_data_op(chip, buf, eccsize, false, false);
2896	if (ret)
2897	return ret;
2898
2899	buf += eccsize;
2900
2901	if (chip->ecc.prepad) {
2902	ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
2903	false, false);
2904	if (ret)
2905	return ret;
2906
2907	oob += chip->ecc.prepad;
2908	}
2909
2910	ret = nand_read_data_op(chip, oob, eccbytes, false, false);
2911	if (ret)
2912	return ret;
2913
2914	oob += eccbytes;
2915
2916	if (chip->ecc.postpad) {
2917	ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
2918	false, false);
2919	if (ret)
2920	return ret;
2921
2922	oob += chip->ecc.postpad;
2923	}
2924	}
2925
2926	size = mtd->oobsize - (oob - chip->oob_poi);
2927	if (size) {
2928	ret = nand_read_data_op(chip, oob, size, false, false);
2929	if (ret)
2930	return ret;
2931	}
2932
2933	return 0;
2934	}
2935
2936	/**
2937	* nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
2938	* @chip: nand chip info structure
2939	* @buf: buffer to store read data
2940	* @oob_required: caller requires OOB data read to chip->oob_poi
2941	* @page: page number to read
2942	*/
2943	static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf,
2944	int oob_required, int page)
2945	{
2946	struct mtd_info *mtd = nand_to_mtd(chip);
2947	int i, eccsize = chip->ecc.size, ret;
2948	int eccbytes = chip->ecc.bytes;
2949	int eccsteps = chip->ecc.steps;
2950	uint8_t *p = buf;
2951	uint8_t *ecc_calc = chip->ecc.calc_buf;
2952	uint8_t *ecc_code = chip->ecc.code_buf;
2953	unsigned int max_bitflips = 0;
2954
2955	chip->ecc.read_page_raw(chip, buf, 1, page);
2956
2957	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2958	chip->ecc.calculate(chip, p, &ecc_calc[i]);
2959
2960	ret = mtd_ooblayout_get_eccbytes(mtd, eccbuf: ecc_code, oobbuf: chip->oob_poi, start: 0,
2961	nbytes: chip->ecc.total);
2962	if (ret)
2963	return ret;
2964
2965	eccsteps = chip->ecc.steps;
2966	p = buf;
2967
2968	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2969	int stat;
2970
2971	stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
2972	if (stat < 0) {
2973	mtd->ecc_stats.failed++;
2974	} else {
2975	mtd->ecc_stats.corrected += stat;
2976	max_bitflips = max_t(unsigned int, max_bitflips, stat);
2977	}
2978	}
2979	return max_bitflips;
2980	}
2981
2982	/**
2983	* nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
2984	* @chip: nand chip info structure
2985	* @data_offs: offset of requested data within the page
2986	* @readlen: data length
2987	* @bufpoi: buffer to store read data
2988	* @page: page number to read
2989	*/
2990	static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs,
2991	uint32_t readlen, uint8_t *bufpoi, int page)
2992	{
2993	struct mtd_info *mtd = nand_to_mtd(chip);
2994	int start_step, end_step, num_steps, ret;
2995	uint8_t *p;
2996	int data_col_addr, i, gaps = 0;
2997	int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
2998	int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
2999	int index, section = 0;
3000	unsigned int max_bitflips = 0;
3001	struct mtd_oob_region oobregion = { };
3002
3003	/* Column address within the page aligned to ECC size (256bytes) */
3004	start_step = data_offs / chip->ecc.size;
3005	end_step = (data_offs + readlen - 1) / chip->ecc.size;
3006	num_steps = end_step - start_step + 1;
3007	index = start_step * chip->ecc.bytes;
3008
3009	/* Data size aligned to ECC ecc.size */
3010	datafrag_len = num_steps * chip->ecc.size;
3011	eccfrag_len = num_steps * chip->ecc.bytes;
3012
3013	data_col_addr = start_step * chip->ecc.size;
3014	/* If we read not a page aligned data */
3015	p = bufpoi + data_col_addr;
3016	ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len);
3017	if (ret)
3018	return ret;
3019
3020	/* Calculate ECC */
3021	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
3022	chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]);
3023
3024	/*
3025	* The performance is faster if we position offsets according to
3026	* ecc.pos. Let's make sure that there are no gaps in ECC positions.
3027	*/
3028	ret = mtd_ooblayout_find_eccregion(mtd, eccbyte: index, section: &section, oobregion: &oobregion);
3029	if (ret)
3030	return ret;
3031
3032	if (oobregion.length < eccfrag_len)
3033	gaps = 1;
3034
3035	if (gaps) {
3036	ret = nand_change_read_column_op(chip, mtd->writesize,
3037	chip->oob_poi, mtd->oobsize,
3038	false);
3039	if (ret)
3040	return ret;
3041	} else {
3042	/*
3043	* Send the command to read the particular ECC bytes take care
3044	* about buswidth alignment in read_buf.
3045	*/
3046	aligned_pos = oobregion.offset & ~(busw - 1);
3047	aligned_len = eccfrag_len;
3048	if (oobregion.offset & (busw - 1))
3049	aligned_len++;
3050	if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
3051	(busw - 1))
3052	aligned_len++;
3053
3054	ret = nand_change_read_column_op(chip,
3055	mtd->writesize + aligned_pos,
3056	&chip->oob_poi[aligned_pos],
3057	aligned_len, false);
3058	if (ret)
3059	return ret;
3060	}
3061
3062	ret = mtd_ooblayout_get_eccbytes(mtd, eccbuf: chip->ecc.code_buf,
3063	oobbuf: chip->oob_poi, start: index, nbytes: eccfrag_len);
3064	if (ret)
3065	return ret;
3066
3067	p = bufpoi + data_col_addr;
3068	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
3069	int stat;
3070
3071	stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i],
3072	&chip->ecc.calc_buf[i]);
3073	if (stat == -EBADMSG &&
3074	(chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3075	/* check for empty pages with bitflips */
3076	stat = nand_check_erased_ecc_chunk(data: p, datalen: chip->ecc.size,
3077	ecc: &chip->ecc.code_buf[i],
3078	ecclen: chip->ecc.bytes,
3079	NULL, extraooblen: 0,
3080	threshold: chip->ecc.strength);
3081	}
3082
3083	if (stat < 0) {
3084	mtd->ecc_stats.failed++;
3085	} else {
3086	mtd->ecc_stats.corrected += stat;
3087	max_bitflips = max_t(unsigned int, max_bitflips, stat);
3088	}
3089	}
3090	return max_bitflips;
3091	}
3092
3093	/**
3094	* nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
3095	* @chip: nand chip info structure
3096	* @buf: buffer to store read data
3097	* @oob_required: caller requires OOB data read to chip->oob_poi
3098	* @page: page number to read
3099	*
3100	* Not for syndrome calculating ECC controllers which need a special oob layout.
3101	*/
3102	static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
3103	int oob_required, int page)
3104	{
3105	struct mtd_info *mtd = nand_to_mtd(chip);
3106	int i, eccsize = chip->ecc.size, ret;
3107	int eccbytes = chip->ecc.bytes;
3108	int eccsteps = chip->ecc.steps;
3109	uint8_t *p = buf;
3110	uint8_t *ecc_calc = chip->ecc.calc_buf;
3111	uint8_t *ecc_code = chip->ecc.code_buf;
3112	unsigned int max_bitflips = 0;
3113
3114	ret = nand_read_page_op(chip, page, 0, NULL, 0);
3115	if (ret)
3116	return ret;
3117
3118	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3119	chip->ecc.hwctl(chip, NAND_ECC_READ);
3120
3121	ret = nand_read_data_op(chip, p, eccsize, false, false);
3122	if (ret)
3123	return ret;
3124
3125	chip->ecc.calculate(chip, p, &ecc_calc[i]);
3126	}
3127
3128	ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false,
3129	false);
3130	if (ret)
3131	return ret;
3132
3133	ret = mtd_ooblayout_get_eccbytes(mtd, eccbuf: ecc_code, oobbuf: chip->oob_poi, start: 0,
3134	nbytes: chip->ecc.total);
3135	if (ret)
3136	return ret;
3137
3138	eccsteps = chip->ecc.steps;
3139	p = buf;
3140
3141	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3142	int stat;
3143
3144	stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
3145	if (stat == -EBADMSG &&
3146	(chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3147	/* check for empty pages with bitflips */
3148	stat = nand_check_erased_ecc_chunk(data: p, datalen: eccsize,
3149	ecc: &ecc_code[i], ecclen: eccbytes,
3150	NULL, extraooblen: 0,
3151	threshold: chip->ecc.strength);
3152	}
3153
3154	if (stat < 0) {
3155	mtd->ecc_stats.failed++;
3156	} else {
3157	mtd->ecc_stats.corrected += stat;
3158	max_bitflips = max_t(unsigned int, max_bitflips, stat);
3159	}
3160	}
3161	return max_bitflips;
3162	}
3163
3164	/**
3165	* nand_read_page_hwecc_oob_first - Hardware ECC page read with ECC
3166	* data read from OOB area
3167	* @chip: nand chip info structure
3168	* @buf: buffer to store read data
3169	* @oob_required: caller requires OOB data read to chip->oob_poi
3170	* @page: page number to read
3171	*
3172	* Hardware ECC for large page chips, which requires the ECC data to be
3173	* extracted from the OOB before the actual data is read.
3174	*/
3175	int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf,
3176	int oob_required, int page)
3177	{
3178	struct mtd_info *mtd = nand_to_mtd(chip);
3179	int i, eccsize = chip->ecc.size, ret;
3180	int eccbytes = chip->ecc.bytes;
3181	int eccsteps = chip->ecc.steps;
3182	uint8_t *p = buf;
3183	uint8_t *ecc_code = chip->ecc.code_buf;
3184	unsigned int max_bitflips = 0;
3185
3186	/* Read the OOB area first */
3187	ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
3188	if (ret)
3189	return ret;
3190
3191	/* Move read cursor to start of page */
3192	ret = nand_change_read_column_op(chip, 0, NULL, 0, false);
3193	if (ret)
3194	return ret;
3195
3196	ret = mtd_ooblayout_get_eccbytes(mtd, eccbuf: ecc_code, oobbuf: chip->oob_poi, start: 0,
3197	nbytes: chip->ecc.total);
3198	if (ret)
3199	return ret;
3200
3201	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3202	int stat;
3203
3204	chip->ecc.hwctl(chip, NAND_ECC_READ);
3205
3206	ret = nand_read_data_op(chip, p, eccsize, false, false);
3207	if (ret)
3208	return ret;
3209
3210	stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL);
3211	if (stat == -EBADMSG &&
3212	(chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3213	/* check for empty pages with bitflips */
3214	stat = nand_check_erased_ecc_chunk(data: p, datalen: eccsize,
3215	ecc: &ecc_code[i],
3216	ecclen: eccbytes, NULL, extraooblen: 0,
3217	threshold: chip->ecc.strength);
3218	}
3219
3220	if (stat < 0) {
3221	mtd->ecc_stats.failed++;
3222	} else {
3223	mtd->ecc_stats.corrected += stat;
3224	max_bitflips = max_t(unsigned int, max_bitflips, stat);
3225	}
3226	}
3227	return max_bitflips;
3228	}
3229	EXPORT_SYMBOL_GPL(nand_read_page_hwecc_oob_first);
3230
3231	/**
3232	* nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
3233	* @chip: nand chip info structure
3234	* @buf: buffer to store read data
3235	* @oob_required: caller requires OOB data read to chip->oob_poi
3236	* @page: page number to read
3237	*
3238	* The hw generator calculates the error syndrome automatically. Therefore we
3239	* need a special oob layout and handling.
3240	*/
3241	static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,
3242	int oob_required, int page)
3243	{
3244	struct mtd_info *mtd = nand_to_mtd(chip);
3245	int ret, i, eccsize = chip->ecc.size;
3246	int eccbytes = chip->ecc.bytes;
3247	int eccsteps = chip->ecc.steps;
3248	int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
3249	uint8_t *p = buf;
3250	uint8_t *oob = chip->oob_poi;
3251	unsigned int max_bitflips = 0;
3252
3253	ret = nand_read_page_op(chip, page, 0, NULL, 0);
3254	if (ret)
3255	return ret;
3256
3257	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3258	int stat;
3259
3260	chip->ecc.hwctl(chip, NAND_ECC_READ);
3261
3262	ret = nand_read_data_op(chip, p, eccsize, false, false);
3263	if (ret)
3264	return ret;
3265
3266	if (chip->ecc.prepad) {
3267	ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
3268	false, false);
3269	if (ret)
3270	return ret;
3271
3272	oob += chip->ecc.prepad;
3273	}
3274
3275	chip->ecc.hwctl(chip, NAND_ECC_READSYN);
3276
3277	ret = nand_read_data_op(chip, oob, eccbytes, false, false);
3278	if (ret)
3279	return ret;
3280
3281	stat = chip->ecc.correct(chip, p, oob, NULL);
3282
3283	oob += eccbytes;
3284
3285	if (chip->ecc.postpad) {
3286	ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
3287	false, false);
3288	if (ret)
3289	return ret;
3290
3291	oob += chip->ecc.postpad;
3292	}
3293
3294	if (stat == -EBADMSG &&
3295	(chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3296	/* check for empty pages with bitflips */
3297	stat = nand_check_erased_ecc_chunk(data: p, datalen: chip->ecc.size,
3298	ecc: oob - eccpadbytes,
3299	ecclen: eccpadbytes,
3300	NULL, extraooblen: 0,
3301	threshold: chip->ecc.strength);
3302	}
3303
3304	if (stat < 0) {
3305	mtd->ecc_stats.failed++;
3306	} else {
3307	mtd->ecc_stats.corrected += stat;
3308	max_bitflips = max_t(unsigned int, max_bitflips, stat);
3309	}
3310	}
3311
3312	/* Calculate remaining oob bytes */
3313	i = mtd->oobsize - (oob - chip->oob_poi);
3314	if (i) {
3315	ret = nand_read_data_op(chip, oob, i, false, false);
3316	if (ret)
3317	return ret;
3318	}
3319
3320	return max_bitflips;
3321	}
3322
3323	/**
3324	* nand_transfer_oob - [INTERN] Transfer oob to client buffer
3325	* @chip: NAND chip object
3326	* @oob: oob destination address
3327	* @ops: oob ops structure
3328	* @len: size of oob to transfer
3329	*/
3330	static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
3331	struct mtd_oob_ops *ops, size_t len)
3332	{
3333	struct mtd_info *mtd = nand_to_mtd(chip);
3334	int ret;
3335
3336	switch (ops->mode) {
3337
3338	case MTD_OPS_PLACE_OOB:
3339	case MTD_OPS_RAW:
3340	memcpy(oob, chip->oob_poi + ops->ooboffs, len);
3341	return oob + len;
3342
3343	case MTD_OPS_AUTO_OOB:
3344	ret = mtd_ooblayout_get_databytes(mtd, databuf: oob, oobbuf: chip->oob_poi,
3345	start: ops->ooboffs, nbytes: len);
3346	BUG_ON(ret);
3347	return oob + len;
3348
3349	default:
3350	BUG();
3351	}
3352	return NULL;
3353	}
3354
3355	static void rawnand_enable_cont_reads(struct nand_chip *chip, unsigned int page,
3356	u32 readlen, int col)
3357	{
3358	struct mtd_info *mtd = nand_to_mtd(chip);
3359	unsigned int first_page, last_page;
3360
3361	chip->cont_read.ongoing = false;
3362
3363	if (!chip->controller->supported_op.cont_read)
3364	return;
3365
3366	/*
3367	* Don't bother making any calculations if the length is too small.
3368	* Side effect: avoids possible integer underflows below.
3369	*/
3370	if (readlen < (2 * mtd->writesize))
3371	return;
3372
3373	/* Derive the page where continuous read should start (the first full page read) */
3374	first_page = page;
3375	if (col)
3376	first_page++;
3377
3378	/* Derive the page where continuous read should stop (the last full page read) */
3379	last_page = page + ((col + readlen) / mtd->writesize) - 1;
3380
3381	/* Configure and enable continuous read when suitable */
3382	if (first_page < last_page) {
3383	chip->cont_read.first_page = first_page;
3384	chip->cont_read.last_page = last_page;
3385	chip->cont_read.ongoing = true;
3386	/* May reset the ongoing flag */
3387	rawnand_cap_cont_reads(chip);
3388	}
3389	}
3390
3391	static void rawnand_cont_read_skip_first_page(struct nand_chip *chip, unsigned int page)
3392	{
3393	if (!chip->cont_read.ongoing || page != chip->cont_read.first_page)
3394	return;
3395
3396	chip->cont_read.first_page++;
3397	rawnand_cap_cont_reads(chip);
3398	}
3399
3400	/**
3401	* nand_setup_read_retry - [INTERN] Set the READ RETRY mode
3402	* @chip: NAND chip object
3403	* @retry_mode: the retry mode to use
3404	*
3405	* Some vendors supply a special command to shift the Vt threshold, to be used
3406	* when there are too many bitflips in a page (i.e., ECC error). After setting
3407	* a new threshold, the host should retry reading the page.
3408	*/
3409	static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
3410	{
3411	pr_debug("setting READ RETRY mode %d\n", retry_mode);
3412
3413	if (retry_mode >= chip->read_retries)
3414	return -EINVAL;
3415
3416	if (!chip->ops.setup_read_retry)
3417	return -EOPNOTSUPP;
3418
3419	return chip->ops.setup_read_retry(chip, retry_mode);
3420	}
3421
3422	static void nand_wait_readrdy(struct nand_chip *chip)
3423	{
3424	const struct nand_interface_config *conf;
3425
3426	if (!(chip->options & NAND_NEED_READRDY))
3427	return;
3428
3429	conf = nand_get_interface_config(chip);
3430	WARN_ON(nand_wait_rdy_op(chip, NAND_COMMON_TIMING_MS(conf, tR_max), 0));
3431	}
3432
3433	/**
3434	* nand_do_read_ops - [INTERN] Read data with ECC
3435	* @chip: NAND chip object
3436	* @from: offset to read from
3437	* @ops: oob ops structure
3438	*
3439	* Internal function. Called with chip held.
3440	*/
3441	static int nand_do_read_ops(struct nand_chip *chip, loff_t from,
3442	struct mtd_oob_ops *ops)
3443	{
3444	int chipnr, page, realpage, col, bytes, aligned, oob_required;
3445	struct mtd_info *mtd = nand_to_mtd(chip);
3446	int ret = 0;
3447	uint32_t readlen = ops->len;
3448	uint32_t oobreadlen = ops->ooblen;
3449	uint32_t max_oobsize = mtd_oobavail(mtd, ops);
3450
3451	uint8_t *bufpoi, *oob, *buf;
3452	int use_bounce_buf;
3453	unsigned int max_bitflips = 0;
3454	int retry_mode = 0;
3455	bool ecc_fail = false;
3456
3457	/* Check if the region is secured */
3458	if (nand_region_is_secured(chip, offset: from, size: readlen))
3459	return -EIO;
3460
3461	chipnr = (int)(from >> chip->chip_shift);
3462	nand_select_target(chip, chipnr);
3463
3464	realpage = (int)(from >> chip->page_shift);
3465	page = realpage & chip->pagemask;
3466
3467	col = (int)(from & (mtd->writesize - 1));
3468
3469	buf = ops->datbuf;
3470	oob = ops->oobbuf;
3471	oob_required = oob ? 1 : 0;
3472
3473	if (likely(ops->mode != MTD_OPS_RAW))
3474	rawnand_enable_cont_reads(chip, page, readlen, col);
3475
3476	while (1) {
3477	struct mtd_ecc_stats ecc_stats = mtd->ecc_stats;
3478
3479	bytes = min(mtd->writesize - col, readlen);
3480	aligned = (bytes == mtd->writesize);
3481
3482	if (!aligned)
3483	use_bounce_buf = 1;
3484	else if (chip->options & NAND_USES_DMA)
3485	use_bounce_buf = !virt_addr_valid(buf) ||
3486	!IS_ALIGNED((unsigned long)buf,
3487	chip->buf_align);
3488	else
3489	use_bounce_buf = 0;
3490
3491	/* Is the current page in the buffer? */
3492	if (realpage != chip->pagecache.page || oob) {
3493	bufpoi = use_bounce_buf ? chip->data_buf : buf;
3494
3495	if (use_bounce_buf && aligned)
3496	pr_debug("%s: using read bounce buffer for buf@%p\n",
3497	__func__, buf);
3498
3499	read_retry:
3500	/*
3501	* Now read the page into the buffer. Absent an error,
3502	* the read methods return max bitflips per ecc step.
3503	*/
3504	if (unlikely(ops->mode == MTD_OPS_RAW))
3505	ret = chip->ecc.read_page_raw(chip, bufpoi,
3506	oob_required,
3507	page);
3508	else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
3509	!oob)
3510	ret = chip->ecc.read_subpage(chip, col, bytes,
3511	bufpoi, page);
3512	else
3513	ret = chip->ecc.read_page(chip, bufpoi,
3514	oob_required, page);
3515	if (ret < 0) {
3516	if (use_bounce_buf)
3517	/* Invalidate page cache */
3518	chip->pagecache.page = -1;
3519	break;
3520	}
3521
3522	/*
3523	* Copy back the data in the initial buffer when reading
3524	* partial pages or when a bounce buffer is required.
3525	*/
3526	if (use_bounce_buf) {
3527	if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
3528	!(mtd->ecc_stats.failed - ecc_stats.failed) &&
3529	(ops->mode != MTD_OPS_RAW)) {
3530	chip->pagecache.page = realpage;
3531	chip->pagecache.bitflips = ret;
3532	} else {
3533	/* Invalidate page cache */
3534	chip->pagecache.page = -1;
3535	}
3536	memcpy(buf, bufpoi + col, bytes);
3537	}
3538
3539	if (unlikely(oob)) {
3540	int toread = min(oobreadlen, max_oobsize);
3541
3542	if (toread) {
3543	oob = nand_transfer_oob(chip, oob, ops,
3544	len: toread);
3545	oobreadlen -= toread;
3546	}
3547	}
3548
3549	nand_wait_readrdy(chip);
3550
3551	if (mtd->ecc_stats.failed - ecc_stats.failed) {
3552	if (retry_mode + 1 < chip->read_retries) {
3553	retry_mode++;
3554	ret = nand_setup_read_retry(chip,
3555	retry_mode);
3556	if (ret < 0)
3557	break;
3558
3559	/* Reset ecc_stats; retry */
3560	mtd->ecc_stats = ecc_stats;
3561	goto read_retry;
3562	} else {
3563	/* No more retry modes; real failure */
3564	ecc_fail = true;
3565	}
3566	}
3567
3568	buf += bytes;
3569	max_bitflips = max_t(unsigned int, max_bitflips, ret);
3570	} else {
3571	memcpy(buf, chip->data_buf + col, bytes);
3572	buf += bytes;
3573	max_bitflips = max_t(unsigned int, max_bitflips,
3574	chip->pagecache.bitflips);
3575
3576	rawnand_cont_read_skip_first_page(chip, page);
3577	}
3578
3579	readlen -= bytes;
3580
3581	/* Reset to retry mode 0 */
3582	if (retry_mode) {
3583	ret = nand_setup_read_retry(chip, retry_mode: 0);
3584	if (ret < 0)
3585	break;
3586	retry_mode = 0;
3587	}
3588
3589	if (!readlen)
3590	break;
3591
3592	/* For subsequent reads align to page boundary */
3593	col = 0;
3594	/* Increment page address */
3595	realpage++;
3596
3597	page = realpage & chip->pagemask;
3598	/* Check, if we cross a chip boundary */
3599	if (!page) {
3600	chipnr++;
3601	nand_deselect_target(chip);
3602	nand_select_target(chip, chipnr);
3603	}
3604	}
3605	nand_deselect_target(chip);
3606
3607	if (WARN_ON_ONCE(chip->cont_read.ongoing))
3608	chip->cont_read.ongoing = false;
3609
3610	ops->retlen = ops->len - (size_t) readlen;
3611	if (oob)
3612	ops->oobretlen = ops->ooblen - oobreadlen;
3613
3614	if (ret < 0)
3615	return ret;
3616
3617	if (ecc_fail)
3618	return -EBADMSG;
3619
3620	return max_bitflips;
3621	}
3622
3623	/**
3624	* nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
3625	* @chip: nand chip info structure
3626	* @page: page number to read
3627	*/
3628	int nand_read_oob_std(struct nand_chip *chip, int page)
3629	{
3630	struct mtd_info *mtd = nand_to_mtd(chip);
3631
3632	return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
3633	}
3634	EXPORT_SYMBOL(nand_read_oob_std);
3635
3636	/**
3637	* nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
3638	* with syndromes
3639	* @chip: nand chip info structure
3640	* @page: page number to read
3641	*/
3642	static int nand_read_oob_syndrome(struct nand_chip *chip, int page)
3643	{
3644	struct mtd_info *mtd = nand_to_mtd(chip);
3645	int length = mtd->oobsize;
3646	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3647	int eccsize = chip->ecc.size;
3648	uint8_t *bufpoi = chip->oob_poi;
3649	int i, toread, sndrnd = 0, pos, ret;
3650
3651	ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
3652	if (ret)
3653	return ret;
3654
3655	for (i = 0; i < chip->ecc.steps; i++) {
3656	if (sndrnd) {
3657	int ret;
3658
3659	pos = eccsize + i * (eccsize + chunk);
3660	if (mtd->writesize > 512)
3661	ret = nand_change_read_column_op(chip, pos,
3662	NULL, 0,
3663	false);
3664	else
3665	ret = nand_read_page_op(chip, page, pos, NULL,
3666	0);
3667
3668	if (ret)
3669	return ret;
3670	} else
3671	sndrnd = 1;
3672	toread = min_t(int, length, chunk);
3673
3674	ret = nand_read_data_op(chip, bufpoi, toread, false, false);
3675	if (ret)
3676	return ret;
3677
3678	bufpoi += toread;
3679	length -= toread;
3680	}
3681	if (length > 0) {
3682	ret = nand_read_data_op(chip, bufpoi, length, false, false);
3683	if (ret)
3684	return ret;
3685	}
3686
3687	return 0;
3688	}
3689
3690	/**
3691	* nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
3692	* @chip: nand chip info structure
3693	* @page: page number to write
3694	*/
3695	int nand_write_oob_std(struct nand_chip *chip, int page)
3696	{
3697	struct mtd_info *mtd = nand_to_mtd(chip);
3698
3699	return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
3700	mtd->oobsize);
3701	}
3702	EXPORT_SYMBOL(nand_write_oob_std);
3703
3704	/**
3705	* nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
3706	* with syndrome - only for large page flash
3707	* @chip: nand chip info structure
3708	* @page: page number to write
3709	*/
3710	static int nand_write_oob_syndrome(struct nand_chip *chip, int page)
3711	{
3712	struct mtd_info *mtd = nand_to_mtd(chip);
3713	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3714	int eccsize = chip->ecc.size, length = mtd->oobsize;
3715	int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
3716	const uint8_t *bufpoi = chip->oob_poi;
3717
3718	/*
3719	* data-ecc-data-ecc ... ecc-oob
3720	* or
3721	* data-pad-ecc-pad-data-pad .... ecc-pad-oob
3722	*/
3723	if (!chip->ecc.prepad && !chip->ecc.postpad) {
3724	pos = steps * (eccsize + chunk);
3725	steps = 0;
3726	} else
3727	pos = eccsize;
3728
3729	ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
3730	if (ret)
3731	return ret;
3732
3733	for (i = 0; i < steps; i++) {
3734	if (sndcmd) {
3735	if (mtd->writesize <= 512) {
3736	uint32_t fill = 0xFFFFFFFF;
3737
3738	len = eccsize;
3739	while (len > 0) {
3740	int num = min_t(int, len, 4);
3741
3742	ret = nand_write_data_op(chip, &fill,
3743	num, false);
3744	if (ret)
3745	return ret;
3746
3747	len -= num;
3748	}
3749	} else {
3750	pos = eccsize + i * (eccsize + chunk);
3751	ret = nand_change_write_column_op(chip, pos,
3752	NULL, 0,
3753	false);
3754	if (ret)
3755	return ret;
3756	}
3757	} else
3758	sndcmd = 1;
3759	len = min_t(int, length, chunk);
3760
3761	ret = nand_write_data_op(chip, bufpoi, len, false);
3762	if (ret)
3763	return ret;
3764
3765	bufpoi += len;
3766	length -= len;
3767	}
3768	if (length > 0) {
3769	ret = nand_write_data_op(chip, bufpoi, length, false);
3770	if (ret)
3771	return ret;
3772	}
3773
3774	return nand_prog_page_end_op(chip);
3775	}
3776
3777	/**
3778	* nand_do_read_oob - [INTERN] NAND read out-of-band
3779	* @chip: NAND chip object
3780	* @from: offset to read from
3781	* @ops: oob operations description structure
3782	*
3783	* NAND read out-of-band data from the spare area.
3784	*/
3785	static int nand_do_read_oob(struct nand_chip *chip, loff_t from,
3786	struct mtd_oob_ops *ops)
3787	{
3788	struct mtd_info *mtd = nand_to_mtd(chip);
3789	unsigned int max_bitflips = 0;
3790	int page, realpage, chipnr;
3791	struct mtd_ecc_stats stats;
3792	int readlen = ops->ooblen;
3793	int len;
3794	uint8_t *buf = ops->oobbuf;
3795	int ret = 0;
3796
3797	pr_debug("%s: from = 0x%08Lx, len = %i\n",
3798	__func__, (unsigned long long)from, readlen);
3799
3800	/* Check if the region is secured */
3801	if (nand_region_is_secured(chip, offset: from, size: readlen))
3802	return -EIO;
3803
3804	stats = mtd->ecc_stats;
3805
3806	len = mtd_oobavail(mtd, ops);
3807
3808	chipnr = (int)(from >> chip->chip_shift);
3809	nand_select_target(chip, chipnr);
3810
3811	/* Shift to get page */
3812	realpage = (int)(from >> chip->page_shift);
3813	page = realpage & chip->pagemask;
3814
3815	while (1) {
3816	if (ops->mode == MTD_OPS_RAW)
3817	ret = chip->ecc.read_oob_raw(chip, page);
3818	else
3819	ret = chip->ecc.read_oob(chip, page);
3820
3821	if (ret < 0)
3822	break;
3823
3824	len = min(len, readlen);
3825	buf = nand_transfer_oob(chip, oob: buf, ops, len);
3826
3827	nand_wait_readrdy(chip);
3828
3829	max_bitflips = max_t(unsigned int, max_bitflips, ret);
3830
3831	readlen -= len;
3832	if (!readlen)
3833	break;
3834
3835	/* Increment page address */
3836	realpage++;
3837
3838	page = realpage & chip->pagemask;
3839	/* Check, if we cross a chip boundary */
3840	if (!page) {
3841	chipnr++;
3842	nand_deselect_target(chip);
3843	nand_select_target(chip, chipnr);
3844	}
3845	}
3846	nand_deselect_target(chip);
3847
3848	ops->oobretlen = ops->ooblen - readlen;
3849
3850	if (ret < 0)
3851	return ret;
3852
3853	if (mtd->ecc_stats.failed - stats.failed)
3854	return -EBADMSG;
3855
3856	return max_bitflips;
3857	}
3858
3859	/**
3860	* nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
3861	* @mtd: MTD device structure
3862	* @from: offset to read from
3863	* @ops: oob operation description structure
3864	*
3865	* NAND read data and/or out-of-band data.
3866	*/
3867	static int nand_read_oob(struct mtd_info *mtd, loff_t from,
3868	struct mtd_oob_ops *ops)
3869	{
3870	struct nand_chip *chip = mtd_to_nand(mtd);
3871	struct mtd_ecc_stats old_stats;
3872	int ret;
3873
3874	ops->retlen = 0;
3875
3876	if (ops->mode != MTD_OPS_PLACE_OOB &&
3877	ops->mode != MTD_OPS_AUTO_OOB &&
3878	ops->mode != MTD_OPS_RAW)
3879	return -ENOTSUPP;
3880
3881	nand_get_device(chip);
3882
3883	old_stats = mtd->ecc_stats;
3884
3885	if (!ops->datbuf)
3886	ret = nand_do_read_oob(chip, from, ops);
3887	else
3888	ret = nand_do_read_ops(chip, from, ops);
3889
3890	if (ops->stats) {
3891	ops->stats->uncorrectable_errors +=
3892	mtd->ecc_stats.failed - old_stats.failed;
3893	ops->stats->corrected_bitflips +=
3894	mtd->ecc_stats.corrected - old_stats.corrected;
3895	}
3896
3897	nand_release_device(chip);
3898	return ret;
3899	}
3900
3901	/**
3902	* nand_write_page_raw_notsupp - dummy raw page write function
3903	* @chip: nand chip info structure
3904	* @buf: data buffer
3905	* @oob_required: must write chip->oob_poi to OOB
3906	* @page: page number to write
3907	*
3908	* Returns -ENOTSUPP unconditionally.
3909	*/
3910	int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf,
3911	int oob_required, int page)
3912	{
3913	return -ENOTSUPP;
3914	}
3915
3916	/**
3917	* nand_write_page_raw - [INTERN] raw page write function
3918	* @chip: nand chip info structure
3919	* @buf: data buffer
3920	* @oob_required: must write chip->oob_poi to OOB
3921	* @page: page number to write
3922	*
3923	* Not for syndrome calculating ECC controllers, which use a special oob layout.
3924	*/
3925	int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
3926	int oob_required, int page)
3927	{
3928	struct mtd_info *mtd = nand_to_mtd(chip);
3929	int ret;
3930
3931	ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
3932	if (ret)
3933	return ret;
3934
3935	if (oob_required) {
3936	ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
3937	false);
3938	if (ret)
3939	return ret;
3940	}
3941
3942	return nand_prog_page_end_op(chip);
3943	}
3944	EXPORT_SYMBOL(nand_write_page_raw);
3945
3946	/**
3947	* nand_monolithic_write_page_raw - Monolithic page write in raw mode
3948	* @chip: NAND chip info structure
3949	* @buf: data buffer to write
3950	* @oob_required: must write chip->oob_poi to OOB
3951	* @page: page number to write
3952	*
3953	* This is a raw page write, ie. without any error detection/correction.
3954	* Monolithic means we are requesting all the relevant data (main plus
3955	* eventually OOB) to be sent over the bus and effectively programmed
3956	* into the NAND chip arrays in a single operation. This is an
3957	* alternative to nand_write_page_raw(), which first sends the main
3958	* data, then eventually send the OOB data by latching more data
3959	* cycles on the NAND bus, and finally sends the program command to
3960	* synchronyze the NAND chip cache.
3961	*/
3962	int nand_monolithic_write_page_raw(struct nand_chip *chip, const u8 *buf,
3963	int oob_required, int page)
3964	{
3965	struct mtd_info *mtd = nand_to_mtd(chip);
3966	unsigned int size = mtd->writesize;
3967	u8 *write_buf = (u8 *)buf;
3968
3969	if (oob_required) {
3970	size += mtd->oobsize;
3971
3972	if (buf != chip->data_buf) {
3973	write_buf = nand_get_data_buf(chip);
3974	memcpy(write_buf, buf, mtd->writesize);
3975	}
3976	}
3977
3978	return nand_prog_page_op(chip, page, 0, write_buf, size);
3979	}
3980	EXPORT_SYMBOL(nand_monolithic_write_page_raw);
3981
3982	/**
3983	* nand_write_page_raw_syndrome - [INTERN] raw page write function
3984	* @chip: nand chip info structure
3985	* @buf: data buffer
3986	* @oob_required: must write chip->oob_poi to OOB
3987	* @page: page number to write
3988	*
3989	* We need a special oob layout and handling even when ECC isn't checked.
3990	*/
3991	static int nand_write_page_raw_syndrome(struct nand_chip *chip,
3992	const uint8_t *buf, int oob_required,
3993	int page)
3994	{
3995	struct mtd_info *mtd = nand_to_mtd(chip);
3996	int eccsize = chip->ecc.size;
3997	int eccbytes = chip->ecc.bytes;
3998	uint8_t *oob = chip->oob_poi;
3999	int steps, size, ret;
4000
4001	ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4002	if (ret)
4003	return ret;
4004
4005	for (steps = chip->ecc.steps; steps > 0; steps--) {
4006	ret = nand_write_data_op(chip, buf, eccsize, false);
4007	if (ret)
4008	return ret;
4009
4010	buf += eccsize;
4011
4012	if (chip->ecc.prepad) {
4013	ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
4014	false);
4015	if (ret)
4016	return ret;
4017
4018	oob += chip->ecc.prepad;
4019	}
4020
4021	ret = nand_write_data_op(chip, oob, eccbytes, false);
4022	if (ret)
4023	return ret;
4024
4025	oob += eccbytes;
4026
4027	if (chip->ecc.postpad) {
4028	ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
4029	false);
4030	if (ret)
4031	return ret;
4032
4033	oob += chip->ecc.postpad;
4034	}
4035	}
4036
4037	size = mtd->oobsize - (oob - chip->oob_poi);
4038	if (size) {
4039	ret = nand_write_data_op(chip, oob, size, false);
4040	if (ret)
4041	return ret;
4042	}
4043
4044	return nand_prog_page_end_op(chip);
4045	}
4046	/**
4047	* nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
4048	* @chip: nand chip info structure
4049	* @buf: data buffer
4050	* @oob_required: must write chip->oob_poi to OOB
4051	* @page: page number to write
4052	*/
4053	static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf,
4054	int oob_required, int page)
4055	{
4056	struct mtd_info *mtd = nand_to_mtd(chip);
4057	int i, eccsize = chip->ecc.size, ret;
4058	int eccbytes = chip->ecc.bytes;
4059	int eccsteps = chip->ecc.steps;
4060	uint8_t *ecc_calc = chip->ecc.calc_buf;
4061	const uint8_t *p = buf;
4062
4063	/* Software ECC calculation */
4064	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
4065	chip->ecc.calculate(chip, p, &ecc_calc[i]);
4066
4067	ret = mtd_ooblayout_set_eccbytes(mtd, eccbuf: ecc_calc, oobbuf: chip->oob_poi, start: 0,
4068	nbytes: chip->ecc.total);
4069	if (ret)
4070	return ret;
4071
4072	return chip->ecc.write_page_raw(chip, buf, 1, page);
4073	}
4074
4075	/**
4076	* nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
4077	* @chip: nand chip info structure
4078	* @buf: data buffer
4079	* @oob_required: must write chip->oob_poi to OOB
4080	* @page: page number to write
4081	*/
4082	static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,
4083	int oob_required, int page)
4084	{
4085	struct mtd_info *mtd = nand_to_mtd(chip);
4086	int i, eccsize = chip->ecc.size, ret;
4087	int eccbytes = chip->ecc.bytes;
4088	int eccsteps = chip->ecc.steps;
4089	uint8_t *ecc_calc = chip->ecc.calc_buf;
4090	const uint8_t *p = buf;
4091
4092	ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4093	if (ret)
4094	return ret;
4095
4096	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
4097	chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4098
4099	ret = nand_write_data_op(chip, p, eccsize, false);
4100	if (ret)
4101	return ret;
4102
4103	chip->ecc.calculate(chip, p, &ecc_calc[i]);
4104	}
4105
4106	ret = mtd_ooblayout_set_eccbytes(mtd, eccbuf: ecc_calc, oobbuf: chip->oob_poi, start: 0,
4107	nbytes: chip->ecc.total);
4108	if (ret)
4109	return ret;
4110
4111	ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
4112	if (ret)
4113	return ret;
4114
4115	return nand_prog_page_end_op(chip);
4116	}
4117
4118
4119	/**
4120	* nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
4121	* @chip: nand chip info structure
4122	* @offset: column address of subpage within the page
4123	* @data_len: data length
4124	* @buf: data buffer
4125	* @oob_required: must write chip->oob_poi to OOB
4126	* @page: page number to write
4127	*/
4128	static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset,
4129	uint32_t data_len, const uint8_t *buf,
4130	int oob_required, int page)
4131	{
4132	struct mtd_info *mtd = nand_to_mtd(chip);
4133	uint8_t *oob_buf = chip->oob_poi;
4134	uint8_t *ecc_calc = chip->ecc.calc_buf;
4135	int ecc_size = chip->ecc.size;
4136	int ecc_bytes = chip->ecc.bytes;
4137	int ecc_steps = chip->ecc.steps;
4138	uint32_t start_step = offset / ecc_size;
4139	uint32_t end_step = (offset + data_len - 1) / ecc_size;
4140	int oob_bytes = mtd->oobsize / ecc_steps;
4141	int step, ret;
4142
4143	ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4144	if (ret)
4145	return ret;
4146
4147	for (step = 0; step < ecc_steps; step++) {
4148	/* configure controller for WRITE access */
4149	chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4150
4151	/* write data (untouched subpages already masked by 0xFF) */
4152	ret = nand_write_data_op(chip, buf, ecc_size, false);
4153	if (ret)
4154	return ret;
4155
4156	/* mask ECC of un-touched subpages by padding 0xFF */
4157	if ((step < start_step) || (step > end_step))
4158	memset(ecc_calc, 0xff, ecc_bytes);
4159	else
4160	chip->ecc.calculate(chip, buf, ecc_calc);
4161
4162	/* mask OOB of un-touched subpages by padding 0xFF */
4163	/* if oob_required, preserve OOB metadata of written subpage */
4164	if (!oob_required || (step < start_step) || (step > end_step))
4165	memset(oob_buf, 0xff, oob_bytes);
4166
4167	buf += ecc_size;
4168	ecc_calc += ecc_bytes;
4169	oob_buf += oob_bytes;
4170	}
4171
4172	/* copy calculated ECC for whole page to chip->buffer->oob */
4173	/* this include masked-value(0xFF) for unwritten subpages */
4174	ecc_calc = chip->ecc.calc_buf;
4175	ret = mtd_ooblayout_set_eccbytes(mtd, eccbuf: ecc_calc, oobbuf: chip->oob_poi, start: 0,
4176	nbytes: chip->ecc.total);
4177	if (ret)
4178	return ret;
4179
4180	/* write OOB buffer to NAND device */
4181	ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
4182	if (ret)
4183	return ret;
4184
4185	return nand_prog_page_end_op(chip);
4186	}
4187
4188
4189	/**
4190	* nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
4191	* @chip: nand chip info structure
4192	* @buf: data buffer
4193	* @oob_required: must write chip->oob_poi to OOB
4194	* @page: page number to write
4195	*
4196	* The hw generator calculates the error syndrome automatically. Therefore we
4197	* need a special oob layout and handling.
4198	*/
4199	static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf,
4200	int oob_required, int page)
4201	{
4202	struct mtd_info *mtd = nand_to_mtd(chip);
4203	int i, eccsize = chip->ecc.size;
4204	int eccbytes = chip->ecc.bytes;
4205	int eccsteps = chip->ecc.steps;
4206	const uint8_t *p = buf;
4207	uint8_t *oob = chip->oob_poi;
4208	int ret;
4209
4210	ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4211	if (ret)
4212	return ret;
4213
4214	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
4215	chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4216
4217	ret = nand_write_data_op(chip, p, eccsize, false);
4218	if (ret)
4219	return ret;
4220
4221	if (chip->ecc.prepad) {
4222	ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
4223	false);
4224	if (ret)
4225	return ret;
4226
4227	oob += chip->ecc.prepad;
4228	}
4229
4230	chip->ecc.calculate(chip, p, oob);
4231
4232	ret = nand_write_data_op(chip, oob, eccbytes, false);
4233	if (ret)
4234	return ret;
4235
4236	oob += eccbytes;
4237
4238	if (chip->ecc.postpad) {
4239	ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
4240	false);
4241	if (ret)
4242	return ret;
4243
4244	oob += chip->ecc.postpad;
4245	}
4246	}
4247
4248	/* Calculate remaining oob bytes */
4249	i = mtd->oobsize - (oob - chip->oob_poi);
4250	if (i) {
4251	ret = nand_write_data_op(chip, oob, i, false);
4252	if (ret)
4253	return ret;
4254	}
4255
4256	return nand_prog_page_end_op(chip);
4257	}
4258
4259	/**
4260	* nand_write_page - write one page
4261	* @chip: NAND chip descriptor
4262	* @offset: address offset within the page
4263	* @data_len: length of actual data to be written
4264	* @buf: the data to write
4265	* @oob_required: must write chip->oob_poi to OOB
4266	* @page: page number to write
4267	* @raw: use _raw version of write_page
4268	*/
4269	static int nand_write_page(struct nand_chip *chip, uint32_t offset,
4270	int data_len, const uint8_t *buf, int oob_required,
4271	int page, int raw)
4272	{
4273	struct mtd_info *mtd = nand_to_mtd(chip);
4274	int status, subpage;
4275
4276	if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
4277	chip->ecc.write_subpage)
4278	subpage = offset || (data_len < mtd->writesize);
4279	else
4280	subpage = 0;
4281
4282	if (unlikely(raw))
4283	status = chip->ecc.write_page_raw(chip, buf, oob_required,
4284	page);
4285	else if (subpage)
4286	status = chip->ecc.write_subpage(chip, offset, data_len, buf,
4287	oob_required, page);
4288	else
4289	status = chip->ecc.write_page(chip, buf, oob_required, page);
4290
4291	if (status < 0)
4292	return status;
4293
4294	return 0;
4295	}
4296
4297	#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
4298
4299	/**
4300	* nand_do_write_ops - [INTERN] NAND write with ECC
4301	* @chip: NAND chip object
4302	* @to: offset to write to
4303	* @ops: oob operations description structure
4304	*
4305	* NAND write with ECC.
4306	*/
4307	static int nand_do_write_ops(struct nand_chip *chip, loff_t to,
4308	struct mtd_oob_ops *ops)
4309	{
4310	struct mtd_info *mtd = nand_to_mtd(chip);
4311	int chipnr, realpage, page, column;
4312	uint32_t writelen = ops->len;
4313
4314	uint32_t oobwritelen = ops->ooblen;
4315	uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
4316
4317	uint8_t *oob = ops->oobbuf;
4318	uint8_t *buf = ops->datbuf;
4319	int ret;
4320	int oob_required = oob ? 1 : 0;
4321
4322	ops->retlen = 0;
4323	if (!writelen)
4324	return 0;
4325
4326	/* Reject writes, which are not page aligned */
4327	if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
4328	pr_notice("%s: attempt to write non page aligned data\n",
4329	__func__);
4330	return -EINVAL;
4331	}
4332
4333	/* Check if the region is secured */
4334	if (nand_region_is_secured(chip, offset: to, size: writelen))
4335	return -EIO;
4336
4337	column = to & (mtd->writesize - 1);
4338
4339	chipnr = (int)(to >> chip->chip_shift);
4340	nand_select_target(chip, chipnr);
4341
4342	/* Check, if it is write protected */
4343	if (nand_check_wp(chip)) {
4344	ret = -EIO;
4345	goto err_out;
4346	}
4347
4348	realpage = (int)(to >> chip->page_shift);
4349	page = realpage & chip->pagemask;
4350
4351	/* Invalidate the page cache, when we write to the cached page */
4352	if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) &&
4353	((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len))
4354	chip->pagecache.page = -1;
4355
4356	/* Don't allow multipage oob writes with offset */
4357	if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
4358	ret = -EINVAL;
4359	goto err_out;
4360	}
4361
4362	while (1) {
4363	int bytes = mtd->writesize;
4364	uint8_t *wbuf = buf;
4365	int use_bounce_buf;
4366	int part_pagewr = (column || writelen < mtd->writesize);
4367
4368	if (part_pagewr)
4369	use_bounce_buf = 1;
4370	else if (chip->options & NAND_USES_DMA)
4371	use_bounce_buf = !virt_addr_valid(buf) ||
4372	!IS_ALIGNED((unsigned long)buf,
4373	chip->buf_align);
4374	else
4375	use_bounce_buf = 0;
4376
4377	/*
4378	* Copy the data from the initial buffer when doing partial page
4379	* writes or when a bounce buffer is required.
4380	*/
4381	if (use_bounce_buf) {
4382	pr_debug("%s: using write bounce buffer for buf@%p\n",
4383	__func__, buf);
4384	if (part_pagewr)
4385	bytes = min_t(int, bytes - column, writelen);
4386	wbuf = nand_get_data_buf(chip);
4387	memset(wbuf, 0xff, mtd->writesize);
4388	memcpy(&wbuf[column], buf, bytes);
4389	}
4390
4391	if (unlikely(oob)) {
4392	size_t len = min(oobwritelen, oobmaxlen);
4393	oob = nand_fill_oob(chip, oob, len, ops);
4394	oobwritelen -= len;
4395	} else {
4396	/* We still need to erase leftover OOB data */
4397	memset(chip->oob_poi, 0xff, mtd->oobsize);
4398	}
4399
4400	ret = nand_write_page(chip, offset: column, data_len: bytes, buf: wbuf,
4401	oob_required, page,
4402	raw: (ops->mode == MTD_OPS_RAW));
4403	if (ret)
4404	break;
4405
4406	writelen -= bytes;
4407	if (!writelen)
4408	break;
4409
4410	column = 0;
4411	buf += bytes;
4412	realpage++;
4413
4414	page = realpage & chip->pagemask;
4415	/* Check, if we cross a chip boundary */
4416	if (!page) {
4417	chipnr++;
4418	nand_deselect_target(chip);
4419	nand_select_target(chip, chipnr);
4420	}
4421	}
4422
4423	ops->retlen = ops->len - writelen;
4424	if (unlikely(oob))
4425	ops->oobretlen = ops->ooblen;
4426
4427	err_out:
4428	nand_deselect_target(chip);
4429	return ret;
4430	}
4431
4432	/**
4433	* panic_nand_write - [MTD Interface] NAND write with ECC
4434	* @mtd: MTD device structure
4435	* @to: offset to write to
4436	* @len: number of bytes to write
4437	* @retlen: pointer to variable to store the number of written bytes
4438	* @buf: the data to write
4439	*
4440	* NAND write with ECC. Used when performing writes in interrupt context, this
4441	* may for example be called by mtdoops when writing an oops while in panic.
4442	*/
4443	static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
4444	size_t *retlen, const uint8_t *buf)
4445	{
4446	struct nand_chip *chip = mtd_to_nand(mtd);
4447	int chipnr = (int)(to >> chip->chip_shift);
4448	struct mtd_oob_ops ops;
4449	int ret;
4450
4451	nand_select_target(chip, chipnr);
4452
4453	/* Wait for the device to get ready */
4454	panic_nand_wait(chip, timeo: 400);
4455
4456	memset(&ops, 0, sizeof(ops));
4457	ops.len = len;
4458	ops.datbuf = (uint8_t *)buf;
4459	ops.mode = MTD_OPS_PLACE_OOB;
4460
4461	ret = nand_do_write_ops(chip, to, ops: &ops);
4462
4463	*retlen = ops.retlen;
4464	return ret;
4465	}
4466
4467	/**
4468	* nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
4469	* @mtd: MTD device structure
4470	* @to: offset to write to
4471	* @ops: oob operation description structure
4472	*/
4473	static int nand_write_oob(struct mtd_info *mtd, loff_t to,
4474	struct mtd_oob_ops *ops)
4475	{
4476	struct nand_chip *chip = mtd_to_nand(mtd);
4477	int ret = 0;
4478
4479	ops->retlen = 0;
4480
4481	nand_get_device(chip);
4482
4483	switch (ops->mode) {
4484	case MTD_OPS_PLACE_OOB:
4485	case MTD_OPS_AUTO_OOB:
4486	case MTD_OPS_RAW:
4487	break;
4488
4489	default:
4490	goto out;
4491	}
4492
4493	if (!ops->datbuf)
4494	ret = nand_do_write_oob(chip, to, ops);
4495	else
4496	ret = nand_do_write_ops(chip, to, ops);
4497
4498	out:
4499	nand_release_device(chip);
4500	return ret;
4501	}
4502
4503	/**
4504	* nand_erase - [MTD Interface] erase block(s)
4505	* @mtd: MTD device structure
4506	* @instr: erase instruction
4507	*
4508	* Erase one ore more blocks.
4509	*/
4510	static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
4511	{
4512	return nand_erase_nand(chip: mtd_to_nand(mtd), instr, allowbbt: 0);
4513	}
4514
4515	/**
4516	* nand_erase_nand - [INTERN] erase block(s)
4517	* @chip: NAND chip object
4518	* @instr: erase instruction
4519	* @allowbbt: allow erasing the bbt area
4520	*
4521	* Erase one ore more blocks.
4522	*/
4523	int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
4524	int allowbbt)
4525	{
4526	int page, pages_per_block, ret, chipnr;
4527	loff_t len;
4528
4529	pr_debug("%s: start = 0x%012llx, len = %llu\n",
4530	__func__, (unsigned long long)instr->addr,
4531	(unsigned long long)instr->len);
4532
4533	if (check_offs_len(chip, ofs: instr->addr, len: instr->len))
4534	return -EINVAL;
4535
4536	/* Check if the region is secured */
4537	if (nand_region_is_secured(chip, offset: instr->addr, size: instr->len))
4538	return -EIO;
4539
4540	/* Grab the lock and see if the device is available */
4541	nand_get_device(chip);
4542
4543	/* Shift to get first page */
4544	page = (int)(instr->addr >> chip->page_shift);
4545	chipnr = (int)(instr->addr >> chip->chip_shift);
4546
4547	/* Calculate pages in each block */
4548	pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
4549
4550	/* Select the NAND device */
4551	nand_select_target(chip, chipnr);
4552
4553	/* Check, if it is write protected */
4554	if (nand_check_wp(chip)) {
4555	pr_debug("%s: device is write protected!\n",
4556	__func__);
4557	ret = -EIO;
4558	goto erase_exit;
4559	}
4560
4561	/* Loop through the pages */
4562	len = instr->len;
4563
4564	while (len) {
4565	loff_t ofs = (loff_t)page << chip->page_shift;
4566
4567	/* Check if we have a bad block, we do not erase bad blocks! */
4568	if (nand_block_checkbad(chip, ofs: ((loff_t) page) <<
4569	chip->page_shift, allowbbt)) {
4570	pr_warn("%s: attempt to erase a bad block at 0x%08llx\n",
4571	__func__, (unsigned long long)ofs);
4572	ret = -EIO;
4573	goto erase_exit;
4574	}
4575
4576	/*
4577	* Invalidate the page cache, if we erase the block which
4578	* contains the current cached page.
4579	*/
4580	if (page <= chip->pagecache.page && chip->pagecache.page <
4581	(page + pages_per_block))
4582	chip->pagecache.page = -1;
4583
4584	ret = nand_erase_op(chip, (page & chip->pagemask) >>
4585	(chip->phys_erase_shift - chip->page_shift));
4586	if (ret) {
4587	pr_debug("%s: failed erase, page 0x%08x\n",
4588	__func__, page);
4589	instr->fail_addr = ofs;
4590	goto erase_exit;
4591	}
4592
4593	/* Increment page address and decrement length */
4594	len -= (1ULL << chip->phys_erase_shift);
4595	page += pages_per_block;
4596
4597	/* Check, if we cross a chip boundary */
4598	if (len && !(page & chip->pagemask)) {
4599	chipnr++;
4600	nand_deselect_target(chip);
4601	nand_select_target(chip, chipnr);
4602	}
4603	}
4604
4605	ret = 0;
4606	erase_exit:
4607
4608	/* Deselect and wake up anyone waiting on the device */
4609	nand_deselect_target(chip);
4610	nand_release_device(chip);
4611
4612	/* Return more or less happy */
4613	return ret;
4614	}
4615
4616	/**
4617	* nand_sync - [MTD Interface] sync
4618	* @mtd: MTD device structure
4619	*
4620	* Sync is actually a wait for chip ready function.
4621	*/
4622	static void nand_sync(struct mtd_info *mtd)
4623	{
4624	struct nand_chip *chip = mtd_to_nand(mtd);
4625
4626	pr_debug("%s: called\n", __func__);
4627
4628	/* Grab the lock and see if the device is available */
4629	nand_get_device(chip);
4630	/* Release it and go back */
4631	nand_release_device(chip);
4632	}
4633
4634	/**
4635	* nand_block_isbad - [MTD Interface] Check if block at offset is bad
4636	* @mtd: MTD device structure
4637	* @offs: offset relative to mtd start
4638	*/
4639	static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
4640	{
4641	struct nand_chip *chip = mtd_to_nand(mtd);
4642	int chipnr = (int)(offs >> chip->chip_shift);
4643	int ret;
4644
4645	/* Select the NAND device */
4646	nand_get_device(chip);
4647
4648	nand_select_target(chip, chipnr);
4649
4650	ret = nand_block_checkbad(chip, ofs: offs, allowbbt: 0);
4651
4652	nand_deselect_target(chip);
4653	nand_release_device(chip);
4654
4655	return ret;
4656	}
4657
4658	/**
4659	* nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
4660	* @mtd: MTD device structure
4661	* @ofs: offset relative to mtd start
4662	*/
4663	static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
4664	{
4665	int ret;
4666
4667	ret = nand_block_isbad(mtd, offs: ofs);
4668	if (ret) {
4669	/* If it was bad already, return success and do nothing */
4670	if (ret > 0)
4671	return 0;
4672	return ret;
4673	}
4674
4675	return nand_block_markbad_lowlevel(chip: mtd_to_nand(mtd), ofs);
4676	}
4677
4678	/**
4679	* nand_suspend - [MTD Interface] Suspend the NAND flash
4680	* @mtd: MTD device structure
4681	*
4682	* Returns 0 for success or negative error code otherwise.
4683	*/
4684	static int nand_suspend(struct mtd_info *mtd)
4685	{
4686	struct nand_chip *chip = mtd_to_nand(mtd);
4687	int ret = 0;
4688
4689	mutex_lock(&chip->lock);
4690	if (chip->ops.suspend)
4691	ret = chip->ops.suspend(chip);
4692	if (!ret)
4693	chip->suspended = 1;
4694	mutex_unlock(lock: &chip->lock);
4695
4696	return ret;
4697	}
4698
4699	/**
4700	* nand_resume - [MTD Interface] Resume the NAND flash
4701	* @mtd: MTD device structure
4702	*/
4703	static void nand_resume(struct mtd_info *mtd)
4704	{
4705	struct nand_chip *chip = mtd_to_nand(mtd);
4706
4707	mutex_lock(&chip->lock);
4708	if (chip->suspended) {
4709	if (chip->ops.resume)
4710	chip->ops.resume(chip);
4711	chip->suspended = 0;
4712	} else {
4713	pr_err("%s called for a chip which is not in suspended state\n",
4714	__func__);
4715	}
4716	mutex_unlock(lock: &chip->lock);
4717
4718	wake_up_all(&chip->resume_wq);
4719	}
4720
4721	/**
4722	* nand_shutdown - [MTD Interface] Finish the current NAND operation and
4723	* prevent further operations
4724	* @mtd: MTD device structure
4725	*/
4726	static void nand_shutdown(struct mtd_info *mtd)
4727	{
4728	nand_suspend(mtd);
4729	}
4730
4731	/**
4732	* nand_lock - [MTD Interface] Lock the NAND flash
4733	* @mtd: MTD device structure
4734	* @ofs: offset byte address
4735	* @len: number of bytes to lock (must be a multiple of block/page size)
4736	*/
4737	static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
4738	{
4739	struct nand_chip *chip = mtd_to_nand(mtd);
4740
4741	if (!chip->ops.lock_area)
4742	return -ENOTSUPP;
4743
4744	return chip->ops.lock_area(chip, ofs, len);
4745	}
4746
4747	/**
4748	* nand_unlock - [MTD Interface] Unlock the NAND flash
4749	* @mtd: MTD device structure
4750	* @ofs: offset byte address
4751	* @len: number of bytes to unlock (must be a multiple of block/page size)
4752	*/
4753	static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
4754	{
4755	struct nand_chip *chip = mtd_to_nand(mtd);
4756
4757	if (!chip->ops.unlock_area)
4758	return -ENOTSUPP;
4759
4760	return chip->ops.unlock_area(chip, ofs, len);
4761	}
4762
4763	/* Set default functions */
4764	static void nand_set_defaults(struct nand_chip *chip)
4765	{
4766	/* If no controller is provided, use the dummy, legacy one. */
4767	if (!chip->controller) {
4768	chip->controller = &chip->legacy.dummy_controller;
4769	nand_controller_init(nfc: chip->controller);
4770	}
4771
4772	nand_legacy_set_defaults(chip);
4773
4774	if (!chip->buf_align)
4775	chip->buf_align = 1;
4776	}
4777
4778	/* Sanitize ONFI strings so we can safely print them */
4779	void sanitize_string(uint8_t *s, size_t len)
4780	{
4781	ssize_t i;
4782
4783	/* Null terminate */
4784	s[len - 1] = 0;
4785
4786	/* Remove non printable chars */
4787	for (i = 0; i < len - 1; i++) {
4788	if (s[i] < ' ' || s[i] > 127)
4789	s[i] = '?';
4790	}
4791
4792	/* Remove trailing spaces */
4793	strim(s);
4794	}
4795
4796	/*
4797	* nand_id_has_period - Check if an ID string has a given wraparound period
4798	* @id_data: the ID string
4799	* @arrlen: the length of the @id_data array
4800	* @period: the period of repitition
4801	*
4802	* Check if an ID string is repeated within a given sequence of bytes at
4803	* specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
4804	* period of 3). This is a helper function for nand_id_len(). Returns non-zero
4805	* if the repetition has a period of @period; otherwise, returns zero.
4806	*/
4807	static int nand_id_has_period(u8 *id_data, int arrlen, int period)
4808	{
4809	int i, j;
4810	for (i = 0; i < period; i++)
4811	for (j = i + period; j < arrlen; j += period)
4812	if (id_data[i] != id_data[j])
4813	return 0;
4814	return 1;
4815	}
4816
4817	/*
4818	* nand_id_len - Get the length of an ID string returned by CMD_READID
4819	* @id_data: the ID string
4820	* @arrlen: the length of the @id_data array
4821
4822	* Returns the length of the ID string, according to known wraparound/trailing
4823	* zero patterns. If no pattern exists, returns the length of the array.
4824	*/
4825	static int nand_id_len(u8 *id_data, int arrlen)
4826	{
4827	int last_nonzero, period;
4828
4829	/* Find last non-zero byte */
4830	for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
4831	if (id_data[last_nonzero])
4832	break;
4833
4834	/* All zeros */
4835	if (last_nonzero < 0)
4836	return 0;
4837
4838	/* Calculate wraparound period */
4839	for (period = 1; period < arrlen; period++)
4840	if (nand_id_has_period(id_data, arrlen, period))
4841	break;
4842
4843	/* There's a repeated pattern */
4844	if (period < arrlen)
4845	return period;
4846
4847	/* There are trailing zeros */
4848	if (last_nonzero < arrlen - 1)
4849	return last_nonzero + 1;
4850
4851	/* No pattern detected */
4852	return arrlen;
4853	}
4854
4855	/* Extract the bits of per cell from the 3rd byte of the extended ID */
4856	static int nand_get_bits_per_cell(u8 cellinfo)
4857	{
4858	int bits;
4859
4860	bits = cellinfo & NAND_CI_CELLTYPE_MSK;
4861	bits >>= NAND_CI_CELLTYPE_SHIFT;
4862	return bits + 1;
4863	}
4864
4865	/*
4866	* Many new NAND share similar device ID codes, which represent the size of the
4867	* chip. The rest of the parameters must be decoded according to generic or
4868	* manufacturer-specific "extended ID" decoding patterns.
4869	*/
4870	void nand_decode_ext_id(struct nand_chip *chip)
4871	{
4872	struct nand_memory_organization *memorg;
4873	struct mtd_info *mtd = nand_to_mtd(chip);
4874	int extid;
4875	u8 *id_data = chip->id.data;
4876
4877	memorg = nanddev_get_memorg(nand: &chip->base);
4878
4879	/* The 3rd id byte holds MLC / multichip data */
4880	memorg->bits_per_cell = nand_get_bits_per_cell(cellinfo: id_data[2]);
4881	/* The 4th id byte is the important one */
4882	extid = id_data[3];
4883
4884	/* Calc pagesize */
4885	memorg->pagesize = 1024 << (extid & 0x03);
4886	mtd->writesize = memorg->pagesize;
4887	extid >>= 2;
4888	/* Calc oobsize */
4889	memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
4890	mtd->oobsize = memorg->oobsize;
4891	extid >>= 2;
4892	/* Calc blocksize. Blocksize is multiples of 64KiB */
4893	memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) /
4894	memorg->pagesize;
4895	mtd->erasesize = (64 * 1024) << (extid & 0x03);
4896	extid >>= 2;
4897	/* Get buswidth information */
4898	if (extid & 0x1)
4899	chip->options |= NAND_BUSWIDTH_16;
4900	}
4901	EXPORT_SYMBOL_GPL(nand_decode_ext_id);
4902
4903	/*
4904	* Old devices have chip data hardcoded in the device ID table. nand_decode_id
4905	* decodes a matching ID table entry and assigns the MTD size parameters for
4906	* the chip.
4907	*/
4908	static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
4909	{
4910	struct mtd_info *mtd = nand_to_mtd(chip);
4911	struct nand_memory_organization *memorg;
4912
4913	memorg = nanddev_get_memorg(nand: &chip->base);
4914
4915	memorg->pages_per_eraseblock = type->erasesize / type->pagesize;
4916	mtd->erasesize = type->erasesize;
4917	memorg->pagesize = type->pagesize;
4918	mtd->writesize = memorg->pagesize;
4919	memorg->oobsize = memorg->pagesize / 32;
4920	mtd->oobsize = memorg->oobsize;
4921
4922	/* All legacy ID NAND are small-page, SLC */
4923	memorg->bits_per_cell = 1;
4924	}
4925
4926	/*
4927	* Set the bad block marker/indicator (BBM/BBI) patterns according to some
4928	* heuristic patterns using various detected parameters (e.g., manufacturer,
4929	* page size, cell-type information).
4930	*/
4931	static void nand_decode_bbm_options(struct nand_chip *chip)
4932	{
4933	struct mtd_info *mtd = nand_to_mtd(chip);
4934
4935	/* Set the bad block position */
4936	if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
4937	chip->badblockpos = NAND_BBM_POS_LARGE;
4938	else
4939	chip->badblockpos = NAND_BBM_POS_SMALL;
4940	}
4941
4942	static inline bool is_full_id_nand(struct nand_flash_dev *type)
4943	{
4944	return type->id_len;
4945	}
4946
4947	static bool find_full_id_nand(struct nand_chip *chip,
4948	struct nand_flash_dev *type)
4949	{
4950	struct nand_device *base = &chip->base;
4951	struct nand_ecc_props requirements;
4952	struct mtd_info *mtd = nand_to_mtd(chip);
4953	struct nand_memory_organization *memorg;
4954	u8 *id_data = chip->id.data;
4955
4956	memorg = nanddev_get_memorg(nand: &chip->base);
4957
4958	if (!strncmp(type->id, id_data, type->id_len)) {
4959	memorg->pagesize = type->pagesize;
4960	mtd->writesize = memorg->pagesize;
4961	memorg->pages_per_eraseblock = type->erasesize /
4962	type->pagesize;
4963	mtd->erasesize = type->erasesize;
4964	memorg->oobsize = type->oobsize;
4965	mtd->oobsize = memorg->oobsize;
4966
4967	memorg->bits_per_cell = nand_get_bits_per_cell(cellinfo: id_data[2]);
4968	memorg->eraseblocks_per_lun =
4969	DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
4970	memorg->pagesize *
4971	memorg->pages_per_eraseblock);
4972	chip->options |= type->options;
4973	requirements.strength = NAND_ECC_STRENGTH(type);
4974	requirements.step_size = NAND_ECC_STEP(type);
4975	nanddev_set_ecc_requirements(nand: base, reqs: &requirements);
4976
4977	chip->parameters.model = kstrdup(s: type->name, GFP_KERNEL);
4978	if (!chip->parameters.model)
4979	return false;
4980
4981	return true;
4982	}
4983	return false;
4984	}
4985
4986	/*
4987	* Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
4988	* compliant and does not have a full-id or legacy-id entry in the nand_ids
4989	* table.
4990	*/
4991	static void nand_manufacturer_detect(struct nand_chip *chip)
4992	{
4993	/*
4994	* Try manufacturer detection if available and use
4995	* nand_decode_ext_id() otherwise.
4996	*/
4997	if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
4998	chip->manufacturer.desc->ops->detect) {
4999	struct nand_memory_organization *memorg;
5000
5001	memorg = nanddev_get_memorg(nand: &chip->base);
5002
5003	/* The 3rd id byte holds MLC / multichip data */
5004	memorg->bits_per_cell = nand_get_bits_per_cell(cellinfo: chip->id.data[2]);
5005	chip->manufacturer.desc->ops->detect(chip);
5006	} else {
5007	nand_decode_ext_id(chip);
5008	}
5009	}
5010
5011	/*
5012	* Manufacturer initialization. This function is called for all NANDs including
5013	* ONFI and JEDEC compliant ones.
5014	* Manufacturer drivers should put all their specific initialization code in
5015	* their ->init() hook.
5016	*/
5017	static int nand_manufacturer_init(struct nand_chip *chip)
5018	{
5019	if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||
5020	!chip->manufacturer.desc->ops->init)
5021	return 0;
5022
5023	return chip->manufacturer.desc->ops->init(chip);
5024	}
5025
5026	/*
5027	* Manufacturer cleanup. This function is called for all NANDs including
5028	* ONFI and JEDEC compliant ones.
5029	* Manufacturer drivers should put all their specific cleanup code in their
5030	* ->cleanup() hook.
5031	*/
5032	static void nand_manufacturer_cleanup(struct nand_chip *chip)
5033	{
5034	/* Release manufacturer private data */
5035	if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
5036	chip->manufacturer.desc->ops->cleanup)
5037	chip->manufacturer.desc->ops->cleanup(chip);
5038	}
5039
5040	static const char *
5041	nand_manufacturer_name(const struct nand_manufacturer_desc *manufacturer_desc)
5042	{
5043	return manufacturer_desc ? manufacturer_desc->name : "Unknown";
5044	}
5045
5046	static void rawnand_check_data_only_read_support(struct nand_chip *chip)
5047	{
5048	/* Use an arbitrary size for the check */
5049	if (!nand_read_data_op(chip, NULL, SZ_512, true, true))
5050	chip->controller->supported_op.data_only_read = 1;
5051	}
5052
5053	static void rawnand_early_check_supported_ops(struct nand_chip *chip)
5054	{
5055	/* The supported_op fields should not be set by individual drivers */
5056	WARN_ON_ONCE(chip->controller->supported_op.data_only_read);
5057
5058	if (!nand_has_exec_op(chip))
5059	return;
5060
5061	rawnand_check_data_only_read_support(chip);
5062	}
5063
5064	static void rawnand_check_cont_read_support(struct nand_chip *chip)
5065	{
5066	struct mtd_info *mtd = nand_to_mtd(chip);
5067
5068	if (!chip->parameters.supports_read_cache)
5069	return;
5070
5071	if (chip->read_retries)
5072	return;
5073
5074	if (!nand_lp_exec_cont_read_page_op(chip, page: 0, offset_in_page: 0, NULL,
5075	len: mtd->writesize, check_only: true))
5076	chip->controller->supported_op.cont_read = 1;
5077	}
5078
5079	static void rawnand_late_check_supported_ops(struct nand_chip *chip)
5080	{
5081	/* The supported_op fields should not be set by individual drivers */
5082	WARN_ON_ONCE(chip->controller->supported_op.cont_read);
5083
5084	/*
5085	* Too many devices do not support sequential cached reads with on-die
5086	* ECC correction enabled, so in this case refuse to perform the
5087	* automation.
5088	*/
5089	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE)
5090	return;
5091
5092	if (!nand_has_exec_op(chip))
5093	return;
5094
5095	/*
5096	* For now, continuous reads can only be used with the core page helpers.
5097	* This can be extended later.
5098	*/
5099	if (!(chip->ecc.read_page == nand_read_page_hwecc ||
5100	chip->ecc.read_page == nand_read_page_syndrome ||
5101	chip->ecc.read_page == nand_read_page_swecc))
5102	return;
5103
5104	rawnand_check_cont_read_support(chip);
5105	}
5106
5107	/*
5108	* Get the flash and manufacturer id and lookup if the type is supported.
5109	*/
5110	static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
5111	{
5112	const struct nand_manufacturer_desc *manufacturer_desc;
5113	struct mtd_info *mtd = nand_to_mtd(chip);
5114	struct nand_memory_organization *memorg;
5115	int busw, ret;
5116	u8 *id_data = chip->id.data;
5117	u8 maf_id, dev_id;
5118	u64 targetsize;
5119
5120	/*
5121	* Let's start by initializing memorg fields that might be left
5122	* unassigned by the ID-based detection logic.
5123	*/
5124	memorg = nanddev_get_memorg(nand: &chip->base);
5125	memorg->planes_per_lun = 1;
5126	memorg->luns_per_target = 1;
5127
5128	/*
5129	* Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
5130	* after power-up.
5131	*/
5132	ret = nand_reset(chip, 0);
5133	if (ret)
5134	return ret;
5135
5136	/* Select the device */
5137	nand_select_target(chip, 0);
5138
5139	rawnand_early_check_supported_ops(chip);
5140
5141	/* Send the command for reading device ID */
5142	ret = nand_readid_op(chip, 0, id_data, 2);
5143	if (ret)
5144	return ret;
5145
5146	/* Read manufacturer and device IDs */
5147	maf_id = id_data[0];
5148	dev_id = id_data[1];
5149
5150	/*
5151	* Try again to make sure, as some systems the bus-hold or other
5152	* interface concerns can cause random data which looks like a
5153	* possibly credible NAND flash to appear. If the two results do
5154	* not match, ignore the device completely.
5155	*/
5156
5157	/* Read entire ID string */
5158	ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data));
5159	if (ret)
5160	return ret;
5161
5162	if (id_data[0] != maf_id || id_data[1] != dev_id) {
5163	pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
5164	maf_id, dev_id, id_data[0], id_data[1]);
5165	return -ENODEV;
5166	}
5167
5168	chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
5169
5170	/* Try to identify manufacturer */
5171	manufacturer_desc = nand_get_manufacturer_desc(id: maf_id);
5172	chip->manufacturer.desc = manufacturer_desc;
5173
5174	if (!type)
5175	type = nand_flash_ids;
5176
5177	/*
5178	* Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic
5179	* override it.
5180	* This is required to make sure initial NAND bus width set by the
5181	* NAND controller driver is coherent with the real NAND bus width
5182	* (extracted by auto-detection code).
5183	*/
5184	busw = chip->options & NAND_BUSWIDTH_16;
5185
5186	/*
5187	* The flag is only set (never cleared), reset it to its default value
5188	* before starting auto-detection.
5189	*/
5190	chip->options &= ~NAND_BUSWIDTH_16;
5191
5192	for (; type->name != NULL; type++) {
5193	if (is_full_id_nand(type)) {
5194	if (find_full_id_nand(chip, type))
5195	goto ident_done;
5196	} else if (dev_id == type->dev_id) {
5197	break;
5198	}
5199	}
5200
5201	if (!type->name || !type->pagesize) {
5202	/* Check if the chip is ONFI compliant */
5203	ret = nand_onfi_detect(chip);
5204	if (ret < 0)
5205	return ret;
5206	else if (ret)
5207	goto ident_done;
5208
5209	/* Check if the chip is JEDEC compliant */
5210	ret = nand_jedec_detect(chip);
5211	if (ret < 0)
5212	return ret;
5213	else if (ret)
5214	goto ident_done;
5215	}
5216
5217	if (!type->name)
5218	return -ENODEV;
5219
5220	chip->parameters.model = kstrdup(s: type->name, GFP_KERNEL);
5221	if (!chip->parameters.model)
5222	return -ENOMEM;
5223
5224	if (!type->pagesize)
5225	nand_manufacturer_detect(chip);
5226	else
5227	nand_decode_id(chip, type);
5228
5229	/* Get chip options */
5230	chip->options |= type->options;
5231
5232	memorg->eraseblocks_per_lun =
5233	DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
5234	memorg->pagesize *
5235	memorg->pages_per_eraseblock);
5236
5237	ident_done:
5238	if (!mtd->name)
5239	mtd->name = chip->parameters.model;
5240
5241	if (chip->options & NAND_BUSWIDTH_AUTO) {
5242	WARN_ON(busw & NAND_BUSWIDTH_16);
5243	nand_set_defaults(chip);
5244	} else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
5245	/*
5246	* Check, if buswidth is correct. Hardware drivers should set
5247	* chip correct!
5248	*/
5249	pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
5250	maf_id, dev_id);
5251	pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),
5252	mtd->name);
5253	pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,
5254	(chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
5255	ret = -EINVAL;
5256
5257	goto free_detect_allocation;
5258	}
5259
5260	nand_decode_bbm_options(chip);
5261
5262	/* Calculate the address shift from the page size */
5263	chip->page_shift = ffs(mtd->writesize) - 1;
5264	/* Convert chipsize to number of pages per chip -1 */
5265	targetsize = nanddev_target_size(nand: &chip->base);
5266	chip->pagemask = (targetsize >> chip->page_shift) - 1;
5267
5268	chip->bbt_erase_shift = chip->phys_erase_shift =
5269	ffs(mtd->erasesize) - 1;
5270	if (targetsize & 0xffffffff)
5271	chip->chip_shift = ffs((unsigned)targetsize) - 1;
5272	else {
5273	chip->chip_shift = ffs((unsigned)(targetsize >> 32));
5274	chip->chip_shift += 32 - 1;
5275	}
5276
5277	if (chip->chip_shift - chip->page_shift > 16)
5278	chip->options |= NAND_ROW_ADDR_3;
5279
5280	chip->badblockbits = 8;
5281
5282	nand_legacy_adjust_cmdfunc(chip);
5283
5284	pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
5285	maf_id, dev_id);
5286	pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),
5287	chip->parameters.model);
5288	pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
5289	(int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
5290	mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
5291	return 0;
5292
5293	free_detect_allocation:
5294	kfree(objp: chip->parameters.model);
5295
5296	return ret;
5297	}
5298
5299	static enum nand_ecc_engine_type
5300	of_get_rawnand_ecc_engine_type_legacy(struct device_node *np)
5301	{
5302	enum nand_ecc_legacy_mode {
5303	NAND_ECC_INVALID,
5304	NAND_ECC_NONE,
5305	NAND_ECC_SOFT,
5306	NAND_ECC_SOFT_BCH,
5307	NAND_ECC_HW,
5308	NAND_ECC_HW_SYNDROME,
5309	NAND_ECC_ON_DIE,
5310	};
5311	const char * const nand_ecc_legacy_modes[] = {
5312	[NAND_ECC_NONE] = "none",
5313	[NAND_ECC_SOFT] = "soft",
5314	[NAND_ECC_SOFT_BCH] = "soft_bch",
5315	[NAND_ECC_HW] = "hw",
5316	[NAND_ECC_HW_SYNDROME] = "hw_syndrome",
5317	[NAND_ECC_ON_DIE] = "on-die",
5318	};
5319	enum nand_ecc_legacy_mode eng_type;
5320	const char *pm;
5321	int err;
5322
5323	err = of_property_read_string(np, propname: "nand-ecc-mode", out_string: &pm);
5324	if (err)
5325	return NAND_ECC_ENGINE_TYPE_INVALID;
5326
5327	for (eng_type = NAND_ECC_NONE;
5328	eng_type < ARRAY_SIZE(nand_ecc_legacy_modes); eng_type++) {
5329	if (!strcasecmp(s1: pm, s2: nand_ecc_legacy_modes[eng_type])) {
5330	switch (eng_type) {
5331	case NAND_ECC_NONE:
5332	return NAND_ECC_ENGINE_TYPE_NONE;
5333	case NAND_ECC_SOFT:
5334	case NAND_ECC_SOFT_BCH:
5335	return NAND_ECC_ENGINE_TYPE_SOFT;
5336	case NAND_ECC_HW:
5337	case NAND_ECC_HW_SYNDROME:
5338	return NAND_ECC_ENGINE_TYPE_ON_HOST;
5339	case NAND_ECC_ON_DIE:
5340	return NAND_ECC_ENGINE_TYPE_ON_DIE;
5341	default:
5342	break;
5343	}
5344	}
5345	}
5346
5347	return NAND_ECC_ENGINE_TYPE_INVALID;
5348	}
5349
5350	static enum nand_ecc_placement
5351	of_get_rawnand_ecc_placement_legacy(struct device_node *np)
5352	{
5353	const char *pm;
5354	int err;
5355
5356	err = of_property_read_string(np, propname: "nand-ecc-mode", out_string: &pm);
5357	if (!err) {
5358	if (!strcasecmp(s1: pm, s2: "hw_syndrome"))
5359	return NAND_ECC_PLACEMENT_INTERLEAVED;
5360	}
5361
5362	return NAND_ECC_PLACEMENT_UNKNOWN;
5363	}
5364
5365	static enum nand_ecc_algo of_get_rawnand_ecc_algo_legacy(struct device_node *np)
5366	{
5367	const char *pm;
5368	int err;
5369
5370	err = of_property_read_string(np, propname: "nand-ecc-mode", out_string: &pm);
5371	if (!err) {
5372	if (!strcasecmp(s1: pm, s2: "soft"))
5373	return NAND_ECC_ALGO_HAMMING;
5374	else if (!strcasecmp(s1: pm, s2: "soft_bch"))
5375	return NAND_ECC_ALGO_BCH;
5376	}
5377
5378	return NAND_ECC_ALGO_UNKNOWN;
5379	}
5380
5381	static void of_get_nand_ecc_legacy_user_config(struct nand_chip *chip)
5382	{
5383	struct device_node *dn = nand_get_flash_node(chip);
5384	struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf;
5385
5386	if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
5387	user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(np: dn);
5388
5389	if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN)
5390	user_conf->algo = of_get_rawnand_ecc_algo_legacy(np: dn);
5391
5392	if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN)
5393	user_conf->placement = of_get_rawnand_ecc_placement_legacy(np: dn);
5394	}
5395
5396	static int of_get_nand_bus_width(struct nand_chip *chip)
5397	{
5398	struct device_node *dn = nand_get_flash_node(chip);
5399	u32 val;
5400	int ret;
5401
5402	ret = of_property_read_u32(np: dn, propname: "nand-bus-width", out_value: &val);
5403	if (ret == -EINVAL)
5404	/* Buswidth defaults to 8 if the property does not exist .*/
5405	return 0;
5406	else if (ret)
5407	return ret;
5408
5409	if (val == 16)
5410	chip->options |= NAND_BUSWIDTH_16;
5411	else if (val != 8)
5412	return -EINVAL;
5413	return 0;
5414	}
5415
5416	static int of_get_nand_secure_regions(struct nand_chip *chip)
5417	{
5418	struct device_node *dn = nand_get_flash_node(chip);
5419	struct property *prop;
5420	int nr_elem, i, j;
5421
5422	/* Only proceed if the "secure-regions" property is present in DT */
5423	prop = of_find_property(np: dn, name: "secure-regions", NULL);
5424	if (!prop)
5425	return 0;
5426
5427	nr_elem = of_property_count_elems_of_size(np: dn, propname: "secure-regions", elem_size: sizeof(u64));
5428	if (nr_elem <= 0)
5429	return nr_elem;
5430
5431	chip->nr_secure_regions = nr_elem / 2;
5432	chip->secure_regions = kcalloc(chip->nr_secure_regions, sizeof(*chip->secure_regions),
5433	GFP_KERNEL);
5434	if (!chip->secure_regions)
5435	return -ENOMEM;
5436
5437	for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) {
5438	of_property_read_u64_index(np: dn, propname: "secure-regions", index: j,
5439	out_value: &chip->secure_regions[i].offset);
5440	of_property_read_u64_index(np: dn, propname: "secure-regions", index: j + 1,
5441	out_value: &chip->secure_regions[i].size);
5442	}
5443
5444	return 0;
5445	}
5446
5447	/**
5448	* rawnand_dt_parse_gpio_cs - Parse the gpio-cs property of a controller
5449	* @dev: Device that will be parsed. Also used for managed allocations.
5450	* @cs_array: Array of GPIO desc pointers allocated on success
5451	* @ncs_array: Number of entries in @cs_array updated on success.
5452	* @return 0 on success, an error otherwise.
5453	*/
5454	int rawnand_dt_parse_gpio_cs(struct device *dev, struct gpio_desc ***cs_array,
5455	unsigned int *ncs_array)
5456	{
5457	struct gpio_desc **descs;
5458	int ndescs, i;
5459
5460	ndescs = gpiod_count(dev, con_id: "cs");
5461	if (ndescs < 0) {
5462	dev_dbg(dev, "No valid cs-gpios property\n");
5463	return 0;
5464	}
5465
5466	descs = devm_kcalloc(dev, n: ndescs, size: sizeof(*descs), GFP_KERNEL);
5467	if (!descs)
5468	return -ENOMEM;
5469
5470	for (i = 0; i < ndescs; i++) {
5471	descs[i] = gpiod_get_index_optional(dev, con_id: "cs", index: i,
5472	flags: GPIOD_OUT_HIGH);
5473	if (IS_ERR(ptr: descs[i]))
5474	return PTR_ERR(ptr: descs[i]);
5475	}
5476
5477	*ncs_array = ndescs;
5478	*cs_array = descs;
5479
5480	return 0;
5481	}
5482	EXPORT_SYMBOL(rawnand_dt_parse_gpio_cs);
5483
5484	static int rawnand_dt_init(struct nand_chip *chip)
5485	{
5486	struct nand_device *nand = mtd_to_nanddev(mtd: nand_to_mtd(chip));
5487	struct device_node *dn = nand_get_flash_node(chip);
5488	int ret;
5489
5490	if (!dn)
5491	return 0;
5492
5493	ret = of_get_nand_bus_width(chip);
5494	if (ret)
5495	return ret;
5496
5497	if (of_property_read_bool(np: dn, propname: "nand-is-boot-medium"))
5498	chip->options |= NAND_IS_BOOT_MEDIUM;
5499
5500	if (of_property_read_bool(np: dn, propname: "nand-on-flash-bbt"))
5501	chip->bbt_options |= NAND_BBT_USE_FLASH;
5502
5503	of_get_nand_ecc_user_config(nand);
5504	of_get_nand_ecc_legacy_user_config(chip);
5505
5506	/*
5507	* If neither the user nor the NAND controller have requested a specific
5508	* ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST.
5509	*/
5510	nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
5511
5512	/*
5513	* Use the user requested engine type, unless there is none, in this
5514	* case default to the NAND controller choice, otherwise fallback to
5515	* the raw NAND default one.
5516	*/
5517	if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID)
5518	chip->ecc.engine_type = nand->ecc.user_conf.engine_type;
5519	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
5520	chip->ecc.engine_type = nand->ecc.defaults.engine_type;
5521
5522	chip->ecc.placement = nand->ecc.user_conf.placement;
5523	chip->ecc.algo = nand->ecc.user_conf.algo;
5524	chip->ecc.strength = nand->ecc.user_conf.strength;
5525	chip->ecc.size = nand->ecc.user_conf.step_size;
5526
5527	return 0;
5528	}
5529
5530	/**
5531	* nand_scan_ident - Scan for the NAND device
5532	* @chip: NAND chip object
5533	* @maxchips: number of chips to scan for
5534	* @table: alternative NAND ID table
5535	*
5536	* This is the first phase of the normal nand_scan() function. It reads the
5537	* flash ID and sets up MTD fields accordingly.
5538	*
5539	* This helper used to be called directly from controller drivers that needed
5540	* to tweak some ECC-related parameters before nand_scan_tail(). This separation
5541	* prevented dynamic allocations during this phase which was unconvenient and
5542	* as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks.
5543	*/
5544	static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
5545	struct nand_flash_dev *table)
5546	{
5547	struct mtd_info *mtd = nand_to_mtd(chip);
5548	struct nand_memory_organization *memorg;
5549	int nand_maf_id, nand_dev_id;
5550	unsigned int i;
5551	int ret;
5552
5553	memorg = nanddev_get_memorg(nand: &chip->base);
5554
5555	/* Assume all dies are deselected when we enter nand_scan_ident(). */
5556	chip->cur_cs = -1;
5557
5558	mutex_init(&chip->lock);
5559	init_waitqueue_head(&chip->resume_wq);
5560
5561	/* Enforce the right timings for reset/detection */
5562	chip->current_interface_config = nand_get_reset_interface_config();
5563
5564	ret = rawnand_dt_init(chip);
5565	if (ret)
5566	return ret;
5567
5568	if (!mtd->name && mtd->dev.parent)
5569	mtd->name = dev_name(dev: mtd->dev.parent);
5570
5571	/* Set the default functions */
5572	nand_set_defaults(chip);
5573
5574	ret = nand_legacy_check_hooks(chip);
5575	if (ret)
5576	return ret;
5577
5578	memorg->ntargets = maxchips;
5579
5580	/* Read the flash type */
5581	ret = nand_detect(chip, type: table);
5582	if (ret) {
5583	if (!(chip->options & NAND_SCAN_SILENT_NODEV))
5584	pr_warn("No NAND device found\n");
5585	nand_deselect_target(chip);
5586	return ret;
5587	}
5588
5589	nand_maf_id = chip->id.data[0];
5590	nand_dev_id = chip->id.data[1];
5591
5592	nand_deselect_target(chip);
5593
5594	/* Check for a chip array */
5595	for (i = 1; i < maxchips; i++) {
5596	u8 id[2];
5597
5598	/* See comment in nand_get_flash_type for reset */
5599	ret = nand_reset(chip, i);
5600	if (ret)
5601	break;
5602
5603	nand_select_target(chip, i);
5604	/* Send the command for reading device ID */
5605	ret = nand_readid_op(chip, 0, id, sizeof(id));
5606	if (ret)
5607	break;
5608	/* Read manufacturer and device IDs */
5609	if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
5610	nand_deselect_target(chip);
5611	break;
5612	}
5613	nand_deselect_target(chip);
5614	}
5615	if (i > 1)
5616	pr_info("%d chips detected\n", i);
5617
5618	/* Store the number of chips and calc total size for mtd */
5619	memorg->ntargets = i;
5620	mtd->size = i * nanddev_target_size(nand: &chip->base);
5621
5622	return 0;
5623	}
5624
5625	static void nand_scan_ident_cleanup(struct nand_chip *chip)
5626	{
5627	kfree(objp: chip->parameters.model);
5628	kfree(objp: chip->parameters.onfi);
5629	}
5630
5631	int rawnand_sw_hamming_init(struct nand_chip *chip)
5632	{
5633	struct nand_ecc_sw_hamming_conf *engine_conf;
5634	struct nand_device *base = &chip->base;
5635	int ret;
5636
5637	base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
5638	base->ecc.user_conf.algo = NAND_ECC_ALGO_HAMMING;
5639	base->ecc.user_conf.strength = chip->ecc.strength;
5640	base->ecc.user_conf.step_size = chip->ecc.size;
5641
5642	ret = nand_ecc_sw_hamming_init_ctx(nand: base);
5643	if (ret)
5644	return ret;
5645
5646	engine_conf = base->ecc.ctx.priv;
5647
5648	if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER)
5649	engine_conf->sm_order = true;
5650
5651	chip->ecc.size = base->ecc.ctx.conf.step_size;
5652	chip->ecc.strength = base->ecc.ctx.conf.strength;
5653	chip->ecc.total = base->ecc.ctx.total;
5654	chip->ecc.steps = nanddev_get_ecc_nsteps(nand: base);
5655	chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(nand: base);
5656
5657	return 0;
5658	}
5659	EXPORT_SYMBOL(rawnand_sw_hamming_init);
5660
5661	int rawnand_sw_hamming_calculate(struct nand_chip *chip,
5662	const unsigned char *buf,
5663	unsigned char *code)
5664	{
5665	struct nand_device *base = &chip->base;
5666
5667	return nand_ecc_sw_hamming_calculate(nand: base, buf, code);
5668	}
5669	EXPORT_SYMBOL(rawnand_sw_hamming_calculate);
5670
5671	int rawnand_sw_hamming_correct(struct nand_chip *chip,
5672	unsigned char *buf,
5673	unsigned char *read_ecc,
5674	unsigned char *calc_ecc)
5675	{
5676	struct nand_device *base = &chip->base;
5677
5678	return nand_ecc_sw_hamming_correct(nand: base, buf, read_ecc, calc_ecc);
5679	}
5680	EXPORT_SYMBOL(rawnand_sw_hamming_correct);
5681
5682	void rawnand_sw_hamming_cleanup(struct nand_chip *chip)
5683	{
5684	struct nand_device *base = &chip->base;
5685
5686	nand_ecc_sw_hamming_cleanup_ctx(nand: base);
5687	}
5688	EXPORT_SYMBOL(rawnand_sw_hamming_cleanup);
5689
5690	int rawnand_sw_bch_init(struct nand_chip *chip)
5691	{
5692	struct nand_device *base = &chip->base;
5693	const struct nand_ecc_props *ecc_conf = nanddev_get_ecc_conf(nand: base);
5694	int ret;
5695
5696	base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
5697	base->ecc.user_conf.algo = NAND_ECC_ALGO_BCH;
5698	base->ecc.user_conf.step_size = chip->ecc.size;
5699	base->ecc.user_conf.strength = chip->ecc.strength;
5700
5701	ret = nand_ecc_sw_bch_init_ctx(nand: base);
5702	if (ret)
5703	return ret;
5704
5705	chip->ecc.size = ecc_conf->step_size;
5706	chip->ecc.strength = ecc_conf->strength;
5707	chip->ecc.total = base->ecc.ctx.total;
5708	chip->ecc.steps = nanddev_get_ecc_nsteps(nand: base);
5709	chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(nand: base);
5710
5711	return 0;
5712	}
5713	EXPORT_SYMBOL(rawnand_sw_bch_init);
5714
5715	static int rawnand_sw_bch_calculate(struct nand_chip *chip,
5716	const unsigned char *buf,
5717	unsigned char *code)
5718	{
5719	struct nand_device *base = &chip->base;
5720
5721	return nand_ecc_sw_bch_calculate(nand: base, buf, code);
5722	}
5723
5724	int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf,
5725	unsigned char *read_ecc, unsigned char *calc_ecc)
5726	{
5727	struct nand_device *base = &chip->base;
5728
5729	return nand_ecc_sw_bch_correct(nand: base, buf, read_ecc, calc_ecc);
5730	}
5731	EXPORT_SYMBOL(rawnand_sw_bch_correct);
5732
5733	void rawnand_sw_bch_cleanup(struct nand_chip *chip)
5734	{
5735	struct nand_device *base = &chip->base;
5736
5737	nand_ecc_sw_bch_cleanup_ctx(nand: base);
5738	}
5739	EXPORT_SYMBOL(rawnand_sw_bch_cleanup);
5740
5741	static int nand_set_ecc_on_host_ops(struct nand_chip *chip)
5742	{
5743	struct nand_ecc_ctrl *ecc = &chip->ecc;
5744
5745	switch (ecc->placement) {
5746	case NAND_ECC_PLACEMENT_UNKNOWN:
5747	case NAND_ECC_PLACEMENT_OOB:
5748	/* Use standard hwecc read page function? */
5749	if (!ecc->read_page)
5750	ecc->read_page = nand_read_page_hwecc;
5751	if (!ecc->write_page)
5752	ecc->write_page = nand_write_page_hwecc;
5753	if (!ecc->read_page_raw)
5754	ecc->read_page_raw = nand_read_page_raw;
5755	if (!ecc->write_page_raw)
5756	ecc->write_page_raw = nand_write_page_raw;
5757	if (!ecc->read_oob)
5758	ecc->read_oob = nand_read_oob_std;
5759	if (!ecc->write_oob)
5760	ecc->write_oob = nand_write_oob_std;
5761	if (!ecc->read_subpage)
5762	ecc->read_subpage = nand_read_subpage;
5763	if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
5764	ecc->write_subpage = nand_write_subpage_hwecc;
5765	fallthrough;
5766
5767	case NAND_ECC_PLACEMENT_INTERLEAVED:
5768	if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
5769	(!ecc->read_page ||
5770	ecc->read_page == nand_read_page_hwecc ||
5771	!ecc->write_page ||
5772	ecc->write_page == nand_write_page_hwecc)) {
5773	WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
5774	return -EINVAL;
5775	}
5776	/* Use standard syndrome read/write page function? */
5777	if (!ecc->read_page)
5778	ecc->read_page = nand_read_page_syndrome;
5779	if (!ecc->write_page)
5780	ecc->write_page = nand_write_page_syndrome;
5781	if (!ecc->read_page_raw)
5782	ecc->read_page_raw = nand_read_page_raw_syndrome;
5783	if (!ecc->write_page_raw)
5784	ecc->write_page_raw = nand_write_page_raw_syndrome;
5785	if (!ecc->read_oob)
5786	ecc->read_oob = nand_read_oob_syndrome;
5787	if (!ecc->write_oob)
5788	ecc->write_oob = nand_write_oob_syndrome;
5789	break;
5790
5791	default:
5792	pr_warn("Invalid NAND_ECC_PLACEMENT %d\n",
5793	ecc->placement);
5794	return -EINVAL;
5795	}
5796
5797	return 0;
5798	}
5799
5800	static int nand_set_ecc_soft_ops(struct nand_chip *chip)
5801	{
5802	struct mtd_info *mtd = nand_to_mtd(chip);
5803	struct nand_device *nanddev = mtd_to_nanddev(mtd);
5804	struct nand_ecc_ctrl *ecc = &chip->ecc;
5805	int ret;
5806
5807	if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT))
5808	return -EINVAL;
5809
5810	switch (ecc->algo) {
5811	case NAND_ECC_ALGO_HAMMING:
5812	ecc->calculate = rawnand_sw_hamming_calculate;
5813	ecc->correct = rawnand_sw_hamming_correct;
5814	ecc->read_page = nand_read_page_swecc;
5815	ecc->read_subpage = nand_read_subpage;
5816	ecc->write_page = nand_write_page_swecc;
5817	if (!ecc->read_page_raw)
5818	ecc->read_page_raw = nand_read_page_raw;
5819	if (!ecc->write_page_raw)
5820	ecc->write_page_raw = nand_write_page_raw;
5821	ecc->read_oob = nand_read_oob_std;
5822	ecc->write_oob = nand_write_oob_std;
5823	if (!ecc->size)
5824	ecc->size = 256;
5825	ecc->bytes = 3;
5826	ecc->strength = 1;
5827
5828	if (IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC))
5829	ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
5830
5831	ret = rawnand_sw_hamming_init(chip);
5832	if (ret) {
5833	WARN(1, "Hamming ECC initialization failed!\n");
5834	return ret;
5835	}
5836
5837	return 0;
5838	case NAND_ECC_ALGO_BCH:
5839	if (!IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)) {
5840	WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");
5841	return -EINVAL;
5842	}
5843	ecc->calculate = rawnand_sw_bch_calculate;
5844	ecc->correct = rawnand_sw_bch_correct;
5845	ecc->read_page = nand_read_page_swecc;
5846	ecc->read_subpage = nand_read_subpage;
5847	ecc->write_page = nand_write_page_swecc;
5848	if (!ecc->read_page_raw)
5849	ecc->read_page_raw = nand_read_page_raw;
5850	if (!ecc->write_page_raw)
5851	ecc->write_page_raw = nand_write_page_raw;
5852	ecc->read_oob = nand_read_oob_std;
5853	ecc->write_oob = nand_write_oob_std;
5854
5855	/*
5856	* We can only maximize ECC config when the default layout is
5857	* used, otherwise we don't know how many bytes can really be
5858	* used.
5859	*/
5860	if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH &&
5861	mtd->ooblayout != nand_get_large_page_ooblayout())
5862	nanddev->ecc.user_conf.flags &= ~NAND_ECC_MAXIMIZE_STRENGTH;
5863
5864	ret = rawnand_sw_bch_init(chip);
5865	if (ret) {
5866	WARN(1, "BCH ECC initialization failed!\n");
5867	return ret;
5868	}
5869
5870	return 0;
5871	default:
5872	WARN(1, "Unsupported ECC algorithm!\n");
5873	return -EINVAL;
5874	}
5875	}
5876
5877	/**
5878	* nand_check_ecc_caps - check the sanity of preset ECC settings
5879	* @chip: nand chip info structure
5880	* @caps: ECC caps info structure
5881	* @oobavail: OOB size that the ECC engine can use
5882	*
5883	* When ECC step size and strength are already set, check if they are supported
5884	* by the controller and the calculated ECC bytes fit within the chip's OOB.
5885	* On success, the calculated ECC bytes is set.
5886	*/
5887	static int
5888	nand_check_ecc_caps(struct nand_chip *chip,
5889	const struct nand_ecc_caps *caps, int oobavail)
5890	{
5891	struct mtd_info *mtd = nand_to_mtd(chip);
5892	const struct nand_ecc_step_info *stepinfo;
5893	int preset_step = chip->ecc.size;
5894	int preset_strength = chip->ecc.strength;
5895	int ecc_bytes, nsteps = mtd->writesize / preset_step;
5896	int i, j;
5897
5898	for (i = 0; i < caps->nstepinfos; i++) {
5899	stepinfo = &caps->stepinfos[i];
5900
5901	if (stepinfo->stepsize != preset_step)
5902	continue;
5903
5904	for (j = 0; j < stepinfo->nstrengths; j++) {
5905	if (stepinfo->strengths[j] != preset_strength)
5906	continue;
5907
5908	ecc_bytes = caps->calc_ecc_bytes(preset_step,
5909	preset_strength);
5910	if (WARN_ON_ONCE(ecc_bytes < 0))
5911	return ecc_bytes;
5912
5913	if (ecc_bytes * nsteps > oobavail) {
5914	pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
5915	preset_step, preset_strength);
5916	return -ENOSPC;
5917	}
5918
5919	chip->ecc.bytes = ecc_bytes;
5920
5921	return 0;
5922	}
5923	}
5924
5925	pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
5926	preset_step, preset_strength);
5927
5928	return -ENOTSUPP;
5929	}
5930
5931	/**
5932	* nand_match_ecc_req - meet the chip's requirement with least ECC bytes
5933	* @chip: nand chip info structure
5934	* @caps: ECC engine caps info structure
5935	* @oobavail: OOB size that the ECC engine can use
5936	*
5937	* If a chip's ECC requirement is provided, try to meet it with the least
5938	* number of ECC bytes (i.e. with the largest number of OOB-free bytes).
5939	* On success, the chosen ECC settings are set.
5940	*/
5941	static int
5942	nand_match_ecc_req(struct nand_chip *chip,
5943	const struct nand_ecc_caps *caps, int oobavail)
5944	{
5945	const struct nand_ecc_props *requirements =
5946	nanddev_get_ecc_requirements(nand: &chip->base);
5947	struct mtd_info *mtd = nand_to_mtd(chip);
5948	const struct nand_ecc_step_info *stepinfo;
5949	int req_step = requirements->step_size;
5950	int req_strength = requirements->strength;
5951	int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
5952	int best_step = 0, best_strength = 0, best_ecc_bytes = 0;
5953	int best_ecc_bytes_total = INT_MAX;
5954	int i, j;
5955
5956	/* No information provided by the NAND chip */
5957	if (!req_step || !req_strength)
5958	return -ENOTSUPP;
5959
5960	/* number of correctable bits the chip requires in a page */
5961	req_corr = mtd->writesize / req_step * req_strength;
5962
5963	for (i = 0; i < caps->nstepinfos; i++) {
5964	stepinfo = &caps->stepinfos[i];
5965	step_size = stepinfo->stepsize;
5966
5967	for (j = 0; j < stepinfo->nstrengths; j++) {
5968	strength = stepinfo->strengths[j];
5969
5970	/*
5971	* If both step size and strength are smaller than the
5972	* chip's requirement, it is not easy to compare the
5973	* resulted reliability.
5974	*/
5975	if (step_size < req_step && strength < req_strength)
5976	continue;
5977
5978	if (mtd->writesize % step_size)
5979	continue;
5980
5981	nsteps = mtd->writesize / step_size;
5982
5983	ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
5984	if (WARN_ON_ONCE(ecc_bytes < 0))
5985	continue;
5986	ecc_bytes_total = ecc_bytes * nsteps;
5987
5988	if (ecc_bytes_total > oobavail ||
5989	strength * nsteps < req_corr)
5990	continue;
5991
5992	/*
5993	* We assume the best is to meet the chip's requrement
5994	* with the least number of ECC bytes.
5995	*/
5996	if (ecc_bytes_total < best_ecc_bytes_total) {
5997	best_ecc_bytes_total = ecc_bytes_total;
5998	best_step = step_size;
5999	best_strength = strength;
6000	best_ecc_bytes = ecc_bytes;
6001	}
6002	}
6003	}
6004
6005	if (best_ecc_bytes_total == INT_MAX)
6006	return -ENOTSUPP;
6007
6008	chip->ecc.size = best_step;
6009	chip->ecc.strength = best_strength;
6010	chip->ecc.bytes = best_ecc_bytes;
6011
6012	return 0;
6013	}
6014
6015	/**
6016	* nand_maximize_ecc - choose the max ECC strength available
6017	* @chip: nand chip info structure
6018	* @caps: ECC engine caps info structure
6019	* @oobavail: OOB size that the ECC engine can use
6020	*
6021	* Choose the max ECC strength that is supported on the controller, and can fit
6022	* within the chip's OOB. On success, the chosen ECC settings are set.
6023	*/
6024	static int
6025	nand_maximize_ecc(struct nand_chip *chip,
6026	const struct nand_ecc_caps *caps, int oobavail)
6027	{
6028	struct mtd_info *mtd = nand_to_mtd(chip);
6029	const struct nand_ecc_step_info *stepinfo;
6030	int step_size, strength, nsteps, ecc_bytes, corr;
6031	int best_corr = 0;
6032	int best_step = 0;
6033	int best_strength = 0, best_ecc_bytes = 0;
6034	int i, j;
6035
6036	for (i = 0; i < caps->nstepinfos; i++) {
6037	stepinfo = &caps->stepinfos[i];
6038	step_size = stepinfo->stepsize;
6039
6040	/* If chip->ecc.size is already set, respect it */
6041	if (chip->ecc.size && step_size != chip->ecc.size)
6042	continue;
6043
6044	for (j = 0; j < stepinfo->nstrengths; j++) {
6045	strength = stepinfo->strengths[j];
6046
6047	if (mtd->writesize % step_size)
6048	continue;
6049
6050	nsteps = mtd->writesize / step_size;
6051
6052	ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
6053	if (WARN_ON_ONCE(ecc_bytes < 0))
6054	continue;
6055
6056	if (ecc_bytes * nsteps > oobavail)
6057	continue;
6058
6059	corr = strength * nsteps;
6060
6061	/*
6062	* If the number of correctable bits is the same,
6063	* bigger step_size has more reliability.
6064	*/
6065	if (corr > best_corr ||
6066	(corr == best_corr && step_size > best_step)) {
6067	best_corr = corr;
6068	best_step = step_size;
6069	best_strength = strength;
6070	best_ecc_bytes = ecc_bytes;
6071	}
6072	}
6073	}
6074
6075	if (!best_corr)
6076	return -ENOTSUPP;
6077
6078	chip->ecc.size = best_step;
6079	chip->ecc.strength = best_strength;
6080	chip->ecc.bytes = best_ecc_bytes;
6081
6082	return 0;
6083	}
6084
6085	/**
6086	* nand_ecc_choose_conf - Set the ECC strength and ECC step size
6087	* @chip: nand chip info structure
6088	* @caps: ECC engine caps info structure
6089	* @oobavail: OOB size that the ECC engine can use
6090	*
6091	* Choose the ECC configuration according to following logic.
6092	*
6093	* 1. If both ECC step size and ECC strength are already set (usually by DT)
6094	* then check if it is supported by this controller.
6095	* 2. If the user provided the nand-ecc-maximize property, then select maximum
6096	* ECC strength.
6097	* 3. Otherwise, try to match the ECC step size and ECC strength closest
6098	* to the chip's requirement. If available OOB size can't fit the chip
6099	* requirement then fallback to the maximum ECC step size and ECC strength.
6100	*
6101	* On success, the chosen ECC settings are set.
6102	*/
6103	int nand_ecc_choose_conf(struct nand_chip *chip,
6104	const struct nand_ecc_caps *caps, int oobavail)
6105	{
6106	struct mtd_info *mtd = nand_to_mtd(chip);
6107	struct nand_device *nanddev = mtd_to_nanddev(mtd);
6108
6109	if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize))
6110	return -EINVAL;
6111
6112	if (chip->ecc.size && chip->ecc.strength)
6113	return nand_check_ecc_caps(chip, caps, oobavail);
6114
6115	if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)
6116	return nand_maximize_ecc(chip, caps, oobavail);
6117
6118	if (!nand_match_ecc_req(chip, caps, oobavail))
6119	return 0;
6120
6121	return nand_maximize_ecc(chip, caps, oobavail);
6122	}
6123	EXPORT_SYMBOL_GPL(nand_ecc_choose_conf);
6124
6125	static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos)
6126	{
6127	struct nand_chip *chip = container_of(nand, struct nand_chip,
6128	base);
6129	unsigned int eb = nanddev_pos_to_row(nand, pos);
6130	int ret;
6131
6132	eb >>= nand->rowconv.eraseblock_addr_shift;
6133
6134	nand_select_target(chip, pos->target);
6135	ret = nand_erase_op(chip, eb);
6136	nand_deselect_target(chip);
6137
6138	return ret;
6139	}
6140
6141	static int rawnand_markbad(struct nand_device *nand,
6142	const struct nand_pos *pos)
6143	{
6144	struct nand_chip *chip = container_of(nand, struct nand_chip,
6145	base);
6146
6147	return nand_markbad_bbm(chip, ofs: nanddev_pos_to_offs(nand, pos));
6148	}
6149
6150	static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos)
6151	{
6152	struct nand_chip *chip = container_of(nand, struct nand_chip,
6153	base);
6154	int ret;
6155
6156	nand_select_target(chip, pos->target);
6157	ret = nand_isbad_bbm(chip, ofs: nanddev_pos_to_offs(nand, pos));
6158	nand_deselect_target(chip);
6159
6160	return ret;
6161	}
6162
6163	static const struct nand_ops rawnand_ops = {
6164	.erase = rawnand_erase,
6165	.markbad = rawnand_markbad,
6166	.isbad = rawnand_isbad,
6167	};
6168
6169	/**
6170	* nand_scan_tail - Scan for the NAND device
6171	* @chip: NAND chip object
6172	*
6173	* This is the second phase of the normal nand_scan() function. It fills out
6174	* all the uninitialized function pointers with the defaults and scans for a
6175	* bad block table if appropriate.
6176	*/
6177	static int nand_scan_tail(struct nand_chip *chip)
6178	{
6179	struct mtd_info *mtd = nand_to_mtd(chip);
6180	struct nand_device *base = &chip->base;
6181	struct nand_ecc_ctrl *ecc = &chip->ecc;
6182	int ret, i;
6183
6184	/* New bad blocks should be marked in OOB, flash-based BBT, or both */
6185	if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
6186	!(chip->bbt_options & NAND_BBT_USE_FLASH))) {
6187	return -EINVAL;
6188	}
6189
6190	chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
6191	if (!chip->data_buf)
6192	return -ENOMEM;
6193
6194	/*
6195	* FIXME: some NAND manufacturer drivers expect the first die to be
6196	* selected when manufacturer->init() is called. They should be fixed
6197	* to explictly select the relevant die when interacting with the NAND
6198	* chip.
6199	*/
6200	nand_select_target(chip, 0);
6201	ret = nand_manufacturer_init(chip);
6202	nand_deselect_target(chip);
6203	if (ret)
6204	goto err_free_buf;
6205
6206	/* Set the internal oob buffer location, just after the page data */
6207	chip->oob_poi = chip->data_buf + mtd->writesize;
6208
6209	/*
6210	* If no default placement scheme is given, select an appropriate one.
6211	*/
6212	if (!mtd->ooblayout &&
6213	!(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
6214	ecc->algo == NAND_ECC_ALGO_BCH) &&
6215	!(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
6216	ecc->algo == NAND_ECC_ALGO_HAMMING)) {
6217	switch (mtd->oobsize) {
6218	case 8:
6219	case 16:
6220	mtd_set_ooblayout(mtd, ooblayout: nand_get_small_page_ooblayout());
6221	break;
6222	case 64:
6223	case 128:
6224	mtd_set_ooblayout(mtd,
6225	ooblayout: nand_get_large_page_hamming_ooblayout());
6226	break;
6227	default:
6228	/*
6229	* Expose the whole OOB area to users if ECC_NONE
6230	* is passed. We could do that for all kind of
6231	* ->oobsize, but we must keep the old large/small
6232	* page with ECC layout when ->oobsize <= 128 for
6233	* compatibility reasons.
6234	*/
6235	if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) {
6236	mtd_set_ooblayout(mtd,
6237	ooblayout: nand_get_large_page_ooblayout());
6238	break;
6239	}
6240
6241	WARN(1, "No oob scheme defined for oobsize %d\n",
6242	mtd->oobsize);
6243	ret = -EINVAL;
6244	goto err_nand_manuf_cleanup;
6245	}
6246	}
6247
6248	/*
6249	* Check ECC mode, default to software if 3byte/512byte hardware ECC is
6250	* selected and we have 256 byte pagesize fallback to software ECC
6251	*/
6252
6253	switch (ecc->engine_type) {
6254	case NAND_ECC_ENGINE_TYPE_ON_HOST:
6255	ret = nand_set_ecc_on_host_ops(chip);
6256	if (ret)
6257	goto err_nand_manuf_cleanup;
6258
6259	if (mtd->writesize >= ecc->size) {
6260	if (!ecc->strength) {
6261	WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
6262	ret = -EINVAL;
6263	goto err_nand_manuf_cleanup;
6264	}
6265	break;
6266	}
6267	pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
6268	ecc->size, mtd->writesize);
6269	ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
6270	ecc->algo = NAND_ECC_ALGO_HAMMING;
6271	fallthrough;
6272
6273	case NAND_ECC_ENGINE_TYPE_SOFT:
6274	ret = nand_set_ecc_soft_ops(chip);
6275	if (ret)
6276	goto err_nand_manuf_cleanup;
6277	break;
6278
6279	case NAND_ECC_ENGINE_TYPE_ON_DIE:
6280	if (!ecc->read_page || !ecc->write_page) {
6281	WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
6282	ret = -EINVAL;
6283	goto err_nand_manuf_cleanup;
6284	}
6285	if (!ecc->read_oob)
6286	ecc->read_oob = nand_read_oob_std;
6287	if (!ecc->write_oob)
6288	ecc->write_oob = nand_write_oob_std;
6289	break;
6290
6291	case NAND_ECC_ENGINE_TYPE_NONE:
6292	pr_warn("NAND_ECC_ENGINE_TYPE_NONE selected by board driver. This is not recommended!\n");
6293	ecc->read_page = nand_read_page_raw;
6294	ecc->write_page = nand_write_page_raw;
6295	ecc->read_oob = nand_read_oob_std;
6296	ecc->read_page_raw = nand_read_page_raw;
6297	ecc->write_page_raw = nand_write_page_raw;
6298	ecc->write_oob = nand_write_oob_std;
6299	ecc->size = mtd->writesize;
6300	ecc->bytes = 0;
6301	ecc->strength = 0;
6302	break;
6303
6304	default:
6305	WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type);
6306	ret = -EINVAL;
6307	goto err_nand_manuf_cleanup;
6308	}
6309
6310	if (ecc->correct || ecc->calculate) {
6311	ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL);
6312	ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL);
6313	if (!ecc->calc_buf || !ecc->code_buf) {
6314	ret = -ENOMEM;
6315	goto err_nand_manuf_cleanup;
6316	}
6317	}
6318
6319	/* For many systems, the standard OOB write also works for raw */
6320	if (!ecc->read_oob_raw)
6321	ecc->read_oob_raw = ecc->read_oob;
6322	if (!ecc->write_oob_raw)
6323	ecc->write_oob_raw = ecc->write_oob;
6324
6325	/* Propagate ECC info to the generic NAND and MTD layers */
6326	mtd->ecc_strength = ecc->strength;
6327	if (!base->ecc.ctx.conf.strength)
6328	base->ecc.ctx.conf.strength = ecc->strength;
6329	mtd->ecc_step_size = ecc->size;
6330	if (!base->ecc.ctx.conf.step_size)
6331	base->ecc.ctx.conf.step_size = ecc->size;
6332
6333	/*
6334	* Set the number of read / write steps for one page depending on ECC
6335	* mode.
6336	*/
6337	if (!ecc->steps)
6338	ecc->steps = mtd->writesize / ecc->size;
6339	if (!base->ecc.ctx.nsteps)
6340	base->ecc.ctx.nsteps = ecc->steps;
6341
6342	/*
6343	* Validity check: Warn if ECC parameters are not compatible with page size.
6344	* Due to the custom handling of ECC blocks in certain controllers the check
6345	* may result in an expected failure.
6346	*/
6347	if (ecc->steps * ecc->size != mtd->writesize)
6348	pr_warn("ECC parameters may be invalid in reference to underlying NAND chip\n");
6349
6350	if (!ecc->total) {
6351	ecc->total = ecc->steps * ecc->bytes;
6352	chip->base.ecc.ctx.total = ecc->total;
6353	}
6354
6355	if (ecc->total > mtd->oobsize) {
6356	WARN(1, "Total number of ECC bytes exceeded oobsize\n");
6357	ret = -EINVAL;
6358	goto err_nand_manuf_cleanup;
6359	}
6360
6361	/*
6362	* The number of bytes available for a client to place data into
6363	* the out of band area.
6364	*/
6365	ret = mtd_ooblayout_count_freebytes(mtd);
6366	if (ret < 0)
6367	ret = 0;
6368
6369	mtd->oobavail = ret;
6370
6371	/* ECC sanity check: warn if it's too weak */
6372	if (!nand_ecc_is_strong_enough(nand: &chip->base))
6373	pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n",
6374	mtd->name, chip->ecc.strength, chip->ecc.size,
6375	nanddev_get_ecc_requirements(&chip->base)->strength,
6376	nanddev_get_ecc_requirements(&chip->base)->step_size);
6377
6378	/* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
6379	if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
6380	switch (ecc->steps) {
6381	case 2:
6382	mtd->subpage_sft = 1;
6383	break;
6384	case 4:
6385	case 8:
6386	case 16:
6387	mtd->subpage_sft = 2;
6388	break;
6389	}
6390	}
6391	chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
6392
6393	/* Invalidate the pagebuffer reference */
6394	chip->pagecache.page = -1;
6395
6396	/* Large page NAND with SOFT_ECC should support subpage reads */
6397	switch (ecc->engine_type) {
6398	case NAND_ECC_ENGINE_TYPE_SOFT:
6399	if (chip->page_shift > 9)
6400	chip->options |= NAND_SUBPAGE_READ;
6401	break;
6402
6403	default:
6404	break;
6405	}
6406
6407	ret = nanddev_init(nand: &chip->base, ops: &rawnand_ops, owner: mtd->owner);
6408	if (ret)
6409	goto err_nand_manuf_cleanup;
6410
6411	/* Adjust the MTD_CAP_ flags when NAND_ROM is set. */
6412	if (chip->options & NAND_ROM)
6413	mtd->flags = MTD_CAP_ROM;
6414
6415	/* Fill in remaining MTD driver data */
6416	mtd->_erase = nand_erase;
6417	mtd->_point = NULL;
6418	mtd->_unpoint = NULL;
6419	mtd->_panic_write = panic_nand_write;
6420	mtd->_read_oob = nand_read_oob;
6421	mtd->_write_oob = nand_write_oob;
6422	mtd->_sync = nand_sync;
6423	mtd->_lock = nand_lock;
6424	mtd->_unlock = nand_unlock;
6425	mtd->_suspend = nand_suspend;
6426	mtd->_resume = nand_resume;
6427	mtd->_reboot = nand_shutdown;
6428	mtd->_block_isreserved = nand_block_isreserved;
6429	mtd->_block_isbad = nand_block_isbad;
6430	mtd->_block_markbad = nand_block_markbad;
6431	mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks;
6432
6433	/*
6434	* Initialize bitflip_threshold to its default prior scan_bbt() call.
6435	* scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
6436	* properly set.
6437	*/
6438	if (!mtd->bitflip_threshold)
6439	mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
6440
6441	/* Find the fastest data interface for this chip */
6442	ret = nand_choose_interface_config(chip);
6443	if (ret)
6444	goto err_nanddev_cleanup;
6445
6446	/* Enter fastest possible mode on all dies. */
6447	for (i = 0; i < nanddev_ntargets(nand: &chip->base); i++) {
6448	ret = nand_setup_interface(chip, chipnr: i);
6449	if (ret)
6450	goto err_free_interface_config;
6451	}
6452
6453	rawnand_late_check_supported_ops(chip);
6454
6455	/*
6456	* Look for secure regions in the NAND chip. These regions are supposed
6457	* to be protected by a secure element like Trustzone. So the read/write
6458	* accesses to these regions will be blocked in the runtime by this
6459	* driver.
6460	*/
6461	ret = of_get_nand_secure_regions(chip);
6462	if (ret)
6463	goto err_free_interface_config;
6464
6465	/* Check, if we should skip the bad block table scan */
6466	if (chip->options & NAND_SKIP_BBTSCAN)
6467	return 0;
6468
6469	/* Build bad block table */
6470	ret = nand_create_bbt(chip);
6471	if (ret)
6472	goto err_free_secure_regions;
6473
6474	return 0;
6475
6476	err_free_secure_regions:
6477	kfree(objp: chip->secure_regions);
6478
6479	err_free_interface_config:
6480	kfree(objp: chip->best_interface_config);
6481
6482	err_nanddev_cleanup:
6483	nanddev_cleanup(nand: &chip->base);
6484
6485	err_nand_manuf_cleanup:
6486	nand_manufacturer_cleanup(chip);
6487
6488	err_free_buf:
6489	kfree(objp: chip->data_buf);
6490	kfree(objp: ecc->code_buf);
6491	kfree(objp: ecc->calc_buf);
6492
6493	return ret;
6494	}
6495
6496	static int nand_attach(struct nand_chip *chip)
6497	{
6498	if (chip->controller->ops && chip->controller->ops->attach_chip)
6499	return chip->controller->ops->attach_chip(chip);
6500
6501	return 0;
6502	}
6503
6504	static void nand_detach(struct nand_chip *chip)
6505	{
6506	if (chip->controller->ops && chip->controller->ops->detach_chip)
6507	chip->controller->ops->detach_chip(chip);
6508	}
6509
6510	/**
6511	* nand_scan_with_ids - [NAND Interface] Scan for the NAND device
6512	* @chip: NAND chip object
6513	* @maxchips: number of chips to scan for.
6514	* @ids: optional flash IDs table
6515	*
6516	* This fills out all the uninitialized function pointers with the defaults.
6517	* The flash ID is read and the mtd/chip structures are filled with the
6518	* appropriate values.
6519	*/
6520	int nand_scan_with_ids(struct nand_chip *chip, unsigned int maxchips,
6521	struct nand_flash_dev *ids)
6522	{
6523	int ret;
6524
6525	if (!maxchips)
6526	return -EINVAL;
6527
6528	ret = nand_scan_ident(chip, maxchips, table: ids);
6529	if (ret)
6530	return ret;
6531
6532	ret = nand_attach(chip);
6533	if (ret)
6534	goto cleanup_ident;
6535
6536	ret = nand_scan_tail(chip);
6537	if (ret)
6538	goto detach_chip;
6539
6540	return 0;
6541
6542	detach_chip:
6543	nand_detach(chip);
6544	cleanup_ident:
6545	nand_scan_ident_cleanup(chip);
6546
6547	return ret;
6548	}
6549	EXPORT_SYMBOL(nand_scan_with_ids);
6550
6551	/**
6552	* nand_cleanup - [NAND Interface] Free resources held by the NAND device
6553	* @chip: NAND chip object
6554	*/
6555	void nand_cleanup(struct nand_chip *chip)
6556	{
6557	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) {
6558	if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
6559	rawnand_sw_hamming_cleanup(chip);
6560	else if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
6561	rawnand_sw_bch_cleanup(chip);
6562	}
6563
6564	nanddev_cleanup(nand: &chip->base);
6565
6566	/* Free secure regions data */
6567	kfree(objp: chip->secure_regions);
6568
6569	/* Free bad block table memory */
6570	kfree(objp: chip->bbt);
6571	kfree(objp: chip->data_buf);
6572	kfree(objp: chip->ecc.code_buf);
6573	kfree(objp: chip->ecc.calc_buf);
6574
6575	/* Free bad block descriptor memory */
6576	if (chip->badblock_pattern && chip->badblock_pattern->options
6577	& NAND_BBT_DYNAMICSTRUCT)
6578	kfree(objp: chip->badblock_pattern);
6579
6580	/* Free the data interface */
6581	kfree(objp: chip->best_interface_config);
6582
6583	/* Free manufacturer priv data. */
6584	nand_manufacturer_cleanup(chip);
6585
6586	/* Free controller specific allocations after chip identification */
6587	nand_detach(chip);
6588
6589	/* Free identification phase allocations */
6590	nand_scan_ident_cleanup(chip);
6591	}
6592
6593	EXPORT_SYMBOL_GPL(nand_cleanup);
6594
6595	MODULE_LICENSE("GPL");
6596	MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
6597	MODULE_AUTHOR("Thomas Gleixner <tglx@kernel.org>");
6598	MODULE_DESCRIPTION("Generic NAND flash driver code");
6599