| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Driver for Xilinx TMR Inject IP. |
| 4 | * |
| 5 | * Copyright (C) 2022 Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * Description: |
| 8 | * This driver is developed for TMR Inject IP,The Triple Modular Redundancy(TMR) |
| 9 | * Inject provides fault injection. |
| 10 | */ |
| 11 | |
| 12 | #include <asm/xilinx_mb_manager.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/of.h> |
| 15 | #include <linux/debugfs.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/fault-inject.h> |
| 18 | |
| 19 | /* TMR Inject Register offsets */ |
| 20 | #define XTMR_INJECT_CR_OFFSET 0x0 |
| 21 | #define XTMR_INJECT_AIR_OFFSET 0x4 |
| 22 | #define XTMR_INJECT_IIR_OFFSET 0xC |
| 23 | #define XTMR_INJECT_EAIR_OFFSET 0x10 |
| 24 | #define XTMR_INJECT_ERR_OFFSET 0x204 |
| 25 | |
| 26 | /* Register Bitmasks/shifts */ |
| 27 | #define XTMR_INJECT_CR_CPUID_SHIFT 8 |
| 28 | #define XTMR_INJECT_CR_IE_SHIFT 10 |
| 29 | #define XTMR_INJECT_IIR_ADDR_MASK GENMASK(31, 16) |
| 30 | |
| 31 | #define XTMR_INJECT_MAGIC_MAX_VAL 255 |
| 32 | |
| 33 | /** |
| 34 | * struct xtmr_inject_dev - Driver data for TMR Inject |
| 35 | * @regs: device physical base address |
| 36 | * @magic: Magic hardware configuration value |
| 37 | */ |
| 38 | struct xtmr_inject_dev { |
| 39 | void __iomem *regs; |
| 40 | u32 magic; |
| 41 | }; |
| 42 | |
| 43 | static DECLARE_FAULT_ATTR(inject_fault); |
| 44 | static char *inject_request; |
| 45 | module_param(inject_request, charp, 0); |
| 46 | MODULE_PARM_DESC(inject_request, "default fault injection attributes" ); |
| 47 | static struct dentry *dbgfs_root; |
| 48 | |
| 49 | /* IO accessors */ |
| 50 | static inline void xtmr_inject_write(struct xtmr_inject_dev *xtmr_inject, |
| 51 | u32 addr, u32 value) |
| 52 | { |
| 53 | iowrite32(value, xtmr_inject->regs + addr); |
| 54 | } |
| 55 | |
| 56 | static inline u32 xtmr_inject_read(struct xtmr_inject_dev *xtmr_inject, |
| 57 | u32 addr) |
| 58 | { |
| 59 | return ioread32(xtmr_inject->regs + addr); |
| 60 | } |
| 61 | |
| 62 | static int xtmr_inject_set(void *data, u64 val) |
| 63 | { |
| 64 | if (val != 1) |
| 65 | return -EINVAL; |
| 66 | |
| 67 | xmb_inject_err(); |
| 68 | return 0; |
| 69 | } |
| 70 | DEFINE_DEBUGFS_ATTRIBUTE(xtmr_inject_fops, NULL, xtmr_inject_set, "%llu\n" ); |
| 71 | |
| 72 | static void xtmr_init_debugfs(struct xtmr_inject_dev *xtmr_inject) |
| 73 | { |
| 74 | struct dentry *dir; |
| 75 | |
| 76 | dbgfs_root = debugfs_create_dir(name: "xtmr_inject" , NULL); |
| 77 | dir = fault_create_debugfs_attr(name: "inject_fault" , parent: dbgfs_root, |
| 78 | attr: &inject_fault); |
| 79 | debugfs_create_file("inject_fault" , 0200, dir, NULL, |
| 80 | &xtmr_inject_fops); |
| 81 | } |
| 82 | |
| 83 | static void xtmr_inject_init(struct xtmr_inject_dev *xtmr_inject) |
| 84 | { |
| 85 | u32 cr_val; |
| 86 | |
| 87 | if (inject_request) |
| 88 | setup_fault_attr(attr: &inject_fault, str: inject_request); |
| 89 | /* Allow fault injection */ |
| 90 | cr_val = xtmr_inject->magic | |
| 91 | (1 << XTMR_INJECT_CR_IE_SHIFT) | |
| 92 | (1 << XTMR_INJECT_CR_CPUID_SHIFT); |
| 93 | xtmr_inject_write(xtmr_inject, XTMR_INJECT_CR_OFFSET, |
| 94 | value: cr_val); |
| 95 | /* Initialize the address inject and instruction inject registers */ |
| 96 | xtmr_inject_write(xtmr_inject, XTMR_INJECT_AIR_OFFSET, |
| 97 | value: XMB_INJECT_ERR_OFFSET); |
| 98 | xtmr_inject_write(xtmr_inject, XTMR_INJECT_IIR_OFFSET, |
| 99 | value: XMB_INJECT_ERR_OFFSET & XTMR_INJECT_IIR_ADDR_MASK); |
| 100 | } |
| 101 | |
| 102 | /** |
| 103 | * xtmr_inject_probe - Driver probe function |
| 104 | * @pdev: Pointer to the platform_device structure |
| 105 | * |
| 106 | * This is the driver probe routine. It does all the memory |
| 107 | * allocation for the device. |
| 108 | * |
| 109 | * Return: 0 on success and failure value on error |
| 110 | */ |
| 111 | static int xtmr_inject_probe(struct platform_device *pdev) |
| 112 | { |
| 113 | struct xtmr_inject_dev *xtmr_inject; |
| 114 | int err; |
| 115 | |
| 116 | xtmr_inject = devm_kzalloc(dev: &pdev->dev, size: sizeof(*xtmr_inject), |
| 117 | GFP_KERNEL); |
| 118 | if (!xtmr_inject) |
| 119 | return -ENOMEM; |
| 120 | |
| 121 | xtmr_inject->regs = devm_platform_ioremap_resource(pdev, index: 0); |
| 122 | if (IS_ERR(ptr: xtmr_inject->regs)) |
| 123 | return PTR_ERR(ptr: xtmr_inject->regs); |
| 124 | |
| 125 | err = of_property_read_u32(np: pdev->dev.of_node, propname: "xlnx,magic" , |
| 126 | out_value: &xtmr_inject->magic); |
| 127 | if (err < 0) { |
| 128 | dev_err(&pdev->dev, "unable to read xlnx,magic property" ); |
| 129 | return err; |
| 130 | } |
| 131 | |
| 132 | if (xtmr_inject->magic > XTMR_INJECT_MAGIC_MAX_VAL) { |
| 133 | dev_err(&pdev->dev, "invalid xlnx,magic property value" ); |
| 134 | return -EINVAL; |
| 135 | } |
| 136 | |
| 137 | /* Initialize TMR Inject */ |
| 138 | xtmr_inject_init(xtmr_inject); |
| 139 | |
| 140 | xtmr_init_debugfs(xtmr_inject); |
| 141 | |
| 142 | platform_set_drvdata(pdev, data: xtmr_inject); |
| 143 | |
| 144 | return 0; |
| 145 | } |
| 146 | |
| 147 | static void xtmr_inject_remove(struct platform_device *pdev) |
| 148 | { |
| 149 | debugfs_remove_recursive(dentry: dbgfs_root); |
| 150 | dbgfs_root = NULL; |
| 151 | } |
| 152 | |
| 153 | static const struct of_device_id xtmr_inject_of_match[] = { |
| 154 | { |
| 155 | .compatible = "xlnx,tmr-inject-1.0" , |
| 156 | }, |
| 157 | { /* end of table */ } |
| 158 | }; |
| 159 | MODULE_DEVICE_TABLE(of, xtmr_inject_of_match); |
| 160 | |
| 161 | static struct platform_driver xtmr_inject_driver = { |
| 162 | .driver = { |
| 163 | .name = "xilinx-tmr_inject" , |
| 164 | .of_match_table = xtmr_inject_of_match, |
| 165 | }, |
| 166 | .probe = xtmr_inject_probe, |
| 167 | .remove = xtmr_inject_remove, |
| 168 | }; |
| 169 | module_platform_driver(xtmr_inject_driver); |
| 170 | MODULE_AUTHOR("Advanced Micro Devices, Inc" ); |
| 171 | MODULE_DESCRIPTION("Xilinx TMR Inject Driver" ); |
| 172 | MODULE_LICENSE("GPL" ); |
| 173 | |