1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for most of the SPI EEPROMs, such as Atmel AT25 models
4 * and Cypress FRAMs FM25 models.
5 *
6 * Copyright (C) 2006 David Brownell
7 */
8
9#include <linux/bits.h>
10#include <linux/cleanup.h>
11#include <linux/delay.h>
12#include <linux/device.h>
13#include <linux/iopoll.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/property.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19
20#include <linux/spi/eeprom.h>
21#include <linux/spi/spi.h>
22#include <linux/spi/spi-mem.h>
23
24#include <linux/nvmem-provider.h>
25
26/*
27 * NOTE: this is an *EEPROM* driver. The vagaries of product naming
28 * mean that some AT25 products are EEPROMs, and others are FLASH.
29 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
30 * not this one!
31 *
32 * EEPROMs that can be used with this driver include, for example:
33 * AT25M02, AT25128B
34 */
35
36#define FM25_SN_LEN 8 /* serial number length */
37#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
38
39struct at25_data {
40 struct spi_eeprom chip;
41 struct spi_mem *spimem;
42 struct mutex lock;
43 unsigned addrlen;
44 struct nvmem_config nvmem_config;
45 struct nvmem_device *nvmem;
46 u8 sernum[FM25_SN_LEN];
47};
48
49#define AT25_WREN 0x06 /* latch the write enable */
50#define AT25_WRDI 0x04 /* reset the write enable */
51#define AT25_RDSR 0x05 /* read status register */
52#define AT25_WRSR 0x01 /* write status register */
53#define AT25_READ 0x03 /* read byte(s) */
54#define AT25_WRITE 0x02 /* write byte(s)/sector */
55#define FM25_SLEEP 0xb9 /* enter sleep mode */
56#define FM25_RDID 0x9f /* read device ID */
57#define FM25_RDSN 0xc3 /* read S/N */
58
59#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
60#define AT25_SR_WEN 0x02 /* write enable (latched) */
61#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
62#define AT25_SR_BP1 0x08
63#define AT25_SR_WPEN 0x80 /* writeprotect enable */
64
65#define AT25_INSTR_BIT3 0x08 /* additional address bit in instr */
66
67#define FM25_ID_LEN 9 /* ID length */
68
69/*
70 * Specs often allow 5ms for a page write, sometimes 20ms;
71 * it's important to recover from write timeouts.
72 */
73#define EE_TIMEOUT 25
74
75/*-------------------------------------------------------------------------*/
76
77#define io_limit PAGE_SIZE /* bytes */
78
79/* Handle the address MSB as part of instruction byte */
80static u8 at25_instr(struct at25_data *at25, u8 instr, unsigned int off)
81{
82 if (!(at25->chip.flags & EE_INSTR_BIT3_IS_ADDR))
83 return instr;
84 if (off < BIT(at25->addrlen * 8))
85 return instr;
86 return instr | AT25_INSTR_BIT3;
87}
88
89static int at25_ee_read(void *priv, unsigned int offset,
90 void *val, size_t count)
91{
92 u8 *bounce __free(kfree) = kmalloc(min(count, io_limit), GFP_KERNEL);
93 struct at25_data *at25 = priv;
94 char *buf = val;
95 unsigned int msg_offset = offset;
96 size_t bytes_left = count;
97 size_t segment;
98 int status;
99
100 if (!bounce)
101 return -ENOMEM;
102
103 if (unlikely(offset >= at25->chip.byte_len))
104 return -EINVAL;
105 if ((offset + count) > at25->chip.byte_len)
106 count = at25->chip.byte_len - offset;
107 if (unlikely(!count))
108 return -EINVAL;
109
110 do {
111 struct spi_mem_op op;
112
113 segment = min(bytes_left, io_limit);
114
115 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(at25_instr(at25, AT25_READ,
116 msg_offset), 1),
117 SPI_MEM_OP_ADDR(at25->addrlen, msg_offset, 1),
118 SPI_MEM_OP_NO_DUMMY,
119 SPI_MEM_OP_DATA_IN(segment, bounce, 1));
120
121 status = spi_mem_adjust_op_size(mem: at25->spimem, op: &op);
122 if (status)
123 return status;
124 segment = op.data.nbytes;
125
126 mutex_lock(&at25->lock);
127 status = spi_mem_exec_op(mem: at25->spimem, op: &op);
128 mutex_unlock(lock: &at25->lock);
129 if (status)
130 return status;
131 memcpy(buf, bounce, segment);
132
133 msg_offset += segment;
134 buf += segment;
135 bytes_left -= segment;
136 } while (bytes_left > 0);
137
138 dev_dbg(&at25->spimem->spi->dev, "read %zu bytes at %d\n",
139 count, offset);
140 return 0;
141}
142
143/*
144 * Read extra registers as ID or serial number
145 *
146 * Allow for the callers to provide @buf on stack (not necessary DMA-capable)
147 * by allocating a bounce buffer internally.
148 */
149static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command,
150 int len)
151{
152 u8 *bounce __free(kfree) = kmalloc(len, GFP_KERNEL);
153 struct spi_mem_op op;
154 int status;
155
156 if (!bounce)
157 return -ENOMEM;
158
159 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(command, 1),
160 SPI_MEM_OP_NO_ADDR,
161 SPI_MEM_OP_NO_DUMMY,
162 SPI_MEM_OP_DATA_IN(len, bounce, 1));
163
164 status = spi_mem_exec_op(mem: at25->spimem, op: &op);
165 dev_dbg(&at25->spimem->spi->dev, "read %d aux bytes --> %d\n", len, status);
166 if (status)
167 return status;
168
169 memcpy(buf, bounce, len);
170
171 return 0;
172}
173
174static ssize_t sernum_show(struct device *dev, struct device_attribute *attr, char *buf)
175{
176 struct at25_data *at25;
177
178 at25 = dev_get_drvdata(dev);
179 return sysfs_emit(buf, fmt: "%*ph\n", (int)sizeof(at25->sernum), at25->sernum);
180}
181static DEVICE_ATTR_RO(sernum);
182
183static struct attribute *sernum_attrs[] = {
184 &dev_attr_sernum.attr,
185 NULL,
186};
187ATTRIBUTE_GROUPS(sernum);
188
189/*
190 * Poll Read Status Register with timeout
191 *
192 * Return:
193 * 0, if the chip is ready
194 * [positive] Status Register value as-is, if the chip is busy
195 * [negative] error code in case of read failure
196 */
197static int at25_wait_ready(struct at25_data *at25)
198{
199 u8 *bounce __free(kfree) = kmalloc(1, GFP_KERNEL);
200 struct spi_mem_op op;
201 int status;
202
203 if (!bounce)
204 return -ENOMEM;
205
206 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(AT25_RDSR, 1),
207 SPI_MEM_OP_NO_ADDR,
208 SPI_MEM_OP_NO_DUMMY,
209 SPI_MEM_OP_DATA_IN(1, bounce, 1));
210
211 read_poll_timeout(spi_mem_exec_op, status,
212 status || !(bounce[0] & AT25_SR_nRDY), false,
213 USEC_PER_MSEC, USEC_PER_MSEC * EE_TIMEOUT,
214 at25->spimem, &op);
215 if (status < 0)
216 return status;
217 if (!(bounce[0] & AT25_SR_nRDY))
218 return 0;
219
220 return bounce[0];
221}
222
223static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
224{
225 u8 *bounce __free(kfree) = kmalloc(min(count, io_limit), GFP_KERNEL);
226 struct at25_data *at25 = priv;
227 const char *buf = val;
228 unsigned int buf_size;
229 int status;
230
231 if (unlikely(off >= at25->chip.byte_len))
232 return -EFBIG;
233 if ((off + count) > at25->chip.byte_len)
234 count = at25->chip.byte_len - off;
235 if (unlikely(!count))
236 return -EINVAL;
237
238 buf_size = at25->chip.page_size;
239
240 if (!bounce)
241 return -ENOMEM;
242
243 /*
244 * For write, rollover is within the page ... so we write at
245 * most one page, then manually roll over to the next page.
246 */
247 guard(mutex)(T: &at25->lock);
248 do {
249 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(AT25_WREN, 1),
250 SPI_MEM_OP_NO_ADDR,
251 SPI_MEM_OP_NO_DUMMY,
252 SPI_MEM_OP_NO_DATA);
253 unsigned int segment;
254
255 status = spi_mem_exec_op(mem: at25->spimem, op: &op);
256 if (status < 0) {
257 dev_dbg(&at25->spimem->spi->dev, "WREN --> %d\n", status);
258 return status;
259 }
260
261 /* Write as much of a page as we can */
262 segment = buf_size - (off % buf_size);
263 if (segment > count)
264 segment = count;
265 if (segment > io_limit)
266 segment = io_limit;
267
268 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(at25_instr(at25, AT25_WRITE, off),
269 1),
270 SPI_MEM_OP_ADDR(at25->addrlen, off, 1),
271 SPI_MEM_OP_NO_DUMMY,
272 SPI_MEM_OP_DATA_OUT(segment, bounce, 1));
273
274 status = spi_mem_adjust_op_size(mem: at25->spimem, op: &op);
275 if (status)
276 return status;
277 segment = op.data.nbytes;
278
279 memcpy(bounce, buf, segment);
280
281 status = spi_mem_exec_op(mem: at25->spimem, op: &op);
282 dev_dbg(&at25->spimem->spi->dev, "write %u bytes at %u --> %d\n",
283 segment, off, status);
284 if (status)
285 return status;
286
287 /*
288 * REVISIT this should detect (or prevent) failed writes
289 * to read-only sections of the EEPROM...
290 */
291
292 status = at25_wait_ready(at25);
293 if (status < 0) {
294 dev_err_probe(dev: &at25->spimem->spi->dev, err: status,
295 fmt: "Read Status Redister command failed\n");
296 return status;
297 }
298 if (status) {
299 dev_dbg(&at25->spimem->spi->dev,
300 "Status %02x\n", status);
301 dev_err(&at25->spimem->spi->dev,
302 "write %u bytes offset %u, timeout after %u msecs\n",
303 segment, off, EE_TIMEOUT);
304 return -ETIMEDOUT;
305 }
306
307 off += segment;
308 buf += segment;
309 count -= segment;
310
311 } while (count > 0);
312
313 return status;
314}
315
316/*-------------------------------------------------------------------------*/
317
318static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
319{
320 u32 val;
321 int err;
322
323 strscpy(chip->name, "at25", sizeof(chip->name));
324
325 err = device_property_read_u32(dev, propname: "size", val: &val);
326 if (err)
327 err = device_property_read_u32(dev, propname: "at25,byte-len", val: &val);
328 if (err) {
329 dev_err(dev, "Error: missing \"size\" property\n");
330 return err;
331 }
332 chip->byte_len = val;
333
334 err = device_property_read_u32(dev, propname: "pagesize", val: &val);
335 if (err)
336 err = device_property_read_u32(dev, propname: "at25,page-size", val: &val);
337 if (err) {
338 dev_err(dev, "Error: missing \"pagesize\" property\n");
339 return err;
340 }
341 chip->page_size = val;
342
343 err = device_property_read_u32(dev, propname: "address-width", val: &val);
344 if (err) {
345 err = device_property_read_u32(dev, propname: "at25,addr-mode", val: &val);
346 if (err) {
347 dev_err(dev, "Error: missing \"address-width\" property\n");
348 return err;
349 }
350 chip->flags = (u16)val;
351 } else {
352 switch (val) {
353 case 9:
354 chip->flags |= EE_INSTR_BIT3_IS_ADDR;
355 fallthrough;
356 case 8:
357 chip->flags |= EE_ADDR1;
358 break;
359 case 16:
360 chip->flags |= EE_ADDR2;
361 break;
362 case 24:
363 chip->flags |= EE_ADDR3;
364 break;
365 default:
366 dev_err(dev,
367 "Error: bad \"address-width\" property: %u\n",
368 val);
369 return -ENODEV;
370 }
371 if (device_property_present(dev, propname: "read-only"))
372 chip->flags |= EE_READONLY;
373 }
374 return 0;
375}
376
377static int at25_fram_to_chip(struct device *dev, struct spi_eeprom *chip)
378{
379 struct at25_data *at25 = container_of(chip, struct at25_data, chip);
380 u8 sernum[FM25_SN_LEN];
381 u8 id[FM25_ID_LEN];
382 u32 val;
383 int i;
384
385 strscpy(chip->name, "fm25", sizeof(chip->name));
386
387 if (!device_property_read_u32(dev, propname: "size", val: &val)) {
388 chip->byte_len = val;
389 } else {
390 /* Get ID of chip */
391 fm25_aux_read(at25, buf: id, FM25_RDID, FM25_ID_LEN);
392 /* There are inside-out FRAM variations, detect them and reverse the ID bytes */
393 if (id[6] == 0x7f && id[2] == 0xc2)
394 for (i = 0; i < ARRAY_SIZE(id) / 2; i++) {
395 u8 tmp = id[i];
396 int j = ARRAY_SIZE(id) - i - 1;
397
398 id[i] = id[j];
399 id[j] = tmp;
400 }
401 if (id[6] != 0xc2) {
402 dev_err(dev, "Error: no Cypress FRAM with device ID (manufacturer ID bank 7: %02x)\n", id[6]);
403 return -ENODEV;
404 }
405
406 switch (id[7]) {
407 case 0x21 ... 0x26:
408 chip->byte_len = BIT(id[7] - 0x21 + 4) * 1024;
409 break;
410 case 0x2a ... 0x30:
411 /* CY15B102QN ... CY15B116QN */
412 chip->byte_len = BIT(((id[7] >> 1) & 0xf) + 13);
413 break;
414 default:
415 dev_err(dev, "Error: unsupported size (id %02x)\n", id[7]);
416 return -ENODEV;
417 }
418
419 if (id[8]) {
420 fm25_aux_read(at25, buf: sernum, FM25_RDSN, FM25_SN_LEN);
421 /* Swap byte order */
422 for (i = 0; i < FM25_SN_LEN; i++)
423 at25->sernum[i] = sernum[FM25_SN_LEN - 1 - i];
424 }
425 }
426
427 if (chip->byte_len > 64 * 1024)
428 chip->flags |= EE_ADDR3;
429 else
430 chip->flags |= EE_ADDR2;
431
432 chip->page_size = PAGE_SIZE;
433 return 0;
434}
435
436static const struct of_device_id at25_of_match[] = {
437 { .compatible = "atmel,at25" },
438 { .compatible = "cypress,fm25" },
439 { }
440};
441MODULE_DEVICE_TABLE(of, at25_of_match);
442
443static const struct spi_device_id at25_spi_ids[] = {
444 { .name = "at25" },
445 { .name = "fm25" },
446 { }
447};
448MODULE_DEVICE_TABLE(spi, at25_spi_ids);
449
450static int at25_probe(struct spi_mem *mem)
451{
452 struct spi_device *spi = mem->spi;
453 struct spi_eeprom *pdata;
454 struct at25_data *at25;
455 bool is_fram;
456 int err;
457
458 at25 = devm_kzalloc(dev: &spi->dev, size: sizeof(*at25), GFP_KERNEL);
459 if (!at25)
460 return -ENOMEM;
461
462 at25->spimem = mem;
463
464 /*
465 * Ping the chip ... the status register is pretty portable,
466 * unlike probing manufacturer IDs.
467 */
468 err = at25_wait_ready(at25);
469 if (err < 0)
470 return dev_err_probe(dev: &spi->dev, err, fmt: "Read Status Register command failed\n");
471 if (err) {
472 dev_err(&spi->dev, "Not ready (%02x)\n", err);
473 return -ENXIO;
474 }
475
476 mutex_init(&at25->lock);
477 spi_set_drvdata(spi, data: at25);
478
479 is_fram = fwnode_device_is_compatible(dev_fwnode(&spi->dev), compat: "cypress,fm25");
480
481 /* Chip description */
482 pdata = dev_get_platdata(dev: &spi->dev);
483 if (pdata) {
484 at25->chip = *pdata;
485 } else {
486 if (is_fram)
487 err = at25_fram_to_chip(dev: &spi->dev, chip: &at25->chip);
488 else
489 err = at25_fw_to_chip(dev: &spi->dev, chip: &at25->chip);
490 if (err)
491 return err;
492 }
493
494 /* For now we only support 8/16/24 bit addressing */
495 if (at25->chip.flags & EE_ADDR1)
496 at25->addrlen = 1;
497 else if (at25->chip.flags & EE_ADDR2)
498 at25->addrlen = 2;
499 else if (at25->chip.flags & EE_ADDR3)
500 at25->addrlen = 3;
501 else {
502 dev_dbg(&spi->dev, "unsupported address type\n");
503 return -EINVAL;
504 }
505
506 at25->nvmem_config.type = is_fram ? NVMEM_TYPE_FRAM : NVMEM_TYPE_EEPROM;
507 at25->nvmem_config.name = dev_name(dev: &spi->dev);
508 at25->nvmem_config.dev = &spi->dev;
509 at25->nvmem_config.read_only = at25->chip.flags & EE_READONLY;
510 at25->nvmem_config.root_only = true;
511 at25->nvmem_config.owner = THIS_MODULE;
512 at25->nvmem_config.compat = true;
513 at25->nvmem_config.base_dev = &spi->dev;
514 at25->nvmem_config.reg_read = at25_ee_read;
515 at25->nvmem_config.reg_write = at25_ee_write;
516 at25->nvmem_config.priv = at25;
517 at25->nvmem_config.stride = 1;
518 at25->nvmem_config.word_size = 1;
519 at25->nvmem_config.size = at25->chip.byte_len;
520
521 at25->nvmem = devm_nvmem_register(dev: &spi->dev, cfg: &at25->nvmem_config);
522 if (IS_ERR(ptr: at25->nvmem))
523 return PTR_ERR(ptr: at25->nvmem);
524
525 dev_info(&spi->dev, "%d %s %s %s%s, pagesize %u\n",
526 (at25->chip.byte_len < 1024) ?
527 at25->chip.byte_len : (at25->chip.byte_len / 1024),
528 (at25->chip.byte_len < 1024) ? "Byte" : "KByte",
529 at25->chip.name, is_fram ? "fram" : "eeprom",
530 (at25->chip.flags & EE_READONLY) ? " (readonly)" : "",
531 at25->chip.page_size);
532 return 0;
533}
534
535/*-------------------------------------------------------------------------*/
536
537static struct spi_mem_driver at25_driver = {
538 .spidrv = {
539 .driver = {
540 .name = "at25",
541 .of_match_table = at25_of_match,
542 .dev_groups = sernum_groups,
543 },
544 .id_table = at25_spi_ids,
545 },
546 .probe = at25_probe,
547};
548
549module_spi_mem_driver(at25_driver);
550
551MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
552MODULE_AUTHOR("David Brownell");
553MODULE_LICENSE("GPL");
554

source code of linux/drivers/misc/eeprom/at25.c