| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* Driver for Realtek PCI-Express card reader |
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| 3 | * |
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| 4 | * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. |
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| 5 | * |
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| 6 | * Author: |
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| 7 | * Ricky Wu <ricky_wu@realtek.com> |
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| 8 | */ |
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| 9 | #ifndef RTS5264_H |
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| 10 | #define RTS5264_H |
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| 11 | |
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| 12 | /*New add*/ |
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| 13 | #define rts5264_vendor_setting_valid(reg) ((reg) & 0x010000) |
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| 14 | #define rts5264_reg_to_aspm(reg) \ |
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| 15 | (((~(reg) >> 28) & 0x02) | (((reg) >> 28) & 0x01)) |
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| 16 | #define rts5264_reg_check_reverse_socket(reg) ((reg) & 0x04) |
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| 17 | #define rts5264_reg_check_wp_reverse(reg) ((reg) & 0x8000) |
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| 18 | #define rts5264_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 22) & 0x03) |
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| 19 | #define rts5264_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 16) & 0x03) |
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| 20 | #define rts5264_reg_to_rtd3(reg) ((reg) & 0x08) |
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| 21 | |
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| 22 | #define RTS5264_AUTOLOAD_CFG0 0xFF7B |
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| 23 | #define RTS5264_AUTOLOAD_CFG1 0xFF7C |
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| 24 | #define RTS5264_AUTOLOAD_CFG3 0xFF7E |
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| 25 | #define RTS5264_AUTOLOAD_CFG4 0xFF7F |
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| 26 | #define RTS5264_FORCE_PRSNT_LOW (1 << 6) |
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| 27 | #define RTS5264_AUX_CLK_16M_EN (1 << 5) |
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| 28 | #define RTS5264_F_HIGH_RC_MASK (1 << 4) |
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| 29 | #define RTS5264_F_HIGH_RC_1_6M (1 << 4) |
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| 30 | #define RTS5264_F_HIGH_RC_400K (0 << 4) |
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| 31 | |
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| 32 | /* SSC_CTL2 0xFC12 */ |
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| 33 | #define RTS5264_SSC_DEPTH_MASK 0x07 |
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| 34 | #define RTS5264_SSC_DEPTH_DISALBE 0x00 |
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| 35 | #define RTS5264_SSC_DEPTH_8M 0x01 |
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| 36 | #define RTS5264_SSC_DEPTH_4M 0x02 |
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| 37 | #define RTS5264_SSC_DEPTH_2M 0x03 |
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| 38 | #define RTS5264_SSC_DEPTH_1M 0x04 |
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| 39 | #define RTS5264_SSC_DEPTH_512K 0x05 |
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| 40 | #define RTS5264_SSC_DEPTH_256K 0x06 |
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| 41 | #define RTS5264_SSC_DEPTH_128K 0x07 |
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| 42 | |
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| 43 | #define RTS5264_CARD_CLK_SRC2 0xFC2F |
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| 44 | #define RTS5264_REG_BIG_KVCO_A 0x20 |
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| 45 | |
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| 46 | /* efuse control register*/ |
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| 47 | #define RTS5264_EFUSE_CTL 0xFC30 |
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| 48 | #define RTS5264_EFUSE_ENABLE 0x80 |
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| 49 | /* EFUSE_MODE: 0=READ 1=PROGRAM */ |
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| 50 | #define RTS5264_EFUSE_MODE_MASK 0x40 |
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| 51 | #define RTS5264_EFUSE_PROGRAM 0x40 |
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| 52 | |
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| 53 | #define RTS5264_EFUSE_ADDR 0xFC31 |
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| 54 | #define RTS5264_EFUSE_ADDR_MASK 0x3F |
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| 55 | |
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| 56 | #define RTS5264_EFUSE_WRITE_DATA 0xFC32 |
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| 57 | #define RTS5264_EFUSE_READ_DATA 0xFC34 |
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| 58 | |
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| 59 | #define RTS5264_SYS_DUMMY_1 0xFC35 |
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| 60 | #define RTS5264_REG_BIG_KVCO 0x04 |
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| 61 | |
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| 62 | /* DMACTL 0xFE2C */ |
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| 63 | #define RTS5264_DMA_PACK_SIZE_MASK 0x70 |
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| 64 | |
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| 65 | #define RTS5264_FW_CFG_INFO2 0xFF52 |
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| 66 | |
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| 67 | #define RTS5264_FW_CFG1 0xFF55 |
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| 68 | #define RTS5264_SYS_CLK_SEL_MCU_CLK (0x01<<7) |
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| 69 | #define RTS5264_CRC_CLK_SEL_MCU_CLK (0x01<<6) |
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| 70 | #define RTS5264_FAKE_MCU_CLOCK_GATING (0x01<<5) |
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| 71 | #define RTS5264_MCU_BUS_SEL_MASK (0x01<<4) |
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| 72 | |
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| 73 | /* FW status register */ |
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| 74 | #define RTS5264_FW_STATUS 0xFF56 |
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| 75 | #define RTS5264_EXPRESS_LINK_FAIL_MASK (0x01<<7) |
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| 76 | |
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| 77 | /* FW control register */ |
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| 78 | #define RTS5264_FW_CTL 0xFF5F |
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| 79 | #define RTS5264_INFORM_RTD3_COLD (0x01<<5) |
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| 80 | |
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| 81 | #define RTS5264_REG_FPDCTL 0xFF60 |
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| 82 | |
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| 83 | #define RTS5264_REG_LDO12_CFG 0xFF6E |
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| 84 | #define RTS5264_LDO12_SR_MASK (0x03<<6) |
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| 85 | #define RTS5264_LDO12_SR_1_0_MS (0x03<<6) |
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| 86 | #define RTS5264_LDO12_SR_0_5_MS (0x02<<6) |
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| 87 | #define RTS5264_LDO12_SR_0_2_5_MS (0x01<<6) |
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| 88 | #define RTS5264_LDO12_SR_0_0_MS (0x00<<6) |
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| 89 | #define RTS5264_LDO12_VO_TUNE_MASK (0x07<<1) |
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| 90 | #define RTS5264_LDO12_115 (0x03<<1) |
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| 91 | #define RTS5264_LDO12_120 (0x04<<1) |
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| 92 | #define RTS5264_LDO12_125 (0x05<<1) |
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| 93 | #define RTS5264_LDO12_130 (0x06<<1) |
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| 94 | #define RTS5264_LDO12_135 (0x07<<1) |
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| 95 | |
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| 96 | /* LDO control register */ |
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| 97 | #define RTS5264_CARD_PWR_CTL 0xFD50 |
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| 98 | #define RTS5264_SD_CLK_ISO (0x01<<7) |
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| 99 | #define RTS5264_PAD_SD_DAT_FW_CTRL (0x01<<6) |
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| 100 | #define RTS5264_PUPDC (0x01<<5) |
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| 101 | #define RTS5264_SD_CMD_ISO (0x01<<4) |
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| 102 | |
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| 103 | #define RTS5264_OCP_VDD3_CTL 0xFD89 |
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| 104 | #define SD_VDD3_DETECT_EN 0x08 |
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| 105 | #define SD_VDD3_OCP_INT_EN 0x04 |
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| 106 | #define SD_VDD3_OCP_INT_CLR 0x02 |
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| 107 | #define SD_VDD3_OC_CLR 0x01 |
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| 108 | |
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| 109 | #define RTS5264_OCP_VDD3_STS 0xFD8A |
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| 110 | #define SD_VDD3_OCP_DETECT 0x08 |
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| 111 | #define SD_VDD3_OC_NOW 0x04 |
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| 112 | #define SD_VDD3_OC_EVER 0x02 |
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| 113 | |
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| 114 | #define RTS5264_OVP_CTL 0xFD8D |
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| 115 | #define RTS5264_OVP_TIME_MASK 0xF0 |
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| 116 | #define RTS5264_OVP_TIME_DFT 0x50 |
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| 117 | #define RTS5264_OVP_DETECT_EN 0x08 |
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| 118 | #define RTS5264_OVP_INT_EN 0x04 |
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| 119 | #define RTS5264_OVP_INT_CLR 0x02 |
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| 120 | #define RTS5264_OVP_CLR 0x01 |
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| 121 | |
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| 122 | #define RTS5264_OVP_STS 0xFD8E |
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| 123 | #define RTS5264_OVP_GLTCH_TIME_MASK 0xF0 |
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| 124 | #define RTS5264_OVP_GLTCH_TIME_DFT 0x50 |
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| 125 | #define RTS5264_VOVER_DET 0x08 |
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| 126 | #define RTS5264_OVP_NOW 0x04 |
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| 127 | #define RTS5264_OVP_EVER 0x02 |
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| 128 | |
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| 129 | #define RTS5264_CMD_OE_START_EARLY 0xFDCB |
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| 130 | #define RTS5264_CMD_OE_EARLY_LEAVE 0x08 |
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| 131 | #define RTS5264_CMD_OE_EARLY_CYCLE_MASK 0x06 |
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| 132 | #define RTS5264_CMD_OE_EARLY_4CYCLE 0x06 |
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| 133 | #define RTS5264_CMD_OE_EARLY_3CYCLE 0x04 |
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| 134 | #define RTS5264_CMD_OE_EARLY_2CYCLE 0x02 |
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| 135 | #define RTS5264_CMD_OE_EARLY_1CYCLE 0x00 |
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| 136 | #define RTS5264_CMD_OE_EARLY_EN 0x01 |
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| 137 | |
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| 138 | #define RTS5264_DAT_OE_START_EARLY 0xFDCC |
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| 139 | #define RTS5264_DAT_OE_EARLY_LEAVE 0x08 |
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| 140 | #define RTS5264_DAT_OE_EARLY_CYCLE_MASK 0x06 |
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| 141 | #define RTS5264_DAT_OE_EARLY_4CYCLE 0x06 |
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| 142 | #define RTS5264_DAT_OE_EARLY_3CYCLE 0x04 |
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| 143 | #define RTS5264_DAT_OE_EARLY_2CYCLE 0x02 |
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| 144 | #define RTS5264_DAT_OE_EARLY_1CYCLE 0x00 |
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| 145 | #define RTS5264_DAT_OE_EARLY_EN 0x01 |
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| 146 | |
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| 147 | #define RTS5264_LDO1233318_POW_CTL 0xFF70 |
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| 148 | #define RTS5264_TUNE_REF_LDO3318 (0x03<<6) |
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| 149 | #define RTS5264_TUNE_REF_LDO3318_DFT (0x02<<6) |
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| 150 | #define RTS5264_LDO3318_POWERON (0x01<<3) |
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| 151 | #define RTS5264_LDO3_POWERON (0x01<<2) |
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| 152 | #define RTS5264_LDO2_POWERON (0x01<<1) |
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| 153 | #define RTS5264_LDO1_POWERON (0x01<<0) |
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| 154 | #define RTS5264_LDO_POWERON_MASK (0x0F<<0) |
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| 155 | |
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| 156 | #define RTS5264_DV3318_CFG 0xFF71 |
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| 157 | #define RTS5264_DV3318_TUNE_MASK (0x07<<4) |
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| 158 | #define RTS5264_DV3318_18 (0x02<<4) |
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| 159 | #define RTS5264_DV3318_19 (0x04<<4) |
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| 160 | #define RTS5264_DV3318_33 (0x07<<4) |
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| 161 | |
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| 162 | #define RTS5264_LDO1_CFG0 0xFF72 |
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| 163 | #define RTS5264_LDO1_OCP_THD_MASK (0x07 << 5) |
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| 164 | #define RTS5264_LDO1_OCP_EN (0x01 << 4) |
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| 165 | #define RTS5264_LDO1_OCP_LMT_THD_MASK (0x03 << 2) |
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| 166 | #define RTS5264_LDO1_OCP_LMT_EN (0x01 << 1) |
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| 167 | |
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| 168 | #define RTS5264_LDO1_OCP_THD_850 (0x00<<5) |
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| 169 | #define RTS5264_LDO1_OCP_THD_950 (0x01<<5) |
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| 170 | #define RTS5264_LDO1_OCP_THD_1050 (0x02<<5) |
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| 171 | #define RTS5264_LDO1_OCP_THD_1100 (0x03<<5) |
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| 172 | #define RTS5264_LDO1_OCP_THD_1150 (0x04<<5) |
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| 173 | #define RTS5264_LDO1_OCP_THD_1200 (0x05<<5) |
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| 174 | #define RTS5264_LDO1_OCP_THD_1300 (0x06<<5) |
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| 175 | #define RTS5264_LDO1_OCP_THD_1350 (0x07<<5) |
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| 176 | |
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| 177 | #define RTS5264_LDO1_LMT_THD_1700 (0x00<<2) |
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| 178 | #define RTS5264_LDO1_LMT_THD_1800 (0x01<<2) |
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| 179 | #define RTS5264_LDO1_LMT_THD_1900 (0x02<<2) |
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| 180 | #define RTS5264_LDO1_LMT_THD_2000 (0x03<<2) |
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| 181 | |
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| 182 | #define RTS5264_LDO1_CFG1 0xFF73 |
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| 183 | #define RTS5264_LDO1_TUNE_MASK (0x07<<1) |
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| 184 | #define RTS5264_LDO1_18 (0x05<<1) |
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| 185 | #define RTS5264_LDO1_33 (0x07<<1) |
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| 186 | #define RTS5264_LDO1_PWD_MASK (0x01<<0) |
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| 187 | |
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| 188 | #define RTS5264_LDO2_CFG0 0xFF74 |
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| 189 | #define RTS5264_LDO2_OCP_THD_MASK (0x07<<5) |
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| 190 | #define RTS5264_LDO2_OCP_EN (0x01<<4) |
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| 191 | #define RTS5264_LDO2_OCP_LMT_THD_MASK (0x03<<2) |
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| 192 | #define RTS5264_LDO2_OCP_LMT_EN (0x01<<1) |
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| 193 | |
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| 194 | #define RTS5264_LDO2_OCP_THD_750 (0x00<<5) |
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| 195 | #define RTS5264_LDO2_OCP_THD_850 (0x01<<5) |
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| 196 | #define RTS5264_LDO2_OCP_THD_900 (0x02<<5) |
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| 197 | #define RTS5264_LDO2_OCP_THD_950 (0x03<<5) |
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| 198 | #define RTS5264_LDO2_OCP_THD_1050 (0x04<<5) |
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| 199 | #define RTS5264_LDO2_OCP_THD_1100 (0x05<<5) |
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| 200 | #define RTS5264_LDO2_OCP_THD_1150 (0x06<<5) |
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| 201 | #define RTS5264_LDO2_OCP_THD_1200 (0x07<<5) |
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| 202 | |
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| 203 | #define RTS5264_LDO2_LMT_THD_1700 (0x00<<2) |
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| 204 | #define RTS5264_LDO2_LMT_THD_1800 (0x01<<2) |
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| 205 | #define RTS5264_LDO2_LMT_THD_1900 (0x02<<2) |
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| 206 | #define RTS5264_LDO2_LMT_THD_2000 (0x03<<2) |
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| 207 | |
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| 208 | #define RTS5264_LDO2_CFG1 0xFF75 |
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| 209 | #define RTS5264_LDO2_TUNE_MASK (0x07<<1) |
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| 210 | #define RTS5264_LDO2_18 (0x02<<1) |
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| 211 | #define RTS5264_LDO2_185 (0x03<<1) |
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| 212 | #define RTS5264_LDO2_19 (0x04<<1) |
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| 213 | #define RTS5264_LDO2_195 (0x05<<1) |
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| 214 | #define RTS5264_LDO2_33 (0x07<<1) |
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| 215 | #define RTS5264_LDO2_PWD_MASK (0x01<<0) |
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| 216 | |
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| 217 | #define RTS5264_LDO3_CFG0 0xFF76 |
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| 218 | #define RTS5264_LDO3_OCP_THD_MASK (0x07<<5) |
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| 219 | #define RTS5264_LDO3_OCP_EN (0x01<<4) |
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| 220 | #define RTS5264_LDO3_OCP_LMT_THD_MASK (0x03<<2) |
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| 221 | #define RTS5264_LDO3_OCP_LMT_EN (0x01<<1) |
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| 222 | |
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| 223 | #define RTS5264_LDO3_OCP_THD_610 (0x00<<5) |
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| 224 | #define RTS5264_LDO3_OCP_THD_630 (0x01<<5) |
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| 225 | #define RTS5264_LDO3_OCP_THD_670 (0x02<<5) |
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| 226 | #define RTS5264_LDO3_OCP_THD_710 (0x03<<5) |
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| 227 | #define RTS5264_LDO3_OCP_THD_750 (0x04<<5) |
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| 228 | #define RTS5264_LDO3_OCP_THD_770 (0x05<<5) |
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| 229 | #define RTS5264_LDO3_OCP_THD_810 (0x06<<5) |
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| 230 | #define RTS5264_LDO3_OCP_THD_850 (0x07<<5) |
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| 231 | |
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| 232 | #define RTS5264_LDO3_LMT_THD_1200 (0x00<<2) |
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| 233 | #define RTS5264_LDO3_LMT_THD_1300 (0x01<<2) |
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| 234 | #define RTS5264_LDO3_LMT_THD_1400 (0x02<<2) |
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| 235 | #define RTS5264_LDO3_LMT_THD_1500 (0x03<<2) |
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| 236 | |
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| 237 | #define RTS5264_LDO3_CFG1 0xFF77 |
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| 238 | #define RTS5264_LDO3_TUNE_MASK (0x07<<1) |
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| 239 | #define RTS5264_LDO3_12 (0x02<<1) |
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| 240 | #define RTS5264_LDO3_125 (0x03<<1) |
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| 241 | #define RTS5264_LDO3_13 (0x04<<1) |
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| 242 | #define RTS5264_LDO3_135 (0x05<<1) |
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| 243 | #define RTS5264_LDO3_33 (0x07<<1) |
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| 244 | #define RTS5264_LDO3_PWD_MASK (0x01<<0) |
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| 245 | |
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| 246 | #define RTS5264_REG_PME_FORCE_CTL 0xFF78 |
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| 247 | #define FORCE_PM_CONTROL 0x20 |
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| 248 | #define FORCE_PM_VALUE 0x10 |
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| 249 | #define REG_EFUSE_BYPASS 0x08 |
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| 250 | #define REG_EFUSE_POR 0x04 |
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| 251 | #define REG_EFUSE_POWER_MASK 0x03 |
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| 252 | #define REG_EFUSE_POWERON 0x03 |
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| 253 | #define REG_EFUSE_POWEROFF 0x00 |
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| 254 | |
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| 255 | #define RTS5264_PWR_CUT 0xFF81 |
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| 256 | #define RTS5264_CFG_MEM_PD 0xF0 |
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| 257 | |
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| 258 | #define RTS5264_OVP_DET 0xFF8A |
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| 259 | #define RTS5264_POW_VDET 0x04 |
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| 260 | #define RTS5264_TUNE_VROV_MASK 0x03 |
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| 261 | #define RTS5264_TUNE_VROV_2V 0x03 |
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| 262 | #define RTS5264_TUNE_VROV_1V8 0x02 |
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| 263 | #define RTS5264_TUNE_VROV_1V6 0x01 |
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| 264 | #define RTS5264_TUNE_VROV_1V4 0x00 |
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| 265 | |
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| 266 | #define RTS5264_CKMUX_MBIAS_PWR 0xFF8B |
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| 267 | #define RTS5264_NON_XTAL_SEL 0x80 |
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| 268 | #define RTS5264_POW_CKMUX 0x40 |
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| 269 | #define RTS5264_LVD_MASK 0x04 |
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| 270 | #define RTS5264_POW_PSW_MASK 0x03 |
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| 271 | #define RTS5264_POW_PSW_DFT 0x03 |
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| 272 | |
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| 273 | /* Single LUN, support SD/SD EXPRESS */ |
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| 274 | #define DEFAULT_SINGLE 0 |
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| 275 | #define SD_LUN 1 |
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| 276 | #define SD_EXPRESS_LUN 2 |
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| 277 | |
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| 278 | #define RTS5264_IC_VER_A 0 |
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| 279 | #define RTS5264_IC_VER_B 2 |
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| 280 | #define RTS5264_IC_VER_C 3 |
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| 281 | |
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| 282 | int rts5264_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, |
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| 283 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); |
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| 284 | |
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| 285 | #endif /* RTS5264_H */ |
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| 286 | |
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