1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (C) 2002 ARM Limited, All Rights Reserved.
4	*
5	* Interrupt architecture for the GIC:
6	*
7	* o There is one Interrupt Distributor, which receives interrupts
8	* from system devices and sends them to the Interrupt Controllers.
9	*
10	* o There is one CPU Interface per CPU, which sends interrupts sent
11	* by the Distributor, and interrupts generated locally, to the
12	* associated CPU. The base address of the CPU interface is usually
13	* aliased so that the same address points to different chips depending
14	* on the CPU it is accessed from.
15	*
16	* Note that IRQs 0-31 are special - they are local to each CPU.
17	* As such, the enable set/clear, pending set/clear and active bit
18	* registers are banked per-cpu for these sources.
19	*/
20	#include <linux/init.h>
21	#include <linux/kernel.h>
22	#include <linux/kstrtox.h>
23	#include <linux/err.h>
24	#include <linux/module.h>
25	#include <linux/list.h>
26	#include <linux/smp.h>
27	#include <linux/cpu.h>
28	#include <linux/cpu_pm.h>
29	#include <linux/cpumask.h>
30	#include <linux/io.h>
31	#include <linux/of.h>
32	#include <linux/of_address.h>
33	#include <linux/of_irq.h>
34	#include <linux/acpi.h>
35	#include <linux/irqdomain.h>
36	#include <linux/interrupt.h>
37	#include <linux/percpu.h>
38	#include <linux/seq_file.h>
39	#include <linux/slab.h>
40	#include <linux/irqchip.h>
41	#include <linux/irqchip/chained_irq.h>
42	#include <linux/irqchip/arm-gic.h>
43
44	#include <asm/cputype.h>
45	#include <asm/irq.h>
46	#include <asm/exception.h>
47	#include <asm/smp_plat.h>
48	#include <asm/virt.h>
49
50	#include "irq-gic-common.h"
51
52	#ifdef CONFIG_ARM64
53	#include <asm/cpufeature.h>
54
55	static void gic_check_cpu_features(void)
56	{
57	WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF),
58	TAINT_CPU_OUT_OF_SPEC,
59	"GICv3 system registers enabled, broken firmware!\n");
60	}
61	#else
62	#define gic_check_cpu_features() do { } while(0)
63	#endif
64
65	union gic_base {
66	void __iomem *common_base;
67	void __iomem * __percpu *percpu_base;
68	};
69
70	struct gic_chip_data {
71	union gic_base dist_base;
72	union gic_base cpu_base;
73	void __iomem *raw_dist_base;
74	void __iomem *raw_cpu_base;
75	u32 percpu_offset;
76	#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
77	u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
78	u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
79	u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
80	u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
81	u32 __percpu *saved_ppi_enable;
82	u32 __percpu *saved_ppi_active;
83	u32 __percpu *saved_ppi_conf;
84	#endif
85	struct irq_domain *domain;
86	unsigned int gic_irqs;
87	};
88
89	#ifdef CONFIG_BL_SWITCHER
90
91	static DEFINE_RAW_SPINLOCK(cpu_map_lock);
92
93	#define gic_lock_irqsave(f) \
94	raw_spin_lock_irqsave(&cpu_map_lock, (f))
95	#define gic_unlock_irqrestore(f) \
96	raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
97
98	#define gic_lock() raw_spin_lock(&cpu_map_lock)
99	#define gic_unlock() raw_spin_unlock(&cpu_map_lock)
100
101	#else
102
103	#define gic_lock_irqsave(f) do { (void)(f); } while(0)
104	#define gic_unlock_irqrestore(f) do { (void)(f); } while(0)
105
106	#define gic_lock() do { } while(0)
107	#define gic_unlock() do { } while(0)
108
109	#endif
110
111	static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
112
113	/*
114	* The GIC mapping of CPU interfaces does not necessarily match
115	* the logical CPU numbering. Let's use a mapping as returned
116	* by the GIC itself.
117	*/
118	#define NR_GIC_CPU_IF 8
119	static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
120
121	static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
122
123	static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
124
125	static struct gic_kvm_info gic_v2_kvm_info __initdata;
126
127	static DEFINE_PER_CPU(u32, sgi_intid);
128
129	#ifdef CONFIG_GIC_NON_BANKED
130	static DEFINE_STATIC_KEY_FALSE(frankengic_key);
131
132	static void enable_frankengic(void)
133	{
134	static_branch_enable(&frankengic_key);
135	}
136
137	static inline void __iomem *__get_base(union gic_base *base)
138	{
139	if (static_branch_unlikely(&frankengic_key))
140	return raw_cpu_read(*base->percpu_base);
141
142	return base->common_base;
143	}
144
145	#define gic_data_dist_base(d) __get_base(&(d)->dist_base)
146	#define gic_data_cpu_base(d) __get_base(&(d)->cpu_base)
147	#else
148	#define gic_data_dist_base(d) ((d)->dist_base.common_base)
149	#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
150	#define enable_frankengic() do { } while(0)
151	#endif
152
153	static inline void __iomem *gic_dist_base(struct irq_data *d)
154	{
155	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
156	return gic_data_dist_base(gic_data);
157	}
158
159	static inline void __iomem *gic_cpu_base(struct irq_data *d)
160	{
161	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
162	return gic_data_cpu_base(gic_data);
163	}
164
165	static inline bool cascading_gic_irq(struct irq_data *d)
166	{
167	void *data = irq_data_get_irq_handler_data(d);
168
169	/*
170	* If handler_data is set, this is a cascading interrupt, and
171	* it cannot possibly be forwarded.
172	*/
173	return data != NULL;
174	}
175
176	/*
177	* Routines to acknowledge, disable and enable interrupts
178	*/
179	static void gic_poke_irq(struct irq_data *d, u32 offset)
180	{
181	u32 mask = 1 << (irqd_to_hwirq(d) % 32);
182
183	writel_relaxed(mask, gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 32) * 4);
184	}
185
186	static int gic_peek_irq(struct irq_data *d, u32 offset)
187	{
188	u32 mask = 1 << (irqd_to_hwirq(d) % 32);
189
190	return !!(readl_relaxed(gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 32) * 4) & mask);
191	}
192
193	static void gic_mask_irq(struct irq_data *d)
194	{
195	gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
196	}
197
198	static void gic_eoimode1_mask_irq(struct irq_data *d)
199	{
200	gic_mask_irq(d);
201	/*
202	* When masking a forwarded interrupt, make sure it is
203	* deactivated as well.
204	*
205	* This ensures that an interrupt that is getting
206	* disabled/masked will not get "stuck", because there is
207	* noone to deactivate it (guest is being terminated).
208	*/
209	if (irqd_is_forwarded_to_vcpu(d))
210	gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
211	}
212
213	static void gic_unmask_irq(struct irq_data *d)
214	{
215	gic_poke_irq(d, GIC_DIST_ENABLE_SET);
216	}
217
218	static void gic_eoi_irq(struct irq_data *d)
219	{
220	irq_hw_number_t hwirq = irqd_to_hwirq(d);
221
222	if (hwirq < 16)
223	hwirq = this_cpu_read(sgi_intid);
224
225	writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
226	}
227
228	static void gic_eoimode1_eoi_irq(struct irq_data *d)
229	{
230	irq_hw_number_t hwirq = irqd_to_hwirq(d);
231
232	/* Do not deactivate an IRQ forwarded to a vcpu. */
233	if (irqd_is_forwarded_to_vcpu(d))
234	return;
235
236	if (hwirq < 16)
237	hwirq = this_cpu_read(sgi_intid);
238
239	writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
240	}
241
242	static int gic_irq_set_irqchip_state(struct irq_data *d,
243	enum irqchip_irq_state which, bool val)
244	{
245	u32 reg;
246
247	switch (which) {
248	case IRQCHIP_STATE_PENDING:
249	reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
250	break;
251
252	case IRQCHIP_STATE_ACTIVE:
253	reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
254	break;
255
256	case IRQCHIP_STATE_MASKED:
257	reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
258	break;
259
260	default:
261	return -EINVAL;
262	}
263
264	gic_poke_irq(d, offset: reg);
265	return 0;
266	}
267
268	static int gic_irq_get_irqchip_state(struct irq_data *d,
269	enum irqchip_irq_state which, bool *val)
270	{
271	switch (which) {
272	case IRQCHIP_STATE_PENDING:
273	*val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
274	break;
275
276	case IRQCHIP_STATE_ACTIVE:
277	*val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
278	break;
279
280	case IRQCHIP_STATE_MASKED:
281	*val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
282	break;
283
284	default:
285	return -EINVAL;
286	}
287
288	return 0;
289	}
290
291	static int gic_set_type(struct irq_data *d, unsigned int type)
292	{
293	irq_hw_number_t gicirq = irqd_to_hwirq(d);
294	void __iomem *base = gic_dist_base(d);
295	int ret;
296
297	/* Interrupt configuration for SGIs can't be changed */
298	if (gicirq < 16)
299	return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
300
301	/* SPIs have restrictions on the supported types */
302	if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
303	type != IRQ_TYPE_EDGE_RISING)
304	return -EINVAL;
305
306	ret = gic_configure_irq(irq: gicirq, type, base: base + GIC_DIST_CONFIG);
307	if (ret && gicirq < 32) {
308	/* Misconfigured PPIs are usually not fatal */
309	pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16);
310	ret = 0;
311	}
312
313	return ret;
314	}
315
316	static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
317	{
318	/* Only interrupts on the primary GIC can be forwarded to a vcpu. */
319	if (cascading_gic_irq(d) || irqd_to_hwirq(d) < 16)
320	return -EINVAL;
321
322	if (vcpu)
323	irqd_set_forwarded_to_vcpu(d);
324	else
325	irqd_clr_forwarded_to_vcpu(d);
326	return 0;
327	}
328
329	static int gic_retrigger(struct irq_data *data)
330	{
331	return !gic_irq_set_irqchip_state(d: data, which: IRQCHIP_STATE_PENDING, val: true);
332	}
333
334	static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
335	{
336	u32 irqstat, irqnr;
337	struct gic_chip_data *gic = &gic_data[0];
338	void __iomem *cpu_base = gic_data_cpu_base(gic);
339
340	do {
341	irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
342	irqnr = irqstat & GICC_IAR_INT_ID_MASK;
343
344	if (unlikely(irqnr >= 1020))
345	break;
346
347	if (static_branch_likely(&supports_deactivate_key))
348	writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
349	isb();
350
351	/*
352	* Ensure any shared data written by the CPU sending the IPI
353	* is read after we've read the ACK register on the GIC.
354	*
355	* Pairs with the write barrier in gic_ipi_send_mask
356	*/
357	if (irqnr <= 15) {
358	smp_rmb();
359
360	/*
361	* The GIC encodes the source CPU in GICC_IAR,
362	* leading to the deactivation to fail if not
363	* written back as is to GICC_EOI. Stash the INTID
364	* away for gic_eoi_irq() to write back. This only
365	* works because we don't nest SGIs...
366	*/
367	this_cpu_write(sgi_intid, irqstat);
368	}
369
370	generic_handle_domain_irq(gic->domain, irqnr);
371	} while (1);
372	}
373
374	static void gic_handle_cascade_irq(struct irq_desc *desc)
375	{
376	struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
377	struct irq_chip *chip = irq_desc_get_chip(desc);
378	unsigned int gic_irq;
379	unsigned long status;
380	int ret;
381
382	chained_irq_enter(chip, desc);
383
384	status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
385
386	gic_irq = (status & GICC_IAR_INT_ID_MASK);
387	if (gic_irq == GICC_INT_SPURIOUS)
388	goto out;
389
390	isb();
391	ret = generic_handle_domain_irq(domain: chip_data->domain, hwirq: gic_irq);
392	if (unlikely(ret))
393	handle_bad_irq(desc);
394	out:
395	chained_irq_exit(chip, desc);
396	}
397
398	static void gic_irq_print_chip(struct irq_data *d, struct seq_file *p)
399	{
400	struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
401
402	if (gic->domain->pm_dev)
403	seq_puts(m: p, s: gic->domain->pm_dev->of_node->name);
404	else
405	seq_printf(m: p, fmt: "GIC-%d", (int)(gic - &gic_data[0]));
406	}
407
408	void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
409	{
410	BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
411	irq_set_chained_handler_and_data(irq, handle: gic_handle_cascade_irq,
412	data: &gic_data[gic_nr]);
413	}
414
415	static u8 gic_get_cpumask(struct gic_chip_data *gic)
416	{
417	void __iomem *base = gic_data_dist_base(gic);
418	u32 mask, i;
419
420	for (i = mask = 0; i < 32; i += 4) {
421	mask = readl_relaxed(base + GIC_DIST_TARGET + i);
422	mask |= mask >> 16;
423	mask |= mask >> 8;
424	if (mask)
425	break;
426	}
427
428	if (!mask && num_possible_cpus() > 1)
429	pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
430
431	return mask;
432	}
433
434	static bool gic_check_gicv2(void __iomem *base)
435	{
436	u32 val = readl_relaxed(base + GIC_CPU_IDENT);
437	return (val & 0xff0fff) == 0x02043B;
438	}
439
440	static void gic_cpu_if_up(struct gic_chip_data *gic)
441	{
442	void __iomem *cpu_base = gic_data_cpu_base(gic);
443	u32 bypass = 0;
444	u32 mode = 0;
445	int i;
446
447	if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
448	mode = GIC_CPU_CTRL_EOImodeNS;
449
450	if (gic_check_gicv2(base: cpu_base))
451	for (i = 0; i < 4; i++)
452	writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
453
454	/*
455	* Preserve bypass disable bits to be written back later
456	*/
457	bypass = readl(addr: cpu_base + GIC_CPU_CTRL);
458	bypass &= GICC_DIS_BYPASS_MASK;
459
460	writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
461	}
462
463
464	static void gic_dist_init(struct gic_chip_data *gic)
465	{
466	unsigned int i;
467	u32 cpumask;
468	unsigned int gic_irqs = gic->gic_irqs;
469	void __iomem *base = gic_data_dist_base(gic);
470
471	writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
472
473	/*
474	* Set all global interrupts to this CPU only.
475	*/
476	cpumask = gic_get_cpumask(gic);
477	cpumask |= cpumask << 8;
478	cpumask |= cpumask << 16;
479	for (i = 32; i < gic_irqs; i += 4)
480	writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
481
482	gic_dist_config(base, gic_irqs, GICD_INT_DEF_PRI);
483
484	writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
485	}
486
487	static int gic_cpu_init(struct gic_chip_data *gic)
488	{
489	void __iomem *dist_base = gic_data_dist_base(gic);
490	void __iomem *base = gic_data_cpu_base(gic);
491	unsigned int cpu_mask, cpu = smp_processor_id();
492	int i;
493
494	/*
495	* Setting up the CPU map is only relevant for the primary GIC
496	* because any nested/secondary GICs do not directly interface
497	* with the CPU(s).
498	*/
499	if (gic == &gic_data[0]) {
500	/*
501	* Get what the GIC says our CPU mask is.
502	*/
503	if (WARN_ON(cpu >= NR_GIC_CPU_IF))
504	return -EINVAL;
505
506	gic_check_cpu_features();
507	cpu_mask = gic_get_cpumask(gic);
508	gic_cpu_map[cpu] = cpu_mask;
509
510	/*
511	* Clear our mask from the other map entries in case they're
512	* still undefined.
513	*/
514	for (i = 0; i < NR_GIC_CPU_IF; i++)
515	if (i != cpu)
516	gic_cpu_map[i] &= ~cpu_mask;
517	}
518
519	gic_cpu_config(base: dist_base, nr: 32, GICD_INT_DEF_PRI);
520
521	writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
522	gic_cpu_if_up(gic);
523
524	return 0;
525	}
526
527	int gic_cpu_if_down(unsigned int gic_nr)
528	{
529	void __iomem *cpu_base;
530	u32 val = 0;
531
532	if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
533	return -EINVAL;
534
535	cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
536	val = readl(addr: cpu_base + GIC_CPU_CTRL);
537	val &= ~GICC_ENABLE;
538	writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
539
540	return 0;
541	}
542
543	#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
544	/*
545	* Saves the GIC distributor registers during suspend or idle. Must be called
546	* with interrupts disabled but before powering down the GIC. After calling
547	* this function, no interrupts will be delivered by the GIC, and another
548	* platform-specific wakeup source must be enabled.
549	*/
550	void gic_dist_save(struct gic_chip_data *gic)
551	{
552	unsigned int gic_irqs;
553	void __iomem *dist_base;
554	int i;
555
556	if (WARN_ON(!gic))
557	return;
558
559	gic_irqs = gic->gic_irqs;
560	dist_base = gic_data_dist_base(gic);
561
562	if (!dist_base)
563	return;
564
565	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
566	gic->saved_spi_conf[i] =
567	readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
568
569	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
570	gic->saved_spi_target[i] =
571	readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
572
573	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
574	gic->saved_spi_enable[i] =
575	readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
576
577	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
578	gic->saved_spi_active[i] =
579	readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
580	}
581
582	/*
583	* Restores the GIC distributor registers during resume or when coming out of
584	* idle. Must be called before enabling interrupts. If a level interrupt
585	* that occurred while the GIC was suspended is still present, it will be
586	* handled normally, but any edge interrupts that occurred will not be seen by
587	* the GIC and need to be handled by the platform-specific wakeup source.
588	*/
589	void gic_dist_restore(struct gic_chip_data *gic)
590	{
591	unsigned int gic_irqs;
592	unsigned int i;
593	void __iomem *dist_base;
594
595	if (WARN_ON(!gic))
596	return;
597
598	gic_irqs = gic->gic_irqs;
599	dist_base = gic_data_dist_base(gic);
600
601	if (!dist_base)
602	return;
603
604	writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
605
606	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
607	writel_relaxed(gic->saved_spi_conf[i],
608	dist_base + GIC_DIST_CONFIG + i * 4);
609
610	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
611	writel_relaxed(REPEAT_BYTE_U32(GICD_INT_DEF_PRI),
612	dist_base + GIC_DIST_PRI + i * 4);
613
614	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
615	writel_relaxed(gic->saved_spi_target[i],
616	dist_base + GIC_DIST_TARGET + i * 4);
617
618	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
619	writel_relaxed(GICD_INT_EN_CLR_X32,
620	dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
621	writel_relaxed(gic->saved_spi_enable[i],
622	dist_base + GIC_DIST_ENABLE_SET + i * 4);
623	}
624
625	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
626	writel_relaxed(GICD_INT_EN_CLR_X32,
627	dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
628	writel_relaxed(gic->saved_spi_active[i],
629	dist_base + GIC_DIST_ACTIVE_SET + i * 4);
630	}
631
632	writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
633	}
634
635	void gic_cpu_save(struct gic_chip_data *gic)
636	{
637	int i;
638	u32 *ptr;
639	void __iomem *dist_base;
640	void __iomem *cpu_base;
641
642	if (WARN_ON(!gic))
643	return;
644
645	dist_base = gic_data_dist_base(gic);
646	cpu_base = gic_data_cpu_base(gic);
647
648	if (!dist_base || !cpu_base)
649	return;
650
651	ptr = raw_cpu_ptr(gic->saved_ppi_enable);
652	for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
653	ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
654
655	ptr = raw_cpu_ptr(gic->saved_ppi_active);
656	for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
657	ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
658
659	ptr = raw_cpu_ptr(gic->saved_ppi_conf);
660	for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
661	ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
662
663	}
664
665	void gic_cpu_restore(struct gic_chip_data *gic)
666	{
667	int i;
668	u32 *ptr;
669	void __iomem *dist_base;
670	void __iomem *cpu_base;
671
672	if (WARN_ON(!gic))
673	return;
674
675	dist_base = gic_data_dist_base(gic);
676	cpu_base = gic_data_cpu_base(gic);
677
678	if (!dist_base || !cpu_base)
679	return;
680
681	ptr = raw_cpu_ptr(gic->saved_ppi_enable);
682	for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
683	writel_relaxed(GICD_INT_EN_CLR_X32,
684	dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
685	writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
686	}
687
688	ptr = raw_cpu_ptr(gic->saved_ppi_active);
689	for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
690	writel_relaxed(GICD_INT_EN_CLR_X32,
691	dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
692	writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
693	}
694
695	ptr = raw_cpu_ptr(gic->saved_ppi_conf);
696	for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
697	writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
698
699	for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
700	writel_relaxed(REPEAT_BYTE_U32(GICD_INT_DEF_PRI),
701	dist_base + GIC_DIST_PRI + i * 4);
702
703	writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
704	gic_cpu_if_up(gic);
705	}
706
707	static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
708	{
709	int i;
710
711	for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
712	switch (cmd) {
713	case CPU_PM_ENTER:
714	gic_cpu_save(&gic_data[i]);
715	break;
716	case CPU_PM_ENTER_FAILED:
717	case CPU_PM_EXIT:
718	gic_cpu_restore(&gic_data[i]);
719	break;
720	case CPU_CLUSTER_PM_ENTER:
721	gic_dist_save(&gic_data[i]);
722	break;
723	case CPU_CLUSTER_PM_ENTER_FAILED:
724	case CPU_CLUSTER_PM_EXIT:
725	gic_dist_restore(&gic_data[i]);
726	break;
727	}
728	}
729
730	return NOTIFY_OK;
731	}
732
733	static struct notifier_block gic_notifier_block = {
734	.notifier_call = gic_notifier,
735	};
736
737	static int gic_pm_init(struct gic_chip_data *gic)
738	{
739	gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
740	sizeof(u32));
741	if (WARN_ON(!gic->saved_ppi_enable))
742	return -ENOMEM;
743
744	gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
745	sizeof(u32));
746	if (WARN_ON(!gic->saved_ppi_active))
747	goto free_ppi_enable;
748
749	gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
750	sizeof(u32));
751	if (WARN_ON(!gic->saved_ppi_conf))
752	goto free_ppi_active;
753
754	if (gic == &gic_data[0])
755	cpu_pm_register_notifier(&gic_notifier_block);
756
757	return 0;
758
759	free_ppi_active:
760	free_percpu(gic->saved_ppi_active);
761	free_ppi_enable:
762	free_percpu(gic->saved_ppi_enable);
763
764	return -ENOMEM;
765	}
766	#else
767	static int gic_pm_init(struct gic_chip_data *gic)
768	{
769	return 0;
770	}
771	#endif
772
773	#ifdef CONFIG_SMP
774	static void rmw_writeb(u8 bval, void __iomem *addr)
775	{
776	static DEFINE_RAW_SPINLOCK(rmw_lock);
777	unsigned long offset = (unsigned long)addr & 3UL;
778	unsigned long shift = offset * 8;
779	unsigned long flags;
780	u32 val;
781
782	raw_spin_lock_irqsave(&rmw_lock, flags);
783
784	addr -= offset;
785	val = readl_relaxed(addr);
786	val &= ~GENMASK(shift + 7, shift);
787	val |= bval << shift;
788	writel_relaxed(val, addr);
789
790	raw_spin_unlock_irqrestore(&rmw_lock, flags);
791	}
792
793	static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
794	bool force)
795	{
796	void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + irqd_to_hwirq(d);
797	struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
798	unsigned int cpu;
799
800	if (unlikely(gic != &gic_data[0]))
801	return -EINVAL;
802
803	if (!force)
804	cpu = cpumask_any_and(mask_val, cpu_online_mask);
805	else
806	cpu = cpumask_first(srcp: mask_val);
807
808	if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
809	return -EINVAL;
810
811	if (static_branch_unlikely(&needs_rmw_access))
812	rmw_writeb(bval: gic_cpu_map[cpu], addr: reg);
813	else
814	writeb_relaxed(gic_cpu_map[cpu], reg);
815	irq_data_update_effective_affinity(d, cpumask_of(cpu));
816
817	return IRQ_SET_MASK_OK_DONE;
818	}
819
820	static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
821	{
822	int cpu;
823	unsigned long flags, map = 0;
824
825	if (unlikely(nr_cpu_ids == 1)) {
826	/* Only one CPU? let's do a self-IPI... */
827	writel_relaxed(2 << 24 | d->hwirq,
828	gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
829	return;
830	}
831
832	gic_lock_irqsave(flags);
833
834	/* Convert our logical CPU mask into a physical one. */
835	for_each_cpu(cpu, mask)
836	map |= gic_cpu_map[cpu];
837
838	/*
839	* Ensure that stores to Normal memory are visible to the
840	* other CPUs before they observe us issuing the IPI.
841	*/
842	dmb(ishst);
843
844	/* this always happens on GIC0 */
845	writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
846
847	gic_unlock_irqrestore(flags);
848	}
849
850	static int gic_starting_cpu(unsigned int cpu)
851	{
852	gic_cpu_init(gic: &gic_data[0]);
853	return 0;
854	}
855
856	static __init void gic_smp_init(void)
857	{
858	struct irq_fwspec sgi_fwspec = {
859	.fwnode = gic_data[0].domain->fwnode,
860	.param_count = 1,
861	};
862	int base_sgi;
863
864	cpuhp_setup_state_nocalls(state: CPUHP_AP_IRQ_GIC_STARTING,
865	name: "irqchip/arm/gic:starting",
866	startup: gic_starting_cpu, NULL);
867
868	base_sgi = irq_domain_alloc_irqs(domain: gic_data[0].domain, nr_irqs: 8, NUMA_NO_NODE, arg: &sgi_fwspec);
869	if (WARN_ON(base_sgi <= 0))
870	return;
871
872	set_smp_ipi_range(base_sgi, 8);
873	}
874	#else
875	#define gic_smp_init() do { } while(0)
876	#define gic_set_affinity NULL
877	#define gic_ipi_send_mask NULL
878	#endif
879
880	static const struct irq_chip gic_chip = {
881	.irq_mask = gic_mask_irq,
882	.irq_unmask = gic_unmask_irq,
883	.irq_eoi = gic_eoi_irq,
884	.irq_set_type = gic_set_type,
885	.irq_retrigger = gic_retrigger,
886	.irq_set_affinity = gic_set_affinity,
887	.ipi_send_mask = gic_ipi_send_mask,
888	.irq_get_irqchip_state = gic_irq_get_irqchip_state,
889	.irq_set_irqchip_state = gic_irq_set_irqchip_state,
890	.irq_print_chip = gic_irq_print_chip,
891	.flags = IRQCHIP_SET_TYPE_MASKED |
892	IRQCHIP_SKIP_SET_WAKE |
893	IRQCHIP_MASK_ON_SUSPEND,
894	};
895
896	static const struct irq_chip gic_chip_mode1 = {
897	.name = "GICv2",
898	.irq_mask = gic_eoimode1_mask_irq,
899	.irq_unmask = gic_unmask_irq,
900	.irq_eoi = gic_eoimode1_eoi_irq,
901	.irq_set_type = gic_set_type,
902	.irq_retrigger = gic_retrigger,
903	.irq_set_affinity = gic_set_affinity,
904	.ipi_send_mask = gic_ipi_send_mask,
905	.irq_get_irqchip_state = gic_irq_get_irqchip_state,
906	.irq_set_irqchip_state = gic_irq_set_irqchip_state,
907	.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
908	.flags = IRQCHIP_SET_TYPE_MASKED |
909	IRQCHIP_SKIP_SET_WAKE |
910	IRQCHIP_MASK_ON_SUSPEND,
911	};
912
913	#ifdef CONFIG_BL_SWITCHER
914	/*
915	* gic_send_sgi - send a SGI directly to given CPU interface number
916	*
917	* cpu_id: the ID for the destination CPU interface
918	* irq: the IPI number to send a SGI for
919	*/
920	void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
921	{
922	BUG_ON(cpu_id >= NR_GIC_CPU_IF);
923	cpu_id = 1 << cpu_id;
924	/* this always happens on GIC0 */
925	writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
926	}
927
928	/*
929	* gic_get_cpu_id - get the CPU interface ID for the specified CPU
930	*
931	* @cpu: the logical CPU number to get the GIC ID for.
932	*
933	* Return the CPU interface ID for the given logical CPU number,
934	* or -1 if the CPU number is too large or the interface ID is
935	* unknown (more than one bit set).
936	*/
937	int gic_get_cpu_id(unsigned int cpu)
938	{
939	unsigned int cpu_bit;
940
941	if (cpu >= NR_GIC_CPU_IF)
942	return -1;
943	cpu_bit = gic_cpu_map[cpu];
944	if (cpu_bit & (cpu_bit - 1))
945	return -1;
946	return __ffs(cpu_bit);
947	}
948
949	/*
950	* gic_migrate_target - migrate IRQs to another CPU interface
951	*
952	* @new_cpu_id: the CPU target ID to migrate IRQs to
953	*
954	* Migrate all peripheral interrupts with a target matching the current CPU
955	* to the interface corresponding to @new_cpu_id. The CPU interface mapping
956	* is also updated. Targets to other CPU interfaces are unchanged.
957	* This must be called with IRQs locally disabled.
958	*/
959	void gic_migrate_target(unsigned int new_cpu_id)
960	{
961	unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
962	void __iomem *dist_base;
963	int i, ror_val, cpu = smp_processor_id();
964	u32 val, cur_target_mask, active_mask;
965
966	BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
967
968	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
969	if (!dist_base)
970	return;
971	gic_irqs = gic_data[gic_nr].gic_irqs;
972
973	cur_cpu_id = __ffs(gic_cpu_map[cpu]);
974	cur_target_mask = 0x01010101 << cur_cpu_id;
975	ror_val = (cur_cpu_id - new_cpu_id) & 31;
976
977	gic_lock();
978
979	/* Update the target interface for this logical CPU */
980	gic_cpu_map[cpu] = 1 << new_cpu_id;
981
982	/*
983	* Find all the peripheral interrupts targeting the current
984	* CPU interface and migrate them to the new CPU interface.
985	* We skip DIST_TARGET 0 to 7 as they are read-only.
986	*/
987	for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
988	val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
989	active_mask = val & cur_target_mask;
990	if (active_mask) {
991	val &= ~active_mask;
992	val |= ror32(active_mask, ror_val);
993	writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
994	}
995	}
996
997	gic_unlock();
998
999	/*
1000	* Now let's migrate and clear any potential SGIs that might be
1001	* pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
1002	* is a banked register, we can only forward the SGI using
1003	* GIC_DIST_SOFTINT. The original SGI source is lost but Linux
1004	* doesn't use that information anyway.
1005	*
1006	* For the same reason we do not adjust SGI source information
1007	* for previously sent SGIs by us to other CPUs either.
1008	*/
1009	for (i = 0; i < 16; i += 4) {
1010	int j;
1011	val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
1012	if (!val)
1013	continue;
1014	writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
1015	for (j = i; j < i + 4; j++) {
1016	if (val & 0xff)
1017	writel_relaxed((1 << (new_cpu_id + 16)) | j,
1018	dist_base + GIC_DIST_SOFTINT);
1019	val >>= 8;
1020	}
1021	}
1022	}
1023
1024	/*
1025	* gic_get_sgir_physaddr - get the physical address for the SGI register
1026	*
1027	* Return the physical address of the SGI register to be used
1028	* by some early assembly code when the kernel is not yet available.
1029	*/
1030	static unsigned long gic_dist_physaddr;
1031
1032	unsigned long gic_get_sgir_physaddr(void)
1033	{
1034	if (!gic_dist_physaddr)
1035	return 0;
1036	return gic_dist_physaddr + GIC_DIST_SOFTINT;
1037	}
1038
1039	static void __init gic_init_physaddr(struct device_node *node)
1040	{
1041	struct resource res;
1042	if (of_address_to_resource(node, 0, &res) == 0) {
1043	gic_dist_physaddr = res.start;
1044	pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
1045	}
1046	}
1047
1048	#else
1049	#define gic_init_physaddr(node) do { } while (0)
1050	#endif
1051
1052	static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1053	irq_hw_number_t hw)
1054	{
1055	struct gic_chip_data *gic = d->host_data;
1056	struct irq_data *irqd = irq_desc_get_irq_data(desc: irq_to_desc(irq));
1057	const struct irq_chip *chip;
1058
1059	chip = (static_branch_likely(&supports_deactivate_key) &&
1060	gic == &gic_data[0]) ? &gic_chip_mode1 : &gic_chip;
1061
1062	switch (hw) {
1063	case 0 ... 31:
1064	irq_set_percpu_devid(irq);
1065	irq_domain_set_info(domain: d, virq: irq, hwirq: hw, chip, chip_data: d->host_data,
1066	handler: handle_percpu_devid_irq, NULL, NULL);
1067	break;
1068	default:
1069	irq_domain_set_info(domain: d, virq: irq, hwirq: hw, chip, chip_data: d->host_data,
1070	handler: handle_fasteoi_irq, NULL, NULL);
1071	irq_set_probe(irq);
1072	irqd_set_single_target(d: irqd);
1073	break;
1074	}
1075
1076	/* Prevents SW retriggers which mess up the ACK/EOI ordering */
1077	irqd_set_handle_enforce_irqctx(d: irqd);
1078	return 0;
1079	}
1080
1081	static int gic_irq_domain_translate(struct irq_domain *d,
1082	struct irq_fwspec *fwspec,
1083	unsigned long *hwirq,
1084	unsigned int *type)
1085	{
1086	if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1087	*hwirq = fwspec->param[0];
1088	*type = IRQ_TYPE_EDGE_RISING;
1089	return 0;
1090	}
1091
1092	if (is_of_node(fwnode: fwspec->fwnode)) {
1093	if (fwspec->param_count < 3)
1094	return -EINVAL;
1095
1096	switch (fwspec->param[0]) {
1097	case 0: /* SPI */
1098	*hwirq = fwspec->param[1] + 32;
1099	break;
1100	case 1: /* PPI */
1101	*hwirq = fwspec->param[1] + 16;
1102	break;
1103	default:
1104	return -EINVAL;
1105	}
1106
1107	*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1108
1109	/* Make it clear that broken DTs are... broken */
1110	WARN(*type == IRQ_TYPE_NONE,
1111	"HW irq %ld has invalid type\n", *hwirq);
1112	return 0;
1113	}
1114
1115	if (is_fwnode_irqchip(fwnode: fwspec->fwnode)) {
1116	if(fwspec->param_count != 2)
1117	return -EINVAL;
1118
1119	if (fwspec->param[0] < 16) {
1120	pr_err(FW_BUG "Illegal GSI%d translation request\n",
1121	fwspec->param[0]);
1122	return -EINVAL;
1123	}
1124
1125	*hwirq = fwspec->param[0];
1126	*type = fwspec->param[1];
1127
1128	WARN(*type == IRQ_TYPE_NONE,
1129	"HW irq %ld has invalid type\n", *hwirq);
1130	return 0;
1131	}
1132
1133	return -EINVAL;
1134	}
1135
1136	static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1137	unsigned int nr_irqs, void *arg)
1138	{
1139	int i, ret;
1140	irq_hw_number_t hwirq;
1141	unsigned int type = IRQ_TYPE_NONE;
1142	struct irq_fwspec *fwspec = arg;
1143
1144	ret = gic_irq_domain_translate(d: domain, fwspec, hwirq: &hwirq, type: &type);
1145	if (ret)
1146	return ret;
1147
1148	for (i = 0; i < nr_irqs; i++) {
1149	ret = gic_irq_domain_map(d: domain, irq: virq + i, hw: hwirq + i);
1150	if (ret)
1151	return ret;
1152	}
1153
1154	return 0;
1155	}
1156
1157	static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1158	.translate = gic_irq_domain_translate,
1159	.alloc = gic_irq_domain_alloc,
1160	.free = irq_domain_free_irqs_top,
1161	};
1162
1163	static int gic_init_bases(struct gic_chip_data *gic,
1164	struct fwnode_handle *handle)
1165	{
1166	int gic_irqs, ret;
1167
1168	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1169	/* Frankein-GIC without banked registers... */
1170	unsigned int cpu;
1171
1172	gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1173	gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1174	if (WARN_ON(!gic->dist_base.percpu_base ||
1175	!gic->cpu_base.percpu_base)) {
1176	ret = -ENOMEM;
1177	goto error;
1178	}
1179
1180	for_each_possible_cpu(cpu) {
1181	u32 mpidr = cpu_logical_map(cpu);
1182	u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1183	unsigned long offset = gic->percpu_offset * core_id;
1184	*per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1185	gic->raw_dist_base + offset;
1186	*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1187	gic->raw_cpu_base + offset;
1188	}
1189
1190	enable_frankengic();
1191	} else {
1192	/* Normal, sane GIC... */
1193	WARN(gic->percpu_offset,
1194	"GIC_NON_BANKED not enabled, ignoring %08x offset!",
1195	gic->percpu_offset);
1196	gic->dist_base.common_base = gic->raw_dist_base;
1197	gic->cpu_base.common_base = gic->raw_cpu_base;
1198	}
1199
1200	/*
1201	* Find out how many interrupts are supported.
1202	* The GIC only supports up to 1020 interrupt sources.
1203	*/
1204	gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1205	gic_irqs = (gic_irqs + 1) * 32;
1206	if (gic_irqs > 1020)
1207	gic_irqs = 1020;
1208	gic->gic_irqs = gic_irqs;
1209
1210	gic->domain = irq_domain_create_linear(fwnode: handle, size: gic_irqs,
1211	ops: &gic_irq_domain_hierarchy_ops,
1212	host_data: gic);
1213	if (WARN_ON(!gic->domain)) {
1214	ret = -ENODEV;
1215	goto error;
1216	}
1217
1218	gic_dist_init(gic);
1219	ret = gic_cpu_init(gic);
1220	if (ret)
1221	goto error;
1222
1223	ret = gic_pm_init(gic);
1224	if (ret)
1225	goto error;
1226
1227	return 0;
1228
1229	error:
1230	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1231	free_percpu(pdata: gic->dist_base.percpu_base);
1232	free_percpu(pdata: gic->cpu_base.percpu_base);
1233	}
1234
1235	return ret;
1236	}
1237
1238	static int __init __gic_init_bases(struct gic_chip_data *gic,
1239	struct fwnode_handle *handle)
1240	{
1241	int i, ret;
1242
1243	if (WARN_ON(!gic || gic->domain))
1244	return -EINVAL;
1245
1246	if (gic == &gic_data[0]) {
1247	/*
1248	* Initialize the CPU interface map to all CPUs.
1249	* It will be refined as each CPU probes its ID.
1250	* This is only necessary for the primary GIC.
1251	*/
1252	for (i = 0; i < NR_GIC_CPU_IF; i++)
1253	gic_cpu_map[i] = 0xff;
1254
1255	set_handle_irq(gic_handle_irq);
1256	if (static_branch_likely(&supports_deactivate_key))
1257	pr_info("GIC: Using split EOI/Deactivate mode\n");
1258	}
1259
1260	ret = gic_init_bases(gic, handle);
1261	if (gic == &gic_data[0])
1262	gic_smp_init();
1263
1264	return ret;
1265	}
1266
1267	static void gic_teardown(struct gic_chip_data *gic)
1268	{
1269	if (WARN_ON(!gic))
1270	return;
1271
1272	if (gic->raw_dist_base)
1273	iounmap(addr: gic->raw_dist_base);
1274	if (gic->raw_cpu_base)
1275	iounmap(addr: gic->raw_cpu_base);
1276	}
1277
1278	static int gic_cnt __initdata;
1279	static bool gicv2_force_probe;
1280
1281	static int __init gicv2_force_probe_cfg(char *buf)
1282	{
1283	return kstrtobool(s: buf, res: &gicv2_force_probe);
1284	}
1285	early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
1286
1287	static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1288	{
1289	struct resource cpuif_res;
1290
1291	of_address_to_resource(dev: node, index: 1, r: &cpuif_res);
1292
1293	if (!is_hyp_mode_available())
1294	return false;
1295	if (resource_size(res: &cpuif_res) < SZ_8K) {
1296	void __iomem *alt;
1297	/*
1298	* Check for a stupid firmware that only exposes the
1299	* first page of a GICv2.
1300	*/
1301	if (!gic_check_gicv2(base: *base))
1302	return false;
1303
1304	if (!gicv2_force_probe) {
1305	pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
1306	return false;
1307	}
1308
1309	alt = ioremap(offset: cpuif_res.start, SZ_8K);
1310	if (!alt)
1311	return false;
1312	if (!gic_check_gicv2(base: alt + SZ_4K)) {
1313	/*
1314	* The first page was that of a GICv2, and
1315	* the second was *something*. Let's trust it
1316	* to be a GICv2, and update the mapping.
1317	*/
1318	pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
1319	&cpuif_res.start);
1320	iounmap(addr: *base);
1321	*base = alt;
1322	return true;
1323	}
1324
1325	/*
1326	* We detected *two* initial GICv2 pages in a
1327	* row. Could be a GICv2 aliased over two 64kB
1328	* pages. Update the resource, map the iospace, and
1329	* pray.
1330	*/
1331	iounmap(addr: alt);
1332	alt = ioremap(offset: cpuif_res.start, SZ_128K);
1333	if (!alt)
1334	return false;
1335	pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
1336	&cpuif_res.start);
1337	cpuif_res.end = cpuif_res.start + SZ_128K -1;
1338	iounmap(addr: *base);
1339	*base = alt;
1340	}
1341	if (resource_size(res: &cpuif_res) == SZ_128K) {
1342	/*
1343	* Verify that we have the first 4kB of a GICv2
1344	* aliased over the first 64kB by checking the
1345	* GICC_IIDR register on both ends.
1346	*/
1347	if (!gic_check_gicv2(base: *base) ||
1348	!gic_check_gicv2(base: *base + 0xf000))
1349	return false;
1350
1351	/*
1352	* Move the base up by 60kB, so that we have a 8kB
1353	* contiguous region, which allows us to use GICC_DIR
1354	* at its normal offset. Please pass me that bucket.
1355	*/
1356	*base += 0xf000;
1357	cpuif_res.start += 0xf000;
1358	pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1359	&cpuif_res.start);
1360	}
1361
1362	return true;
1363	}
1364
1365	static bool gic_enable_rmw_access(void *data)
1366	{
1367	/*
1368	* The EMEV2 class of machines has a broken interconnect, and
1369	* locks up on accesses that are less than 32bit. So far, only
1370	* the affinity setting requires it.
1371	*/
1372	if (of_machine_is_compatible(compat: "renesas,emev2")) {
1373	static_branch_enable(&needs_rmw_access);
1374	return true;
1375	}
1376
1377	return false;
1378	}
1379
1380	static const struct gic_quirk gic_quirks[] = {
1381	{
1382	.desc = "broken byte access",
1383	.compatible = "arm,pl390",
1384	.init = gic_enable_rmw_access,
1385	},
1386	{ },
1387	};
1388
1389	static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1390	{
1391	if (!gic || !node)
1392	return -EINVAL;
1393
1394	gic->raw_dist_base = of_iomap(node, index: 0);
1395	if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1396	goto error;
1397
1398	gic->raw_cpu_base = of_iomap(node, index: 1);
1399	if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1400	goto error;
1401
1402	if (of_property_read_u32(np: node, propname: "cpu-offset", out_value: &gic->percpu_offset))
1403	gic->percpu_offset = 0;
1404
1405	gic_enable_of_quirks(np: node, quirks: gic_quirks, data: gic);
1406
1407	return 0;
1408
1409	error:
1410	gic_teardown(gic);
1411
1412	return -ENOMEM;
1413	}
1414
1415	int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1416	{
1417	int ret;
1418
1419	if (!dev || !dev->of_node || !gic || !irq)
1420	return -EINVAL;
1421
1422	*gic = devm_kzalloc(dev, size: sizeof(**gic), GFP_KERNEL);
1423	if (!*gic)
1424	return -ENOMEM;
1425
1426	ret = gic_of_setup(gic: *gic, node: dev->of_node);
1427	if (ret)
1428	return ret;
1429
1430	ret = gic_init_bases(gic: *gic, handle: &dev->of_node->fwnode);
1431	if (ret) {
1432	gic_teardown(gic: *gic);
1433	return ret;
1434	}
1435
1436	irq_domain_set_pm_device(d: (*gic)->domain, dev);
1437	irq_set_chained_handler_and_data(irq, handle: gic_handle_cascade_irq, data: *gic);
1438
1439	return 0;
1440	}
1441
1442	static void __init gic_of_setup_kvm_info(struct device_node *node)
1443	{
1444	int ret;
1445	struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1446	struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1447
1448	gic_v2_kvm_info.type = GIC_V2;
1449
1450	gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, index: 0);
1451	if (!gic_v2_kvm_info.maint_irq)
1452	return;
1453
1454	ret = of_address_to_resource(dev: node, index: 2, r: vctrl_res);
1455	if (ret)
1456	return;
1457
1458	ret = of_address_to_resource(dev: node, index: 3, r: vcpu_res);
1459	if (ret)
1460	return;
1461
1462	gic_v2_kvm_info.gicc_base = gic_data[0].cpu_base.common_base;
1463
1464	if (static_branch_likely(&supports_deactivate_key))
1465	vgic_set_kvm_info(info: &gic_v2_kvm_info);
1466	}
1467
1468	int __init
1469	gic_of_init(struct device_node *node, struct device_node *parent)
1470	{
1471	struct gic_chip_data *gic;
1472	int irq, ret;
1473
1474	if (WARN_ON(!node))
1475	return -ENODEV;
1476
1477	if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1478	return -EINVAL;
1479
1480	gic = &gic_data[gic_cnt];
1481
1482	ret = gic_of_setup(gic, node);
1483	if (ret)
1484	return ret;
1485
1486	/*
1487	* Disable split EOI/Deactivate if either HYP is not available
1488	* or the CPU interface is too small.
1489	*/
1490	if (gic_cnt == 0 && !gic_check_eoimode(node, base: &gic->raw_cpu_base))
1491	static_branch_disable(&supports_deactivate_key);
1492
1493	ret = __gic_init_bases(gic, handle: &node->fwnode);
1494	if (ret) {
1495	gic_teardown(gic);
1496	return ret;
1497	}
1498
1499	if (!gic_cnt) {
1500	gic_init_physaddr(node);
1501	gic_of_setup_kvm_info(node);
1502	}
1503
1504	if (parent) {
1505	irq = irq_of_parse_and_map(node, index: 0);
1506	gic_cascade_irq(gic_nr: gic_cnt, irq);
1507	}
1508
1509	if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1510	gicv2m_init(parent_handle: &node->fwnode, parent: gic_data[gic_cnt].domain);
1511
1512	gic_cnt++;
1513	return 0;
1514	}
1515	IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1516	IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1517	IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1518	IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1519	IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1520	IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1521	IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1522	IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1523	IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1524
1525	#ifdef CONFIG_ACPI
1526	static struct
1527	{
1528	phys_addr_t cpu_phys_base;
1529	u32 maint_irq;
1530	int maint_irq_mode;
1531	phys_addr_t vctrl_base;
1532	phys_addr_t vcpu_base;
1533	} acpi_data __initdata;
1534
1535	static int __init
1536	gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header,
1537	const unsigned long end)
1538	{
1539	struct acpi_madt_generic_interrupt *processor;
1540	phys_addr_t gic_cpu_base;
1541	static int cpu_base_assigned;
1542
1543	processor = (struct acpi_madt_generic_interrupt *)header;
1544
1545	if (BAD_MADT_GICC_ENTRY(processor, end))
1546	return -EINVAL;
1547
1548	/*
1549	* There is no support for non-banked GICv1/2 register in ACPI spec.
1550	* All CPU interface addresses have to be the same.
1551	*/
1552	gic_cpu_base = processor->base_address;
1553	if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1554	return -EINVAL;
1555
1556	acpi_data.cpu_phys_base = gic_cpu_base;
1557	acpi_data.maint_irq = processor->vgic_interrupt;
1558	acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1559	ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1560	acpi_data.vctrl_base = processor->gich_base_address;
1561	acpi_data.vcpu_base = processor->gicv_base_address;
1562
1563	cpu_base_assigned = 1;
1564	return 0;
1565	}
1566
1567	/* The things you have to do to just *count* something... */
1568	static int __init acpi_dummy_func(union acpi_subtable_headers *header,
1569	const unsigned long end)
1570	{
1571	return 0;
1572	}
1573
1574	static bool __init acpi_gic_redist_is_present(void)
1575	{
1576	return acpi_table_parse_madt(id: ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1577	handler: acpi_dummy_func, max_entries: 0) > 0;
1578	}
1579
1580	static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1581	struct acpi_probe_entry *ape)
1582	{
1583	struct acpi_madt_generic_distributor *dist;
1584	dist = (struct acpi_madt_generic_distributor *)header;
1585
1586	return (dist->version == ape->driver_data &&
1587	(dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1588	!acpi_gic_redist_is_present()));
1589	}
1590
1591	#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1592	#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1593	#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1594	#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1595
1596	static void __init gic_acpi_setup_kvm_info(void)
1597	{
1598	int irq;
1599	struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1600	struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1601
1602	gic_v2_kvm_info.type = GIC_V2;
1603
1604	if (!acpi_data.vctrl_base)
1605	return;
1606
1607	vctrl_res->flags = IORESOURCE_MEM;
1608	vctrl_res->start = acpi_data.vctrl_base;
1609	vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1610
1611	if (!acpi_data.vcpu_base)
1612	return;
1613
1614	vcpu_res->flags = IORESOURCE_MEM;
1615	vcpu_res->start = acpi_data.vcpu_base;
1616	vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1617
1618	irq = acpi_register_gsi(NULL, gsi: acpi_data.maint_irq,
1619	triggering: acpi_data.maint_irq_mode,
1620	ACPI_ACTIVE_HIGH);
1621	if (irq <= 0)
1622	return;
1623
1624	gic_v2_kvm_info.maint_irq = irq;
1625	gic_v2_kvm_info.gicc_base = gic_data[0].cpu_base.common_base;
1626
1627	vgic_set_kvm_info(info: &gic_v2_kvm_info);
1628	}
1629
1630	static struct fwnode_handle *gsi_domain_handle;
1631
1632	static struct fwnode_handle *gic_v2_get_gsi_domain_id(u32 gsi)
1633	{
1634	return gsi_domain_handle;
1635	}
1636
1637	static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
1638	const unsigned long end)
1639	{
1640	struct acpi_madt_generic_distributor *dist;
1641	struct gic_chip_data *gic = &gic_data[0];
1642	int count, ret;
1643
1644	/* Collect CPU base addresses */
1645	count = acpi_table_parse_madt(id: ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1646	handler: gic_acpi_parse_madt_cpu, max_entries: 0);
1647	if (count <= 0) {
1648	pr_err("No valid GICC entries exist\n");
1649	return -EINVAL;
1650	}
1651
1652	gic->raw_cpu_base = ioremap(offset: acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1653	if (!gic->raw_cpu_base) {
1654	pr_err("Unable to map GICC registers\n");
1655	return -ENOMEM;
1656	}
1657
1658	dist = (struct acpi_madt_generic_distributor *)header;
1659	gic->raw_dist_base = ioremap(offset: dist->base_address,
1660	ACPI_GICV2_DIST_MEM_SIZE);
1661	if (!gic->raw_dist_base) {
1662	pr_err("Unable to map GICD registers\n");
1663	gic_teardown(gic);
1664	return -ENOMEM;
1665	}
1666
1667	/*
1668	* Disable split EOI/Deactivate if HYP is not available. ACPI
1669	* guarantees that we'll always have a GICv2, so the CPU
1670	* interface will always be the right size.
1671	*/
1672	if (!is_hyp_mode_available())
1673	static_branch_disable(&supports_deactivate_key);
1674
1675	/*
1676	* Initialize GIC instance zero (no multi-GIC support).
1677	*/
1678	gsi_domain_handle = irq_domain_alloc_fwnode(pa: &dist->base_address);
1679	if (!gsi_domain_handle) {
1680	pr_err("Unable to allocate domain handle\n");
1681	gic_teardown(gic);
1682	return -ENOMEM;
1683	}
1684
1685	ret = __gic_init_bases(gic, handle: gsi_domain_handle);
1686	if (ret) {
1687	pr_err("Failed to initialise GIC\n");
1688	irq_domain_free_fwnode(fwnode: gsi_domain_handle);
1689	gic_teardown(gic);
1690	return ret;
1691	}
1692
1693	acpi_set_irq_model(model: ACPI_IRQ_MODEL_GIC, fn: gic_v2_get_gsi_domain_id);
1694
1695	if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1696	gicv2m_init(NULL, parent: gic_data[0].domain);
1697
1698	if (static_branch_likely(&supports_deactivate_key))
1699	gic_acpi_setup_kvm_info();
1700
1701	return 0;
1702	}
1703	IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1704	gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1705	gic_v2_acpi_init);
1706	IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1707	gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1708	gic_v2_acpi_init);
1709	#endif
1710