1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
4 *
5 * Copyright (C) 2014-2024 Broadcom
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/init.h>
11#include <linux/slab.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/spinlock.h>
15#include <linux/of.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip.h>
23#include <linux/irqchip/chained_irq.h>
24
25struct brcmstb_intc_init_params {
26 irq_flow_handler_t handler;
27 int cpu_status;
28 int cpu_clear;
29 int cpu_mask_status;
30 int cpu_mask_set;
31 int cpu_mask_clear;
32};
33
34/* Register offsets in the L2 latched interrupt controller */
35static const struct brcmstb_intc_init_params l2_edge_intc_init = {
36 .handler = handle_edge_irq,
37 .cpu_status = 0x00,
38 .cpu_clear = 0x08,
39 .cpu_mask_status = 0x0c,
40 .cpu_mask_set = 0x10,
41 .cpu_mask_clear = 0x14
42};
43
44/* Register offsets in the L2 level interrupt controller */
45static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
46 .handler = handle_level_irq,
47 .cpu_status = 0x00,
48 .cpu_clear = -1, /* Register not present */
49 .cpu_mask_status = 0x04,
50 .cpu_mask_set = 0x08,
51 .cpu_mask_clear = 0x0C
52};
53
54/* L2 intc private data structure */
55struct brcmstb_l2_intc_data {
56 struct irq_domain *domain;
57 struct irq_chip_generic *gc;
58 int status_offset;
59 int mask_offset;
60 bool can_wake;
61 u32 saved_mask; /* for suspend/resume */
62};
63
64static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
65{
66 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
67 struct irq_chip *chip = irq_desc_get_chip(desc);
68 unsigned int irq;
69 u32 status;
70
71 chained_irq_enter(chip, desc);
72
73 status = irq_reg_readl(gc: b->gc, reg_offset: b->status_offset) &
74 ~(irq_reg_readl(gc: b->gc, reg_offset: b->mask_offset));
75
76 if (status == 0) {
77 raw_spin_lock(&desc->lock);
78 handle_bad_irq(desc);
79 raw_spin_unlock(&desc->lock);
80 goto out;
81 }
82
83 do {
84 irq = ffs(status) - 1;
85 status &= ~(1 << irq);
86 generic_handle_domain_irq(domain: b->domain, hwirq: irq);
87 } while (status);
88out:
89 /* Don't ack parent before all device writes are done */
90 wmb();
91
92 chained_irq_exit(chip, desc);
93}
94
95static void __brcmstb_l2_intc_suspend(struct irq_data *d, bool save)
96{
97 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
98 struct irq_chip_type *ct = irq_data_get_chip_type(d);
99 struct brcmstb_l2_intc_data *b = gc->private;
100
101 guard(raw_spinlock_irqsave)(l: &gc->lock);
102 /* Save the current mask */
103 if (save)
104 b->saved_mask = irq_reg_readl(gc, reg_offset: ct->regs.mask);
105
106 if (b->can_wake) {
107 /* Program the wakeup mask */
108 irq_reg_writel(gc, val: ~gc->wake_active, reg_offset: ct->regs.disable);
109 irq_reg_writel(gc, val: gc->wake_active, reg_offset: ct->regs.enable);
110 }
111}
112
113static void brcmstb_l2_intc_shutdown(struct irq_data *d)
114{
115 __brcmstb_l2_intc_suspend(d, save: false);
116}
117
118static void brcmstb_l2_intc_suspend(struct irq_data *d)
119{
120 __brcmstb_l2_intc_suspend(d, save: true);
121}
122
123static void brcmstb_l2_intc_resume(struct irq_data *d)
124{
125 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
126 struct irq_chip_type *ct = irq_data_get_chip_type(d);
127 struct brcmstb_l2_intc_data *b = gc->private;
128
129 guard(raw_spinlock_irqsave)(l: &gc->lock);
130 if (ct->chip.irq_ack) {
131 /* Clear unmasked non-wakeup interrupts */
132 irq_reg_writel(gc, val: ~b->saved_mask & ~gc->wake_active,
133 reg_offset: ct->regs.ack);
134 }
135
136 /* Restore the saved mask */
137 irq_reg_writel(gc, val: b->saved_mask, reg_offset: ct->regs.disable);
138 irq_reg_writel(gc, val: ~b->saved_mask, reg_offset: ct->regs.enable);
139}
140
141static int brcmstb_l2_intc_probe(struct platform_device *pdev, struct device_node *parent,
142 const struct brcmstb_intc_init_params *init_params)
143{
144 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
145 unsigned int set = 0;
146 struct device_node *np = pdev->dev.of_node;
147 struct brcmstb_l2_intc_data *data;
148 struct irq_chip_type *ct;
149 int ret;
150 unsigned int flags;
151 int parent_irq;
152 void __iomem *base;
153
154 data = kzalloc(sizeof(*data), GFP_KERNEL);
155 if (!data)
156 return -ENOMEM;
157
158 base = of_iomap(node: np, index: 0);
159 if (!base) {
160 pr_err("failed to remap intc L2 registers\n");
161 ret = -ENOMEM;
162 goto out_free;
163 }
164
165 /* Disable all interrupts by default */
166 writel(val: 0xffffffff, addr: base + init_params->cpu_mask_set);
167
168 /* Wakeup interrupts may be retained from S5 (cold boot) */
169 data->can_wake = of_property_read_bool(np, propname: "brcm,irq-can-wake");
170 if (!data->can_wake && (init_params->cpu_clear >= 0))
171 writel(val: 0xffffffff, addr: base + init_params->cpu_clear);
172
173 parent_irq = irq_of_parse_and_map(node: np, index: 0);
174 if (!parent_irq) {
175 pr_err("failed to find parent interrupt\n");
176 ret = -EINVAL;
177 goto out_unmap;
178 }
179
180 data->domain = irq_domain_create_linear(of_fwnode_handle(np), size: 32,
181 ops: &irq_generic_chip_ops, NULL);
182 if (!data->domain) {
183 ret = -ENOMEM;
184 goto out_unmap;
185 }
186
187 /* MIPS chips strapped for BE will automagically configure the
188 * peripheral registers for CPU-native byte order.
189 */
190 flags = 0;
191 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
192 flags |= IRQ_GC_BE_IO;
193
194 if (init_params->handler == handle_level_irq)
195 set |= IRQ_LEVEL;
196
197 /* Allocate a single Generic IRQ chip for this node */
198 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
199 np->full_name, init_params->handler, clr, set, flags);
200 if (ret) {
201 pr_err("failed to allocate generic irq chip\n");
202 goto out_free_domain;
203 }
204
205 /* Set the IRQ chaining logic */
206 irq_set_chained_handler_and_data(irq: parent_irq,
207 handle: brcmstb_l2_intc_irq_handle, data);
208
209 data->gc = irq_get_domain_generic_chip(d: data->domain, hw_irq: 0);
210 data->gc->reg_base = base;
211 data->gc->private = data;
212 data->status_offset = init_params->cpu_status;
213 data->mask_offset = init_params->cpu_mask_status;
214
215 ct = data->gc->chip_types;
216
217 if (init_params->cpu_clear >= 0) {
218 ct->regs.ack = init_params->cpu_clear;
219 ct->chip.irq_ack = irq_gc_ack_set_bit;
220 ct->chip.irq_mask_ack = irq_gc_mask_disable_and_ack_set;
221 } else {
222 /* No Ack - but still slightly more efficient to define this */
223 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
224 }
225
226 ct->chip.irq_mask = irq_gc_mask_disable_reg;
227 ct->regs.disable = init_params->cpu_mask_set;
228 ct->regs.mask = init_params->cpu_mask_status;
229
230 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
231 ct->regs.enable = init_params->cpu_mask_clear;
232
233 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
234 ct->chip.irq_resume = brcmstb_l2_intc_resume;
235 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_shutdown;
236
237 if (data->can_wake) {
238 /* This IRQ chip can wake the system, set all child interrupts
239 * in wake_enabled mask
240 */
241 data->gc->wake_enabled = 0xffffffff;
242 ct->chip.irq_set_wake = irq_gc_set_wake;
243 enable_irq_wake(irq: parent_irq);
244 }
245
246 pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
247
248 return 0;
249
250out_free_domain:
251 irq_domain_remove(domain: data->domain);
252out_unmap:
253 iounmap(addr: base);
254out_free:
255 kfree(objp: data);
256 return ret;
257}
258
259static int brcmstb_l2_edge_intc_probe(struct platform_device *pdev, struct device_node *parent)
260{
261 return brcmstb_l2_intc_probe(pdev, parent, init_params: &l2_edge_intc_init);
262}
263
264static int brcmstb_l2_lvl_intc_probe(struct platform_device *pdev, struct device_node *parent)
265{
266 return brcmstb_l2_intc_probe(pdev, parent, init_params: &l2_lvl_intc_init);
267}
268
269IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
270IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_probe)
271IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_probe)
272IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_probe)
273IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_probe)
274IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
275MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
276MODULE_LICENSE("GPL v2");
277

source code of linux/drivers/irqchip/irq-brcmstb-l2.c