1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2010 Broadcom
4 * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
5 *
6 * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
7 *
8 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
9 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
10 * to look in the bank 1 status register for more information.
11 *
12 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
13 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
14 * status register, but bank 0 bit 8 is _not_ set.
15 *
16 * Quirk 2: You can't mask the register 1/2 pending interrupts
17 *
18 * In a proper cascaded interrupt controller, the interrupt lines with
19 * cascaded interrupt controllers on them are just normal interrupt lines.
20 * You can mask the interrupts and get on with things. With this controller
21 * you can't do that.
22 *
23 * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
24 *
25 * Those interrupts that have shortcuts can only be masked/unmasked in
26 * their respective banks' enable/disable registers. Doing so in the bank 0
27 * enable/disable registers has no effect.
28 *
29 * The FIQ control register:
30 * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
31 * Bit 7: Enable FIQ generation
32 * Bits 8+: Unused
33 *
34 * An interrupt must be disabled before configuring it for FIQ generation
35 * otherwise both handlers will fire at the same time!
36 */
37
38#include <linux/io.h>
39#include <linux/slab.h>
40#include <linux/of_address.h>
41#include <linux/of_irq.h>
42#include <linux/irqchip.h>
43#include <linux/irqdomain.h>
44
45#include <asm/exception.h>
46
47/* Put the bank and irq (32 bits) into the hwirq */
48#define MAKE_HWIRQ(b, n) ((b << 5) | (n))
49#define HWIRQ_BANK(i) (i >> 5)
50#define HWIRQ_BIT(i) BIT(i & 0x1f)
51
52#define NR_IRQS_BANK0 8
53#define BANK0_HWIRQ_MASK 0xff
54/* Shortcuts can't be disabled so any unknown new ones need to be masked */
55#define SHORTCUT1_MASK 0x00007c00
56#define SHORTCUT2_MASK 0x001f8000
57#define SHORTCUT_SHIFT 10
58#define BANK1_HWIRQ BIT(8)
59#define BANK2_HWIRQ BIT(9)
60#define BANK0_VALID_MASK (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
61 | SHORTCUT1_MASK | SHORTCUT2_MASK)
62
63#define REG_FIQ_CONTROL 0x0c
64#define FIQ_CONTROL_ENABLE BIT(7)
65
66#define NR_BANKS 3
67#define IRQS_PER_BANK 32
68
69static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
70static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
71static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
72static const int bank_irqs[] __initconst = { 8, 32, 32 };
73
74static const int shortcuts[] = {
75 7, 9, 10, 18, 19, /* Bank 1 */
76 21, 22, 23, 24, 25, 30 /* Bank 2 */
77};
78
79struct armctrl_ic {
80 void __iomem *base;
81 void __iomem *pending[NR_BANKS];
82 void __iomem *enable[NR_BANKS];
83 void __iomem *disable[NR_BANKS];
84 struct irq_domain *domain;
85};
86
87static struct armctrl_ic intc __read_mostly;
88static void __exception_irq_entry bcm2835_handle_irq(
89 struct pt_regs *regs);
90static void bcm2836_chained_handle_irq(struct irq_desc *desc);
91
92static void armctrl_mask_irq(struct irq_data *d)
93{
94 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
95}
96
97static void armctrl_unmask_irq(struct irq_data *d)
98{
99 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
100}
101
102static struct irq_chip armctrl_chip = {
103 .name = "ARMCTRL-level",
104 .irq_mask = armctrl_mask_irq,
105 .irq_unmask = armctrl_unmask_irq,
106 .flags = IRQCHIP_MASK_ON_SUSPEND |
107 IRQCHIP_SKIP_SET_WAKE,
108};
109
110static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
111 const u32 *intspec, unsigned int intsize,
112 unsigned long *out_hwirq, unsigned int *out_type)
113{
114 if (WARN_ON(intsize != 2))
115 return -EINVAL;
116
117 if (WARN_ON(intspec[0] >= NR_BANKS))
118 return -EINVAL;
119
120 if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
121 return -EINVAL;
122
123 if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
124 return -EINVAL;
125
126 *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
127 *out_type = IRQ_TYPE_NONE;
128 return 0;
129}
130
131static const struct irq_domain_ops armctrl_ops = {
132 .xlate = armctrl_xlate
133};
134
135static int __init armctrl_of_init(struct device_node *node,
136 struct device_node *parent,
137 bool is_2836)
138{
139 void __iomem *base;
140 int irq, b, i;
141 u32 reg;
142
143 base = of_iomap(node, index: 0);
144 if (!base)
145 panic(fmt: "%pOF: unable to map IC registers\n", node);
146
147 intc.domain = irq_domain_create_linear(of_fwnode_handle(node), MAKE_HWIRQ(NR_BANKS, 0),
148 ops: &armctrl_ops, NULL);
149 if (!intc.domain)
150 panic(fmt: "%pOF: unable to create IRQ domain\n", node);
151
152 for (b = 0; b < NR_BANKS; b++) {
153 intc.pending[b] = base + reg_pending[b];
154 intc.enable[b] = base + reg_enable[b];
155 intc.disable[b] = base + reg_disable[b];
156
157 for (i = 0; i < bank_irqs[b]; i++) {
158 irq = irq_create_mapping(domain: intc.domain, MAKE_HWIRQ(b, i));
159 BUG_ON(irq <= 0);
160 irq_set_chip_and_handler(irq, chip: &armctrl_chip,
161 handle: handle_level_irq);
162 irq_set_probe(irq);
163 }
164
165 reg = readl_relaxed(intc.enable[b]);
166 if (reg) {
167 writel_relaxed(reg, intc.disable[b]);
168 pr_err(FW_BUG "Bootloader left irq enabled: "
169 "bank %d irq %*pbl\n", b, IRQS_PER_BANK, &reg);
170 }
171 }
172
173 reg = readl_relaxed(base + REG_FIQ_CONTROL);
174 if (reg & FIQ_CONTROL_ENABLE) {
175 writel_relaxed(0, base + REG_FIQ_CONTROL);
176 pr_err(FW_BUG "Bootloader left fiq enabled\n");
177 }
178
179 if (is_2836) {
180 int parent_irq = irq_of_parse_and_map(node, index: 0);
181
182 if (!parent_irq) {
183 panic(fmt: "%pOF: unable to get parent interrupt.\n",
184 node);
185 }
186 irq_set_chained_handler(irq: parent_irq, handle: bcm2836_chained_handle_irq);
187 } else {
188 set_handle_irq(bcm2835_handle_irq);
189 }
190
191 return 0;
192}
193
194static int __init bcm2835_armctrl_of_init(struct device_node *node,
195 struct device_node *parent)
196{
197 return armctrl_of_init(node, parent, is_2836: false);
198}
199
200static int __init bcm2836_armctrl_of_init(struct device_node *node,
201 struct device_node *parent)
202{
203 return armctrl_of_init(node, parent, is_2836: true);
204}
205
206
207/*
208 * Handle each interrupt across the entire interrupt controller. This reads the
209 * status register before handling each interrupt, which is necessary given that
210 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
211 */
212
213static u32 armctrl_translate_bank(int bank)
214{
215 u32 stat = readl_relaxed(intc.pending[bank]);
216
217 return MAKE_HWIRQ(bank, ffs(stat) - 1);
218}
219
220static u32 armctrl_translate_shortcut(int bank, u32 stat)
221{
222 return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
223}
224
225static u32 get_next_armctrl_hwirq(void)
226{
227 u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
228
229 if (stat == 0)
230 return ~0;
231 else if (stat & BANK0_HWIRQ_MASK)
232 return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
233 else if (stat & SHORTCUT1_MASK)
234 return armctrl_translate_shortcut(bank: 1, stat: stat & SHORTCUT1_MASK);
235 else if (stat & SHORTCUT2_MASK)
236 return armctrl_translate_shortcut(bank: 2, stat: stat & SHORTCUT2_MASK);
237 else if (stat & BANK1_HWIRQ)
238 return armctrl_translate_bank(bank: 1);
239 else if (stat & BANK2_HWIRQ)
240 return armctrl_translate_bank(bank: 2);
241 else
242 BUG();
243}
244
245static void __exception_irq_entry bcm2835_handle_irq(
246 struct pt_regs *regs)
247{
248 u32 hwirq;
249
250 while ((hwirq = get_next_armctrl_hwirq()) != ~0)
251 generic_handle_domain_irq(intc.domain, hwirq);
252}
253
254static void bcm2836_chained_handle_irq(struct irq_desc *desc)
255{
256 u32 hwirq;
257
258 while ((hwirq = get_next_armctrl_hwirq()) != ~0)
259 generic_handle_domain_irq(domain: intc.domain, hwirq);
260}
261
262IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
263 bcm2835_armctrl_of_init);
264IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
265 bcm2836_armctrl_of_init);
266

source code of linux/drivers/irqchip/irq-bcm2835.c