1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2024 Raspberry Pi Ltd., All Rights Reserved.
4 * Copyright (c) 2024 SUSE
5 */
6
7#include <linux/bitmap.h>
8#include <linux/irqchip.h>
9#include <linux/irqdomain.h>
10#include <linux/msi.h>
11#include <linux/of_address.h>
12#include <linux/of_platform.h>
13
14#include <linux/irqchip/irq-msi-lib.h>
15
16#define MIP_INT_RAISE 0x00
17#define MIP_INT_CLEAR 0x10
18#define MIP_INT_CFGL_HOST 0x20
19#define MIP_INT_CFGH_HOST 0x30
20#define MIP_INT_MASKL_HOST 0x40
21#define MIP_INT_MASKH_HOST 0x50
22#define MIP_INT_MASKL_VPU 0x60
23#define MIP_INT_MASKH_VPU 0x70
24#define MIP_INT_STATUSL_HOST 0x80
25#define MIP_INT_STATUSH_HOST 0x90
26#define MIP_INT_STATUSL_VPU 0xa0
27#define MIP_INT_STATUSH_VPU 0xb0
28
29/**
30 * struct mip_priv - MSI-X interrupt controller data
31 * @lock: Used to protect bitmap alloc/free
32 * @base: Base address of MMIO area
33 * @msg_addr: PCIe MSI-X address
34 * @msi_base: MSI base
35 * @num_msis: Count of MSIs
36 * @msi_offset: MSI offset
37 * @bitmap: A bitmap for hwirqs
38 * @parent: Parent domain (GIC)
39 * @dev: A device pointer
40 */
41struct mip_priv {
42 spinlock_t lock;
43 void __iomem *base;
44 u64 msg_addr;
45 u32 msi_base;
46 u32 num_msis;
47 u32 msi_offset;
48 unsigned long *bitmap;
49 struct irq_domain *parent;
50 struct device *dev;
51};
52
53static void mip_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
54{
55 struct mip_priv *mip = irq_data_get_irq_chip_data(d);
56
57 msg->address_hi = upper_32_bits(mip->msg_addr);
58 msg->address_lo = lower_32_bits(mip->msg_addr);
59 msg->data = d->hwirq;
60}
61
62static struct irq_chip mip_middle_irq_chip = {
63 .name = "MIP",
64 .irq_mask = irq_chip_mask_parent,
65 .irq_unmask = irq_chip_unmask_parent,
66 .irq_eoi = irq_chip_eoi_parent,
67 .irq_set_affinity = irq_chip_set_affinity_parent,
68 .irq_set_type = irq_chip_set_type_parent,
69 .irq_compose_msi_msg = mip_compose_msi_msg,
70};
71
72static int mip_alloc_hwirq(struct mip_priv *mip, unsigned int nr_irqs)
73{
74 guard(spinlock)(l: &mip->lock);
75 return bitmap_find_free_region(bitmap: mip->bitmap, bits: mip->num_msis, ilog2(nr_irqs));
76}
77
78static void mip_free_hwirq(struct mip_priv *mip, unsigned int hwirq,
79 unsigned int nr_irqs)
80{
81 guard(spinlock)(l: &mip->lock);
82 bitmap_release_region(bitmap: mip->bitmap, pos: hwirq, ilog2(nr_irqs));
83}
84
85static int mip_middle_domain_alloc(struct irq_domain *domain, unsigned int virq,
86 unsigned int nr_irqs, void *arg)
87{
88 struct mip_priv *mip = domain->host_data;
89 struct irq_fwspec fwspec = {0};
90 unsigned int hwirq, i;
91 struct irq_data *irqd;
92 int irq, ret;
93
94 irq = mip_alloc_hwirq(mip, nr_irqs);
95 if (irq < 0)
96 return irq;
97
98 hwirq = irq + mip->msi_offset;
99
100 fwspec.fwnode = domain->parent->fwnode;
101 fwspec.param_count = 3;
102 fwspec.param[0] = 0;
103 fwspec.param[1] = hwirq + mip->msi_base;
104 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
105
106 ret = irq_domain_alloc_irqs_parent(domain, irq_base: virq, nr_irqs, arg: &fwspec);
107 if (ret)
108 goto err_free_hwirq;
109
110 for (i = 0; i < nr_irqs; i++) {
111 irqd = irq_domain_get_irq_data(domain: domain->parent, virq: virq + i);
112 irqd->chip->irq_set_type(irqd, IRQ_TYPE_EDGE_RISING);
113
114 ret = irq_domain_set_hwirq_and_chip(domain, virq: virq + i, hwirq: hwirq + i,
115 chip: &mip_middle_irq_chip, chip_data: mip);
116 if (ret)
117 goto err_free;
118
119 irqd = irq_get_irq_data(irq: virq + i);
120 irqd_set_single_target(d: irqd);
121 irqd_set_affinity_on_activate(d: irqd);
122 }
123
124 return 0;
125
126err_free:
127 irq_domain_free_irqs_parent(domain, irq_base: virq, nr_irqs);
128err_free_hwirq:
129 mip_free_hwirq(mip, hwirq: irq, nr_irqs);
130 return ret;
131}
132
133static void mip_middle_domain_free(struct irq_domain *domain, unsigned int virq,
134 unsigned int nr_irqs)
135{
136 struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
137 struct mip_priv *mip;
138 unsigned int hwirq;
139
140 if (!irqd)
141 return;
142
143 mip = irq_data_get_irq_chip_data(d: irqd);
144 hwirq = irqd_to_hwirq(d: irqd);
145 irq_domain_free_irqs_parent(domain, irq_base: virq, nr_irqs);
146 mip_free_hwirq(mip, hwirq: hwirq - mip->msi_offset, nr_irqs);
147}
148
149static const struct irq_domain_ops mip_middle_domain_ops = {
150 .select = msi_lib_irq_domain_select,
151 .alloc = mip_middle_domain_alloc,
152 .free = mip_middle_domain_free,
153};
154
155#define MIP_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
156 MSI_FLAG_USE_DEF_CHIP_OPS | \
157 MSI_FLAG_PCI_MSI_MASK_PARENT)
158
159#define MIP_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \
160 MSI_FLAG_MULTI_PCI_MSI | \
161 MSI_FLAG_PCI_MSIX)
162
163static const struct msi_parent_ops mip_msi_parent_ops = {
164 .supported_flags = MIP_MSI_FLAGS_SUPPORTED,
165 .required_flags = MIP_MSI_FLAGS_REQUIRED,
166 .chip_flags = MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK,
167 .bus_select_token = DOMAIN_BUS_GENERIC_MSI,
168 .bus_select_mask = MATCH_PCI_MSI,
169 .prefix = "MIP-MSI-",
170 .init_dev_msi_info = msi_lib_init_dev_msi_info,
171};
172
173static int mip_init_domains(struct mip_priv *mip, struct device_node *np)
174{
175 struct irq_domain_info info = {
176 .fwnode = of_fwnode_handle(np),
177 .ops = &mip_middle_domain_ops,
178 .host_data = mip,
179 .size = mip->num_msis,
180 .parent = mip->parent,
181 .dev = mip->dev,
182 };
183
184 if (!msi_create_parent_irq_domain(info: &info, msi_parent_ops: &mip_msi_parent_ops))
185 return -ENOMEM;
186
187 /*
188 * All MSI-X unmasked for the host, masked for the VPU, and edge-triggered.
189 */
190 writel(val: 0, addr: mip->base + MIP_INT_MASKL_HOST);
191 writel(val: 0, addr: mip->base + MIP_INT_MASKH_HOST);
192 writel(val: ~0, addr: mip->base + MIP_INT_MASKL_VPU);
193 writel(val: ~0, addr: mip->base + MIP_INT_MASKH_VPU);
194 writel(val: ~0, addr: mip->base + MIP_INT_CFGL_HOST);
195 writel(val: ~0, addr: mip->base + MIP_INT_CFGH_HOST);
196
197 return 0;
198}
199
200static int mip_parse_dt(struct mip_priv *mip, struct device_node *np)
201{
202 struct of_phandle_args args;
203 u64 size;
204 int ret;
205
206 ret = of_property_read_u32(np, propname: "brcm,msi-offset", out_value: &mip->msi_offset);
207 if (ret)
208 mip->msi_offset = 0;
209
210 ret = of_parse_phandle_with_args(np, list_name: "msi-ranges", cells_name: "#interrupt-cells",
211 index: 0, out_args: &args);
212 if (ret)
213 return ret;
214
215 ret = of_property_read_u32_index(np, propname: "msi-ranges", index: args.args_count + 1,
216 out_value: &mip->num_msis);
217 if (ret)
218 goto err_put;
219
220 ret = of_property_read_reg(np, idx: 1, addr: &mip->msg_addr, size: &size);
221 if (ret)
222 goto err_put;
223
224 mip->msi_base = args.args[1];
225
226 mip->parent = irq_find_host(node: args.np);
227 if (!mip->parent)
228 ret = -EINVAL;
229
230err_put:
231 of_node_put(node: args.np);
232 return ret;
233}
234
235static int mip_msi_probe(struct platform_device *pdev, struct device_node *parent)
236{
237 struct device_node *node = pdev->dev.of_node;
238 struct mip_priv *mip;
239 int ret;
240
241 mip = kzalloc(sizeof(*mip), GFP_KERNEL);
242 if (!mip)
243 return -ENOMEM;
244
245 spin_lock_init(&mip->lock);
246 mip->dev = &pdev->dev;
247
248 ret = mip_parse_dt(mip, np: node);
249 if (ret)
250 goto err_priv;
251
252 mip->base = of_iomap(node, index: 0);
253 if (!mip->base) {
254 ret = -ENXIO;
255 goto err_priv;
256 }
257
258 mip->bitmap = bitmap_zalloc(nbits: mip->num_msis, GFP_KERNEL);
259 if (!mip->bitmap) {
260 ret = -ENOMEM;
261 goto err_base;
262 }
263
264 ret = mip_init_domains(mip, np: node);
265 if (ret)
266 goto err_map;
267
268 dev_dbg(&pdev->dev, "MIP: MSI-X count: %u, base: %u, offset: %u, msg_addr: %llx\n",
269 mip->num_msis, mip->msi_base, mip->msi_offset, mip->msg_addr);
270
271 return 0;
272
273err_map:
274 bitmap_free(bitmap: mip->bitmap);
275err_base:
276 iounmap(addr: mip->base);
277err_priv:
278 kfree(objp: mip);
279 return ret;
280}
281
282IRQCHIP_PLATFORM_DRIVER_BEGIN(mip_msi)
283IRQCHIP_MATCH("brcm,bcm2712-mip", mip_msi_probe)
284IRQCHIP_PLATFORM_DRIVER_END(mip_msi)
285MODULE_DESCRIPTION("Broadcom BCM2712 MSI-X interrupt controller");
286MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.com>");
287MODULE_AUTHOR("Stanimir Varbanov <svarbanov@suse.de>");
288MODULE_LICENSE("GPL");
289

source code of linux/drivers/irqchip/irq-bcm2712-mip.c