1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright The Asahi Linux Contributors
4 *
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
8 * Copyright 2015 Broadcom
9 */
10
11/*
12 * AIC is a fairly simple interrupt controller with the following features:
13 *
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
20 * interchangeable if not symmetric)
21 * - Automatic prioritization (single event/ack register per CPU, lower IRQs =
22 * higher priority)
23 * - Automatic masking on ack
24 * - Default "this CPU" register view and explicit per-CPU views
25 *
26 * In addition, this driver also handles FIQs, as these are routed to the same
27 * IRQ vector. These are used for Fast IPIs, the ARMv8 timer IRQs, and
28 * performance counters (TODO).
29 *
30 * Implementation notes:
31 *
32 * - This driver creates two IRQ domains, one for HW IRQs and internal FIQs,
33 * and one for IPIs.
34 * - Since Linux needs more than 2 IPIs, we implement a software IRQ controller
35 * and funnel all IPIs into one per-CPU IPI (the second "self" IPI is unused).
36 * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu.
37 * - DT bindings use 3-cell form (like GIC):
38 * - <0 nr flags> - hwirq #nr
39 * - <1 nr flags> - FIQ #nr
40 * - nr=0 Physical HV timer
41 * - nr=1 Virtual HV timer
42 * - nr=2 Physical guest timer
43 * - nr=3 Virtual guest timer
44 */
45
46#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
47
48#include <linux/bits.h>
49#include <linux/bitfield.h>
50#include <linux/cpuhotplug.h>
51#include <linux/io.h>
52#include <linux/irqchip.h>
53#include <linux/irqchip/arm-vgic-info.h>
54#include <linux/irqdomain.h>
55#include <linux/jump_label.h>
56#include <linux/limits.h>
57#include <linux/of_address.h>
58#include <linux/slab.h>
59#include <asm/apple_m1_pmu.h>
60#include <asm/cputype.h>
61#include <asm/exception.h>
62#include <asm/sysreg.h>
63#include <asm/virt.h>
64
65#include <dt-bindings/interrupt-controller/apple-aic.h>
66
67/*
68 * AIC v1 registers (MMIO)
69 */
70
71#define AIC_INFO 0x0004
72#define AIC_INFO_NR_IRQ GENMASK(15, 0)
73
74#define AIC_CONFIG 0x0010
75
76#define AIC_WHOAMI 0x2000
77#define AIC_EVENT 0x2004
78#define AIC_EVENT_DIE GENMASK(31, 24)
79#define AIC_EVENT_TYPE GENMASK(23, 16)
80#define AIC_EVENT_NUM GENMASK(15, 0)
81
82#define AIC_EVENT_TYPE_FIQ 0 /* Software use */
83#define AIC_EVENT_TYPE_IRQ 1
84#define AIC_EVENT_TYPE_IPI 4
85#define AIC_EVENT_IPI_OTHER 1
86#define AIC_EVENT_IPI_SELF 2
87
88#define AIC_IPI_SEND 0x2008
89#define AIC_IPI_ACK 0x200c
90#define AIC_IPI_MASK_SET 0x2024
91#define AIC_IPI_MASK_CLR 0x2028
92
93#define AIC_IPI_SEND_CPU(cpu) BIT(cpu)
94
95#define AIC_IPI_OTHER BIT(0)
96#define AIC_IPI_SELF BIT(31)
97
98#define AIC_TARGET_CPU 0x3000
99
100#define AIC_CPU_IPI_SET(cpu) (0x5008 + ((cpu) << 7))
101#define AIC_CPU_IPI_CLR(cpu) (0x500c + ((cpu) << 7))
102#define AIC_CPU_IPI_MASK_SET(cpu) (0x5024 + ((cpu) << 7))
103#define AIC_CPU_IPI_MASK_CLR(cpu) (0x5028 + ((cpu) << 7))
104
105#define AIC_MAX_IRQ 0x400
106
107/*
108 * AIC v2 registers (MMIO)
109 */
110
111#define AIC2_VERSION 0x0000
112#define AIC2_VERSION_VER GENMASK(7, 0)
113
114#define AIC2_INFO1 0x0004
115#define AIC2_INFO1_NR_IRQ GENMASK(15, 0)
116#define AIC2_INFO1_LAST_DIE GENMASK(27, 24)
117
118#define AIC2_INFO2 0x0008
119
120#define AIC2_INFO3 0x000c
121#define AIC2_INFO3_MAX_IRQ GENMASK(15, 0)
122#define AIC2_INFO3_MAX_DIE GENMASK(27, 24)
123
124#define AIC2_RESET 0x0010
125#define AIC2_RESET_RESET BIT(0)
126
127#define AIC2_CONFIG 0x0014
128#define AIC2_CONFIG_ENABLE BIT(0)
129#define AIC2_CONFIG_PREFER_PCPU BIT(28)
130
131#define AIC2_TIMEOUT 0x0028
132#define AIC2_CLUSTER_PRIO 0x0030
133#define AIC2_DELAY_GROUPS 0x0100
134
135#define AIC2_IRQ_CFG 0x2000
136
137/*
138 * AIC2 registers are laid out like this, starting at AIC2_IRQ_CFG:
139 *
140 * Repeat for each die:
141 * IRQ_CFG: u32 * MAX_IRQS
142 * SW_SET: u32 * (MAX_IRQS / 32)
143 * SW_CLR: u32 * (MAX_IRQS / 32)
144 * MASK_SET: u32 * (MAX_IRQS / 32)
145 * MASK_CLR: u32 * (MAX_IRQS / 32)
146 * HW_STATE: u32 * (MAX_IRQS / 32)
147 *
148 * This is followed by a set of event registers, each 16K page aligned.
149 * The first one is the AP event register we will use. Unfortunately,
150 * the actual implemented die count is not specified anywhere in the
151 * capability registers, so we have to explicitly specify the event
152 * register as a second reg entry in the device tree to remain
153 * forward-compatible.
154 */
155
156#define AIC2_IRQ_CFG_TARGET GENMASK(3, 0)
157#define AIC2_IRQ_CFG_DELAY_IDX GENMASK(7, 5)
158
159#define MASK_REG(x) (4 * ((x) >> 5))
160#define MASK_BIT(x) BIT((x) & GENMASK(4, 0))
161
162/*
163 * IMP-DEF sysregs that control FIQ sources
164 */
165
166/* IPI request registers */
167#define SYS_IMP_APL_IPI_RR_LOCAL_EL1 sys_reg(3, 5, 15, 0, 0)
168#define SYS_IMP_APL_IPI_RR_GLOBAL_EL1 sys_reg(3, 5, 15, 0, 1)
169#define IPI_RR_CPU GENMASK(7, 0)
170/* Cluster only used for the GLOBAL register */
171#define IPI_RR_CLUSTER GENMASK(23, 16)
172#define IPI_RR_TYPE GENMASK(29, 28)
173#define IPI_RR_IMMEDIATE 0
174#define IPI_RR_RETRACT 1
175#define IPI_RR_DEFERRED 2
176#define IPI_RR_NOWAKE 3
177
178/* IPI status register */
179#define SYS_IMP_APL_IPI_SR_EL1 sys_reg(3, 5, 15, 1, 1)
180#define IPI_SR_PENDING BIT(0)
181
182/* Guest timer FIQ enable register */
183#define SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2 sys_reg(3, 5, 15, 1, 3)
184#define VM_TMR_FIQ_ENABLE_V BIT(0)
185#define VM_TMR_FIQ_ENABLE_P BIT(1)
186
187/* Deferred IPI countdown register */
188#define SYS_IMP_APL_IPI_CR_EL1 sys_reg(3, 5, 15, 3, 1)
189
190/* Uncore PMC control register */
191#define SYS_IMP_APL_UPMCR0_EL1 sys_reg(3, 7, 15, 0, 4)
192#define UPMCR0_IMODE GENMASK(18, 16)
193#define UPMCR0_IMODE_OFF 0
194#define UPMCR0_IMODE_AIC 2
195#define UPMCR0_IMODE_HALT 3
196#define UPMCR0_IMODE_FIQ 4
197
198/* Uncore PMC status register */
199#define SYS_IMP_APL_UPMSR_EL1 sys_reg(3, 7, 15, 6, 4)
200#define UPMSR_IACT BIT(0)
201
202/* MPIDR fields */
203#define MPIDR_CPU(x) MPIDR_AFFINITY_LEVEL(x, 0)
204#define MPIDR_CLUSTER(x) MPIDR_AFFINITY_LEVEL(x, 1)
205
206#define AIC_IRQ_HWIRQ(die, irq) (FIELD_PREP(AIC_EVENT_DIE, die) | \
207 FIELD_PREP(AIC_EVENT_TYPE, AIC_EVENT_TYPE_IRQ) | \
208 FIELD_PREP(AIC_EVENT_NUM, irq))
209#define AIC_FIQ_HWIRQ(x) (FIELD_PREP(AIC_EVENT_TYPE, AIC_EVENT_TYPE_FIQ) | \
210 FIELD_PREP(AIC_EVENT_NUM, x))
211#define AIC_HWIRQ_IRQ(x) FIELD_GET(AIC_EVENT_NUM, x)
212#define AIC_HWIRQ_DIE(x) FIELD_GET(AIC_EVENT_DIE, x)
213#define AIC_NR_SWIPI 32
214
215/*
216 * FIQ hwirq index definitions: FIQ sources use the DT binding defines
217 * directly, except that timers are special. At the irqchip level, the
218 * two timer types are represented by their access method: _EL0 registers
219 * or _EL02 registers. In the DT binding, the timers are represented
220 * by their purpose (HV or guest). This mapping is for when the kernel is
221 * running at EL2 (with VHE). When the kernel is running at EL1, the
222 * mapping differs and aic_irq_domain_translate() performs the remapping.
223 */
224enum fiq_hwirq {
225 /* Must be ordered as in apple-aic.h */
226 AIC_TMR_EL0_PHYS = AIC_TMR_HV_PHYS,
227 AIC_TMR_EL0_VIRT = AIC_TMR_HV_VIRT,
228 AIC_TMR_EL02_PHYS = AIC_TMR_GUEST_PHYS,
229 AIC_TMR_EL02_VIRT = AIC_TMR_GUEST_VIRT,
230 AIC_CPU_PMU_Effi = AIC_CPU_PMU_E,
231 AIC_CPU_PMU_Perf = AIC_CPU_PMU_P,
232 /* No need for this to be discovered from DT */
233 AIC_VGIC_MI,
234 AIC_NR_FIQ
235};
236
237/* True if UNCORE/UNCORE2 and Sn_... IPI registers are present and used (A11+) */
238static DEFINE_STATIC_KEY_TRUE(use_fast_ipi);
239/* True if SYS_IMP_APL_IPI_RR_LOCAL_EL1 exists for local fast IPIs (M1+) */
240static DEFINE_STATIC_KEY_TRUE(use_local_fast_ipi);
241
242struct aic_info {
243 int version;
244
245 /* Register offsets */
246 u32 event;
247 u32 target_cpu;
248 u32 irq_cfg;
249 u32 sw_set;
250 u32 sw_clr;
251 u32 mask_set;
252 u32 mask_clr;
253
254 u32 die_stride;
255
256 /* Features */
257 bool fast_ipi;
258 bool local_fast_ipi;
259};
260
261static const struct aic_info aic1_info __initconst = {
262 .version = 1,
263
264 .event = AIC_EVENT,
265 .target_cpu = AIC_TARGET_CPU,
266};
267
268static const struct aic_info aic1_fipi_info __initconst = {
269 .version = 1,
270
271 .event = AIC_EVENT,
272 .target_cpu = AIC_TARGET_CPU,
273
274 .fast_ipi = true,
275};
276
277static const struct aic_info aic1_local_fipi_info __initconst = {
278 .version = 1,
279
280 .event = AIC_EVENT,
281 .target_cpu = AIC_TARGET_CPU,
282
283 .fast_ipi = true,
284 .local_fast_ipi = true,
285};
286
287static const struct aic_info aic2_info __initconst = {
288 .version = 2,
289
290 .irq_cfg = AIC2_IRQ_CFG,
291
292 .fast_ipi = true,
293 .local_fast_ipi = true,
294};
295
296static const struct of_device_id aic_info_match[] = {
297 {
298 .compatible = "apple,t8103-aic",
299 .data = &aic1_local_fipi_info,
300 },
301 {
302 .compatible = "apple,t8015-aic",
303 .data = &aic1_fipi_info,
304 },
305 {
306 .compatible = "apple,aic",
307 .data = &aic1_info,
308 },
309 {
310 .compatible = "apple,aic2",
311 .data = &aic2_info,
312 },
313 {}
314};
315
316struct aic_irq_chip {
317 void __iomem *base;
318 void __iomem *event;
319 struct irq_domain *hw_domain;
320 struct {
321 cpumask_t aff;
322 } *fiq_aff[AIC_NR_FIQ];
323
324 int nr_irq;
325 int max_irq;
326 int nr_die;
327 int max_die;
328
329 struct aic_info info;
330};
331
332static DEFINE_PER_CPU(uint32_t, aic_fiq_unmasked);
333
334static struct aic_irq_chip *aic_irqc;
335
336static void aic_handle_ipi(struct pt_regs *regs);
337
338static u32 aic_ic_read(struct aic_irq_chip *ic, u32 reg)
339{
340 return readl_relaxed(ic->base + reg);
341}
342
343static void aic_ic_write(struct aic_irq_chip *ic, u32 reg, u32 val)
344{
345 writel_relaxed(val, ic->base + reg);
346}
347
348/*
349 * IRQ irqchip
350 */
351
352static void aic_irq_mask(struct irq_data *d)
353{
354 irq_hw_number_t hwirq = irqd_to_hwirq(d);
355 struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d);
356
357 u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride;
358 u32 irq = AIC_HWIRQ_IRQ(hwirq);
359
360 aic_ic_write(ic, reg: ic->info.mask_set + off + MASK_REG(irq), MASK_BIT(irq));
361}
362
363static void aic_irq_unmask(struct irq_data *d)
364{
365 irq_hw_number_t hwirq = irqd_to_hwirq(d);
366 struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d);
367
368 u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride;
369 u32 irq = AIC_HWIRQ_IRQ(hwirq);
370
371 aic_ic_write(ic, reg: ic->info.mask_clr + off + MASK_REG(irq), MASK_BIT(irq));
372}
373
374static void aic_irq_eoi(struct irq_data *d)
375{
376 /*
377 * Reading the interrupt reason automatically acknowledges and masks
378 * the IRQ, so we just unmask it here if needed.
379 */
380 if (!irqd_irq_masked(d))
381 aic_irq_unmask(d);
382}
383
384static void __exception_irq_entry aic_handle_irq(struct pt_regs *regs)
385{
386 struct aic_irq_chip *ic = aic_irqc;
387 u32 event, type, irq;
388
389 do {
390 /*
391 * We cannot use a relaxed read here, as reads from DMA buffers
392 * need to be ordered after the IRQ fires.
393 */
394 event = readl(ic->event + ic->info.event);
395 type = FIELD_GET(AIC_EVENT_TYPE, event);
396 irq = FIELD_GET(AIC_EVENT_NUM, event);
397
398 if (type == AIC_EVENT_TYPE_IRQ)
399 generic_handle_domain_irq(aic_irqc->hw_domain, event);
400 else if (type == AIC_EVENT_TYPE_IPI && irq == 1)
401 aic_handle_ipi(regs);
402 else if (event != 0)
403 pr_err_ratelimited("Unknown IRQ event %d, %d\n", type, irq);
404 } while (event);
405
406 /*
407 * vGIC maintenance interrupts end up here too, so we need to check
408 * for them separately. It should however only trigger when NV is
409 * in use, and be cleared when coming back from the handler.
410 */
411 if (is_kernel_in_hyp_mode() &&
412 (read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_En) &&
413 read_sysreg_s(SYS_ICH_MISR_EL2) != 0) {
414 u64 val;
415
416 generic_handle_domain_irq(aic_irqc->hw_domain,
417 AIC_FIQ_HWIRQ(AIC_VGIC_MI));
418
419 if (unlikely((read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_En) &&
420 (val = read_sysreg_s(SYS_ICH_MISR_EL2)))) {
421 pr_err_ratelimited("vGIC IRQ fired and not handled by KVM (MISR=%llx), disabling.\n",
422 val);
423 sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EL2_En, 0);
424 }
425 }
426}
427
428static int aic_irq_set_affinity(struct irq_data *d,
429 const struct cpumask *mask_val, bool force)
430{
431 irq_hw_number_t hwirq = irqd_to_hwirq(d);
432 struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d);
433 int cpu;
434
435 BUG_ON(!ic->info.target_cpu);
436
437 if (force)
438 cpu = cpumask_first(srcp: mask_val);
439 else
440 cpu = cpumask_any_and(mask_val, cpu_online_mask);
441
442 aic_ic_write(ic, reg: ic->info.target_cpu + AIC_HWIRQ_IRQ(hwirq) * 4, BIT(cpu));
443 irq_data_update_effective_affinity(d, cpumask_of(cpu));
444
445 return IRQ_SET_MASK_OK;
446}
447
448static int aic_irq_set_type(struct irq_data *d, unsigned int type)
449{
450 /*
451 * Some IRQs (e.g. MSIs) implicitly have edge semantics, and we don't
452 * have a way to find out the type of any given IRQ, so just allow both.
453 */
454 return (type == IRQ_TYPE_LEVEL_HIGH || type == IRQ_TYPE_EDGE_RISING) ? 0 : -EINVAL;
455}
456
457static struct irq_chip aic_chip = {
458 .name = "AIC",
459 .irq_mask = aic_irq_mask,
460 .irq_unmask = aic_irq_unmask,
461 .irq_eoi = aic_irq_eoi,
462 .irq_set_affinity = aic_irq_set_affinity,
463 .irq_set_type = aic_irq_set_type,
464};
465
466static struct irq_chip aic2_chip = {
467 .name = "AIC2",
468 .irq_mask = aic_irq_mask,
469 .irq_unmask = aic_irq_unmask,
470 .irq_eoi = aic_irq_eoi,
471 .irq_set_type = aic_irq_set_type,
472};
473
474/*
475 * FIQ irqchip
476 */
477
478static unsigned long aic_fiq_get_idx(struct irq_data *d)
479{
480 return AIC_HWIRQ_IRQ(irqd_to_hwirq(d));
481}
482
483static void aic_fiq_set_mask(struct irq_data *d)
484{
485 /* Only the guest timers have real mask bits, unfortunately. */
486 switch (aic_fiq_get_idx(d)) {
487 case AIC_TMR_EL02_PHYS:
488 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENABLE_P, 0);
489 isb();
490 break;
491 case AIC_TMR_EL02_VIRT:
492 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENABLE_V, 0);
493 isb();
494 break;
495 default:
496 break;
497 }
498}
499
500static void aic_fiq_clear_mask(struct irq_data *d)
501{
502 switch (aic_fiq_get_idx(d)) {
503 case AIC_TMR_EL02_PHYS:
504 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, 0, VM_TMR_FIQ_ENABLE_P);
505 isb();
506 break;
507 case AIC_TMR_EL02_VIRT:
508 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, 0, VM_TMR_FIQ_ENABLE_V);
509 isb();
510 break;
511 default:
512 break;
513 }
514}
515
516static void aic_fiq_mask(struct irq_data *d)
517{
518 aic_fiq_set_mask(d);
519 __this_cpu_and(aic_fiq_unmasked, ~BIT(aic_fiq_get_idx(d)));
520}
521
522static void aic_fiq_unmask(struct irq_data *d)
523{
524 aic_fiq_clear_mask(d);
525 __this_cpu_or(aic_fiq_unmasked, BIT(aic_fiq_get_idx(d)));
526}
527
528static void aic_fiq_eoi(struct irq_data *d)
529{
530 /* We mask to ack (where we can), so we need to unmask at EOI. */
531 if (__this_cpu_read(aic_fiq_unmasked) & BIT(aic_fiq_get_idx(d)))
532 aic_fiq_clear_mask(d);
533}
534
535#define TIMER_FIRING(x) \
536 (((x) & (ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_MASK | \
537 ARCH_TIMER_CTRL_IT_STAT)) == \
538 (ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_STAT))
539
540static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs)
541{
542 /*
543 * It would be really nice if we had a system register that lets us get
544 * the FIQ source state without having to peek down into sources...
545 * but such a register does not seem to exist.
546 *
547 * So, we have these potential sources to test for:
548 * - Fast IPIs (not yet used)
549 * - The 4 timers (CNTP, CNTV for each of HV and guest)
550 * - Per-core PMCs (not yet supported)
551 * - Per-cluster uncore PMCs (not yet supported)
552 *
553 * Since not dealing with any of these results in a FIQ storm,
554 * we check for everything here, even things we don't support yet.
555 */
556
557 if (static_branch_likely(&use_fast_ipi) &&
558 (read_sysreg_s(SYS_IMP_APL_IPI_SR_EL1) & IPI_SR_PENDING))
559 aic_handle_ipi(regs);
560
561 if (TIMER_FIRING(read_sysreg(cntp_ctl_el0)))
562 generic_handle_domain_irq(aic_irqc->hw_domain,
563 AIC_FIQ_HWIRQ(AIC_TMR_EL0_PHYS));
564
565 if (TIMER_FIRING(read_sysreg(cntv_ctl_el0)))
566 generic_handle_domain_irq(aic_irqc->hw_domain,
567 AIC_FIQ_HWIRQ(AIC_TMR_EL0_VIRT));
568
569 if (is_kernel_in_hyp_mode()) {
570 uint64_t enabled = read_sysreg_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2);
571
572 if ((enabled & VM_TMR_FIQ_ENABLE_P) &&
573 TIMER_FIRING(read_sysreg_s(SYS_CNTP_CTL_EL02)))
574 generic_handle_domain_irq(aic_irqc->hw_domain,
575 AIC_FIQ_HWIRQ(AIC_TMR_EL02_PHYS));
576
577 if ((enabled & VM_TMR_FIQ_ENABLE_V) &&
578 TIMER_FIRING(read_sysreg_s(SYS_CNTV_CTL_EL02)))
579 generic_handle_domain_irq(aic_irqc->hw_domain,
580 AIC_FIQ_HWIRQ(AIC_TMR_EL02_VIRT));
581 }
582
583 if ((read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & (PMCR0_IMODE | PMCR0_IACT)) ==
584 (FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_FIQ) | PMCR0_IACT))
585 generic_handle_domain_irq(aic_irqc->hw_domain,
586 AIC_FIQ_HWIRQ(AIC_CPU_PMU_P));
587
588 if (static_branch_likely(&use_fast_ipi) &&
589 (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) == UPMCR0_IMODE_FIQ) &&
590 (read_sysreg_s(SYS_IMP_APL_UPMSR_EL1) & UPMSR_IACT)) {
591 /* Same story with uncore PMCs */
592 pr_err_ratelimited("Uncore PMC FIQ fired. Masking.\n");
593 sysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE,
594 FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF));
595 }
596}
597
598static int aic_fiq_set_type(struct irq_data *d, unsigned int type)
599{
600 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
601}
602
603static struct irq_chip fiq_chip = {
604 .name = "AIC-FIQ",
605 .irq_mask = aic_fiq_mask,
606 .irq_unmask = aic_fiq_unmask,
607 .irq_ack = aic_fiq_set_mask,
608 .irq_eoi = aic_fiq_eoi,
609 .irq_set_type = aic_fiq_set_type,
610};
611
612/*
613 * Main IRQ domain
614 */
615
616static int aic_irq_domain_map(struct irq_domain *id, unsigned int irq,
617 irq_hw_number_t hw)
618{
619 struct aic_irq_chip *ic = id->host_data;
620 u32 type = FIELD_GET(AIC_EVENT_TYPE, hw);
621 struct irq_chip *chip = &aic_chip;
622
623 if (ic->info.version == 2)
624 chip = &aic2_chip;
625
626 if (type == AIC_EVENT_TYPE_IRQ) {
627 irq_domain_set_info(domain: id, virq: irq, hwirq: hw, chip, chip_data: id->host_data,
628 handler: handle_fasteoi_irq, NULL, NULL);
629 irqd_set_single_target(d: irq_desc_get_irq_data(desc: irq_to_desc(irq)));
630 } else {
631 irq_set_percpu_devid(irq);
632 irq_domain_set_info(domain: id, virq: irq, hwirq: hw, chip: &fiq_chip, chip_data: id->host_data,
633 handler: handle_percpu_devid_irq, NULL, NULL);
634 }
635
636 return 0;
637}
638
639static int aic_irq_get_fwspec_info(struct irq_fwspec *fwspec, struct irq_fwspec_info *info)
640{
641 const struct cpumask *mask;
642 u32 intid;
643
644 info->flags = 0;
645 info->affinity = NULL;
646
647 if (fwspec->param[0] != AIC_FIQ)
648 return 0;
649
650 if (fwspec->param_count == 3)
651 intid = fwspec->param[1];
652 else
653 intid = fwspec->param[2];
654
655 if (aic_irqc->fiq_aff[intid])
656 mask = &aic_irqc->fiq_aff[intid]->aff;
657 else
658 mask = cpu_possible_mask;
659
660 info->affinity = mask;
661 info->flags = IRQ_FWSPEC_INFO_AFFINITY_VALID;
662
663 return 0;
664}
665
666static int aic_irq_domain_translate(struct irq_domain *id,
667 struct irq_fwspec *fwspec,
668 unsigned long *hwirq,
669 unsigned int *type)
670{
671 struct aic_irq_chip *ic = id->host_data;
672 u32 *args;
673 u32 die = 0;
674
675 if (fwspec->param_count < 3 || fwspec->param_count > 4 ||
676 !is_of_node(fwnode: fwspec->fwnode))
677 return -EINVAL;
678
679 args = &fwspec->param[1];
680
681 if (fwspec->param_count == 4) {
682 die = args[0];
683 args++;
684 }
685
686 switch (fwspec->param[0]) {
687 case AIC_IRQ:
688 if (die >= ic->nr_die)
689 return -EINVAL;
690 if (args[0] >= ic->nr_irq)
691 return -EINVAL;
692 *hwirq = AIC_IRQ_HWIRQ(die, args[0]);
693 break;
694 case AIC_FIQ:
695 if (die != 0)
696 return -EINVAL;
697 if (args[0] >= AIC_NR_FIQ)
698 return -EINVAL;
699 *hwirq = AIC_FIQ_HWIRQ(args[0]);
700
701 /*
702 * In EL1 the non-redirected registers are the guest's,
703 * not EL2's, so remap the hwirqs to match.
704 */
705 if (!is_kernel_in_hyp_mode()) {
706 switch (args[0]) {
707 case AIC_TMR_GUEST_PHYS:
708 *hwirq = AIC_FIQ_HWIRQ(AIC_TMR_EL0_PHYS);
709 break;
710 case AIC_TMR_GUEST_VIRT:
711 *hwirq = AIC_FIQ_HWIRQ(AIC_TMR_EL0_VIRT);
712 break;
713 case AIC_TMR_HV_PHYS:
714 case AIC_TMR_HV_VIRT:
715 return -ENOENT;
716 default:
717 break;
718 }
719 }
720
721 /* Merge the two PMUs on a single interrupt */
722 if (*hwirq == AIC_CPU_PMU_E)
723 *hwirq = AIC_CPU_PMU_P;
724 break;
725 default:
726 return -EINVAL;
727 }
728
729 *type = args[1] & IRQ_TYPE_SENSE_MASK;
730
731 return 0;
732}
733
734static int aic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
735 unsigned int nr_irqs, void *arg)
736{
737 unsigned int type = IRQ_TYPE_NONE;
738 struct irq_fwspec *fwspec = arg;
739 irq_hw_number_t hwirq;
740 int i, ret;
741
742 ret = aic_irq_domain_translate(id: domain, fwspec, hwirq: &hwirq, type: &type);
743 if (ret)
744 return ret;
745
746 for (i = 0; i < nr_irqs; i++) {
747 ret = aic_irq_domain_map(id: domain, irq: virq + i, hw: hwirq + i);
748 if (ret)
749 return ret;
750 }
751
752 return 0;
753}
754
755static void aic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
756 unsigned int nr_irqs)
757{
758 int i;
759
760 for (i = 0; i < nr_irqs; i++) {
761 struct irq_data *d = irq_domain_get_irq_data(domain, virq: virq + i);
762
763 irq_set_handler(irq: virq + i, NULL);
764 irq_domain_reset_irq_data(irq_data: d);
765 }
766}
767
768static const struct irq_domain_ops aic_irq_domain_ops = {
769 .translate = aic_irq_domain_translate,
770 .alloc = aic_irq_domain_alloc,
771 .free = aic_irq_domain_free,
772 .get_fwspec_info = aic_irq_get_fwspec_info,
773};
774
775/*
776 * IPI irqchip
777 */
778
779static void aic_ipi_send_fast(int cpu)
780{
781 u64 mpidr = cpu_logical_map(cpu);
782 u64 my_mpidr = read_cpuid_mpidr();
783 u64 cluster = MPIDR_CLUSTER(mpidr);
784 u64 idx = MPIDR_CPU(mpidr);
785
786 if (static_branch_likely(&use_local_fast_ipi) && MPIDR_CLUSTER(my_mpidr) == cluster) {
787 write_sysreg_s(FIELD_PREP(IPI_RR_CPU, idx), SYS_IMP_APL_IPI_RR_LOCAL_EL1);
788 } else {
789 write_sysreg_s(FIELD_PREP(IPI_RR_CPU, idx) | FIELD_PREP(IPI_RR_CLUSTER, cluster),
790 SYS_IMP_APL_IPI_RR_GLOBAL_EL1);
791 }
792 isb();
793}
794
795static void aic_handle_ipi(struct pt_regs *regs)
796{
797 /*
798 * Ack the IPI. We need to order this after the AIC event read, but
799 * that is enforced by normal MMIO ordering guarantees.
800 *
801 * For the Fast IPI case, this needs to be ordered before the vIPI
802 * handling below, so we need to isb();
803 */
804 if (static_branch_likely(&use_fast_ipi)) {
805 write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1);
806 isb();
807 } else {
808 aic_ic_write(ic: aic_irqc, AIC_IPI_ACK, AIC_IPI_OTHER);
809 }
810
811 ipi_mux_process();
812
813 /*
814 * No ordering needed here; at worst this just changes the timing of
815 * when the next IPI will be delivered.
816 */
817 if (!static_branch_likely(&use_fast_ipi))
818 aic_ic_write(ic: aic_irqc, AIC_IPI_MASK_CLR, AIC_IPI_OTHER);
819}
820
821static void aic_ipi_send_single(unsigned int cpu)
822{
823 if (static_branch_likely(&use_fast_ipi))
824 aic_ipi_send_fast(cpu);
825 else
826 aic_ic_write(ic: aic_irqc, AIC_IPI_SEND, AIC_IPI_SEND_CPU(cpu));
827}
828
829static int __init aic_init_smp(struct aic_irq_chip *irqc, struct device_node *node)
830{
831 int base_ipi;
832
833 base_ipi = ipi_mux_create(AIC_NR_SWIPI, mux_send: aic_ipi_send_single);
834 if (WARN_ON(base_ipi <= 0))
835 return -ENODEV;
836
837 set_smp_ipi_range(base_ipi, AIC_NR_SWIPI);
838
839 return 0;
840}
841
842static int aic_init_cpu(unsigned int cpu)
843{
844 /* Mask all hard-wired per-CPU IRQ/FIQ sources */
845
846 /* Pending Fast IPI FIQs */
847 if (static_branch_likely(&use_fast_ipi))
848 write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1);
849
850 /* Timer FIQs */
851 sysreg_clear_set(cntp_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK);
852 sysreg_clear_set(cntv_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK);
853
854 /* EL2-only (VHE mode) IRQ sources */
855 if (is_kernel_in_hyp_mode()) {
856 /* Guest timers */
857 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2,
858 VM_TMR_FIQ_ENABLE_V | VM_TMR_FIQ_ENABLE_P, 0);
859
860 /* vGIC maintenance IRQ */
861 sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EL2_En, 0);
862 }
863
864 /* PMC FIQ */
865 sysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT,
866 FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF));
867
868 /* Uncore PMC FIQ */
869 if (static_branch_likely(&use_fast_ipi)) {
870 sysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE,
871 FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF));
872 }
873
874 /* Commit all of the above */
875 isb();
876
877 if (aic_irqc->info.version == 1) {
878 /*
879 * Make sure the kernel's idea of logical CPU order is the same as AIC's
880 * If we ever end up with a mismatch here, we will have to introduce
881 * a mapping table similar to what other irqchip drivers do.
882 */
883 WARN_ON(aic_ic_read(aic_irqc, AIC_WHOAMI) != smp_processor_id());
884
885 /*
886 * Always keep IPIs unmasked at the hardware level (except auto-masking
887 * by AIC during processing). We manage masks at the vIPI level.
888 * These registers only exist on AICv1, AICv2 always uses fast IPIs.
889 */
890 aic_ic_write(ic: aic_irqc, AIC_IPI_ACK, AIC_IPI_SELF | AIC_IPI_OTHER);
891 if (static_branch_likely(&use_fast_ipi)) {
892 aic_ic_write(ic: aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF | AIC_IPI_OTHER);
893 } else {
894 aic_ic_write(ic: aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF);
895 aic_ic_write(ic: aic_irqc, AIC_IPI_MASK_CLR, AIC_IPI_OTHER);
896 }
897 }
898
899 /* Initialize the local mask state */
900 __this_cpu_write(aic_fiq_unmasked, 0);
901
902 return 0;
903}
904
905static struct gic_kvm_info vgic_info __initdata = {
906 .type = GIC_V3,
907 .no_maint_irq_mask = true,
908 .no_hw_deactivation = true,
909};
910
911static void build_fiq_affinity(struct aic_irq_chip *ic, struct device_node *aff)
912{
913 int i, n;
914 u32 fiq;
915
916 if (of_property_read_u32(np: aff, propname: "apple,fiq-index", out_value: &fiq) ||
917 WARN_ON(fiq >= AIC_NR_FIQ) || ic->fiq_aff[fiq])
918 return;
919
920 n = of_property_count_elems_of_size(np: aff, propname: "cpus", elem_size: sizeof(u32));
921 if (WARN_ON(n < 0))
922 return;
923
924 ic->fiq_aff[fiq] = kzalloc(sizeof(*ic->fiq_aff[fiq]), GFP_KERNEL);
925 if (!ic->fiq_aff[fiq])
926 return;
927
928 for (i = 0; i < n; i++) {
929 struct device_node *cpu_node;
930 u32 cpu_phandle;
931 int cpu;
932
933 if (of_property_read_u32_index(np: aff, propname: "cpus", index: i, out_value: &cpu_phandle))
934 continue;
935
936 cpu_node = of_find_node_by_phandle(handle: cpu_phandle);
937 if (WARN_ON(!cpu_node))
938 continue;
939
940 cpu = of_cpu_node_to_id(np: cpu_node);
941 of_node_put(node: cpu_node);
942 if (WARN_ON(cpu < 0))
943 continue;
944
945 cpumask_set_cpu(cpu, dstp: &ic->fiq_aff[fiq]->aff);
946 }
947}
948
949static int __init aic_of_ic_init(struct device_node *node, struct device_node *parent)
950{
951 int i, die;
952 u32 off, start_off;
953 void __iomem *regs;
954 struct aic_irq_chip *irqc;
955 struct device_node *affs;
956 const struct of_device_id *match;
957
958 regs = of_iomap(node, index: 0);
959 if (WARN_ON(!regs))
960 return -EIO;
961
962 irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
963 if (!irqc) {
964 iounmap(addr: regs);
965 return -ENOMEM;
966 }
967
968 irqc->base = regs;
969
970 match = of_match_node(matches: aic_info_match, node);
971 if (!match)
972 goto err_unmap;
973
974 irqc->info = *(struct aic_info *)match->data;
975
976 aic_irqc = irqc;
977
978 switch (irqc->info.version) {
979 case 1: {
980 u32 info;
981
982 info = aic_ic_read(ic: irqc, AIC_INFO);
983 irqc->nr_irq = FIELD_GET(AIC_INFO_NR_IRQ, info);
984 irqc->max_irq = AIC_MAX_IRQ;
985 irqc->nr_die = irqc->max_die = 1;
986
987 off = start_off = irqc->info.target_cpu;
988 off += sizeof(u32) * irqc->max_irq; /* TARGET_CPU */
989
990 irqc->event = irqc->base;
991
992 break;
993 }
994 case 2: {
995 u32 info1, info3;
996
997 info1 = aic_ic_read(ic: irqc, AIC2_INFO1);
998 info3 = aic_ic_read(ic: irqc, AIC2_INFO3);
999
1000 irqc->nr_irq = FIELD_GET(AIC2_INFO1_NR_IRQ, info1);
1001 irqc->max_irq = FIELD_GET(AIC2_INFO3_MAX_IRQ, info3);
1002 irqc->nr_die = FIELD_GET(AIC2_INFO1_LAST_DIE, info1) + 1;
1003 irqc->max_die = FIELD_GET(AIC2_INFO3_MAX_DIE, info3);
1004
1005 off = start_off = irqc->info.irq_cfg;
1006 off += sizeof(u32) * irqc->max_irq; /* IRQ_CFG */
1007
1008 irqc->event = of_iomap(node, index: 1);
1009 if (WARN_ON(!irqc->event))
1010 goto err_unmap;
1011
1012 break;
1013 }
1014 }
1015
1016 irqc->info.sw_set = off;
1017 off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_SET */
1018 irqc->info.sw_clr = off;
1019 off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_CLR */
1020 irqc->info.mask_set = off;
1021 off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_SET */
1022 irqc->info.mask_clr = off;
1023 off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_CLR */
1024 off += sizeof(u32) * (irqc->max_irq >> 5); /* HW_STATE */
1025
1026 if (!irqc->info.fast_ipi)
1027 static_branch_disable(&use_fast_ipi);
1028
1029 if (!irqc->info.local_fast_ipi)
1030 static_branch_disable(&use_local_fast_ipi);
1031
1032 irqc->info.die_stride = off - start_off;
1033
1034 irqc->hw_domain = irq_domain_create_tree(of_fwnode_handle(node),
1035 ops: &aic_irq_domain_ops, host_data: irqc);
1036 if (WARN_ON(!irqc->hw_domain))
1037 goto err_unmap;
1038
1039 irq_domain_update_bus_token(domain: irqc->hw_domain, bus_token: DOMAIN_BUS_WIRED);
1040
1041 if (aic_init_smp(irqc, node))
1042 goto err_remove_domain;
1043
1044 affs = of_get_child_by_name(node, name: "affinities");
1045 if (affs) {
1046 struct device_node *chld;
1047
1048 for_each_child_of_node(affs, chld)
1049 build_fiq_affinity(ic: irqc, aff: chld);
1050 }
1051 of_node_put(node: affs);
1052
1053 set_handle_irq(aic_handle_irq);
1054 set_handle_fiq(aic_handle_fiq);
1055
1056 off = 0;
1057 for (die = 0; die < irqc->nr_die; die++) {
1058 for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++)
1059 aic_ic_write(ic: irqc, reg: irqc->info.mask_set + off + i * 4, U32_MAX);
1060 for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++)
1061 aic_ic_write(ic: irqc, reg: irqc->info.sw_clr + off + i * 4, U32_MAX);
1062 if (irqc->info.target_cpu)
1063 for (i = 0; i < irqc->nr_irq; i++)
1064 aic_ic_write(ic: irqc, reg: irqc->info.target_cpu + off + i * 4, val: 1);
1065 off += irqc->info.die_stride;
1066 }
1067
1068 if (irqc->info.version == 2) {
1069 u32 config = aic_ic_read(ic: irqc, AIC2_CONFIG);
1070
1071 config |= AIC2_CONFIG_ENABLE;
1072 aic_ic_write(ic: irqc, AIC2_CONFIG, val: config);
1073 }
1074
1075 if (!is_kernel_in_hyp_mode())
1076 pr_info("Kernel running in EL1, mapping interrupts");
1077
1078 if (static_branch_likely(&use_fast_ipi))
1079 pr_info("Using Fast IPIs");
1080
1081 cpuhp_setup_state(state: CPUHP_AP_IRQ_APPLE_AIC_STARTING,
1082 name: "irqchip/apple-aic/ipi:starting",
1083 startup: aic_init_cpu, NULL);
1084
1085 if (is_kernel_in_hyp_mode()) {
1086 struct irq_fwspec mi = {
1087 .fwnode = of_fwnode_handle(node),
1088 .param_count = 3,
1089 .param = {
1090 [0] = AIC_FIQ, /* This is a lie */
1091 [1] = AIC_VGIC_MI,
1092 [2] = IRQ_TYPE_LEVEL_HIGH,
1093 },
1094 };
1095
1096 vgic_info.maint_irq = irq_create_fwspec_mapping(fwspec: &mi);
1097 WARN_ON(!vgic_info.maint_irq);
1098 }
1099
1100 vgic_set_kvm_info(info: &vgic_info);
1101
1102 pr_info("Initialized with %d/%d IRQs * %d/%d die(s), %d FIQs, %d vIPIs",
1103 irqc->nr_irq, irqc->max_irq, irqc->nr_die, irqc->max_die, AIC_NR_FIQ, AIC_NR_SWIPI);
1104
1105 return 0;
1106
1107err_remove_domain:
1108 irq_domain_remove(domain: irqc->hw_domain);
1109err_unmap:
1110 if (irqc->event && irqc->event != irqc->base)
1111 iounmap(addr: irqc->event);
1112 iounmap(addr: irqc->base);
1113 kfree(objp: irqc);
1114 return -ENODEV;
1115}
1116
1117IRQCHIP_DECLARE(apple_aic, "apple,aic", aic_of_ic_init);
1118IRQCHIP_DECLARE(apple_aic2, "apple,aic2", aic_of_ic_init);
1119

source code of linux/drivers/irqchip/irq-apple-aic.c