| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ |
| 3 | |
| 4 | #ifndef _IONIC_LIF_CFG_H_ |
| 5 | |
| 6 | #define IONIC_VERSION(a, b) (((a) << 16) + ((b) << 8)) |
| 7 | #define IONIC_PAGE_SIZE_SUPPORTED 0x40201000 /* 4kb, 2Mb, 1Gb */ |
| 8 | |
| 9 | #define IONIC_EXPDB_64B_WQE BIT(0) |
| 10 | #define IONIC_EXPDB_128B_WQE BIT(1) |
| 11 | #define IONIC_EXPDB_256B_WQE BIT(2) |
| 12 | #define IONIC_EXPDB_512B_WQE BIT(3) |
| 13 | |
| 14 | struct ionic_lif_cfg { |
| 15 | struct device *hwdev; |
| 16 | struct ionic_lif *lif; |
| 17 | |
| 18 | int lif_index; |
| 19 | int lif_hw_index; |
| 20 | |
| 21 | u32 dbid; |
| 22 | int dbid_count; |
| 23 | u64 __iomem *dbpage; |
| 24 | struct ionic_intr __iomem *intr_ctrl; |
| 25 | phys_addr_t db_phys; |
| 26 | |
| 27 | u64 page_size_supported; |
| 28 | u32 npts_per_lif; |
| 29 | u32 nmrs_per_lif; |
| 30 | u32 nahs_per_lif; |
| 31 | |
| 32 | u32 aq_base; |
| 33 | u32 cq_base; |
| 34 | u32 eq_base; |
| 35 | |
| 36 | int aq_count; |
| 37 | int eq_count; |
| 38 | int cq_count; |
| 39 | int qp_count; |
| 40 | |
| 41 | u16 stats_type; |
| 42 | u8 aq_qtype; |
| 43 | u8 sq_qtype; |
| 44 | u8 rq_qtype; |
| 45 | u8 cq_qtype; |
| 46 | u8 eq_qtype; |
| 47 | |
| 48 | u8 udma_count; |
| 49 | u8 udma_qgrp_shift; |
| 50 | |
| 51 | u8 rdma_version; |
| 52 | u8 qp_opcodes; |
| 53 | u8 admin_opcodes; |
| 54 | |
| 55 | u8 max_stride; |
| 56 | bool sq_expdb; |
| 57 | bool rq_expdb; |
| 58 | u8 expdb_mask; |
| 59 | }; |
| 60 | |
| 61 | void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg); |
| 62 | struct net_device *ionic_lif_netdev(struct ionic_lif *lif); |
| 63 | void ionic_lif_fw_version(struct ionic_lif *lif, char *str, size_t len); |
| 64 | u8 ionic_lif_asic_rev(struct ionic_lif *lif); |
| 65 | |
| 66 | #endif /* _IONIC_LIF_CFG_H_ */ |
| 67 | |