1// SPDX-License-Identifier: GPL-2.0-only
2
3#include <linux/bits.h>
4#include <linux/i2c.h>
5#include <linux/i2c-mux.h>
6#include <linux/mod_devicetable.h>
7#include <linux/mfd/syscon.h>
8#include <linux/mutex.h>
9#include <linux/platform_device.h>
10#include <linux/regmap.h>
11#include <linux/unaligned.h>
12
13enum rtl9300_bus_freq {
14 RTL9300_I2C_STD_FREQ,
15 RTL9300_I2C_FAST_FREQ,
16};
17
18struct rtl9300_i2c;
19
20struct rtl9300_i2c_chan {
21 struct i2c_adapter adap;
22 struct rtl9300_i2c *i2c;
23 enum rtl9300_bus_freq bus_freq;
24 u8 sda_num;
25};
26
27enum rtl9300_i2c_reg_scope {
28 REG_SCOPE_GLOBAL,
29 REG_SCOPE_MASTER,
30};
31
32struct rtl9300_i2c_reg_field {
33 struct reg_field field;
34 enum rtl9300_i2c_reg_scope scope;
35};
36
37enum rtl9300_i2c_reg_fields {
38 F_DATA_WIDTH = 0,
39 F_DEV_ADDR,
40 F_I2C_FAIL,
41 F_I2C_TRIG,
42 F_MEM_ADDR,
43 F_MEM_ADDR_WIDTH,
44 F_RD_MODE,
45 F_RWOP,
46 F_SCL_FREQ,
47 F_SCL_SEL,
48 F_SDA_OUT_SEL,
49 F_SDA_SEL,
50
51 /* keep last */
52 F_NUM_FIELDS
53};
54
55struct rtl9300_i2c_drv_data {
56 struct rtl9300_i2c_reg_field field_desc[F_NUM_FIELDS];
57 int (*select_scl)(struct rtl9300_i2c *i2c, u8 scl);
58 u32 data_reg;
59 u8 max_nchan;
60};
61
62#define RTL9300_I2C_MUX_NCHAN 8
63#define RTL9310_I2C_MUX_NCHAN 12
64
65struct rtl9300_i2c {
66 struct regmap *regmap;
67 struct device *dev;
68 struct rtl9300_i2c_chan chans[RTL9310_I2C_MUX_NCHAN];
69 struct regmap_field *fields[F_NUM_FIELDS];
70 u32 reg_base;
71 u32 data_reg;
72 u8 scl_num;
73 u8 sda_num;
74 struct mutex lock;
75};
76
77DEFINE_GUARD(rtl9300_i2c, struct rtl9300_i2c *, mutex_lock(&_T->lock), mutex_unlock(&_T->lock))
78
79enum rtl9300_i2c_xfer_type {
80 RTL9300_I2C_XFER_BYTE,
81 RTL9300_I2C_XFER_WORD,
82 RTL9300_I2C_XFER_BLOCK,
83};
84
85struct rtl9300_i2c_xfer {
86 enum rtl9300_i2c_xfer_type type;
87 u16 dev_addr;
88 u8 reg_addr;
89 u8 reg_addr_len;
90 u8 *data;
91 u8 data_len;
92 bool write;
93};
94
95#define RTL9300_I2C_MST_CTRL1 0x0
96#define RTL9300_I2C_MST_CTRL2 0x4
97#define RTL9300_I2C_MST_DATA_WORD0 0x8
98#define RTL9300_I2C_MST_DATA_WORD1 0xc
99#define RTL9300_I2C_MST_DATA_WORD2 0x10
100#define RTL9300_I2C_MST_DATA_WORD3 0x14
101#define RTL9300_I2C_MST_GLB_CTRL 0x384
102
103#define RTL9310_I2C_MST_IF_CTRL 0x1004
104#define RTL9310_I2C_MST_IF_SEL 0x1008
105#define RTL9310_I2C_MST_CTRL 0x0
106#define RTL9310_I2C_MST_MEMADDR_CTRL 0x4
107#define RTL9310_I2C_MST_DATA_CTRL 0x8
108
109static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)
110{
111 int ret;
112
113 ret = regmap_field_write(field: i2c->fields[F_MEM_ADDR_WIDTH], val: len);
114 if (ret)
115 return ret;
116
117 return regmap_field_write(field: i2c->fields[F_MEM_ADDR], val: reg);
118}
119
120static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)
121{
122 return regmap_field_write(field: i2c->fields[F_SCL_SEL], val: 1);
123}
124
125static int rtl9310_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)
126{
127 return regmap_field_update_bits(field: i2c->fields[F_SCL_SEL], BIT(scl), BIT(scl));
128}
129
130static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan)
131{
132 struct rtl9300_i2c_drv_data *drv_data;
133 int ret;
134
135 if (i2c->sda_num == chan->sda_num)
136 return 0;
137
138 ret = regmap_field_write(field: i2c->fields[F_SCL_FREQ], val: chan->bus_freq);
139 if (ret)
140 return ret;
141
142 drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(dev: i2c->dev);
143 ret = drv_data->select_scl(i2c, i2c->scl_num);
144 if (ret)
145 return ret;
146
147 ret = regmap_field_update_bits(field: i2c->fields[F_SDA_SEL], BIT(chan->sda_num),
148 BIT(chan->sda_num));
149 if (ret)
150 return ret;
151
152 ret = regmap_field_write(field: i2c->fields[F_SDA_OUT_SEL], val: chan->sda_num);
153 if (ret)
154 return ret;
155
156 i2c->sda_num = chan->sda_num;
157 return 0;
158}
159
160static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, u8 len)
161{
162 u32 vals[4] = {};
163 int i, ret;
164
165 if (len > 16)
166 return -EIO;
167
168 ret = regmap_bulk_read(map: i2c->regmap, reg: i2c->data_reg, val: vals, ARRAY_SIZE(vals));
169 if (ret)
170 return ret;
171
172 for (i = 0; i < len; i++) {
173 buf[i] = vals[i/4] & 0xff;
174 vals[i/4] >>= 8;
175 }
176
177 return 0;
178}
179
180static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, u8 len)
181{
182 u32 vals[4] = {};
183 int i;
184
185 if (len > 16)
186 return -EIO;
187
188 for (i = 0; i < len; i++) {
189 unsigned int shift = (i % 4) * 8;
190 unsigned int reg = i / 4;
191
192 vals[reg] |= buf[i] << shift;
193 }
194
195 return regmap_bulk_write(map: i2c->regmap, reg: i2c->data_reg, val: vals, ARRAY_SIZE(vals));
196}
197
198static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data)
199{
200 return regmap_write(map: i2c->regmap, reg: i2c->data_reg, val: data);
201}
202
203static int rtl9300_i2c_prepare_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer)
204{
205 int ret;
206
207 if (xfer->data_len < 1 || xfer->data_len > 16)
208 return -EINVAL;
209
210 ret = regmap_field_write(field: i2c->fields[F_DEV_ADDR], val: xfer->dev_addr);
211 if (ret)
212 return ret;
213
214 ret = rtl9300_i2c_reg_addr_set(i2c, reg: xfer->reg_addr, len: xfer->reg_addr_len);
215 if (ret)
216 return ret;
217
218 ret = regmap_field_write(field: i2c->fields[F_RWOP], val: xfer->write);
219 if (ret)
220 return ret;
221
222 ret = regmap_field_write(field: i2c->fields[F_DATA_WIDTH], val: (xfer->data_len - 1) & 0xf);
223 if (ret)
224 return ret;
225
226 if (xfer->write) {
227 switch (xfer->type) {
228 case RTL9300_I2C_XFER_BYTE:
229 ret = rtl9300_i2c_writel(i2c, data: *xfer->data);
230 break;
231 case RTL9300_I2C_XFER_WORD:
232 ret = rtl9300_i2c_writel(i2c, get_unaligned((const u16 *)xfer->data));
233 break;
234 default:
235 ret = rtl9300_i2c_write(i2c, buf: xfer->data, len: xfer->data_len);
236 break;
237 }
238 }
239
240 return ret;
241}
242
243static int rtl9300_i2c_do_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer)
244{
245 u32 val;
246 int ret;
247
248 ret = regmap_field_write(field: i2c->fields[F_I2C_TRIG], val: 1);
249 if (ret)
250 return ret;
251
252 ret = regmap_field_read_poll_timeout(i2c->fields[F_I2C_TRIG], val, !val, 100, 100000);
253 if (ret)
254 return ret;
255
256 ret = regmap_field_read(field: i2c->fields[F_I2C_FAIL], val: &val);
257 if (ret)
258 return ret;
259 if (val)
260 return -EIO;
261
262 if (!xfer->write) {
263 switch (xfer->type) {
264 case RTL9300_I2C_XFER_BYTE:
265 ret = regmap_read(map: i2c->regmap, reg: i2c->data_reg, val: &val);
266 if (ret)
267 return ret;
268
269 *xfer->data = val & 0xff;
270 break;
271 case RTL9300_I2C_XFER_WORD:
272 ret = regmap_read(map: i2c->regmap, reg: i2c->data_reg, val: &val);
273 if (ret)
274 return ret;
275
276 put_unaligned(val & 0xffff, (u16*)xfer->data);
277 break;
278 default:
279 ret = rtl9300_i2c_read(i2c, buf: xfer->data, len: xfer->data_len);
280 if (ret)
281 return ret;
282 break;
283 }
284 }
285
286 return 0;
287}
288
289static int rtl9300_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, unsigned short flags,
290 char read_write, u8 command, int size,
291 union i2c_smbus_data *data)
292{
293 struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap);
294 struct rtl9300_i2c *i2c = chan->i2c;
295 struct rtl9300_i2c_xfer xfer = {0};
296 int ret;
297
298 if (addr > 0x7f)
299 return -EINVAL;
300
301 guard(rtl9300_i2c)(T: i2c);
302
303 ret = rtl9300_i2c_config_chan(i2c, chan);
304 if (ret)
305 return ret;
306
307 xfer.dev_addr = addr & 0x7f;
308 xfer.write = (read_write == I2C_SMBUS_WRITE);
309 xfer.reg_addr = command;
310 xfer.reg_addr_len = 1;
311
312 switch (size) {
313 case I2C_SMBUS_BYTE:
314 xfer.data = (read_write == I2C_SMBUS_READ) ? &data->byte : &command;
315 xfer.data_len = 1;
316 xfer.reg_addr = 0;
317 xfer.reg_addr_len = 0;
318 xfer.type = RTL9300_I2C_XFER_BYTE;
319 break;
320 case I2C_SMBUS_BYTE_DATA:
321 xfer.data = &data->byte;
322 xfer.data_len = 1;
323 xfer.type = RTL9300_I2C_XFER_BYTE;
324 break;
325 case I2C_SMBUS_WORD_DATA:
326 xfer.data = (u8 *)&data->word;
327 xfer.data_len = 2;
328 xfer.type = RTL9300_I2C_XFER_WORD;
329 break;
330 case I2C_SMBUS_BLOCK_DATA:
331 xfer.data = &data->block[0];
332 xfer.data_len = data->block[0] + 1;
333 xfer.type = RTL9300_I2C_XFER_BLOCK;
334 break;
335 case I2C_SMBUS_I2C_BLOCK_DATA:
336 xfer.data = &data->block[1];
337 xfer.data_len = data->block[0];
338 xfer.type = RTL9300_I2C_XFER_BLOCK;
339 break;
340 default:
341 dev_err(&adap->dev, "Unsupported transaction %d\n", size);
342 return -EOPNOTSUPP;
343 }
344
345 ret = rtl9300_i2c_prepare_xfer(i2c, xfer: &xfer);
346 if (ret)
347 return ret;
348
349 return rtl9300_i2c_do_xfer(i2c, xfer: &xfer);
350}
351
352static u32 rtl9300_i2c_func(struct i2c_adapter *a)
353{
354 return I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
355 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
356 I2C_FUNC_SMBUS_I2C_BLOCK;
357}
358
359static const struct i2c_algorithm rtl9300_i2c_algo = {
360 .smbus_xfer = rtl9300_i2c_smbus_xfer,
361 .functionality = rtl9300_i2c_func,
362};
363
364static struct i2c_adapter_quirks rtl9300_i2c_quirks = {
365 .flags = I2C_AQ_NO_CLK_STRETCH | I2C_AQ_NO_ZERO_LEN,
366 .max_read_len = 16,
367 .max_write_len = 16,
368};
369
370static int rtl9300_i2c_probe(struct platform_device *pdev)
371{
372 struct device *dev = &pdev->dev;
373 struct rtl9300_i2c *i2c;
374 struct fwnode_handle *child;
375 struct rtl9300_i2c_drv_data *drv_data;
376 struct reg_field fields[F_NUM_FIELDS];
377 u32 clock_freq, scl_num, sda_num;
378 int ret, i = 0;
379
380 i2c = devm_kzalloc(dev, size: sizeof(*i2c), GFP_KERNEL);
381 if (!i2c)
382 return -ENOMEM;
383
384 i2c->regmap = syscon_node_to_regmap(np: dev->parent->of_node);
385 if (IS_ERR(ptr: i2c->regmap))
386 return PTR_ERR(ptr: i2c->regmap);
387 i2c->dev = dev;
388
389 mutex_init(&i2c->lock);
390
391 ret = device_property_read_u32(dev, propname: "reg", val: &i2c->reg_base);
392 if (ret)
393 return ret;
394
395 ret = device_property_read_u32(dev, propname: "realtek,scl", val: &scl_num);
396 if (ret || scl_num != 1)
397 scl_num = 0;
398 i2c->scl_num = (u8)scl_num;
399
400 platform_set_drvdata(pdev, data: i2c);
401
402 drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(dev: i2c->dev);
403 if (device_get_child_node_count(dev) > drv_data->max_nchan)
404 return dev_err_probe(dev, err: -EINVAL, fmt: "Too many channels\n");
405
406 i2c->data_reg = i2c->reg_base + drv_data->data_reg;
407 for (i = 0; i < F_NUM_FIELDS; i++) {
408 fields[i] = drv_data->field_desc[i].field;
409 if (drv_data->field_desc[i].scope == REG_SCOPE_MASTER)
410 fields[i].reg += i2c->reg_base;
411 }
412 ret = devm_regmap_field_bulk_alloc(dev, regmap: i2c->regmap, field: i2c->fields,
413 reg_field: fields, num_fields: F_NUM_FIELDS);
414 if (ret)
415 return ret;
416
417 i = 0;
418 device_for_each_child_node(dev, child) {
419 struct rtl9300_i2c_chan *chan = &i2c->chans[i];
420 struct i2c_adapter *adap = &chan->adap;
421
422 ret = fwnode_property_read_u32(fwnode: child, propname: "reg", val: &sda_num);
423 if (ret)
424 return ret;
425
426 ret = fwnode_property_read_u32(fwnode: child, propname: "clock-frequency", val: &clock_freq);
427 if (ret)
428 clock_freq = I2C_MAX_STANDARD_MODE_FREQ;
429
430 switch (clock_freq) {
431 case I2C_MAX_STANDARD_MODE_FREQ:
432 chan->bus_freq = RTL9300_I2C_STD_FREQ;
433 break;
434 case I2C_MAX_FAST_MODE_FREQ:
435 chan->bus_freq = RTL9300_I2C_FAST_FREQ;
436 break;
437 default:
438 dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n",
439 sda_num, clock_freq);
440 break;
441 }
442
443 chan->sda_num = sda_num;
444 chan->i2c = i2c;
445 adap = &i2c->chans[i].adap;
446 adap->owner = THIS_MODULE;
447 adap->algo = &rtl9300_i2c_algo;
448 adap->quirks = &rtl9300_i2c_quirks;
449 adap->retries = 3;
450 adap->dev.parent = dev;
451 i2c_set_adapdata(adap, data: chan);
452 adap->dev.of_node = to_of_node(child);
453 snprintf(buf: adap->name, size: sizeof(adap->name), fmt: "%s SDA%d\n", dev_name(dev), sda_num);
454 i++;
455
456 ret = devm_i2c_add_adapter(dev, adapter: adap);
457 if (ret)
458 return ret;
459 }
460 i2c->sda_num = 0xff;
461
462 /* only use standard read format */
463 ret = regmap_field_write(field: i2c->fields[F_RD_MODE], val: 0);
464 if (ret)
465 return ret;
466
467 return 0;
468}
469
470#define GLB_REG_FIELD(reg, msb, lsb) \
471 { .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_GLOBAL }
472#define MST_REG_FIELD(reg, msb, lsb) \
473 { .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_MASTER }
474
475static const struct rtl9300_i2c_drv_data rtl9300_i2c_drv_data = {
476 .field_desc = {
477 [F_MEM_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 8, 31),
478 [F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 4, 6),
479 [F_SCL_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 3, 3),
480 [F_RWOP] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 2, 2),
481 [F_I2C_FAIL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 1, 1),
482 [F_I2C_TRIG] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0),
483 [F_RD_MODE] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 15, 15),
484 [F_DEV_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 8, 14),
485 [F_DATA_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 4, 7),
486 [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 2, 3),
487 [F_SCL_FREQ] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 0, 1),
488 [F_SDA_SEL] = GLB_REG_FIELD(RTL9300_I2C_MST_GLB_CTRL, 0, 7),
489 },
490 .select_scl = rtl9300_i2c_select_scl,
491 .data_reg = RTL9300_I2C_MST_DATA_WORD0,
492 .max_nchan = RTL9300_I2C_MUX_NCHAN,
493};
494
495static const struct rtl9300_i2c_drv_data rtl9310_i2c_drv_data = {
496 .field_desc = {
497 [F_SCL_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 12, 13),
498 [F_SDA_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 0, 11),
499 [F_SCL_FREQ] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 30, 31),
500 [F_DEV_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 11, 17),
501 [F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 18, 21),
502 [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 9, 10),
503 [F_DATA_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 5, 8),
504 [F_RD_MODE] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 4, 4),
505 [F_RWOP] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 2, 2),
506 [F_I2C_FAIL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 1, 1),
507 [F_I2C_TRIG] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0),
508 [F_MEM_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_MEMADDR_CTRL, 0, 23),
509 },
510 .select_scl = rtl9310_i2c_select_scl,
511 .data_reg = RTL9310_I2C_MST_DATA_CTRL,
512 .max_nchan = RTL9310_I2C_MUX_NCHAN,
513};
514
515static const struct of_device_id i2c_rtl9300_dt_ids[] = {
516 { .compatible = "realtek,rtl9301-i2c", .data = (void *) &rtl9300_i2c_drv_data },
517 { .compatible = "realtek,rtl9302b-i2c", .data = (void *) &rtl9300_i2c_drv_data },
518 { .compatible = "realtek,rtl9302c-i2c", .data = (void *) &rtl9300_i2c_drv_data },
519 { .compatible = "realtek,rtl9303-i2c", .data = (void *) &rtl9300_i2c_drv_data },
520 { .compatible = "realtek,rtl9310-i2c", .data = (void *) &rtl9310_i2c_drv_data },
521 { .compatible = "realtek,rtl9311-i2c", .data = (void *) &rtl9310_i2c_drv_data },
522 { .compatible = "realtek,rtl9312-i2c", .data = (void *) &rtl9310_i2c_drv_data },
523 { .compatible = "realtek,rtl9313-i2c", .data = (void *) &rtl9310_i2c_drv_data },
524 {}
525};
526MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids);
527
528static struct platform_driver rtl9300_i2c_driver = {
529 .probe = rtl9300_i2c_probe,
530 .driver = {
531 .name = "i2c-rtl9300",
532 .of_match_table = i2c_rtl9300_dt_ids,
533 },
534};
535
536module_platform_driver(rtl9300_i2c_driver);
537
538MODULE_DESCRIPTION("RTL9300 I2C controller driver");
539MODULE_LICENSE("GPL");
540

source code of linux/drivers/i2c/busses/i2c-rtl9300.c