1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Nvidia GPU I2C controller Driver
4 *
5 * Copyright (C) 2018 NVIDIA Corporation. All rights reserved.
6 * Author: Ajay Gupta <ajayg@nvidia.com>
7 */
8#include <linux/delay.h>
9#include <linux/i2c.h>
10#include <linux/interrupt.h>
11#include <linux/iopoll.h>
12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/platform_device.h>
15#include <linux/pm.h>
16#include <linux/pm_runtime.h>
17#include <linux/power_supply.h>
18
19#include <linux/unaligned.h>
20
21#include "i2c-ccgx-ucsi.h"
22
23/* I2C definitions */
24#define I2C_MST_CNTL 0x00
25#define I2C_MST_CNTL_GEN_START BIT(0)
26#define I2C_MST_CNTL_GEN_STOP BIT(1)
27#define I2C_MST_CNTL_CMD_READ (1 << 2)
28#define I2C_MST_CNTL_CMD_WRITE (2 << 2)
29#define I2C_MST_CNTL_BURST_SIZE_SHIFT 6
30#define I2C_MST_CNTL_GEN_NACK BIT(28)
31#define I2C_MST_CNTL_STATUS GENMASK(30, 29)
32#define I2C_MST_CNTL_STATUS_OKAY (0 << 29)
33#define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29)
34#define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29)
35#define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29)
36#define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31)
37
38#define I2C_MST_ADDR 0x04
39
40#define I2C_MST_I2C0_TIMING 0x08
41#define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e
42#define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16
43#define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255
44#define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24)
45
46#define I2C_MST_DATA 0x0c
47
48#define I2C_MST_HYBRID_PADCTL 0x20
49#define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0)
50#define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14)
51#define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15)
52
53struct gpu_i2c_dev {
54 struct device *dev;
55 void __iomem *regs;
56 struct i2c_adapter adapter;
57 struct i2c_board_info *gpu_ccgx_ucsi;
58 struct i2c_client *ccgx_client;
59};
60
61static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
62{
63 u32 val;
64
65 /* enable I2C */
66 val = readl(addr: i2cd->regs + I2C_MST_HYBRID_PADCTL);
67 val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
68 I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
69 I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
70 writel(val, addr: i2cd->regs + I2C_MST_HYBRID_PADCTL);
71
72 /* enable 100KHZ mode */
73 val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
74 val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
75 << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
76 val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
77 writel(val, addr: i2cd->regs + I2C_MST_I2C0_TIMING);
78}
79
80static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
81{
82 u32 val;
83 int ret;
84
85 ret = readl_poll_timeout(i2cd->regs + I2C_MST_CNTL, val,
86 !(val & I2C_MST_CNTL_CYCLE_TRIGGER) ||
87 (val & I2C_MST_CNTL_STATUS) != I2C_MST_CNTL_STATUS_BUS_BUSY,
88 500, 1000 * USEC_PER_MSEC);
89
90 if (ret) {
91 dev_err(i2cd->dev, "i2c timeout error %x\n", val);
92 return -ETIMEDOUT;
93 }
94
95 val = readl(addr: i2cd->regs + I2C_MST_CNTL);
96 switch (val & I2C_MST_CNTL_STATUS) {
97 case I2C_MST_CNTL_STATUS_OKAY:
98 return 0;
99 case I2C_MST_CNTL_STATUS_NO_ACK:
100 return -ENXIO;
101 case I2C_MST_CNTL_STATUS_TIMEOUT:
102 return -ETIMEDOUT;
103 default:
104 return 0;
105 }
106}
107
108static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
109{
110 int status;
111 u32 val;
112
113 val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
114 (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
115 I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
116 writel(val, addr: i2cd->regs + I2C_MST_CNTL);
117
118 status = gpu_i2c_check_status(i2cd);
119 if (status < 0)
120 return status;
121
122 val = readl(addr: i2cd->regs + I2C_MST_DATA);
123 switch (len) {
124 case 1:
125 data[0] = val;
126 break;
127 case 2:
128 put_unaligned_be16(val, p: data);
129 break;
130 case 3:
131 put_unaligned_be24(val, p: data);
132 break;
133 case 4:
134 put_unaligned_be32(val, p: data);
135 break;
136 default:
137 break;
138 }
139 return status;
140}
141
142static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
143{
144 writel(I2C_MST_CNTL_GEN_START, addr: i2cd->regs + I2C_MST_CNTL);
145 return gpu_i2c_check_status(i2cd);
146}
147
148static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
149{
150 writel(I2C_MST_CNTL_GEN_STOP, addr: i2cd->regs + I2C_MST_CNTL);
151 return gpu_i2c_check_status(i2cd);
152}
153
154static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
155{
156 u32 val;
157
158 writel(val: data, addr: i2cd->regs + I2C_MST_DATA);
159
160 val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
161 writel(val, addr: i2cd->regs + I2C_MST_CNTL);
162
163 return gpu_i2c_check_status(i2cd);
164}
165
166static int gpu_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
167{
168 struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
169 int status, status2;
170 bool send_stop = true;
171 int i, j;
172
173 /*
174 * The controller supports maximum 4 byte read due to known
175 * limitation of sending STOP after every read.
176 */
177 pm_runtime_get_sync(dev: i2cd->dev);
178 for (i = 0; i < num; i++) {
179 if (msgs[i].flags & I2C_M_RD) {
180 /* program client address before starting read */
181 writel(val: msgs[i].addr, addr: i2cd->regs + I2C_MST_ADDR);
182 /* gpu_i2c_read has implicit start */
183 status = gpu_i2c_read(i2cd, data: msgs[i].buf, len: msgs[i].len);
184 if (status < 0)
185 goto exit;
186 } else {
187 u8 addr = i2c_8bit_addr_from_msg(msg: msgs + i);
188
189 status = gpu_i2c_start(i2cd);
190 if (status < 0) {
191 if (i == 0)
192 send_stop = false;
193 goto exit;
194 }
195
196 status = gpu_i2c_write(i2cd, data: addr);
197 if (status < 0)
198 goto exit;
199
200 for (j = 0; j < msgs[i].len; j++) {
201 status = gpu_i2c_write(i2cd, data: msgs[i].buf[j]);
202 if (status < 0)
203 goto exit;
204 }
205 }
206 }
207 send_stop = false;
208 status = gpu_i2c_stop(i2cd);
209 if (status < 0)
210 goto exit;
211
212 status = i;
213exit:
214 if (send_stop) {
215 status2 = gpu_i2c_stop(i2cd);
216 if (status2 < 0)
217 dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
218 }
219 pm_runtime_put_autosuspend(dev: i2cd->dev);
220 return status;
221}
222
223static const struct i2c_adapter_quirks gpu_i2c_quirks = {
224 .max_read_len = 4,
225 .max_comb_2nd_msg_len = 4,
226 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
227};
228
229static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
230{
231 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
232}
233
234static const struct i2c_algorithm gpu_i2c_algorithm = {
235 .xfer = gpu_i2c_xfer,
236 .functionality = gpu_i2c_functionality,
237};
238
239/*
240 * This driver is for Nvidia GPU cards with USB Type-C interface.
241 * We want to identify the cards using vendor ID and class code only
242 * to avoid dependency of adding product id for any new card which
243 * requires this driver.
244 * Currently there is no class code defined for UCSI device over PCI
245 * so using UNKNOWN class for now and it will be updated when UCSI
246 * over PCI gets a class code.
247 * There is no other NVIDIA cards with UNKNOWN class code. Even if the
248 * driver gets loaded for an undesired card then eventually i2c_read()
249 * (initiated from UCSI i2c_client) will timeout or UCSI commands will
250 * timeout.
251 */
252#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
253static const struct pci_device_id gpu_i2c_ids[] = {
254 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
255 PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
256 { }
257};
258MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
259
260static const struct property_entry ccgx_props[] = {
261 /* Use FW built for NVIDIA GPU only */
262 PROPERTY_ENTRY_STRING("firmware-name", "nvidia,gpu"),
263 /* USB-C doesn't power the system */
264 PROPERTY_ENTRY_U8("scope", POWER_SUPPLY_SCOPE_DEVICE),
265 { }
266};
267
268static const struct software_node ccgx_node = {
269 .properties = ccgx_props,
270};
271
272static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
273{
274 struct device *dev = &pdev->dev;
275 struct gpu_i2c_dev *i2cd;
276 int status;
277
278 i2cd = devm_kzalloc(dev, size: sizeof(*i2cd), GFP_KERNEL);
279 if (!i2cd)
280 return -ENOMEM;
281
282 i2cd->dev = dev;
283 dev_set_drvdata(dev, data: i2cd);
284
285 status = pcim_enable_device(pdev);
286 if (status < 0)
287 return dev_err_probe(dev, err: status, fmt: "pcim_enable_device failed\n");
288
289 pci_set_master(dev: pdev);
290
291 i2cd->regs = pcim_iomap(pdev, bar: 0, maxlen: 0);
292 if (!i2cd->regs)
293 return dev_err_probe(dev, err: -ENOMEM, fmt: "pcim_iomap failed\n");
294
295 status = pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_MSI);
296 if (status < 0)
297 return dev_err_probe(dev, err: status, fmt: "pci_alloc_irq_vectors err\n");
298
299 gpu_enable_i2c_bus(i2cd);
300
301 i2c_set_adapdata(adap: &i2cd->adapter, data: i2cd);
302 i2cd->adapter.owner = THIS_MODULE;
303 strscpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
304 sizeof(i2cd->adapter.name));
305 i2cd->adapter.algo = &gpu_i2c_algorithm;
306 i2cd->adapter.quirks = &gpu_i2c_quirks;
307 i2cd->adapter.dev.parent = dev;
308 status = i2c_add_adapter(adap: &i2cd->adapter);
309 if (status < 0)
310 goto free_irq_vectors;
311
312 i2cd->ccgx_client = i2c_new_ccgx_ucsi(adapter: &i2cd->adapter, irq: pdev->irq, swnode: &ccgx_node);
313 if (IS_ERR(ptr: i2cd->ccgx_client)) {
314 status = dev_err_probe(dev, err: PTR_ERR(ptr: i2cd->ccgx_client), fmt: "register UCSI failed\n");
315 goto del_adapter;
316 }
317
318 pm_runtime_set_autosuspend_delay(dev, delay: 3000);
319 pm_runtime_use_autosuspend(dev);
320 pm_runtime_put_autosuspend(dev);
321 pm_runtime_allow(dev);
322
323 return 0;
324
325del_adapter:
326 i2c_del_adapter(adap: &i2cd->adapter);
327free_irq_vectors:
328 pci_free_irq_vectors(dev: pdev);
329 return status;
330}
331
332static void gpu_i2c_remove(struct pci_dev *pdev)
333{
334 struct gpu_i2c_dev *i2cd = pci_get_drvdata(pdev);
335
336 pm_runtime_get_noresume(dev: i2cd->dev);
337 i2c_del_adapter(adap: &i2cd->adapter);
338 pci_free_irq_vectors(dev: pdev);
339}
340
341#define gpu_i2c_suspend NULL
342
343static __maybe_unused int gpu_i2c_resume(struct device *dev)
344{
345 struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
346
347 gpu_enable_i2c_bus(i2cd);
348 /*
349 * Runtime resume ccgx client so that it can see for any
350 * connector change event. Old ccg firmware has known
351 * issue of not triggering interrupt when a device is
352 * connected to runtime resume the controller.
353 */
354 pm_request_resume(dev: &i2cd->ccgx_client->dev);
355 return 0;
356}
357
358static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume,
359 NULL);
360
361static struct pci_driver gpu_i2c_driver = {
362 .name = "nvidia-gpu",
363 .id_table = gpu_i2c_ids,
364 .probe = gpu_i2c_probe,
365 .remove = gpu_i2c_remove,
366 .driver = {
367 .pm = &gpu_i2c_driver_pm,
368 },
369};
370
371module_pci_driver(gpu_i2c_driver);
372
373MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
374MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
375MODULE_LICENSE("GPL v2");
376

source code of linux/drivers/i2c/busses/i2c-nvidia-gpu.c