1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2014 Broadcom Corporation
3
4#include <linux/delay.h>
5#include <linux/i2c.h>
6#include <linux/interrupt.h>
7#include <linux/io.h>
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <linux/slab.h>
13
14#define IDM_CTRL_DIRECT_OFFSET 0x00
15#define CFG_OFFSET 0x00
16#define CFG_RESET_SHIFT 31
17#define CFG_EN_SHIFT 30
18#define CFG_SLAVE_ADDR_0_SHIFT 28
19#define CFG_M_RETRY_CNT_SHIFT 16
20#define CFG_M_RETRY_CNT_MASK 0x0f
21
22#define TIM_CFG_OFFSET 0x04
23#define TIM_CFG_MODE_400_SHIFT 31
24#define TIM_RAND_SLAVE_STRETCH_SHIFT 24
25#define TIM_RAND_SLAVE_STRETCH_MASK 0x7f
26#define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16
27#define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f
28
29#define S_CFG_SMBUS_ADDR_OFFSET 0x08
30#define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31
31#define S_CFG_NIC_SMB_ADDR3_SHIFT 24
32#define S_CFG_NIC_SMB_ADDR3_MASK 0x7f
33#define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23
34#define S_CFG_NIC_SMB_ADDR2_SHIFT 16
35#define S_CFG_NIC_SMB_ADDR2_MASK 0x7f
36#define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15
37#define S_CFG_NIC_SMB_ADDR1_SHIFT 8
38#define S_CFG_NIC_SMB_ADDR1_MASK 0x7f
39#define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7
40#define S_CFG_NIC_SMB_ADDR0_SHIFT 0
41#define S_CFG_NIC_SMB_ADDR0_MASK 0x7f
42
43#define M_FIFO_CTRL_OFFSET 0x0c
44#define M_FIFO_RX_FLUSH_SHIFT 31
45#define M_FIFO_TX_FLUSH_SHIFT 30
46#define M_FIFO_RX_CNT_SHIFT 16
47#define M_FIFO_RX_CNT_MASK 0x7f
48#define M_FIFO_RX_THLD_SHIFT 8
49#define M_FIFO_RX_THLD_MASK 0x3f
50
51#define S_FIFO_CTRL_OFFSET 0x10
52#define S_FIFO_RX_FLUSH_SHIFT 31
53#define S_FIFO_TX_FLUSH_SHIFT 30
54#define S_FIFO_RX_CNT_SHIFT 16
55#define S_FIFO_RX_CNT_MASK 0x7f
56#define S_FIFO_RX_THLD_SHIFT 8
57#define S_FIFO_RX_THLD_MASK 0x3f
58
59#define M_CMD_OFFSET 0x30
60#define M_CMD_START_BUSY_SHIFT 31
61#define M_CMD_STATUS_SHIFT 25
62#define M_CMD_STATUS_MASK 0x07
63#define M_CMD_STATUS_SUCCESS 0x0
64#define M_CMD_STATUS_LOST_ARB 0x1
65#define M_CMD_STATUS_NACK_ADDR 0x2
66#define M_CMD_STATUS_NACK_DATA 0x3
67#define M_CMD_STATUS_TIMEOUT 0x4
68#define M_CMD_STATUS_FIFO_UNDERRUN 0x5
69#define M_CMD_STATUS_RX_FIFO_FULL 0x6
70#define M_CMD_PROTOCOL_SHIFT 9
71#define M_CMD_PROTOCOL_MASK 0xf
72#define M_CMD_PROTOCOL_QUICK 0x0
73#define M_CMD_PROTOCOL_BLK_WR 0x7
74#define M_CMD_PROTOCOL_BLK_RD 0x8
75#define M_CMD_PROTOCOL_PROCESS 0xa
76#define M_CMD_PEC_SHIFT 8
77#define M_CMD_RD_CNT_SHIFT 0
78#define M_CMD_RD_CNT_MASK 0xff
79
80#define S_CMD_OFFSET 0x34
81#define S_CMD_START_BUSY_SHIFT 31
82#define S_CMD_STATUS_SHIFT 23
83#define S_CMD_STATUS_MASK 0x07
84#define S_CMD_STATUS_SUCCESS 0x0
85#define S_CMD_STATUS_TIMEOUT 0x5
86#define S_CMD_STATUS_MASTER_ABORT 0x7
87
88#define IE_OFFSET 0x38
89#define IE_M_RX_FIFO_FULL_SHIFT 31
90#define IE_M_RX_THLD_SHIFT 30
91#define IE_M_START_BUSY_SHIFT 28
92#define IE_M_TX_UNDERRUN_SHIFT 27
93#define IE_S_RX_FIFO_FULL_SHIFT 26
94#define IE_S_RX_THLD_SHIFT 25
95#define IE_S_RX_EVENT_SHIFT 24
96#define IE_S_START_BUSY_SHIFT 23
97#define IE_S_TX_UNDERRUN_SHIFT 22
98#define IE_S_RD_EVENT_SHIFT 21
99
100#define IS_OFFSET 0x3c
101#define IS_M_RX_FIFO_FULL_SHIFT 31
102#define IS_M_RX_THLD_SHIFT 30
103#define IS_M_START_BUSY_SHIFT 28
104#define IS_M_TX_UNDERRUN_SHIFT 27
105#define IS_S_RX_FIFO_FULL_SHIFT 26
106#define IS_S_RX_THLD_SHIFT 25
107#define IS_S_RX_EVENT_SHIFT 24
108#define IS_S_START_BUSY_SHIFT 23
109#define IS_S_TX_UNDERRUN_SHIFT 22
110#define IS_S_RD_EVENT_SHIFT 21
111
112#define M_TX_OFFSET 0x40
113#define M_TX_WR_STATUS_SHIFT 31
114#define M_TX_DATA_SHIFT 0
115#define M_TX_DATA_MASK 0xff
116
117#define M_RX_OFFSET 0x44
118#define M_RX_STATUS_SHIFT 30
119#define M_RX_STATUS_MASK 0x03
120#define M_RX_PEC_ERR_SHIFT 29
121#define M_RX_DATA_SHIFT 0
122#define M_RX_DATA_MASK 0xff
123
124#define S_TX_OFFSET 0x48
125#define S_TX_WR_STATUS_SHIFT 31
126#define S_TX_DATA_SHIFT 0
127#define S_TX_DATA_MASK 0xff
128
129#define S_RX_OFFSET 0x4c
130#define S_RX_STATUS_SHIFT 30
131#define S_RX_STATUS_MASK 0x03
132#define S_RX_PEC_ERR_SHIFT 29
133#define S_RX_DATA_SHIFT 0
134#define S_RX_DATA_MASK 0xff
135
136#define I2C_TIMEOUT_MSEC 50000
137#define M_TX_RX_FIFO_SIZE 64
138#define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
139
140#define M_RX_MAX_READ_LEN 255
141#define M_RX_FIFO_THLD_VALUE 50
142
143#define IE_M_ALL_INTERRUPT_SHIFT 27
144#define IE_M_ALL_INTERRUPT_MASK 0x1e
145
146#define SLAVE_READ_WRITE_BIT_MASK 0x1
147#define SLAVE_READ_WRITE_BIT_SHIFT 0x1
148#define SLAVE_MAX_SIZE_TRANSACTION 64
149#define SLAVE_CLOCK_STRETCH_TIME 25
150
151#define IE_S_ALL_INTERRUPT_SHIFT 21
152#define IE_S_ALL_INTERRUPT_MASK 0x3f
153/*
154 * It takes ~18us to reading 10bytes of data, hence to keep tasklet
155 * running for less time, max slave read per tasklet is set to 10 bytes.
156 */
157#define MAX_SLAVE_RX_PER_INT 10
158
159enum i2c_slave_read_status {
160 I2C_SLAVE_RX_FIFO_EMPTY = 0,
161 I2C_SLAVE_RX_START,
162 I2C_SLAVE_RX_DATA,
163 I2C_SLAVE_RX_END,
164};
165
166enum bus_speed_index {
167 I2C_SPD_100K = 0,
168 I2C_SPD_400K,
169};
170
171enum bcm_iproc_i2c_type {
172 IPROC_I2C,
173 IPROC_I2C_NIC
174};
175
176struct bcm_iproc_i2c_dev {
177 struct device *device;
178 enum bcm_iproc_i2c_type type;
179 int irq;
180
181 void __iomem *base;
182 void __iomem *idm_base;
183
184 u32 ape_addr_mask;
185
186 /* lock for indirect access through IDM */
187 spinlock_t idm_lock;
188
189 struct i2c_adapter adapter;
190 unsigned int bus_speed;
191
192 struct completion done;
193 int xfer_is_done;
194
195 struct i2c_msg *msg;
196
197 struct i2c_client *slave;
198
199 /* bytes that have been transferred */
200 unsigned int tx_bytes;
201 /* bytes that have been read */
202 unsigned int rx_bytes;
203 unsigned int thld_bytes;
204
205 bool slave_rx_only;
206 bool rx_start_rcvd;
207 bool slave_read_complete;
208 u32 tx_underrun;
209 u32 slave_int_mask;
210 struct tasklet_struct slave_rx_tasklet;
211};
212
213/* tasklet to process slave rx data */
214static void slave_rx_tasklet_fn(unsigned long);
215
216/*
217 * Can be expanded in the future if more interrupt status bits are utilized
218 */
219#define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
220 | BIT(IS_M_RX_THLD_SHIFT))
221
222#define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
223 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
224 | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
225 | BIT(IS_S_RX_THLD_SHIFT))
226
227static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
228 u32 offset)
229{
230 u32 val;
231 unsigned long flags;
232
233 if (iproc_i2c->idm_base) {
234 spin_lock_irqsave(&iproc_i2c->idm_lock, flags);
235 writel(val: iproc_i2c->ape_addr_mask,
236 addr: iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
237 val = readl(addr: iproc_i2c->base + offset);
238 spin_unlock_irqrestore(lock: &iproc_i2c->idm_lock, flags);
239 } else {
240 val = readl(addr: iproc_i2c->base + offset);
241 }
242
243 return val;
244}
245
246static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
247 u32 offset, u32 val)
248{
249 unsigned long flags;
250
251 if (iproc_i2c->idm_base) {
252 spin_lock_irqsave(&iproc_i2c->idm_lock, flags);
253 writel(val: iproc_i2c->ape_addr_mask,
254 addr: iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
255 writel(val, addr: iproc_i2c->base + offset);
256 spin_unlock_irqrestore(lock: &iproc_i2c->idm_lock, flags);
257 } else {
258 writel(val, addr: iproc_i2c->base + offset);
259 }
260}
261
262static void bcm_iproc_i2c_slave_init(struct bcm_iproc_i2c_dev *iproc_i2c,
263 bool need_reset)
264{
265 u32 val;
266
267 iproc_i2c->tx_underrun = 0;
268 if (need_reset) {
269 /* put controller in reset */
270 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
271 val |= BIT(CFG_RESET_SHIFT);
272 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
273
274 /* wait approximately 100 usec as per spec */
275 usleep_range(min: 100, max: 200);
276
277 /* bring controller out of reset */
278 val &= ~(BIT(CFG_RESET_SHIFT));
279 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
280 }
281
282 /* flush TX/RX FIFOs */
283 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
284 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
285
286 /* Maximum slave stretch time */
287 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
288 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
289 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
290 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
291
292 /* Configure the slave address */
293 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
294 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
295 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
296 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
297 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
298
299 /* clear all pending slave interrupts */
300 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
301
302 /* Enable interrupt register to indicate a valid byte in receive fifo */
303 val = BIT(IE_S_RX_EVENT_SHIFT);
304 /* Enable interrupt register to indicate Slave Rx FIFO Full */
305 val |= BIT(IE_S_RX_FIFO_FULL_SHIFT);
306 /* Enable interrupt register to indicate a Master read transaction */
307 val |= BIT(IE_S_RD_EVENT_SHIFT);
308 /* Enable interrupt register for the Slave BUSY command */
309 val |= BIT(IE_S_START_BUSY_SHIFT);
310 iproc_i2c->slave_int_mask = val;
311 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
312}
313
314static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
315 bool enable)
316{
317 u32 val;
318
319 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
320 if (enable)
321 val |= BIT(CFG_EN_SHIFT);
322 else
323 val &= ~BIT(CFG_EN_SHIFT);
324 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
325}
326
327static bool bcm_iproc_i2c_check_slave_status
328 (struct bcm_iproc_i2c_dev *iproc_i2c, u32 status)
329{
330 u32 val;
331 bool recover = false;
332
333 /* check slave transmit status only if slave is transmitting */
334 if (!iproc_i2c->slave_rx_only) {
335 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
336 /* status is valid only when START_BUSY is cleared */
337 if (!(val & BIT(S_CMD_START_BUSY_SHIFT))) {
338 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
339 if (val == S_CMD_STATUS_TIMEOUT ||
340 val == S_CMD_STATUS_MASTER_ABORT) {
341 dev_warn(iproc_i2c->device,
342 (val == S_CMD_STATUS_TIMEOUT) ?
343 "slave random stretch time timeout\n" :
344 "Master aborted read transaction\n");
345 recover = true;
346 }
347 }
348 }
349
350 /* RX_EVENT is not valid when START_BUSY is set */
351 if ((status & BIT(IS_S_RX_EVENT_SHIFT)) &&
352 (status & BIT(IS_S_START_BUSY_SHIFT))) {
353 dev_warn(iproc_i2c->device, "Slave aborted read transaction\n");
354 recover = true;
355 }
356
357 if (recover) {
358 /* re-initialize i2c for recovery */
359 bcm_iproc_i2c_enable_disable(iproc_i2c, enable: false);
360 bcm_iproc_i2c_slave_init(iproc_i2c, need_reset: true);
361 bcm_iproc_i2c_enable_disable(iproc_i2c, enable: true);
362 }
363
364 return recover;
365}
366
367static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)
368{
369 u8 rx_data, rx_status;
370 u32 rx_bytes = 0;
371 u32 val;
372
373 while (rx_bytes < MAX_SLAVE_RX_PER_INT) {
374 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
375 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
376 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
377
378 if (rx_status == I2C_SLAVE_RX_START) {
379 /* Start of SMBUS Master write */
380 i2c_slave_event(client: iproc_i2c->slave,
381 event: I2C_SLAVE_WRITE_REQUESTED, val: &rx_data);
382 iproc_i2c->rx_start_rcvd = true;
383 iproc_i2c->slave_read_complete = false;
384 } else if (rx_status == I2C_SLAVE_RX_DATA &&
385 iproc_i2c->rx_start_rcvd) {
386 /* Middle of SMBUS Master write */
387 i2c_slave_event(client: iproc_i2c->slave,
388 event: I2C_SLAVE_WRITE_RECEIVED, val: &rx_data);
389 } else if (rx_status == I2C_SLAVE_RX_END &&
390 iproc_i2c->rx_start_rcvd) {
391 /* End of SMBUS Master write */
392 if (iproc_i2c->slave_rx_only)
393 i2c_slave_event(client: iproc_i2c->slave,
394 event: I2C_SLAVE_WRITE_RECEIVED,
395 val: &rx_data);
396
397 i2c_slave_event(client: iproc_i2c->slave, event: I2C_SLAVE_STOP,
398 val: &rx_data);
399 } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
400 iproc_i2c->rx_start_rcvd = false;
401 iproc_i2c->slave_read_complete = true;
402 break;
403 }
404
405 rx_bytes++;
406 }
407}
408
409static void slave_rx_tasklet_fn(unsigned long data)
410{
411 struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;
412 u32 int_clr;
413
414 bcm_iproc_i2c_slave_read(iproc_i2c);
415
416 /* clear pending IS_S_RX_EVENT_SHIFT interrupt */
417 int_clr = BIT(IS_S_RX_EVENT_SHIFT);
418
419 if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
420 /*
421 * In case of single byte master-read request,
422 * IS_S_TX_UNDERRUN_SHIFT event is generated before
423 * IS_S_START_BUSY_SHIFT event. Hence start slave data send
424 * from first IS_S_TX_UNDERRUN_SHIFT event.
425 *
426 * This means don't send any data from slave when
427 * IS_S_RD_EVENT_SHIFT event is generated else it will increment
428 * eeprom or other backend slave driver read pointer twice.
429 */
430 iproc_i2c->tx_underrun = 0;
431 iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
432
433 /* clear IS_S_RD_EVENT_SHIFT interrupt */
434 int_clr |= BIT(IS_S_RD_EVENT_SHIFT);
435 }
436
437 /* clear slave interrupt */
438 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val: int_clr);
439 /* enable slave interrupts */
440 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: iproc_i2c->slave_int_mask);
441}
442
443static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
444 u32 status)
445{
446 u32 val;
447 u8 value;
448
449 if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
450 iproc_i2c->tx_underrun++;
451 if (iproc_i2c->tx_underrun == 1)
452 /* Start of SMBUS for Master Read */
453 i2c_slave_event(client: iproc_i2c->slave,
454 event: I2C_SLAVE_READ_REQUESTED,
455 val: &value);
456 else
457 /* Master read other than start */
458 i2c_slave_event(client: iproc_i2c->slave,
459 event: I2C_SLAVE_READ_PROCESSED,
460 val: &value);
461
462 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val: value);
463 /* start transfer */
464 val = BIT(S_CMD_START_BUSY_SHIFT);
465 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
466
467 /* clear interrupt */
468 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
469 BIT(IS_S_TX_UNDERRUN_SHIFT));
470 }
471
472 /* Stop received from master in case of master read transaction */
473 if (status & BIT(IS_S_START_BUSY_SHIFT)) {
474 /*
475 * Disable interrupt for TX FIFO becomes empty and
476 * less than PKT_LENGTH bytes were output on the SMBUS
477 */
478 iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
479 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
480 val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
481 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
482
483 /* End of SMBUS for Master Read */
484 val = BIT(S_TX_WR_STATUS_SHIFT);
485 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
486
487 val = BIT(S_CMD_START_BUSY_SHIFT);
488 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
489
490 /* flush TX FIFOs */
491 val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
492 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
493 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
494
495 i2c_slave_event(client: iproc_i2c->slave, event: I2C_SLAVE_STOP, val: &value);
496
497 /* clear interrupt */
498 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
499 BIT(IS_S_START_BUSY_SHIFT));
500 }
501
502 /* if the controller has been reset, immediately return from the ISR */
503 if (bcm_iproc_i2c_check_slave_status(iproc_i2c, status))
504 return true;
505
506 /*
507 * Slave events in case of master-write, master-write-read and,
508 * master-read
509 *
510 * Master-write : only IS_S_RX_EVENT_SHIFT event
511 * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
512 * events
513 * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
514 * events or only IS_S_RD_EVENT_SHIFT
515 *
516 * iproc has a slave rx fifo size of 64 bytes. Rx fifo full interrupt
517 * (IS_S_RX_FIFO_FULL_SHIFT) will be generated when RX fifo becomes
518 * full. This can happen if Master issues write requests of more than
519 * 64 bytes.
520 */
521 if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
522 status & BIT(IS_S_RD_EVENT_SHIFT) ||
523 status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
524 /* disable slave interrupts */
525 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
526 val &= ~iproc_i2c->slave_int_mask;
527 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
528
529 if (status & BIT(IS_S_RD_EVENT_SHIFT))
530 /* Master-write-read request */
531 iproc_i2c->slave_rx_only = false;
532 else
533 /* Master-write request only */
534 iproc_i2c->slave_rx_only = true;
535
536 /* schedule tasklet to read data later */
537 tasklet_schedule(t: &iproc_i2c->slave_rx_tasklet);
538
539 /* clear IS_S_RX_FIFO_FULL_SHIFT interrupt */
540 if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
541 val = BIT(IS_S_RX_FIFO_FULL_SHIFT);
542 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val);
543 }
544 }
545
546 return true;
547}
548
549static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
550{
551 struct i2c_msg *msg = iproc_i2c->msg;
552 u32 val;
553
554 /* Read valid data from RX FIFO */
555 while (iproc_i2c->rx_bytes < msg->len) {
556 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
557
558 /* rx fifo empty */
559 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
560 break;
561
562 msg->buf[iproc_i2c->rx_bytes] =
563 (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
564 iproc_i2c->rx_bytes++;
565 }
566}
567
568static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
569{
570 struct i2c_msg *msg = iproc_i2c->msg;
571 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
572 unsigned int i;
573 u32 val;
574
575 /* can only fill up to the FIFO size */
576 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
577 for (i = 0; i < tx_bytes; i++) {
578 /* start from where we left over */
579 unsigned int idx = iproc_i2c->tx_bytes + i;
580
581 val = msg->buf[idx];
582
583 /* mark the last byte */
584 if (idx == msg->len - 1) {
585 val |= BIT(M_TX_WR_STATUS_SHIFT);
586
587 if (iproc_i2c->irq) {
588 u32 tmp;
589
590 /*
591 * Since this is the last byte, we should now
592 * disable TX FIFO underrun interrupt
593 */
594 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
595 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
596 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
597 val: tmp);
598 }
599 }
600
601 /* load data into TX FIFO */
602 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
603 }
604
605 /* update number of transferred bytes */
606 iproc_i2c->tx_bytes += tx_bytes;
607}
608
609static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
610{
611 struct i2c_msg *msg = iproc_i2c->msg;
612 u32 bytes_left, val;
613
614 bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
615 bytes_left = msg->len - iproc_i2c->rx_bytes;
616 if (bytes_left == 0) {
617 if (iproc_i2c->irq) {
618 /* finished reading all data, disable rx thld event */
619 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
620 val &= ~BIT(IS_M_RX_THLD_SHIFT);
621 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
622 }
623 } else if (bytes_left < iproc_i2c->thld_bytes) {
624 /* set bytes left as threshold */
625 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
626 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
627 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
628 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
629 iproc_i2c->thld_bytes = bytes_left;
630 }
631 /*
632 * bytes_left >= iproc_i2c->thld_bytes,
633 * hence no need to change the THRESHOLD SET.
634 * It will remain as iproc_i2c->thld_bytes itself
635 */
636}
637
638static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
639 u32 status)
640{
641 /* TX FIFO is empty and we have more data to send */
642 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
643 bcm_iproc_i2c_send(iproc_i2c);
644
645 /* RX FIFO threshold is reached and data needs to be read out */
646 if (status & BIT(IS_M_RX_THLD_SHIFT))
647 bcm_iproc_i2c_read(iproc_i2c);
648
649 /* transfer is done */
650 if (status & BIT(IS_M_START_BUSY_SHIFT)) {
651 iproc_i2c->xfer_is_done = 1;
652 if (iproc_i2c->irq)
653 complete(&iproc_i2c->done);
654 }
655}
656
657static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
658{
659 struct bcm_iproc_i2c_dev *iproc_i2c = data;
660 u32 slave_status;
661 u32 status;
662 bool ret;
663
664 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
665 /* process only slave interrupt which are enabled */
666 slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
667 ISR_MASK_SLAVE;
668
669 if (slave_status) {
670 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, status: slave_status);
671 if (ret)
672 return IRQ_HANDLED;
673 else
674 return IRQ_NONE;
675 }
676
677 status &= ISR_MASK;
678 if (!status)
679 return IRQ_NONE;
680
681 /* process all master based events */
682 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
683 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val: status);
684
685 return IRQ_HANDLED;
686}
687
688static void bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
689{
690 u32 val;
691
692 /* put controller in reset */
693 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
694 val |= BIT(CFG_RESET_SHIFT);
695 val &= ~(BIT(CFG_EN_SHIFT));
696 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
697
698 /* wait approximately 100 usec as per spec */
699 usleep_range(min: 100, max: 200);
700
701 /* bring controller out of reset */
702 val &= ~(BIT(CFG_RESET_SHIFT));
703 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
704
705 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
706 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
707 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
708 /* disable all interrupts */
709 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
710 val &= ~(IE_M_ALL_INTERRUPT_MASK <<
711 IE_M_ALL_INTERRUPT_SHIFT);
712 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
713
714 /* clear all pending interrupts */
715 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val: 0xffffffff);
716}
717
718static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
719 struct i2c_msg *msg)
720{
721 u32 val;
722
723 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
724 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
725
726 switch (val) {
727 case M_CMD_STATUS_SUCCESS:
728 return 0;
729
730 case M_CMD_STATUS_LOST_ARB:
731 dev_err(iproc_i2c->device, "lost bus arbitration\n");
732 return -EAGAIN;
733
734 case M_CMD_STATUS_NACK_ADDR:
735 dev_err(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
736 return -ENXIO;
737
738 case M_CMD_STATUS_NACK_DATA:
739 dev_err(iproc_i2c->device, "NAK data\n");
740 return -ENXIO;
741
742 case M_CMD_STATUS_TIMEOUT:
743 dev_err(iproc_i2c->device, "bus timeout\n");
744 return -ETIMEDOUT;
745
746 case M_CMD_STATUS_FIFO_UNDERRUN:
747 dev_err(iproc_i2c->device, "FIFO under-run\n");
748 return -ENXIO;
749
750 case M_CMD_STATUS_RX_FIFO_FULL:
751 dev_err(iproc_i2c->device, "RX FIFO full\n");
752 return -ETIMEDOUT;
753
754 default:
755 dev_err(iproc_i2c->device, "unknown error code=%d\n", val);
756
757 /* re-initialize i2c for recovery */
758 bcm_iproc_i2c_enable_disable(iproc_i2c, enable: false);
759 bcm_iproc_i2c_init(iproc_i2c);
760 bcm_iproc_i2c_enable_disable(iproc_i2c, enable: true);
761
762 return -EIO;
763 }
764}
765
766static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
767 struct i2c_msg *msg,
768 u32 cmd)
769{
770 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
771 u32 val, status;
772 int ret;
773
774 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, val: cmd);
775
776 if (iproc_i2c->irq) {
777 time_left = wait_for_completion_timeout(x: &iproc_i2c->done,
778 timeout: time_left);
779 /* disable all interrupts */
780 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: 0);
781 /* read it back to flush the write */
782 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
783 /* make sure the interrupt handler isn't running */
784 synchronize_irq(irq: iproc_i2c->irq);
785
786 } else { /* polling mode */
787 unsigned long timeout = jiffies + time_left;
788
789 do {
790 status = iproc_i2c_rd_reg(iproc_i2c,
791 IS_OFFSET) & ISR_MASK;
792 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
793 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val: status);
794
795 if (time_after(jiffies, timeout)) {
796 time_left = 0;
797 break;
798 }
799
800 cpu_relax();
801 cond_resched();
802 } while (!iproc_i2c->xfer_is_done);
803 }
804
805 if (!time_left && !iproc_i2c->xfer_is_done) {
806 /* flush both TX/RX FIFOs */
807 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
808 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
809 return -ETIMEDOUT;
810 }
811
812 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
813 if (ret) {
814 /* flush both TX/RX FIFOs */
815 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
816 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
817 return ret;
818 }
819
820 return 0;
821}
822
823/*
824 * If 'process_call' is true, then this is a multi-msg transfer that requires
825 * a repeated start between the messages.
826 * More specifically, it must be a write (reg) followed by a read (data).
827 * The i2c quirks are set to enforce this rule.
828 */
829static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
830 struct i2c_msg *msgs, bool process_call)
831{
832 int i;
833 u8 addr;
834 u32 val, tmp, val_intr_en;
835 unsigned int tx_bytes;
836 struct i2c_msg *msg = &msgs[0];
837
838 /* check if bus is busy */
839 if (iproc_i2c_rd_reg(iproc_i2c,
840 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT)) {
841 dev_warn(iproc_i2c->device, "bus is busy\n");
842 return -EBUSY;
843 }
844
845 iproc_i2c->msg = msg;
846
847 /* format and load slave address into the TX FIFO */
848 addr = i2c_8bit_addr_from_msg(msg);
849 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val: addr);
850
851 /*
852 * For a write transaction, load data into the TX FIFO. Only allow
853 * loading up to TX FIFO size - 1 bytes of data since the first byte
854 * has been used up by the slave address
855 */
856 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
857 if (!(msg->flags & I2C_M_RD)) {
858 for (i = 0; i < tx_bytes; i++) {
859 val = msg->buf[i];
860
861 /* mark the last byte */
862 if (!process_call && (i == msg->len - 1))
863 val |= BIT(M_TX_WR_STATUS_SHIFT);
864
865 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
866 }
867 iproc_i2c->tx_bytes = tx_bytes;
868 }
869
870 /* Process the read message if this is process call */
871 if (process_call) {
872 msg++;
873 iproc_i2c->msg = msg; /* point to second msg */
874
875 /*
876 * The last byte to be sent out should be a slave
877 * address with read operation
878 */
879 addr = i2c_8bit_addr_from_msg(msg);
880 /* mark it the last byte out */
881 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
882 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
883 }
884
885 /* mark as incomplete before starting the transaction */
886 if (iproc_i2c->irq)
887 reinit_completion(x: &iproc_i2c->done);
888
889 iproc_i2c->xfer_is_done = 0;
890
891 /*
892 * Enable the "start busy" interrupt, which will be triggered after the
893 * transaction is done, i.e., the internal start_busy bit, transitions
894 * from 1 to 0.
895 */
896 val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
897
898 /*
899 * If TX data size is larger than the TX FIFO, need to enable TX
900 * underrun interrupt, which will be triggerred when the TX FIFO is
901 * empty. When that happens we can then pump more data into the FIFO
902 */
903 if (!process_call && !(msg->flags & I2C_M_RD) &&
904 msg->len > iproc_i2c->tx_bytes)
905 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
906
907 /*
908 * Now we can activate the transfer. For a read operation, specify the
909 * number of bytes to read
910 */
911 val = BIT(M_CMD_START_BUSY_SHIFT);
912
913 if (msg->len == 0) {
914 /* SMBUS QUICK Command (Read/Write) */
915 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
916 } else if (msg->flags & I2C_M_RD) {
917 u32 protocol;
918
919 iproc_i2c->rx_bytes = 0;
920 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
921 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
922 else
923 iproc_i2c->thld_bytes = msg->len;
924
925 /* set threshold value */
926 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
927 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
928 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
929 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val: tmp);
930
931 /* enable the RX threshold interrupt */
932 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
933
934 protocol = process_call ?
935 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
936
937 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
938 (msg->len << M_CMD_RD_CNT_SHIFT);
939 } else {
940 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
941 }
942
943 if (iproc_i2c->irq)
944 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: val_intr_en);
945
946 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, cmd: val);
947}
948
949static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
950 struct i2c_msg msgs[], int num)
951{
952 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adap: adapter);
953 bool process_call = false;
954 int ret;
955
956 if (num == 2) {
957 /* Repeated start, use process call */
958 process_call = true;
959 if (msgs[1].flags & I2C_M_NOSTART) {
960 dev_err(iproc_i2c->device, "Invalid repeated start\n");
961 return -EOPNOTSUPP;
962 }
963 }
964
965 ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
966 if (ret) {
967 dev_err(iproc_i2c->device, "xfer failed\n");
968 return ret;
969 }
970
971 return num;
972}
973
974static u32 bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
975{
976 u32 val;
977
978 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
979
980 if (adap->algo->reg_slave)
981 val |= I2C_FUNC_SLAVE;
982
983 return val;
984}
985
986static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
987{
988 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adap: slave->adapter);
989
990 if (iproc_i2c->slave)
991 return -EBUSY;
992
993 if (slave->flags & I2C_CLIENT_TEN)
994 return -EAFNOSUPPORT;
995
996 iproc_i2c->slave = slave;
997
998 tasklet_init(t: &iproc_i2c->slave_rx_tasklet, func: slave_rx_tasklet_fn,
999 data: (unsigned long)iproc_i2c);
1000
1001 bcm_iproc_i2c_slave_init(iproc_i2c, need_reset: false);
1002
1003 return 0;
1004}
1005
1006static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1007{
1008 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adap: slave->adapter);
1009 u32 tmp;
1010
1011 if (!iproc_i2c->slave)
1012 return -EINVAL;
1013
1014 disable_irq(irq: iproc_i2c->irq);
1015
1016 tasklet_kill(t: &iproc_i2c->slave_rx_tasklet);
1017
1018 /* disable all slave interrupts */
1019 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1020 tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1021 IE_S_ALL_INTERRUPT_SHIFT);
1022 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: tmp);
1023
1024 /* Erase the slave address programmed */
1025 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1026 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1027 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val: tmp);
1028
1029 /* flush TX/RX FIFOs */
1030 tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
1031 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val: tmp);
1032
1033 /* clear all pending slave interrupts */
1034 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
1035
1036 iproc_i2c->slave = NULL;
1037
1038 enable_irq(irq: iproc_i2c->irq);
1039
1040 return 0;
1041}
1042
1043static struct i2c_algorithm bcm_iproc_algo = {
1044 .xfer = bcm_iproc_i2c_xfer,
1045 .functionality = bcm_iproc_i2c_functionality,
1046 .reg_slave = bcm_iproc_i2c_reg_slave,
1047 .unreg_slave = bcm_iproc_i2c_unreg_slave,
1048};
1049
1050static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
1051 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
1052 .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
1053 .max_read_len = M_RX_MAX_READ_LEN,
1054};
1055
1056static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
1057{
1058 unsigned int bus_speed;
1059 u32 val;
1060 int ret = of_property_read_u32(np: iproc_i2c->device->of_node,
1061 propname: "clock-frequency", out_value: &bus_speed);
1062 if (ret < 0) {
1063 dev_info(iproc_i2c->device,
1064 "unable to interpret clock-frequency DT property\n");
1065 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
1066 }
1067
1068 if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ)
1069 return dev_err_probe(dev: iproc_i2c->device, err: -EINVAL,
1070 fmt: "%d Hz not supported (out of 100-400 kHz range)\n",
1071 bus_speed);
1072 else if (bus_speed < I2C_MAX_FAST_MODE_FREQ)
1073 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
1074 else
1075 bus_speed = I2C_MAX_FAST_MODE_FREQ;
1076
1077 iproc_i2c->bus_speed = bus_speed;
1078 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1079 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1080 val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1081 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1082
1083 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
1084
1085 return 0;
1086}
1087
1088static int bcm_iproc_i2c_probe(struct platform_device *pdev)
1089{
1090 struct bcm_iproc_i2c_dev *iproc_i2c;
1091 struct i2c_adapter *adap;
1092 int irq, ret;
1093
1094 iproc_i2c = devm_kzalloc(dev: &pdev->dev, size: sizeof(*iproc_i2c),
1095 GFP_KERNEL);
1096 if (!iproc_i2c)
1097 return -ENOMEM;
1098
1099 platform_set_drvdata(pdev, data: iproc_i2c);
1100 iproc_i2c->device = &pdev->dev;
1101 iproc_i2c->type = (kernel_ulong_t)of_device_get_match_data(dev: &pdev->dev);
1102 init_completion(x: &iproc_i2c->done);
1103
1104 iproc_i2c->base = devm_platform_ioremap_resource(pdev, index: 0);
1105 if (IS_ERR(ptr: iproc_i2c->base))
1106 return PTR_ERR(ptr: iproc_i2c->base);
1107
1108 if (iproc_i2c->type == IPROC_I2C_NIC) {
1109 iproc_i2c->idm_base = devm_platform_ioremap_resource(pdev, index: 1);
1110 if (IS_ERR(ptr: iproc_i2c->idm_base))
1111 return PTR_ERR(ptr: iproc_i2c->idm_base);
1112
1113 ret = of_property_read_u32(np: iproc_i2c->device->of_node,
1114 propname: "brcm,ape-hsls-addr-mask",
1115 out_value: &iproc_i2c->ape_addr_mask);
1116 if (ret < 0)
1117 return dev_err_probe(dev: iproc_i2c->device, err: ret,
1118 fmt: "'brcm,ape-hsls-addr-mask' missing\n");
1119
1120 spin_lock_init(&iproc_i2c->idm_lock);
1121
1122 /* no slave support */
1123 bcm_iproc_algo.reg_slave = NULL;
1124 bcm_iproc_algo.unreg_slave = NULL;
1125 }
1126
1127 bcm_iproc_i2c_init(iproc_i2c);
1128
1129 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
1130 if (ret)
1131 return ret;
1132
1133 irq = platform_get_irq(pdev, 0);
1134 if (irq > 0) {
1135 ret = devm_request_irq(dev: iproc_i2c->device, irq,
1136 handler: bcm_iproc_i2c_isr, irqflags: 0, devname: pdev->name,
1137 dev_id: iproc_i2c);
1138 if (ret < 0)
1139 return dev_err_probe(dev: iproc_i2c->device, err: ret,
1140 fmt: "unable to request irq %i\n", irq);
1141
1142 iproc_i2c->irq = irq;
1143 } else {
1144 dev_warn(iproc_i2c->device,
1145 "no irq resource, falling back to poll mode\n");
1146 }
1147
1148 bcm_iproc_i2c_enable_disable(iproc_i2c, enable: true);
1149
1150 adap = &iproc_i2c->adapter;
1151 i2c_set_adapdata(adap, data: iproc_i2c);
1152 snprintf(buf: adap->name, size: sizeof(adap->name), fmt: "Broadcom iProc (%s)",
1153 of_node_full_name(np: iproc_i2c->device->of_node));
1154 adap->algo = &bcm_iproc_algo;
1155 adap->quirks = &bcm_iproc_i2c_quirks;
1156 adap->dev.parent = &pdev->dev;
1157 adap->dev.of_node = pdev->dev.of_node;
1158
1159 return i2c_add_adapter(adap);
1160}
1161
1162static void bcm_iproc_i2c_remove(struct platform_device *pdev)
1163{
1164 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
1165
1166 if (iproc_i2c->irq) {
1167 /*
1168 * Make sure there's no pending interrupt when we remove the
1169 * adapter
1170 */
1171 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: 0);
1172 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1173 synchronize_irq(irq: iproc_i2c->irq);
1174 }
1175
1176 i2c_del_adapter(adap: &iproc_i2c->adapter);
1177 bcm_iproc_i2c_enable_disable(iproc_i2c, enable: false);
1178}
1179
1180static int bcm_iproc_i2c_suspend(struct device *dev)
1181{
1182 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1183
1184 if (iproc_i2c->irq) {
1185 /*
1186 * Make sure there's no pending interrupt when we go into
1187 * suspend
1188 */
1189 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: 0);
1190 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1191 synchronize_irq(irq: iproc_i2c->irq);
1192 }
1193
1194 /* now disable the controller */
1195 bcm_iproc_i2c_enable_disable(iproc_i2c, enable: false);
1196
1197 return 0;
1198}
1199
1200static int bcm_iproc_i2c_resume(struct device *dev)
1201{
1202 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1203 u32 val;
1204
1205 /*
1206 * Power domain could have been shut off completely in system deep
1207 * sleep, so re-initialize the block here
1208 */
1209 bcm_iproc_i2c_init(iproc_i2c);
1210
1211 /* configure to the desired bus speed */
1212 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1213 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1214 val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1215 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1216
1217 bcm_iproc_i2c_enable_disable(iproc_i2c, enable: true);
1218
1219 return 0;
1220}
1221
1222static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1223 .suspend_late = &bcm_iproc_i2c_suspend,
1224 .resume_early = &bcm_iproc_i2c_resume
1225};
1226
1227static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1228 {
1229 .compatible = "brcm,iproc-i2c",
1230 .data = (int *)IPROC_I2C,
1231 }, {
1232 .compatible = "brcm,iproc-nic-i2c",
1233 .data = (int *)IPROC_I2C_NIC,
1234 },
1235 { /* sentinel */ }
1236};
1237MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1238
1239static struct platform_driver bcm_iproc_i2c_driver = {
1240 .driver = {
1241 .name = "bcm-iproc-i2c",
1242 .of_match_table = bcm_iproc_i2c_of_match,
1243 .pm = pm_sleep_ptr(&bcm_iproc_i2c_pm_ops),
1244 },
1245 .probe = bcm_iproc_i2c_probe,
1246 .remove = bcm_iproc_i2c_remove,
1247};
1248module_platform_driver(bcm_iproc_i2c_driver);
1249
1250MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1251MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1252MODULE_LICENSE("GPL v2");
1253

source code of linux/drivers/i2c/busses/i2c-bcm-iproc.c