1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 */
6
7#ifndef _CORESIGHT_TMC_H
8#define _CORESIGHT_TMC_H
9
10#include <linux/dma-mapping.h>
11#include <linux/idr.h>
12#include <linux/miscdevice.h>
13#include <linux/mutex.h>
14#include <linux/refcount.h>
15#include <linux/crc32.h>
16
17#define TMC_RSZ 0x004
18#define TMC_STS 0x00c
19#define TMC_RRD 0x010
20#define TMC_RRP 0x014
21#define TMC_RWP 0x018
22#define TMC_TRG 0x01c
23#define TMC_CTL 0x020
24#define TMC_RWD 0x024
25#define TMC_MODE 0x028
26#define TMC_LBUFLEVEL 0x02c
27#define TMC_CBUFLEVEL 0x030
28#define TMC_BUFWM 0x034
29#define TMC_RRPHI 0x038
30#define TMC_RWPHI 0x03c
31#define TMC_AXICTL 0x110
32#define TMC_DBALO 0x118
33#define TMC_DBAHI 0x11c
34#define TMC_FFSR 0x300
35#define TMC_FFCR 0x304
36#define TMC_PSCR 0x308
37#define TMC_ITMISCOP0 0xee0
38#define TMC_ITTRFLIN 0xee8
39#define TMC_ITATBDATA0 0xeec
40#define TMC_ITATBCTR2 0xef0
41#define TMC_ITATBCTR1 0xef4
42#define TMC_ITATBCTR0 0xef8
43#define TMC_AUTHSTATUS 0xfb8
44
45/* register description */
46/* TMC_CTL - 0x020 */
47#define TMC_CTL_CAPT_EN BIT(0)
48/* TMC_STS - 0x00C */
49#define TMC_STS_TMCREADY_BIT 2
50#define TMC_STS_FULL BIT(0)
51#define TMC_STS_TRIGGERED BIT(1)
52#define TMC_STS_MEMERR BIT(5)
53/*
54 * TMC_AXICTL - 0x110
55 *
56 * TMC AXICTL format for SoC-400
57 * Bits [0-1] : ProtCtrlBit0-1
58 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
59 * Bit 6 : Reserved
60 * Bit 7 : ScatterGatherMode
61 * Bits [8-11] : WrBurstLen
62 * Bits [12-31] : Reserved.
63 * TMC AXICTL format for SoC-600, as above except:
64 * Bits [2-5] : AXI WCACHE
65 * Bits [16-19] : AXI RCACHE
66 * Bits [20-31] : Reserved
67 */
68#define TMC_AXICTL_CLEAR_MASK 0xfbf
69#define TMC_AXICTL_ARCACHE_MASK (0xf << 16)
70
71#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
72#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
73#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
74#define TMC_AXICTL_WR_BURST(v) (((v) & 0xf) << 8)
75#define TMC_AXICTL_WR_BURST_16 0xf
76/* Write-back Read and Write-allocate */
77#define TMC_AXICTL_AXCACHE_OS (0xf << 2)
78#define TMC_AXICTL_ARCACHE_OS (0xf << 16)
79
80/* TMC_FFSR - 0x300 */
81#define TMC_FFSR_FT_STOPPED BIT(1)
82
83/* TMC_FFCR - 0x304 */
84#define TMC_FFCR_FLUSHMAN_BIT 6
85#define TMC_FFCR_EN_FMT BIT(0)
86#define TMC_FFCR_EN_TI BIT(1)
87#define TMC_FFCR_FON_FLIN BIT(4)
88#define TMC_FFCR_FON_TRIG_EVT BIT(5)
89#define TMC_FFCR_TRIGON_TRIGIN BIT(8)
90#define TMC_FFCR_STOP_ON_FLUSH BIT(12)
91
92
93#define TMC_DEVID_NOSCAT BIT(24)
94
95#define TMC_DEVID_AXIAW_VALID BIT(16)
96#define TMC_DEVID_AXIAW_SHIFT 17
97#define TMC_DEVID_AXIAW_MASK 0x7f
98
99#define TMC_AUTH_NSID_MASK GENMASK(1, 0)
100
101/* Major version 1 Minor version 0 */
102#define CS_CRASHDATA_VERSION (1 << 16)
103
104enum tmc_config_type {
105 TMC_CONFIG_TYPE_ETB,
106 TMC_CONFIG_TYPE_ETR,
107 TMC_CONFIG_TYPE_ETF,
108};
109
110enum tmc_mode {
111 TMC_MODE_CIRCULAR_BUFFER,
112 TMC_MODE_SOFTWARE_FIFO,
113 TMC_MODE_HARDWARE_FIFO,
114};
115
116enum tmc_mem_intf_width {
117 TMC_MEM_INTF_WIDTH_32BITS = 1,
118 TMC_MEM_INTF_WIDTH_64BITS = 2,
119 TMC_MEM_INTF_WIDTH_128BITS = 4,
120 TMC_MEM_INTF_WIDTH_256BITS = 8,
121};
122
123/* TMC ETR Capability bit definitions */
124#define TMC_ETR_SG (0x1U << 0)
125/* ETR has separate read/write cache encodings */
126#define TMC_ETR_AXI_ARCACHE (0x1U << 1)
127/*
128 * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
129 * retained when TMC leaves Disabled state, allowing us to continue
130 * the tracing from a point where we stopped. This also implies that
131 * the RRP/RWP/STS.Full should always be programmed to the correct
132 * value. Unfortunately this is not advertised by the hardware,
133 * so we have to rely on PID of the IP to detect the functionality.
134 */
135#define TMC_ETR_SAVE_RESTORE (0x1U << 2)
136
137/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
138#define CORESIGHT_SOC_600_ETR_CAPS \
139 (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
140
141/* TMC metadata region for ETR and ETF configurations */
142struct tmc_crash_metadata {
143 uint32_t crc32_mdata; /* crc of metadata */
144 uint32_t crc32_tdata; /* crc of tracedata */
145 uint32_t version; /* 31:16 Major version, 15:0 Minor version */
146 uint32_t valid; /* Indicate if this ETF/ETR was enabled */
147 uint32_t tmc_ram_size; /* Ram Size register */
148 uint32_t tmc_sts; /* Status register */
149 uint32_t tmc_mode; /* Mode register */
150 uint32_t tmc_ffcr; /* Formatter and flush control register */
151 uint32_t tmc_ffsr; /* Formatter and flush status register */
152 uint32_t reserved32;
153 uint64_t tmc_rrp; /* Ram Read pointer register */
154 uint64_t tmc_rwp; /* Ram Write pointer register */
155 uint64_t tmc_dba; /* Data buffer address register */
156 uint64_t trace_paddr; /* Phys address of trace buffer */
157 uint64_t reserved64[3];
158};
159
160enum etr_mode {
161 ETR_MODE_FLAT, /* Uses contiguous flat buffer */
162 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
163 ETR_MODE_CATU, /* Use SG mechanism in CATU */
164 ETR_MODE_RESRV, /* Use reserved region contiguous buffer */
165 ETR_MODE_AUTO, /* Use the default mechanism */
166};
167
168struct etr_buf_operations;
169
170/**
171 * struct etr_buf - Details of the buffer used by ETR
172 * refcount ; Number of sources currently using this etr_buf.
173 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc.
174 * @full : Trace data overflow
175 * @size : Size of the buffer.
176 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI}
177 * @offset : Offset of the trace data in the buffer for consumption.
178 * @len : Available trace data @buf (may round up to the beginning).
179 * @ops : ETR buffer operations for the mode.
180 * @private : Backend specific information for the buf
181 */
182struct etr_buf {
183 refcount_t refcount;
184 enum etr_mode mode;
185 bool full;
186 ssize_t size;
187 dma_addr_t hwaddr;
188 unsigned long offset;
189 s64 len;
190 const struct etr_buf_operations *ops;
191 void *private;
192};
193
194/**
195 * @paddr : Start address of reserved memory region.
196 * @vaddr : Corresponding CPU virtual address.
197 * @size : Size of reserved memory region.
198 * @offset : Offset of the trace data in the buffer for consumption.
199 * @reading : Flag to indicate if reading is active
200 * @len : Available trace data @buf (may round up to the beginning).
201 */
202struct tmc_resrv_buf {
203 phys_addr_t paddr;
204 void *vaddr;
205 size_t size;
206 unsigned long offset;
207 bool reading;
208 s64 len;
209};
210
211/**
212 * struct tmc_drvdata - specifics associated to an TMC component
213 * @atclk: optional clock for the core parts of the TMC.
214 * @pclk: APB clock if present, otherwise NULL
215 * @base: memory mapped base address for this component.
216 * @csdev: component vitals needed by the framework.
217 * @miscdev: specifics to handle "/dev/xyz.tmc" entry.
218 * @crashdev: specifics to handle "/dev/crash_tmc_xyz" entry for reading
219 * crash tracedata.
220 * @spinlock: only one at a time pls.
221 * @pid: Process ID of the process that owns the session that is using
222 * this component. For example this would be the pid of the Perf
223 * process.
224 * @stop_on_flush: Stop on flush trigger user configuration.
225 * @buf: Snapshot of the trace data for ETF/ETB.
226 * @etr_buf: details of buffer used in TMC-ETR
227 * @len: size of the available trace for ETF/ETB.
228 * @size: trace buffer size for this TMC (common for all modes).
229 * @max_burst_size: The maximum burst size that can be initiated by
230 * TMC-ETR on AXI bus.
231 * @config_type: TMC variant, must be of type @tmc_config_type.
232 * @memwidth: width of the memory interface databus, in bytes.
233 * @trigger_cntr: amount of words to store after a trigger.
234 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the
235 * device configuration register (DEVID)
236 * @idr: Holds etr_bufs allocated for this ETR.
237 * @idr_mutex: Access serialisation for idr.
238 * @sysfs_buf: SYSFS buffer for ETR.
239 * @perf_buf: PERF buffer for ETR.
240 * @resrv_buf: Used by ETR as hardware trace buffer and for trace data
241 * retention (after crash) only when ETR_MODE_RESRV buffer
242 * mode is enabled. Used by ETF for trace data retention
243 * (after crash) by default.
244 * @crash_mdata: Reserved memory for storing tmc crash metadata.
245 * Used by ETR/ETF.
246 */
247struct tmc_drvdata {
248 struct clk *atclk;
249 struct clk *pclk;
250 void __iomem *base;
251 struct coresight_device *csdev;
252 struct miscdevice miscdev;
253 struct miscdevice crashdev;
254 raw_spinlock_t spinlock;
255 pid_t pid;
256 bool reading;
257 bool stop_on_flush;
258 union {
259 char *buf; /* TMC ETB */
260 struct etr_buf *etr_buf; /* TMC ETR */
261 };
262 u32 len;
263 u32 size;
264 u32 max_burst_size;
265 enum tmc_config_type config_type;
266 enum tmc_mem_intf_width memwidth;
267 u32 trigger_cntr;
268 u32 etr_caps;
269 enum etr_mode etr_mode;
270 struct idr idr;
271 struct mutex idr_mutex;
272 struct etr_buf *sysfs_buf;
273 struct etr_buf *perf_buf;
274 struct tmc_resrv_buf resrv_buf;
275 struct tmc_resrv_buf crash_mdata;
276};
277
278struct etr_buf_operations {
279 int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf,
280 int node, void **pages);
281 void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp);
282 ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len,
283 char **bufpp);
284 void (*free)(struct etr_buf *etr_buf);
285};
286
287/**
288 * struct tmc_pages - Collection of pages used for SG.
289 * @nr_pages: Number of pages in the list.
290 * @daddrs: Array of DMA'able page address.
291 * @pages: Array pages for the buffer.
292 */
293struct tmc_pages {
294 int nr_pages;
295 dma_addr_t *daddrs;
296 struct page **pages;
297};
298
299/*
300 * struct tmc_sg_table - Generic SG table for TMC
301 * @dev: Device for DMA allocations
302 * @table_vaddr: Contiguous Virtual address for PageTable
303 * @data_vaddr: Contiguous Virtual address for Data Buffer
304 * @table_daddr: DMA address of the PageTable base
305 * @node: Node for Page allocations
306 * @table_pages: List of pages & dma address for Table
307 * @data_pages: List of pages & dma address for Data
308 */
309struct tmc_sg_table {
310 struct device *dev;
311 void *table_vaddr;
312 void *data_vaddr;
313 dma_addr_t table_daddr;
314 int node;
315 struct tmc_pages table_pages;
316 struct tmc_pages data_pages;
317};
318
319/* Generic functions */
320int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
321void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
322void tmc_enable_hw(struct tmc_drvdata *drvdata);
323void tmc_disable_hw(struct tmc_drvdata *drvdata);
324u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
325int tmc_read_prepare_crashdata(struct tmc_drvdata *drvdata);
326
327/* ETB/ETF functions */
328int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
329int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata);
330extern const struct coresight_ops tmc_etb_cs_ops;
331extern const struct coresight_ops tmc_etf_cs_ops;
332
333ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata,
334 loff_t pos, size_t len, char **bufpp);
335/* ETR functions */
336int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
337int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
338void tmc_etr_disable_hw(struct tmc_drvdata *drvdata);
339extern const struct coresight_ops tmc_etr_cs_ops;
340ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
341 loff_t pos, size_t len, char **bufpp);
342
343
344#define TMC_REG_PAIR(name, lo_off, hi_off) \
345static inline u64 \
346tmc_read_##name(struct tmc_drvdata *drvdata) \
347{ \
348 return csdev_access_relaxed_read_pair(&drvdata->csdev->access, lo_off, hi_off); \
349} \
350static inline void \
351tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \
352{ \
353 csdev_access_relaxed_write_pair(&drvdata->csdev->access, val, lo_off, hi_off); \
354}
355
356TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
357TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
358TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
359
360/* Initialise the caps from unadvertised static capabilities of the device */
361static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps)
362{
363 WARN_ON(drvdata->etr_caps);
364 drvdata->etr_caps = dev_caps;
365}
366
367static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap)
368{
369 drvdata->etr_caps |= cap;
370}
371
372static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap)
373{
374 return !!(drvdata->etr_caps & cap);
375}
376
377struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev,
378 int node,
379 int nr_tpages,
380 int nr_dpages,
381 void **pages);
382void tmc_free_sg_table(struct tmc_sg_table *sg_table);
383void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table);
384void tmc_sg_table_sync_data_range(struct tmc_sg_table *table,
385 u64 offset, u64 size);
386ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table,
387 u64 offset, size_t len, char **bufpp);
388
389static inline unsigned long
390tmc_sg_table_buf_size(struct tmc_sg_table *sg_table)
391{
392 return (unsigned long)sg_table->data_pages.nr_pages << PAGE_SHIFT;
393}
394
395static inline bool tmc_has_reserved_buffer(struct tmc_drvdata *drvdata)
396{
397 if (drvdata->resrv_buf.vaddr &&
398 drvdata->resrv_buf.size)
399 return true;
400 return false;
401}
402
403static inline bool tmc_has_crash_mdata_buffer(struct tmc_drvdata *drvdata)
404{
405 if (drvdata->crash_mdata.vaddr &&
406 drvdata->crash_mdata.size)
407 return true;
408 return false;
409}
410
411static inline void tmc_crashdata_set_invalid(struct tmc_drvdata *drvdata)
412{
413 struct tmc_crash_metadata *mdata;
414
415 mdata = (struct tmc_crash_metadata *)drvdata->crash_mdata.vaddr;
416
417 if (tmc_has_crash_mdata_buffer(drvdata))
418 mdata->valid = false;
419}
420
421static inline uint32_t find_crash_metadata_crc(struct tmc_crash_metadata *md)
422{
423 unsigned long crc_size;
424
425 crc_size = sizeof(struct tmc_crash_metadata) -
426 offsetof(struct tmc_crash_metadata, crc32_tdata);
427 return crc32_le(crc: 0, p: (void *)&md->crc32_tdata, len: crc_size);
428}
429
430static inline uint32_t find_crash_tracedata_crc(struct tmc_drvdata *drvdata,
431 struct tmc_crash_metadata *md)
432{
433 unsigned long crc_size;
434
435 /* Take CRC of configured buffer size to keep it simple */
436 crc_size = md->tmc_ram_size << 2;
437 return crc32_le(crc: 0, p: (void *)drvdata->resrv_buf.vaddr, len: crc_size);
438}
439
440struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);
441
442void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);
443void tmc_etr_remove_catu_ops(void);
444struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev,
445 enum cs_mode mode,
446 struct coresight_path *path);
447extern const struct attribute_group coresight_etr_group;
448
449#endif
450

source code of linux/drivers/hwtracing/coresight/coresight-tmc.h