| 1 | /* SPDX-License-Identifier: MIT */ |
|---|---|
| 2 | /* |
| 3 | * Copyright © 2021 Intel Corporation |
| 4 | */ |
| 5 | |
| 6 | #ifndef _XE_HW_ENGINE_H_ |
| 7 | #define _XE_HW_ENGINE_H_ |
| 8 | |
| 9 | #include "xe_hw_engine_types.h" |
| 10 | |
| 11 | struct drm_printer; |
| 12 | struct drm_xe_engine_class_instance; |
| 13 | struct xe_device; |
| 14 | struct xe_exec_queue; |
| 15 | |
| 16 | #ifdef CONFIG_DRM_XE_JOB_TIMEOUT_MIN |
| 17 | #define XE_HW_ENGINE_JOB_TIMEOUT_MIN CONFIG_DRM_XE_JOB_TIMEOUT_MIN |
| 18 | #else |
| 19 | #define XE_HW_ENGINE_JOB_TIMEOUT_MIN 1 |
| 20 | #endif |
| 21 | #ifdef CONFIG_DRM_XE_JOB_TIMEOUT_MAX |
| 22 | #define XE_HW_ENGINE_JOB_TIMEOUT_MAX CONFIG_DRM_XE_JOB_TIMEOUT_MAX |
| 23 | #else |
| 24 | #define XE_HW_ENGINE_JOB_TIMEOUT_MAX (10 * 1000) |
| 25 | #endif |
| 26 | #ifdef CONFIG_DRM_XE_TIMESLICE_MIN |
| 27 | #define XE_HW_ENGINE_TIMESLICE_MIN CONFIG_DRM_XE_TIMESLICE_MIN |
| 28 | #else |
| 29 | #define XE_HW_ENGINE_TIMESLICE_MIN 1 |
| 30 | #endif |
| 31 | #ifdef CONFIG_DRM_XE_TIMESLICE_MAX |
| 32 | #define XE_HW_ENGINE_TIMESLICE_MAX CONFIG_DRM_XE_TIMESLICE_MAX |
| 33 | #else |
| 34 | #define XE_HW_ENGINE_TIMESLICE_MAX (10 * 1000 * 1000) |
| 35 | #endif |
| 36 | #ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT |
| 37 | #define XE_HW_ENGINE_PREEMPT_TIMEOUT CONFIG_DRM_XE_PREEMPT_TIMEOUT |
| 38 | #else |
| 39 | #define XE_HW_ENGINE_PREEMPT_TIMEOUT (640 * 1000) |
| 40 | #endif |
| 41 | #ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN |
| 42 | #define XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN |
| 43 | #else |
| 44 | #define XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN 1 |
| 45 | #endif |
| 46 | #ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX |
| 47 | #define XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX |
| 48 | #else |
| 49 | #define XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX (10 * 1000 * 1000) |
| 50 | #endif |
| 51 | |
| 52 | int xe_hw_engines_init_early(struct xe_gt *gt); |
| 53 | int xe_hw_engines_init(struct xe_gt *gt); |
| 54 | void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec); |
| 55 | void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe); |
| 56 | u32 xe_hw_engine_mask_per_class(struct xe_gt *gt, |
| 57 | enum xe_engine_class engine_class); |
| 58 | struct xe_hw_engine_snapshot * |
| 59 | xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe, struct xe_exec_queue *q); |
| 60 | void xe_hw_engine_snapshot_free(struct xe_hw_engine_snapshot *snapshot); |
| 61 | void xe_hw_engine_print(struct xe_hw_engine *hwe, struct drm_printer *p); |
| 62 | void xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe); |
| 63 | |
| 64 | bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe); |
| 65 | |
| 66 | struct xe_hw_engine * |
| 67 | xe_hw_engine_lookup(struct xe_device *xe, |
| 68 | struct drm_xe_engine_class_instance eci); |
| 69 | |
| 70 | static inline bool xe_hw_engine_is_valid(struct xe_hw_engine *hwe) |
| 71 | { |
| 72 | return hwe->name; |
| 73 | } |
| 74 | |
| 75 | const char *xe_hw_engine_class_to_str(enum xe_engine_class class); |
| 76 | u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe); |
| 77 | enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe); |
| 78 | |
| 79 | void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val); |
| 80 | u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg); |
| 81 | |
| 82 | #endif |
| 83 |