| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _XE_MCHBAR_REGS_H_ |
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| 7 | #define _XE_MCHBAR_REGS_H_ |
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| 8 | |
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| 9 | #include "regs/xe_reg_defs.h" |
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| 10 | |
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| 11 | /* |
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| 12 | * MCHBAR mirror. |
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| 13 | * |
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| 14 | * This mirrors the MCHBAR MMIO space whose location is determined by |
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| 15 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in |
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| 16 | * every way. |
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| 17 | */ |
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| 18 | |
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| 19 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
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| 20 | |
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| 21 | #define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930) |
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| 22 | #define PKG_TDP GENMASK_ULL(14, 0) |
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| 23 | #define PKG_MIN_PWR GENMASK_ULL(30, 16) |
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| 24 | #define PKG_MAX_PWR GENMASK_ULL(46, 32) |
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| 25 | #define PKG_MAX_WIN GENMASK_ULL(54, 48) |
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| 26 | #define PKG_MAX_WIN_X GENMASK_ULL(54, 53) |
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| 27 | #define PKG_MAX_WIN_Y GENMASK_ULL(52, 48) |
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| 28 | |
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| 29 | |
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| 30 | #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938) |
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| 31 | #define PKG_PWR_UNIT REG_GENMASK(3, 0) |
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| 32 | #define PKG_ENERGY_UNIT REG_GENMASK(12, 8) |
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| 33 | #define PKG_TIME_UNIT REG_GENMASK(19, 16) |
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| 34 | |
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| 35 | #define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c) |
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| 36 | |
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| 37 | #define PCU_CR_PACKAGE_TEMPERATURE XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5978) |
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| 38 | #define TEMP_MASK REG_GENMASK(7, 0) |
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| 39 | |
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| 40 | #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0) |
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| 41 | #define PWR_LIM_VAL REG_GENMASK(14, 0) |
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| 42 | #define PWR_LIM_EN REG_BIT(15) |
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| 43 | #define PWR_LIM REG_GENMASK(15, 0) |
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| 44 | #define PWR_LIM_TIME REG_GENMASK(23, 17) |
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| 45 | #define PWR_LIM_TIME_X REG_GENMASK(23, 22) |
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| 46 | #define PWR_LIM_TIME_Y REG_GENMASK(21, 17) |
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| 47 | |
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| 48 | #endif /* _XE_MCHBAR_REGS_H_ */ |
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| 49 | |
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