| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _XE_MI_COMMANDS_H_ |
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| 7 | #define _XE_MI_COMMANDS_H_ |
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| 8 | |
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| 9 | #include "instructions/xe_instr_defs.h" |
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| 10 | |
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| 11 | /* |
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| 12 | * MI (Memory Interface) commands are supported by all GT engines. They |
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| 13 | * provide general memory operations and command streamer control. MI commands |
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| 14 | * have a command type of 0x0 (MI_COMMAND) in bits 31:29 of the instruction |
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| 15 | * header dword and a specific MI opcode in bits 28:23. |
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| 16 | */ |
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| 17 | |
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| 18 | #define MI_OPCODE REG_GENMASK(28, 23) |
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| 19 | #define MI_SUBOPCODE REG_GENMASK(22, 17) /* used with MI_EXPANSION */ |
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| 20 | |
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| 21 | #define __MI_INSTR(opcode) \ |
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| 22 | (XE_INSTR_MI | REG_FIELD_PREP(MI_OPCODE, opcode)) |
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| 23 | |
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| 24 | #define MI_NOOP __MI_INSTR(0x0) |
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| 25 | #define MI_USER_INTERRUPT __MI_INSTR(0x2) |
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| 26 | #define MI_ARB_CHECK __MI_INSTR(0x5) |
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| 27 | |
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| 28 | #define MI_ARB_ON_OFF __MI_INSTR(0x8) |
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| 29 | #define MI_ARB_ENABLE REG_BIT(0) |
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| 30 | #define MI_ARB_DISABLE 0x0 |
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| 31 | |
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| 32 | #define MI_BATCH_BUFFER_END __MI_INSTR(0xA) |
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| 33 | #define MI_TOPOLOGY_FILTER __MI_INSTR(0xD) |
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| 34 | #define MI_FORCE_WAKEUP __MI_INSTR(0x1D) |
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| 35 | #define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1)) |
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| 36 | |
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| 37 | #define MI_STORE_DATA_IMM __MI_INSTR(0x20) |
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| 38 | #define MI_SDI_GGTT REG_BIT(22) |
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| 39 | #define MI_SDI_LEN_DW GENMASK(9, 0) |
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| 40 | #define MI_SDI_NUM_DW(x) REG_FIELD_PREP(MI_SDI_LEN_DW, (x) + 3 - 2) |
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| 41 | #define MI_SDI_NUM_QW(x) (REG_FIELD_PREP(MI_SDI_LEN_DW, 2 * (x) + 3 - 2) | \ |
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| 42 | REG_BIT(21)) |
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| 43 | |
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| 44 | #define MI_LOAD_REGISTER_IMM __MI_INSTR(0x22) |
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| 45 | #define MI_LRI_LRM_CS_MMIO REG_BIT(19) |
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| 46 | #define MI_LRI_MMIO_REMAP_EN REG_BIT(17) |
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| 47 | #define MI_LRI_NUM_REGS(x) XE_INSTR_NUM_DW(2 * (x) + 1) |
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| 48 | #define MI_LRI_FORCE_POSTED REG_BIT(12) |
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| 49 | #define MI_LRI_LEN(x) (((x) & 0xff) + 1) |
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| 50 | |
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| 51 | #define MI_STORE_REGISTER_MEM (__MI_INSTR(0x24) | XE_INSTR_NUM_DW(4)) |
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| 52 | #define MI_SRM_USE_GGTT REG_BIT(22) |
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| 53 | #define MI_SRM_ADD_CS_OFFSET REG_BIT(19) |
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| 54 | |
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| 55 | #define MI_FLUSH_DW __MI_INSTR(0x26) |
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| 56 | #define MI_FLUSH_DW_PROTECTED_MEM_EN REG_BIT(22) |
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| 57 | #define MI_FLUSH_DW_STORE_INDEX REG_BIT(21) |
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| 58 | #define MI_INVALIDATE_TLB REG_BIT(18) |
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| 59 | #define MI_FLUSH_DW_CCS REG_BIT(16) |
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| 60 | #define MI_FLUSH_DW_OP_STOREDW REG_BIT(14) |
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| 61 | #define MI_FLUSH_DW_LEN_DW REG_GENMASK(5, 0) |
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| 62 | #define MI_FLUSH_IMM_DW REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 4 - 2) |
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| 63 | #define MI_FLUSH_IMM_QW REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 5 - 2) |
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| 64 | #define MI_FLUSH_DW_USE_GTT REG_BIT(2) |
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| 65 | |
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| 66 | #define MI_LOAD_REGISTER_MEM (__MI_INSTR(0x29) | XE_INSTR_NUM_DW(4)) |
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| 67 | #define MI_LRM_USE_GGTT REG_BIT(22) |
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| 68 | #define MI_LRM_ASYNC REG_BIT(21) |
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| 69 | |
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| 70 | #define MI_LOAD_REGISTER_REG (__MI_INSTR(0x2a) | XE_INSTR_NUM_DW(3)) |
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| 71 | #define MI_LRR_DST_CS_MMIO REG_BIT(19) |
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| 72 | #define MI_LRR_SRC_CS_MMIO REG_BIT(18) |
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| 73 | |
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| 74 | #define MI_COPY_MEM_MEM (__MI_INSTR(0x2e) | XE_INSTR_NUM_DW(5)) |
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| 75 | #define MI_COPY_MEM_MEM_SRC_GGTT REG_BIT(22) |
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| 76 | #define MI_COPY_MEM_MEM_DST_GGTT REG_BIT(21) |
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| 77 | |
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| 78 | #define MI_BATCH_BUFFER_START __MI_INSTR(0x31) |
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| 79 | |
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| 80 | #define MI_SET_APPID __MI_INSTR(0x0e) |
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| 81 | #define MI_SET_APPID_SESSION_ID_MASK REG_GENMASK(6, 0) |
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| 82 | #define MI_SET_APPID_SESSION_ID(x) REG_FIELD_PREP(MI_SET_APPID_SESSION_ID_MASK, x) |
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| 83 | |
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| 84 | #endif |
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| 85 | |
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