| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _XE_INSTR_DEFS_H_ |
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| 7 | #define _XE_INSTR_DEFS_H_ |
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| 8 | |
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| 9 | #include "regs/xe_reg_defs.h" |
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| 10 | |
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| 11 | /* |
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| 12 | * The first dword of any GPU instruction is the "instruction header." Bits |
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| 13 | * 31:29 identify the general type of the command and determine how exact |
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| 14 | * opcodes and sub-opcodes will be encoded in the remaining bits. |
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| 15 | */ |
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| 16 | #define XE_INSTR_CMD_TYPE GENMASK(31, 29) |
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| 17 | #define XE_INSTR_MI REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x0) |
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| 18 | #define XE_INSTR_GSC REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x2) |
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| 19 | #define XE_INSTR_VIDEOPIPE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3) |
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| 20 | #define XE_INSTR_GFXPIPE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3) |
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| 21 | #define XE_INSTR_GFX_STATE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x4) |
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| 22 | |
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| 23 | /* |
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| 24 | * Most (but not all) instructions have a "length" field in the instruction |
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| 25 | * header. The value expected is the total number of dwords for the |
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| 26 | * instruction, minus two. |
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| 27 | * |
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| 28 | * Some instructions have length fields longer or shorter than 8 bits, but |
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| 29 | * those are rare. This definition can be used for the common case where |
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| 30 | * the length field is from 7:0. |
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| 31 | */ |
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| 32 | #define XE_INSTR_LEN_MASK GENMASK(7, 0) |
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| 33 | #define XE_INSTR_NUM_DW(x) REG_FIELD_PREP(XE_INSTR_LEN_MASK, (x) - 2) |
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| 34 | |
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| 35 | #endif |
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| 36 | |
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