| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _XE_GPU_COMMANDS_H_ |
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| 7 | #define _XE_GPU_COMMANDS_H_ |
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| 8 | |
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| 9 | #include "regs/xe_reg_defs.h" |
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| 10 | |
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| 11 | #define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3) |
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| 12 | #define SRC_ACCESS_TYPE_SHIFT 21 |
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| 13 | #define DST_ACCESS_TYPE_SHIFT 20 |
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| 14 | #define CCS_SIZE_MASK GENMASK(17, 8) |
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| 15 | #define XE2_CCS_SIZE_MASK GENMASK(18, 9) |
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| 16 | #define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 26) |
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| 17 | #define XE2_XY_CTRL_SURF_MOCS_INDEX_MASK GENMASK(31, 28) |
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| 18 | #define NUM_CCS_BYTES_PER_BLOCK 256 |
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| 19 | #define NUM_BYTES_PER_CCS_BYTE(_xe) (GRAPHICS_VER(_xe) >= 20 ? 512 : 256) |
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| 20 | |
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| 21 | #define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22) |
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| 22 | #define XY_FAST_COLOR_BLT_DEPTH_32 (2 << 19) |
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| 23 | #define XY_FAST_COLOR_BLT_DW 16 |
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| 24 | #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 22) |
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| 25 | #define XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_MASK GENMASK(27, 24) |
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| 26 | #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 |
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| 27 | |
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| 28 | #define XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) |
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| 29 | #define XY_FAST_COPY_BLT_DEPTH_32 (3<<24) |
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| 30 | #define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31) |
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| 31 | #define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30) |
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| 32 | #define XE2_XY_FAST_COPY_BLT_MOCS_INDEX_MASK GENMASK(23, 20) |
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| 33 | |
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| 34 | #define MEM_COPY_CMD (2 << 29 | 0x5a << 22 | 0x8) |
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| 35 | #define MEM_COPY_PAGE_COPY_MODE REG_BIT(19) |
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| 36 | #define MEM_COPY_MATRIX_COPY REG_BIT(17) |
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| 37 | #define MEM_COPY_SRC_MOCS_INDEX_MASK GENMASK(31, 28) |
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| 38 | #define MEM_COPY_DST_MOCS_INDEX_MASK GENMASK(6, 3) |
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| 39 | |
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| 40 | #define PVC_MEM_SET_CMD (2 << 29 | 0x5b << 22) |
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| 41 | #define PVC_MEM_SET_CMD_LEN_DW 7 |
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| 42 | #define PVC_MEM_SET_MATRIX REG_BIT(17) |
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| 43 | #define PVC_MEM_SET_DATA_FIELD GENMASK(31, 24) |
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| 44 | /* Bspec lists field as [6:0], but index alone is from [6:1] */ |
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| 45 | #define PVC_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 1) |
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| 46 | #define XE2_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 3) |
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| 47 | |
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| 48 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) |
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| 49 | |
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| 50 | #define PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE BIT(10) /* gen12 */ |
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| 51 | #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */ |
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| 52 | |
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| 53 | #define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) |
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| 54 | #define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) |
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| 55 | #define PIPE_CONTROL_AMFS_FLUSH (1<<25) |
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| 56 | #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) |
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| 57 | #define PIPE_CONTROL_LRI_POST_SYNC BIT(23) |
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| 58 | #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) |
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| 59 | #define PIPE_CONTROL_CS_STALL (1<<20) |
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| 60 | #define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19) |
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| 61 | #define PIPE_CONTROL_TLB_INVALIDATE BIT(18) |
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| 62 | #define PIPE_CONTROL_PSD_SYNC (1<<17) |
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| 63 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
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| 64 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) |
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| 65 | #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) |
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| 66 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) |
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| 67 | #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) |
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| 68 | #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) |
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| 69 | #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) |
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| 70 | #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) |
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| 71 | #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
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| 72 | #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) |
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| 73 | #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) |
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| 74 | #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) |
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| 75 | #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
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| 76 | |
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| 77 | #endif |
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| 78 | |
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