1/*
2 * Copyright © 2014-2015 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24/**
25 * DOC: Render command list generation
26 *
27 * In the V3D hardware, render command lists are what load and store
28 * tiles of a framebuffer and optionally call out to binner-generated
29 * command lists to do the 3D drawing for that tile.
30 *
31 * In the VC4 driver, render command list generation is performed by the
32 * kernel instead of userspace. We do this because validating a
33 * user-submitted command list is hard to get right and has high CPU overhead,
34 * while the number of valid configurations for render command lists is
35 * actually fairly low.
36 */
37
38#include <drm/drm_print.h>
39
40#include "uapi/drm/vc4_drm.h"
41#include "vc4_drv.h"
42#include "vc4_packet.h"
43
44struct vc4_rcl_setup {
45 struct drm_gem_dma_object *color_read;
46 struct drm_gem_dma_object *color_write;
47 struct drm_gem_dma_object *zs_read;
48 struct drm_gem_dma_object *zs_write;
49 struct drm_gem_dma_object *msaa_color_write;
50 struct drm_gem_dma_object *msaa_zs_write;
51
52 struct drm_gem_dma_object *rcl;
53 u32 next_offset;
54
55 u32 next_write_bo_index;
56};
57
58static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val)
59{
60 *(u8 *)(setup->rcl->vaddr + setup->next_offset) = val;
61 setup->next_offset += 1;
62}
63
64static inline void rcl_u16(struct vc4_rcl_setup *setup, u16 val)
65{
66 *(u16 *)(setup->rcl->vaddr + setup->next_offset) = val;
67 setup->next_offset += 2;
68}
69
70static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val)
71{
72 *(u32 *)(setup->rcl->vaddr + setup->next_offset) = val;
73 setup->next_offset += 4;
74}
75
76/*
77 * Emits a no-op STORE_TILE_BUFFER_GENERAL.
78 *
79 * If we emit a PACKET_TILE_COORDINATES, it must be followed by a store of
80 * some sort before another load is triggered.
81 */
82static void vc4_store_before_load(struct vc4_rcl_setup *setup)
83{
84 rcl_u8(setup, val: VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
85 rcl_u16(setup,
86 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE,
87 VC4_LOADSTORE_TILE_BUFFER_BUFFER) |
88 VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR |
89 VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR |
90 VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR);
91 rcl_u32(setup, val: 0); /* no address, since we're in None mode */
92}
93
94/*
95 * Calculates the physical address of the start of a tile in a RCL surface.
96 *
97 * Unlike the other load/store packets,
98 * VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER don't look at the tile
99 * coordinates packet, and instead just store to the address given.
100 */
101static uint32_t vc4_full_res_offset(struct vc4_exec_info *exec,
102 struct drm_gem_dma_object *bo,
103 struct drm_vc4_submit_rcl_surface *surf,
104 uint8_t x, uint8_t y)
105{
106 return bo->dma_addr + surf->offset + VC4_TILE_BUFFER_SIZE *
107 (DIV_ROUND_UP(exec->args->width, 32) * y + x);
108}
109
110/*
111 * Emits a PACKET_TILE_COORDINATES if one isn't already pending.
112 *
113 * The tile coordinates packet triggers a pending load if there is one, are
114 * used for clipping during rendering, and determine where loads/stores happen
115 * relative to their base address.
116 */
117static void vc4_tile_coordinates(struct vc4_rcl_setup *setup,
118 uint32_t x, uint32_t y)
119{
120 rcl_u8(setup, val: VC4_PACKET_TILE_COORDINATES);
121 rcl_u8(setup, val: x);
122 rcl_u8(setup, val: y);
123}
124
125static void emit_tile(struct vc4_exec_info *exec,
126 struct vc4_rcl_setup *setup,
127 uint8_t x, uint8_t y, bool first, bool last)
128{
129 struct drm_vc4_submit_cl *args = exec->args;
130 bool has_bin = args->bin_cl_size != 0;
131
132 /* Note that the load doesn't actually occur until the
133 * tile coords packet is processed, and only one load
134 * may be outstanding at a time.
135 */
136 if (setup->color_read) {
137 if (args->color_read.flags &
138 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
139 rcl_u8(setup, val: VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
140 rcl_u32(setup,
141 val: vc4_full_res_offset(exec, bo: setup->color_read,
142 surf: &args->color_read, x, y) |
143 VC4_LOADSTORE_FULL_RES_DISABLE_ZS);
144 } else {
145 rcl_u8(setup, val: VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
146 rcl_u16(setup, val: args->color_read.bits);
147 rcl_u32(setup, val: setup->color_read->dma_addr +
148 args->color_read.offset);
149 }
150 }
151
152 if (setup->zs_read) {
153 if (setup->color_read) {
154 /* Exec previous load. */
155 vc4_tile_coordinates(setup, x, y);
156 vc4_store_before_load(setup);
157 }
158
159 if (args->zs_read.flags &
160 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
161 rcl_u8(setup, val: VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
162 rcl_u32(setup,
163 val: vc4_full_res_offset(exec, bo: setup->zs_read,
164 surf: &args->zs_read, x, y) |
165 VC4_LOADSTORE_FULL_RES_DISABLE_COLOR);
166 } else {
167 rcl_u8(setup, val: VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
168 rcl_u16(setup, val: args->zs_read.bits);
169 rcl_u32(setup, val: setup->zs_read->dma_addr +
170 args->zs_read.offset);
171 }
172 }
173
174 /* Clipping depends on tile coordinates having been
175 * emitted, so we always need one here.
176 */
177 vc4_tile_coordinates(setup, x, y);
178
179 /* Wait for the binner before jumping to the first
180 * tile's lists.
181 */
182 if (first && has_bin)
183 rcl_u8(setup, val: VC4_PACKET_WAIT_ON_SEMAPHORE);
184
185 if (has_bin) {
186 rcl_u8(setup, val: VC4_PACKET_BRANCH_TO_SUB_LIST);
187 rcl_u32(setup, val: (exec->tile_alloc_offset +
188 (y * exec->bin_tiles_x + x) * 32));
189 }
190
191 if (setup->msaa_color_write) {
192 bool last_tile_write = (!setup->msaa_zs_write &&
193 !setup->zs_write &&
194 !setup->color_write);
195 uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_ZS;
196
197 if (!last_tile_write)
198 bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL;
199 else if (last)
200 bits |= VC4_LOADSTORE_FULL_RES_EOF;
201 rcl_u8(setup, val: VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
202 rcl_u32(setup,
203 val: vc4_full_res_offset(exec, bo: setup->msaa_color_write,
204 surf: &args->msaa_color_write, x, y) |
205 bits);
206 }
207
208 if (setup->msaa_zs_write) {
209 bool last_tile_write = (!setup->zs_write &&
210 !setup->color_write);
211 uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_COLOR;
212
213 if (setup->msaa_color_write)
214 vc4_tile_coordinates(setup, x, y);
215 if (!last_tile_write)
216 bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL;
217 else if (last)
218 bits |= VC4_LOADSTORE_FULL_RES_EOF;
219 rcl_u8(setup, val: VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
220 rcl_u32(setup,
221 val: vc4_full_res_offset(exec, bo: setup->msaa_zs_write,
222 surf: &args->msaa_zs_write, x, y) |
223 bits);
224 }
225
226 if (setup->zs_write) {
227 bool last_tile_write = !setup->color_write;
228
229 if (setup->msaa_color_write || setup->msaa_zs_write)
230 vc4_tile_coordinates(setup, x, y);
231
232 rcl_u8(setup, val: VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
233 rcl_u16(setup, val: args->zs_write.bits |
234 (last_tile_write ?
235 0 : VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR));
236 rcl_u32(setup,
237 val: (setup->zs_write->dma_addr + args->zs_write.offset) |
238 ((last && last_tile_write) ?
239 VC4_LOADSTORE_TILE_BUFFER_EOF : 0));
240 }
241
242 if (setup->color_write) {
243 if (setup->msaa_color_write || setup->msaa_zs_write ||
244 setup->zs_write) {
245 vc4_tile_coordinates(setup, x, y);
246 }
247
248 if (last)
249 rcl_u8(setup, val: VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);
250 else
251 rcl_u8(setup, val: VC4_PACKET_STORE_MS_TILE_BUFFER);
252 }
253}
254
255static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
256 struct vc4_rcl_setup *setup)
257{
258 struct drm_vc4_submit_cl *args = exec->args;
259 bool has_bin = args->bin_cl_size != 0;
260 uint8_t min_x_tile = args->min_x_tile;
261 uint8_t min_y_tile = args->min_y_tile;
262 uint8_t max_x_tile = args->max_x_tile;
263 uint8_t max_y_tile = args->max_y_tile;
264 uint8_t xtiles = max_x_tile - min_x_tile + 1;
265 uint8_t ytiles = max_y_tile - min_y_tile + 1;
266 uint8_t xi, yi;
267 uint32_t size, loop_body_size;
268 bool positive_x = true;
269 bool positive_y = true;
270
271 if (args->flags & VC4_SUBMIT_CL_FIXED_RCL_ORDER) {
272 if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X))
273 positive_x = false;
274 if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y))
275 positive_y = false;
276 }
277
278 size = VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE;
279 loop_body_size = VC4_PACKET_TILE_COORDINATES_SIZE;
280
281 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) {
282 size += VC4_PACKET_CLEAR_COLORS_SIZE +
283 VC4_PACKET_TILE_COORDINATES_SIZE +
284 VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
285 }
286
287 if (setup->color_read) {
288 if (args->color_read.flags &
289 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
290 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
291 } else {
292 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
293 }
294 }
295 if (setup->zs_read) {
296 if (setup->color_read) {
297 loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE;
298 loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
299 }
300
301 if (args->zs_read.flags &
302 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
303 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
304 } else {
305 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
306 }
307 }
308
309 if (has_bin) {
310 size += VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE;
311 loop_body_size += VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE;
312 }
313
314 if (setup->msaa_color_write)
315 loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE;
316 if (setup->msaa_zs_write)
317 loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE;
318
319 if (setup->zs_write)
320 loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
321 if (setup->color_write)
322 loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE;
323
324 /* We need a VC4_PACKET_TILE_COORDINATES in between each store. */
325 loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE *
326 ((setup->msaa_color_write != NULL) +
327 (setup->msaa_zs_write != NULL) +
328 (setup->color_write != NULL) +
329 (setup->zs_write != NULL) - 1);
330
331 size += xtiles * ytiles * loop_body_size;
332
333 setup->rcl = &vc4_bo_create(dev, size, from_cache: true, type: VC4_BO_TYPE_RCL)->base;
334 if (IS_ERR(ptr: setup->rcl))
335 return PTR_ERR(ptr: setup->rcl);
336 list_add_tail(new: &to_vc4_bo(&setup->rcl->base)->unref_head,
337 head: &exec->unref_list);
338
339 /* The tile buffer gets cleared when the previous tile is stored. If
340 * the clear values changed between frames, then the tile buffer has
341 * stale clear values in it, so we have to do a store in None mode (no
342 * writes) so that we trigger the tile buffer clear.
343 */
344 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) {
345 rcl_u8(setup, val: VC4_PACKET_CLEAR_COLORS);
346 rcl_u32(setup, val: args->clear_color[0]);
347 rcl_u32(setup, val: args->clear_color[1]);
348 rcl_u32(setup, val: args->clear_z);
349 rcl_u8(setup, val: args->clear_s);
350
351 vc4_tile_coordinates(setup, x: 0, y: 0);
352
353 rcl_u8(setup, val: VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
354 rcl_u16(setup, VC4_LOADSTORE_TILE_BUFFER_NONE);
355 rcl_u32(setup, val: 0); /* no address, since we're in None mode */
356 }
357
358 rcl_u8(setup, val: VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
359 rcl_u32(setup,
360 val: (setup->color_write ? (setup->color_write->dma_addr +
361 args->color_write.offset) :
362 0));
363 rcl_u16(setup, val: args->width);
364 rcl_u16(setup, val: args->height);
365 rcl_u16(setup, val: args->color_write.bits);
366
367 for (yi = 0; yi < ytiles; yi++) {
368 int y = positive_y ? min_y_tile + yi : max_y_tile - yi;
369 for (xi = 0; xi < xtiles; xi++) {
370 int x = positive_x ? min_x_tile + xi : max_x_tile - xi;
371 bool first = (xi == 0 && yi == 0);
372 bool last = (xi == xtiles - 1 && yi == ytiles - 1);
373
374 emit_tile(exec, setup, x, y, first, last);
375 }
376 }
377
378 BUG_ON(setup->next_offset != size);
379 exec->ct1ca = setup->rcl->dma_addr;
380 exec->ct1ea = setup->rcl->dma_addr + setup->next_offset;
381
382 return 0;
383}
384
385static int vc4_full_res_bounds_check(struct vc4_exec_info *exec,
386 struct drm_gem_dma_object *obj,
387 struct drm_vc4_submit_rcl_surface *surf)
388{
389 struct drm_vc4_submit_cl *args = exec->args;
390 u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32);
391
392 if (surf->offset > obj->base.size) {
393 DRM_DEBUG("surface offset %d > BO size %zd\n",
394 surf->offset, obj->base.size);
395 return -EINVAL;
396 }
397
398 if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE <
399 render_tiles_stride * args->max_y_tile + args->max_x_tile) {
400 DRM_DEBUG("MSAA tile %d, %d out of bounds "
401 "(bo size %zd, offset %d).\n",
402 args->max_x_tile, args->max_y_tile,
403 obj->base.size,
404 surf->offset);
405 return -EINVAL;
406 }
407
408 return 0;
409}
410
411static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
412 struct drm_gem_dma_object **obj,
413 struct drm_vc4_submit_rcl_surface *surf)
414{
415 if (surf->flags != 0 || surf->bits != 0) {
416 DRM_DEBUG("MSAA surface had nonzero flags/bits\n");
417 return -EINVAL;
418 }
419
420 if (surf->hindex == ~0)
421 return 0;
422
423 *obj = vc4_use_bo(exec, hindex: surf->hindex);
424 if (!*obj)
425 return -EINVAL;
426
427 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
428
429 if (surf->offset & 0xf) {
430 DRM_DEBUG("MSAA write must be 16b aligned.\n");
431 return -EINVAL;
432 }
433
434 return vc4_full_res_bounds_check(exec, obj: *obj, surf);
435}
436
437static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
438 struct drm_gem_dma_object **obj,
439 struct drm_vc4_submit_rcl_surface *surf,
440 bool is_write)
441{
442 uint8_t tiling = VC4_GET_FIELD(surf->bits,
443 VC4_LOADSTORE_TILE_BUFFER_TILING);
444 uint8_t buffer = VC4_GET_FIELD(surf->bits,
445 VC4_LOADSTORE_TILE_BUFFER_BUFFER);
446 uint8_t format = VC4_GET_FIELD(surf->bits,
447 VC4_LOADSTORE_TILE_BUFFER_FORMAT);
448 int cpp;
449 int ret;
450
451 if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
452 DRM_DEBUG("Extra flags set\n");
453 return -EINVAL;
454 }
455
456 if (surf->hindex == ~0)
457 return 0;
458
459 *obj = vc4_use_bo(exec, hindex: surf->hindex);
460 if (!*obj)
461 return -EINVAL;
462
463 if (is_write)
464 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
465
466 if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
467 if (surf == &exec->args->zs_write) {
468 DRM_DEBUG("general zs write may not be a full-res.\n");
469 return -EINVAL;
470 }
471
472 if (surf->bits != 0) {
473 DRM_DEBUG("load/store general bits set with "
474 "full res load/store.\n");
475 return -EINVAL;
476 }
477
478 ret = vc4_full_res_bounds_check(exec, obj: *obj, surf);
479 if (ret)
480 return ret;
481
482 return 0;
483 }
484
485 if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK |
486 VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK |
487 VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) {
488 DRM_DEBUG("Unknown bits in load/store: 0x%04x\n",
489 surf->bits);
490 return -EINVAL;
491 }
492
493 if (tiling > VC4_TILING_FORMAT_LT) {
494 DRM_DEBUG("Bad tiling format\n");
495 return -EINVAL;
496 }
497
498 if (buffer == VC4_LOADSTORE_TILE_BUFFER_ZS) {
499 if (format != 0) {
500 DRM_DEBUG("No color format should be set for ZS\n");
501 return -EINVAL;
502 }
503 cpp = 4;
504 } else if (buffer == VC4_LOADSTORE_TILE_BUFFER_COLOR) {
505 switch (format) {
506 case VC4_LOADSTORE_TILE_BUFFER_BGR565:
507 case VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER:
508 cpp = 2;
509 break;
510 case VC4_LOADSTORE_TILE_BUFFER_RGBA8888:
511 cpp = 4;
512 break;
513 default:
514 DRM_DEBUG("Bad tile buffer format\n");
515 return -EINVAL;
516 }
517 } else {
518 DRM_DEBUG("Bad load/store buffer %d.\n", buffer);
519 return -EINVAL;
520 }
521
522 if (surf->offset & 0xf) {
523 DRM_DEBUG("load/store buffer must be 16b aligned.\n");
524 return -EINVAL;
525 }
526
527 if (!vc4_check_tex_size(exec, fbo: *obj, offset: surf->offset, tiling_format: tiling,
528 width: exec->args->width, height: exec->args->height, cpp)) {
529 return -EINVAL;
530 }
531
532 return 0;
533}
534
535static int
536vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
537 struct vc4_rcl_setup *setup,
538 struct drm_gem_dma_object **obj,
539 struct drm_vc4_submit_rcl_surface *surf)
540{
541 uint8_t tiling = VC4_GET_FIELD(surf->bits,
542 VC4_RENDER_CONFIG_MEMORY_FORMAT);
543 uint8_t format = VC4_GET_FIELD(surf->bits,
544 VC4_RENDER_CONFIG_FORMAT);
545 int cpp;
546
547 if (surf->flags != 0) {
548 DRM_DEBUG("No flags supported on render config.\n");
549 return -EINVAL;
550 }
551
552 if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK |
553 VC4_RENDER_CONFIG_FORMAT_MASK |
554 VC4_RENDER_CONFIG_MS_MODE_4X |
555 VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) {
556 DRM_DEBUG("Unknown bits in render config: 0x%04x\n",
557 surf->bits);
558 return -EINVAL;
559 }
560
561 if (surf->hindex == ~0)
562 return 0;
563
564 *obj = vc4_use_bo(exec, hindex: surf->hindex);
565 if (!*obj)
566 return -EINVAL;
567
568 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
569
570 if (tiling > VC4_TILING_FORMAT_LT) {
571 DRM_DEBUG("Bad tiling format\n");
572 return -EINVAL;
573 }
574
575 switch (format) {
576 case VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED:
577 case VC4_RENDER_CONFIG_FORMAT_BGR565:
578 cpp = 2;
579 break;
580 case VC4_RENDER_CONFIG_FORMAT_RGBA8888:
581 cpp = 4;
582 break;
583 default:
584 DRM_DEBUG("Bad tile buffer format\n");
585 return -EINVAL;
586 }
587
588 if (!vc4_check_tex_size(exec, fbo: *obj, offset: surf->offset, tiling_format: tiling,
589 width: exec->args->width, height: exec->args->height, cpp)) {
590 return -EINVAL;
591 }
592
593 return 0;
594}
595
596int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
597{
598 struct vc4_dev *vc4 = to_vc4_dev(dev);
599 struct vc4_rcl_setup setup = {0};
600 struct drm_vc4_submit_cl *args = exec->args;
601 bool has_bin = args->bin_cl_size != 0;
602 int ret;
603
604 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
605 return -ENODEV;
606
607 if (args->min_x_tile > args->max_x_tile ||
608 args->min_y_tile > args->max_y_tile) {
609 DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n",
610 args->min_x_tile, args->min_y_tile,
611 args->max_x_tile, args->max_y_tile);
612 return -EINVAL;
613 }
614
615 if (has_bin &&
616 (args->max_x_tile > exec->bin_tiles_x ||
617 args->max_y_tile > exec->bin_tiles_y)) {
618 DRM_DEBUG("Render tiles (%d,%d) outside of bin config "
619 "(%d,%d)\n",
620 args->max_x_tile, args->max_y_tile,
621 exec->bin_tiles_x, exec->bin_tiles_y);
622 return -EINVAL;
623 }
624
625 ret = vc4_rcl_render_config_surface_setup(exec, setup: &setup,
626 obj: &setup.color_write,
627 surf: &args->color_write);
628 if (ret)
629 return ret;
630
631 ret = vc4_rcl_surface_setup(exec, obj: &setup.color_read, surf: &args->color_read,
632 is_write: false);
633 if (ret)
634 return ret;
635
636 ret = vc4_rcl_surface_setup(exec, obj: &setup.zs_read, surf: &args->zs_read,
637 is_write: false);
638 if (ret)
639 return ret;
640
641 ret = vc4_rcl_surface_setup(exec, obj: &setup.zs_write, surf: &args->zs_write,
642 is_write: true);
643 if (ret)
644 return ret;
645
646 ret = vc4_rcl_msaa_surface_setup(exec, obj: &setup.msaa_color_write,
647 surf: &args->msaa_color_write);
648 if (ret)
649 return ret;
650
651 ret = vc4_rcl_msaa_surface_setup(exec, obj: &setup.msaa_zs_write,
652 surf: &args->msaa_zs_write);
653 if (ret)
654 return ret;
655
656 /* We shouldn't even have the job submitted to us if there's no
657 * surface to write out.
658 */
659 if (!setup.color_write && !setup.zs_write &&
660 !setup.msaa_color_write && !setup.msaa_zs_write) {
661 DRM_DEBUG("RCL requires color or Z/S write\n");
662 return -EINVAL;
663 }
664
665 return vc4_create_rcl_bo(dev, exec, setup: &setup);
666}
667

source code of linux/drivers/gpu/drm/vc4/vc4_render_cl.c