1// SPDX-License-Identifier: MIT
2/*
3 * Copyright (C) 2013-2019 NVIDIA Corporation
4 * Copyright (C) 2015 Rob Clark
5 */
6
7#include <drm/display/drm_dp_helper.h>
8#include <drm/drm_crtc.h>
9#include <drm/drm_print.h>
10
11#include "dp.h"
12
13static const u8 drm_dp_edp_revisions[] = { 0x11, 0x12, 0x13, 0x14 };
14
15static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps)
16{
17 caps->enhanced_framing = false;
18 caps->tps3_supported = false;
19 caps->fast_training = false;
20 caps->channel_coding = false;
21 caps->alternate_scrambler_reset = false;
22}
23
24void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
25 const struct drm_dp_link_caps *src)
26{
27 dest->enhanced_framing = src->enhanced_framing;
28 dest->tps3_supported = src->tps3_supported;
29 dest->fast_training = src->fast_training;
30 dest->channel_coding = src->channel_coding;
31 dest->alternate_scrambler_reset = src->alternate_scrambler_reset;
32}
33
34static void drm_dp_link_reset(struct drm_dp_link *link)
35{
36 unsigned int i;
37
38 if (!link)
39 return;
40
41 link->revision = 0;
42 link->max_rate = 0;
43 link->max_lanes = 0;
44
45 drm_dp_link_caps_reset(caps: &link->caps);
46 link->aux_rd_interval.cr = 0;
47 link->aux_rd_interval.ce = 0;
48 link->edp = 0;
49
50 link->rate = 0;
51 link->lanes = 0;
52
53 for (i = 0; i < DP_MAX_SUPPORTED_RATES; i++)
54 link->rates[i] = 0;
55
56 link->num_rates = 0;
57}
58
59/**
60 * drm_dp_link_add_rate() - add a rate to the list of supported rates
61 * @link: the link to add the rate to
62 * @rate: the rate to add
63 *
64 * Add a link rate to the list of supported link rates.
65 *
66 * Returns:
67 * 0 on success or one of the following negative error codes on failure:
68 * - ENOSPC if the maximum number of supported rates has been reached
69 * - EEXISTS if the link already supports this rate
70 *
71 * See also:
72 * drm_dp_link_remove_rate()
73 */
74int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate)
75{
76 unsigned int i, pivot;
77
78 if (link->num_rates == DP_MAX_SUPPORTED_RATES)
79 return -ENOSPC;
80
81 for (pivot = 0; pivot < link->num_rates; pivot++)
82 if (rate <= link->rates[pivot])
83 break;
84
85 if (pivot != link->num_rates && rate == link->rates[pivot])
86 return -EEXIST;
87
88 for (i = link->num_rates; i > pivot; i--)
89 link->rates[i] = link->rates[i - 1];
90
91 link->rates[pivot] = rate;
92 link->num_rates++;
93
94 return 0;
95}
96
97/**
98 * drm_dp_link_remove_rate() - remove a rate from the list of supported rates
99 * @link: the link from which to remove the rate
100 * @rate: the rate to remove
101 *
102 * Removes a link rate from the list of supported link rates.
103 *
104 * Returns:
105 * 0 on success or one of the following negative error codes on failure:
106 * - EINVAL if the specified rate is not among the supported rates
107 *
108 * See also:
109 * drm_dp_link_add_rate()
110 */
111int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate)
112{
113 unsigned int i;
114
115 for (i = 0; i < link->num_rates; i++)
116 if (rate == link->rates[i])
117 break;
118
119 if (i == link->num_rates)
120 return -EINVAL;
121
122 link->num_rates--;
123
124 while (i < link->num_rates) {
125 link->rates[i] = link->rates[i + 1];
126 i++;
127 }
128
129 return 0;
130}
131
132/**
133 * drm_dp_link_update_rates() - normalize the supported link rates array
134 * @link: the link for which to normalize the supported link rates
135 *
136 * Users should call this function after they've manually modified the array
137 * of supported link rates. This function removes any stale entries, compacts
138 * the array and updates the supported link rate count. Note that calling the
139 * drm_dp_link_remove_rate() function already does this janitorial work.
140 *
141 * See also:
142 * drm_dp_link_add_rate(), drm_dp_link_remove_rate()
143 */
144void drm_dp_link_update_rates(struct drm_dp_link *link)
145{
146 unsigned int i, count = 0;
147
148 for (i = 0; i < link->num_rates; i++) {
149 if (link->rates[i] != 0)
150 link->rates[count++] = link->rates[i];
151 }
152
153 for (i = count; i < link->num_rates; i++)
154 link->rates[i] = 0;
155
156 link->num_rates = count;
157}
158
159/**
160 * drm_dp_link_probe() - probe a DisplayPort link for capabilities
161 * @aux: DisplayPort AUX channel
162 * @link: pointer to structure in which to return link capabilities
163 *
164 * The structure filled in by this function can usually be passed directly
165 * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
166 * configure the link based on the link's capabilities.
167 *
168 * Returns 0 on success or a negative error code on failure.
169 */
170int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
171{
172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value;
173 unsigned int rd_interval;
174 int err;
175
176 drm_dp_link_reset(link);
177
178 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer: dpcd, size: sizeof(dpcd));
179 if (err < 0)
180 return err;
181
182 link->revision = dpcd[DP_DPCD_REV];
183 link->max_rate = drm_dp_max_link_rate(dpcd);
184 link->max_lanes = drm_dp_max_lane_count(dpcd);
185
186 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd);
187 link->caps.tps3_supported = drm_dp_tps3_supported(dpcd);
188 link->caps.fast_training = drm_dp_fast_training_cap(dpcd);
189 link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd);
190
191 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
192 link->caps.alternate_scrambler_reset = true;
193
194 err = drm_dp_dpcd_readb(aux, DP_EDP_DPCD_REV, valuep: &value);
195 if (err < 0)
196 return err;
197
198 if (value >= ARRAY_SIZE(drm_dp_edp_revisions))
199 DRM_ERROR("unsupported eDP version: %02x\n", value);
200 else
201 link->edp = drm_dp_edp_revisions[value];
202 }
203
204 /*
205 * The DPCD stores the AUX read interval in units of 4 ms. There are
206 * two special cases:
207 *
208 * 1) if the TRAINING_AUX_RD_INTERVAL field is 0, the clock recovery
209 * and channel equalization should use 100 us or 400 us AUX read
210 * intervals, respectively
211 *
212 * 2) for DP v1.4 and above, clock recovery should always use 100 us
213 * AUX read intervals
214 */
215 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
216 DP_TRAINING_AUX_RD_MASK;
217
218 if (rd_interval > 4) {
219 DRM_DEBUG_KMS("AUX interval %u out of range (max. 4)\n",
220 rd_interval);
221 rd_interval = 4;
222 }
223
224 rd_interval *= 4 * USEC_PER_MSEC;
225
226 if (rd_interval == 0 || link->revision >= DP_DPCD_REV_14)
227 link->aux_rd_interval.cr = 100;
228
229 if (rd_interval == 0)
230 link->aux_rd_interval.ce = 400;
231
232 link->rate = link->max_rate;
233 link->lanes = link->max_lanes;
234
235 /* Parse SUPPORTED_LINK_RATES from eDP 1.4 */
236 if (link->edp >= 0x14) {
237 u8 supported_rates[DP_MAX_SUPPORTED_RATES * 2];
238 unsigned int i;
239 u16 rate;
240
241 err = drm_dp_dpcd_read(aux, DP_SUPPORTED_LINK_RATES,
242 buffer: supported_rates,
243 size: sizeof(supported_rates));
244 if (err < 0)
245 return err;
246
247 for (i = 0; i < DP_MAX_SUPPORTED_RATES; i++) {
248 rate = supported_rates[i * 2 + 1] << 8 |
249 supported_rates[i * 2 + 0];
250
251 drm_dp_link_add_rate(link, rate: rate * 200);
252 }
253 }
254
255 return 0;
256}
257
258/**
259 * drm_dp_link_configure() - configure a DisplayPort link
260 * @aux: DisplayPort AUX channel
261 * @link: pointer to a structure containing the link configuration
262 *
263 * Returns 0 on success or a negative error code on failure.
264 */
265int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
266{
267 u8 values[2], value;
268 int err;
269
270 if (link->ops && link->ops->configure) {
271 err = link->ops->configure(link);
272 if (err < 0) {
273 DRM_ERROR("failed to configure DP link: %d\n", err);
274 return err;
275 }
276 }
277
278 values[0] = drm_dp_link_rate_to_bw_code(link_rate: link->rate);
279 values[1] = link->lanes;
280
281 if (link->caps.enhanced_framing)
282 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
283
284 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, buffer: values, size: sizeof(values));
285 if (err < 0)
286 return err;
287
288 if (link->caps.channel_coding)
289 value = DP_SET_ANSI_8B10B;
290 else
291 value = 0;
292
293 err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, value);
294 if (err < 0)
295 return err;
296
297 if (link->caps.alternate_scrambler_reset) {
298 err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET,
299 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
300 if (err < 0)
301 return err;
302 }
303
304 return 0;
305}
306
307/**
308 * drm_dp_link_choose() - choose the lowest possible configuration for a mode
309 * @link: DRM DP link object
310 * @mode: DRM display mode
311 * @info: DRM display information
312 *
313 * According to the eDP specification, a source should select a configuration
314 * with the lowest number of lanes and the lowest possible link rate that can
315 * match the bitrate requirements of a video mode. However it must ensure not
316 * to exceed the capabilities of the sink.
317 *
318 * Returns: 0 on success or a negative error code on failure.
319 */
320int drm_dp_link_choose(struct drm_dp_link *link,
321 const struct drm_display_mode *mode,
322 const struct drm_display_info *info)
323{
324 /* available link symbol clock rates */
325 static const unsigned int rates[3] = { 162000, 270000, 540000 };
326 /* available number of lanes */
327 static const unsigned int lanes[3] = { 1, 2, 4 };
328 unsigned long requirement, capacity;
329 unsigned int rate = link->max_rate;
330 unsigned int i, j;
331
332 /* bandwidth requirement */
333 requirement = mode->clock * info->bpc * 3;
334
335 for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) {
336 for (j = 0; j < ARRAY_SIZE(rates) && rates[j] <= rate; j++) {
337 /*
338 * Capacity for this combination of lanes and rate,
339 * factoring in the ANSI 8B/10B encoding.
340 *
341 * Link rates in the DRM DP helpers are really link
342 * symbol frequencies, so a tenth of the actual rate
343 * of the link.
344 */
345 capacity = lanes[i] * (rates[j] * 10) * 8 / 10;
346
347 if (capacity >= requirement) {
348 DRM_DEBUG_KMS("using %u lanes at %u kHz (%lu/%lu kbps)\n",
349 lanes[i], rates[j], requirement,
350 capacity);
351 link->lanes = lanes[i];
352 link->rate = rates[j];
353 return 0;
354 }
355 }
356 }
357
358 return -ERANGE;
359}
360
361/**
362 * DOC: Link training
363 *
364 * These functions contain common logic and helpers to implement DisplayPort
365 * link training.
366 */
367
368/**
369 * drm_dp_link_train_init() - initialize DisplayPort link training state
370 * @train: DisplayPort link training state
371 */
372void drm_dp_link_train_init(struct drm_dp_link_train *train)
373{
374 struct drm_dp_link_train_set *request = &train->request;
375 struct drm_dp_link_train_set *adjust = &train->adjust;
376 unsigned int i;
377
378 for (i = 0; i < 4; i++) {
379 request->voltage_swing[i] = 0;
380 adjust->voltage_swing[i] = 0;
381
382 request->pre_emphasis[i] = 0;
383 adjust->pre_emphasis[i] = 0;
384
385 request->post_cursor[i] = 0;
386 adjust->post_cursor[i] = 0;
387 }
388
389 train->pattern = DP_TRAINING_PATTERN_DISABLE;
390 train->clock_recovered = false;
391 train->channel_equalized = false;
392}
393
394static bool drm_dp_link_train_valid(const struct drm_dp_link_train *train)
395{
396 return train->clock_recovered && train->channel_equalized;
397}
398
399static int drm_dp_link_apply_training(struct drm_dp_link *link)
400{
401 struct drm_dp_link_train_set *request = &link->train.request;
402 unsigned int lanes = link->lanes, *vs, *pe, *pc, i;
403 struct drm_dp_aux *aux = link->aux;
404 u8 values[4], pattern = 0;
405 int err;
406
407 err = link->ops->apply_training(link);
408 if (err < 0) {
409 DRM_ERROR("failed to apply link training: %d\n", err);
410 return err;
411 }
412
413 vs = request->voltage_swing;
414 pe = request->pre_emphasis;
415 pc = request->post_cursor;
416
417 /* write currently selected voltage-swing and pre-emphasis levels */
418 for (i = 0; i < lanes; i++)
419 values[i] = DP_TRAIN_VOLTAGE_SWING_LEVEL(vs[i]) |
420 DP_TRAIN_PRE_EMPHASIS_LEVEL(pe[i]);
421
422 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, buffer: values, size: lanes);
423 if (err < 0) {
424 DRM_ERROR("failed to set training parameters: %d\n", err);
425 return err;
426 }
427
428 /* write currently selected post-cursor level (if supported) */
429 if (link->revision >= 0x12 && link->rate == 540000) {
430 values[0] = values[1] = 0;
431
432 for (i = 0; i < lanes; i++)
433 values[i / 2] |= DP_LANE_POST_CURSOR(i, pc[i]);
434
435 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_1_SET2, buffer: values,
436 DIV_ROUND_UP(lanes, 2));
437 if (err < 0) {
438 DRM_ERROR("failed to set post-cursor: %d\n", err);
439 return err;
440 }
441 }
442
443 /* write link pattern */
444 if (link->train.pattern != DP_TRAINING_PATTERN_DISABLE)
445 pattern |= DP_LINK_SCRAMBLING_DISABLE;
446
447 pattern |= link->train.pattern;
448
449 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, value: pattern);
450 if (err < 0) {
451 DRM_ERROR("failed to set training pattern: %d\n", err);
452 return err;
453 }
454
455 return 0;
456}
457
458static void drm_dp_link_train_wait(struct drm_dp_link *link)
459{
460 unsigned long min = 0;
461
462 switch (link->train.pattern) {
463 case DP_TRAINING_PATTERN_1:
464 min = link->aux_rd_interval.cr;
465 break;
466
467 case DP_TRAINING_PATTERN_2:
468 case DP_TRAINING_PATTERN_3:
469 min = link->aux_rd_interval.ce;
470 break;
471
472 default:
473 break;
474 }
475
476 if (min > 0)
477 usleep_range(min, max: 2 * min);
478}
479
480static void drm_dp_link_get_adjustments(struct drm_dp_link *link,
481 u8 status[DP_LINK_STATUS_SIZE])
482{
483 struct drm_dp_link_train_set *adjust = &link->train.adjust;
484 unsigned int i;
485 u8 post_cursor;
486 int err;
487
488 err = drm_dp_dpcd_read(aux: link->aux, DP_ADJUST_REQUEST_POST_CURSOR2,
489 buffer: &post_cursor, size: sizeof(post_cursor));
490 if (err < 0) {
491 DRM_ERROR("failed to read post_cursor2: %d\n", err);
492 post_cursor = 0;
493 }
494
495 for (i = 0; i < link->lanes; i++) {
496 adjust->voltage_swing[i] =
497 drm_dp_get_adjust_request_voltage(link_status: status, lane: i) >>
498 DP_TRAIN_VOLTAGE_SWING_SHIFT;
499
500 adjust->pre_emphasis[i] =
501 drm_dp_get_adjust_request_pre_emphasis(link_status: status, lane: i) >>
502 DP_TRAIN_PRE_EMPHASIS_SHIFT;
503
504 adjust->post_cursor[i] =
505 (post_cursor >> (i << 1)) & 0x3;
506 }
507}
508
509static void drm_dp_link_train_adjust(struct drm_dp_link_train *train)
510{
511 struct drm_dp_link_train_set *request = &train->request;
512 struct drm_dp_link_train_set *adjust = &train->adjust;
513 unsigned int i;
514
515 for (i = 0; i < 4; i++)
516 if (request->voltage_swing[i] != adjust->voltage_swing[i])
517 request->voltage_swing[i] = adjust->voltage_swing[i];
518
519 for (i = 0; i < 4; i++)
520 if (request->pre_emphasis[i] != adjust->pre_emphasis[i])
521 request->pre_emphasis[i] = adjust->pre_emphasis[i];
522
523 for (i = 0; i < 4; i++)
524 if (request->post_cursor[i] != adjust->post_cursor[i])
525 request->post_cursor[i] = adjust->post_cursor[i];
526}
527
528static int drm_dp_link_recover_clock(struct drm_dp_link *link)
529{
530 u8 status[DP_LINK_STATUS_SIZE];
531 int err;
532
533 err = drm_dp_link_apply_training(link);
534 if (err < 0)
535 return err;
536
537 drm_dp_link_train_wait(link);
538
539 err = drm_dp_dpcd_read_link_status(aux: link->aux, status);
540 if (err < 0) {
541 DRM_ERROR("failed to read link status: %d\n", err);
542 return err;
543 }
544
545 if (!drm_dp_clock_recovery_ok(link_status: status, lane_count: link->lanes))
546 drm_dp_link_get_adjustments(link, status);
547 else
548 link->train.clock_recovered = true;
549
550 return 0;
551}
552
553static int drm_dp_link_clock_recovery(struct drm_dp_link *link)
554{
555 unsigned int repeat;
556 int err;
557
558 /* start clock recovery using training pattern 1 */
559 link->train.pattern = DP_TRAINING_PATTERN_1;
560
561 for (repeat = 1; repeat < 5; repeat++) {
562 err = drm_dp_link_recover_clock(link);
563 if (err < 0) {
564 DRM_ERROR("failed to recover clock: %d\n", err);
565 return err;
566 }
567
568 if (link->train.clock_recovered)
569 break;
570
571 drm_dp_link_train_adjust(train: &link->train);
572 }
573
574 return 0;
575}
576
577static int drm_dp_link_equalize_channel(struct drm_dp_link *link)
578{
579 struct drm_dp_aux *aux = link->aux;
580 u8 status[DP_LINK_STATUS_SIZE];
581 int err;
582
583 err = drm_dp_link_apply_training(link);
584 if (err < 0)
585 return err;
586
587 drm_dp_link_train_wait(link);
588
589 err = drm_dp_dpcd_read_link_status(aux, status);
590 if (err < 0) {
591 DRM_ERROR("failed to read link status: %d\n", err);
592 return err;
593 }
594
595 if (!drm_dp_clock_recovery_ok(link_status: status, lane_count: link->lanes)) {
596 DRM_ERROR("clock recovery lost while equalizing channel\n");
597 link->train.clock_recovered = false;
598 return 0;
599 }
600
601 if (!drm_dp_channel_eq_ok(link_status: status, lane_count: link->lanes))
602 drm_dp_link_get_adjustments(link, status);
603 else
604 link->train.channel_equalized = true;
605
606 return 0;
607}
608
609static int drm_dp_link_channel_equalization(struct drm_dp_link *link)
610{
611 unsigned int repeat;
612 int err;
613
614 /* start channel equalization using pattern 2 or 3 */
615 if (link->caps.tps3_supported)
616 link->train.pattern = DP_TRAINING_PATTERN_3;
617 else
618 link->train.pattern = DP_TRAINING_PATTERN_2;
619
620 for (repeat = 1; repeat < 5; repeat++) {
621 err = drm_dp_link_equalize_channel(link);
622 if (err < 0) {
623 DRM_ERROR("failed to equalize channel: %d\n", err);
624 return err;
625 }
626
627 if (link->train.channel_equalized)
628 break;
629
630 drm_dp_link_train_adjust(train: &link->train);
631 }
632
633 return 0;
634}
635
636static int drm_dp_link_downgrade(struct drm_dp_link *link)
637{
638 switch (link->rate) {
639 case 162000:
640 return -EINVAL;
641
642 case 270000:
643 link->rate = 162000;
644 break;
645
646 case 540000:
647 link->rate = 270000;
648 return 0;
649 }
650
651 return 0;
652}
653
654static void drm_dp_link_train_disable(struct drm_dp_link *link)
655{
656 int err;
657
658 link->train.pattern = DP_TRAINING_PATTERN_DISABLE;
659
660 err = drm_dp_link_apply_training(link);
661 if (err < 0)
662 DRM_ERROR("failed to disable link training: %d\n", err);
663}
664
665static int drm_dp_link_train_full(struct drm_dp_link *link)
666{
667 int err;
668
669retry:
670 DRM_DEBUG_KMS("full-training link: %u lane%s at %u MHz\n",
671 link->lanes, (link->lanes > 1) ? "s" : "",
672 link->rate / 100);
673
674 err = drm_dp_link_configure(aux: link->aux, link);
675 if (err < 0) {
676 DRM_ERROR("failed to configure DP link: %d\n", err);
677 return err;
678 }
679
680 err = drm_dp_link_clock_recovery(link);
681 if (err < 0) {
682 DRM_ERROR("clock recovery failed: %d\n", err);
683 goto out;
684 }
685
686 if (!link->train.clock_recovered) {
687 DRM_ERROR("clock recovery failed, downgrading link\n");
688
689 err = drm_dp_link_downgrade(link);
690 if (err < 0)
691 goto out;
692
693 goto retry;
694 }
695
696 DRM_DEBUG_KMS("clock recovery succeeded\n");
697
698 err = drm_dp_link_channel_equalization(link);
699 if (err < 0) {
700 DRM_ERROR("channel equalization failed: %d\n", err);
701 goto out;
702 }
703
704 if (!link->train.channel_equalized) {
705 DRM_ERROR("channel equalization failed, downgrading link\n");
706
707 err = drm_dp_link_downgrade(link);
708 if (err < 0)
709 goto out;
710
711 goto retry;
712 }
713
714 DRM_DEBUG_KMS("channel equalization succeeded\n");
715
716out:
717 drm_dp_link_train_disable(link);
718 return err;
719}
720
721static int drm_dp_link_train_fast(struct drm_dp_link *link)
722{
723 u8 status[DP_LINK_STATUS_SIZE];
724 int err;
725
726 DRM_DEBUG_KMS("fast-training link: %u lane%s at %u MHz\n",
727 link->lanes, (link->lanes > 1) ? "s" : "",
728 link->rate / 100);
729
730 err = drm_dp_link_configure(aux: link->aux, link);
731 if (err < 0) {
732 DRM_ERROR("failed to configure DP link: %d\n", err);
733 return err;
734 }
735
736 /* transmit training pattern 1 for 500 microseconds */
737 link->train.pattern = DP_TRAINING_PATTERN_1;
738
739 err = drm_dp_link_apply_training(link);
740 if (err < 0)
741 goto out;
742
743 usleep_range(min: 500, max: 1000);
744
745 /* transmit training pattern 2 or 3 for 500 microseconds */
746 if (link->caps.tps3_supported)
747 link->train.pattern = DP_TRAINING_PATTERN_3;
748 else
749 link->train.pattern = DP_TRAINING_PATTERN_2;
750
751 err = drm_dp_link_apply_training(link);
752 if (err < 0)
753 goto out;
754
755 usleep_range(min: 500, max: 1000);
756
757 err = drm_dp_dpcd_read_link_status(aux: link->aux, status);
758 if (err < 0) {
759 DRM_ERROR("failed to read link status: %d\n", err);
760 goto out;
761 }
762
763 if (!drm_dp_clock_recovery_ok(link_status: status, lane_count: link->lanes)) {
764 DRM_ERROR("clock recovery failed\n");
765 err = -EIO;
766 }
767
768 if (!drm_dp_channel_eq_ok(link_status: status, lane_count: link->lanes)) {
769 DRM_ERROR("channel equalization failed\n");
770 err = -EIO;
771 }
772
773out:
774 drm_dp_link_train_disable(link);
775 return err;
776}
777
778/**
779 * drm_dp_link_train() - perform DisplayPort link training
780 * @link: a DP link object
781 *
782 * Uses the context stored in the DP link object to perform link training. It
783 * is expected that drivers will call drm_dp_link_probe() to obtain the link
784 * capabilities before performing link training.
785 *
786 * If the sink supports fast link training (no AUX CH handshake) and valid
787 * training settings are available, this function will try to perform fast
788 * link training and fall back to full link training on failure.
789 *
790 * Returns: 0 on success or a negative error code on failure.
791 */
792int drm_dp_link_train(struct drm_dp_link *link)
793{
794 int err;
795
796 drm_dp_link_train_init(train: &link->train);
797
798 if (link->caps.fast_training) {
799 if (drm_dp_link_train_valid(train: &link->train)) {
800 err = drm_dp_link_train_fast(link);
801 if (err < 0)
802 DRM_ERROR("fast link training failed: %d\n",
803 err);
804 else
805 return 0;
806 } else {
807 DRM_DEBUG_KMS("training parameters not available\n");
808 }
809 } else {
810 DRM_DEBUG_KMS("fast link training not supported\n");
811 }
812
813 err = drm_dp_link_train_full(link);
814 if (err < 0)
815 DRM_ERROR("full link training failed: %d\n", err);
816
817 return err;
818}
819

source code of linux/drivers/gpu/drm/tegra/dp.c