1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include <linux/bitfield.h>
7#include <linux/clk.h>
8#include <linux/component.h>
9#include <linux/iopoll.h>
10#include <linux/irq.h>
11#include <linux/of.h>
12#include <linux/of_platform.h>
13#include <linux/phy/phy.h>
14#include <linux/platform_device.h>
15#include <linux/reset.h>
16#include <linux/units.h>
17
18#include <video/mipi_display.h>
19#include <video/videomode.h>
20
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_bridge.h>
23#include <drm/drm_bridge_connector.h>
24#include <drm/drm_mipi_dsi.h>
25#include <drm/drm_of.h>
26#include <drm/drm_panel.h>
27#include <drm/drm_print.h>
28#include <drm/drm_probe_helper.h>
29#include <drm/drm_simple_kms_helper.h>
30
31#include "mtk_ddp_comp.h"
32#include "mtk_disp_drv.h"
33#include "mtk_drm_drv.h"
34
35#define DSI_START 0x00
36
37#define DSI_INTEN 0x08
38
39#define DSI_INTSTA 0x0c
40#define LPRX_RD_RDY_INT_FLAG BIT(0)
41#define CMD_DONE_INT_FLAG BIT(1)
42#define TE_RDY_INT_FLAG BIT(2)
43#define VM_DONE_INT_FLAG BIT(3)
44#define EXT_TE_RDY_INT_FLAG BIT(4)
45#define DSI_BUSY BIT(31)
46
47#define DSI_CON_CTRL 0x10
48#define DSI_RESET BIT(0)
49#define DSI_EN BIT(1)
50#define DPHY_RESET BIT(2)
51
52#define DSI_MODE_CTRL 0x14
53#define MODE (3)
54#define CMD_MODE 0
55#define SYNC_PULSE_MODE 1
56#define SYNC_EVENT_MODE 2
57#define BURST_MODE 3
58#define FRM_MODE BIT(16)
59#define MIX_MODE BIT(17)
60
61#define DSI_TXRX_CTRL 0x18
62#define VC_NUM BIT(1)
63#define LANE_NUM GENMASK(5, 2)
64#define DIS_EOT BIT(6)
65#define NULL_EN BIT(7)
66#define TE_FREERUN BIT(8)
67#define EXT_TE_EN BIT(9)
68#define EXT_TE_EDGE BIT(10)
69#define MAX_RTN_SIZE GENMASK(15, 12)
70#define HSTX_CKLP_EN BIT(16)
71
72#define DSI_PSCTRL 0x1c
73#define DSI_PS_WC GENMASK(13, 0)
74#define DSI_PS_SEL GENMASK(17, 16)
75#define PACKED_PS_16BIT_RGB565 0
76#define PACKED_PS_18BIT_RGB666 1
77#define LOOSELY_PS_24BIT_RGB666 2
78#define PACKED_PS_24BIT_RGB888 3
79
80#define DSI_VSA_NL 0x20
81#define DSI_VBP_NL 0x24
82#define DSI_VFP_NL 0x28
83#define DSI_VACT_NL 0x2C
84#define VACT_NL GENMASK(14, 0)
85#define DSI_SIZE_CON 0x38
86#define DSI_HEIGHT GENMASK(30, 16)
87#define DSI_WIDTH GENMASK(14, 0)
88#define DSI_HSA_WC 0x50
89#define DSI_HBP_WC 0x54
90#define DSI_HFP_WC 0x58
91#define HFP_HS_VB_PS_WC GENMASK(30, 16)
92#define HFP_HS_EN BIT(31)
93
94#define DSI_CMDQ_SIZE 0x60
95#define CMDQ_SIZE 0x3f
96#define CMDQ_SIZE_SEL BIT(15)
97
98#define DSI_HSTX_CKL_WC 0x64
99#define HSTX_CKL_WC GENMASK(15, 2)
100
101#define DSI_RX_DATA0 0x74
102#define DSI_RX_DATA1 0x78
103#define DSI_RX_DATA2 0x7c
104#define DSI_RX_DATA3 0x80
105
106#define DSI_RACK 0x84
107#define RACK BIT(0)
108
109#define DSI_PHY_LCCON 0x104
110#define LC_HS_TX_EN BIT(0)
111#define LC_ULPM_EN BIT(1)
112#define LC_WAKEUP_EN BIT(2)
113
114#define DSI_PHY_LD0CON 0x108
115#define LD0_HS_TX_EN BIT(0)
116#define LD0_ULPM_EN BIT(1)
117#define LD0_WAKEUP_EN BIT(2)
118
119#define DSI_PHY_TIMECON0 0x110
120#define LPX GENMASK(7, 0)
121#define HS_PREP GENMASK(15, 8)
122#define HS_ZERO GENMASK(23, 16)
123#define HS_TRAIL GENMASK(31, 24)
124
125#define DSI_PHY_TIMECON1 0x114
126#define TA_GO GENMASK(7, 0)
127#define TA_SURE GENMASK(15, 8)
128#define TA_GET GENMASK(23, 16)
129#define DA_HS_EXIT GENMASK(31, 24)
130
131#define DSI_PHY_TIMECON2 0x118
132#define CONT_DET GENMASK(7, 0)
133#define DA_HS_SYNC GENMASK(15, 8)
134#define CLK_ZERO GENMASK(23, 16)
135#define CLK_TRAIL GENMASK(31, 24)
136
137#define DSI_PHY_TIMECON3 0x11c
138#define CLK_HS_PREP GENMASK(7, 0)
139#define CLK_HS_POST GENMASK(15, 8)
140#define CLK_HS_EXIT GENMASK(23, 16)
141
142/* DSI_VM_CMD_CON */
143#define VM_CMD_EN BIT(0)
144#define TS_VFP_EN BIT(5)
145
146/* DSI_SHADOW_DEBUG */
147#define FORCE_COMMIT BIT(0)
148#define BYPASS_SHADOW BIT(1)
149
150/* CMDQ related bits */
151#define CONFIG GENMASK(7, 0)
152#define SHORT_PACKET 0
153#define LONG_PACKET 2
154#define BTA BIT(2)
155#define DATA_ID GENMASK(15, 8)
156#define DATA_0 GENMASK(23, 16)
157#define DATA_1 GENMASK(31, 24)
158
159#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
160
161#define MTK_DSI_HOST_IS_READ(type) \
162 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
163 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
164 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
165 (type == MIPI_DSI_DCS_READ))
166
167struct mtk_phy_timing {
168 u32 lpx;
169 u32 da_hs_prepare;
170 u32 da_hs_zero;
171 u32 da_hs_trail;
172
173 u32 ta_go;
174 u32 ta_sure;
175 u32 ta_get;
176 u32 da_hs_exit;
177
178 u32 clk_hs_zero;
179 u32 clk_hs_trail;
180
181 u32 clk_hs_prepare;
182 u32 clk_hs_post;
183 u32 clk_hs_exit;
184};
185
186struct phy;
187
188struct mtk_dsi_driver_data {
189 const u32 reg_cmdq_off;
190 const u32 reg_vm_cmd_off;
191 const u32 reg_shadow_dbg_off;
192 bool has_shadow_ctl;
193 bool has_size_ctl;
194 bool cmdq_long_packet_ctl;
195 bool support_per_frame_lp;
196};
197
198struct mtk_dsi {
199 struct device *dev;
200 struct mipi_dsi_host host;
201 struct drm_encoder encoder;
202 struct drm_bridge bridge;
203 struct drm_bridge *next_bridge;
204 struct drm_connector *connector;
205 struct phy *phy;
206
207 void __iomem *regs;
208
209 struct clk *engine_clk;
210 struct clk *digital_clk;
211 struct clk *hs_clk;
212
213 u32 data_rate;
214
215 unsigned long mode_flags;
216 enum mipi_dsi_pixel_format format;
217 unsigned int lanes;
218 struct videomode vm;
219 struct mtk_phy_timing phy_timing;
220 int refcount;
221 bool enabled;
222 bool lanes_ready;
223 u32 irq_data;
224 wait_queue_head_t irq_wait_queue;
225 const struct mtk_dsi_driver_data *driver_data;
226};
227
228static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b)
229{
230 return container_of(b, struct mtk_dsi, bridge);
231}
232
233static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
234{
235 return container_of(h, struct mtk_dsi, host);
236}
237
238static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
239{
240 u32 temp = readl(addr: dsi->regs + offset);
241
242 writel(val: (temp & ~mask) | (data & mask), addr: dsi->regs + offset);
243}
244
245static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
246{
247 u32 timcon0, timcon1, timcon2, timcon3;
248 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ);
249 struct mtk_phy_timing *timing = &dsi->phy_timing;
250
251 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
252 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
253 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
254 timing->da_hs_prepare;
255 timing->da_hs_trail = timing->da_hs_prepare + 1;
256
257 timing->ta_go = 4 * timing->lpx - 2;
258 timing->ta_sure = timing->lpx + 2;
259 timing->ta_get = 4 * timing->lpx;
260 timing->da_hs_exit = 2 * timing->lpx + 1;
261
262 timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
263 timing->clk_hs_post = timing->clk_hs_prepare + 8;
264 timing->clk_hs_trail = timing->clk_hs_prepare;
265 timing->clk_hs_zero = timing->clk_hs_trail * 4;
266 timing->clk_hs_exit = 2 * timing->clk_hs_trail;
267
268 timcon0 = FIELD_PREP(LPX, timing->lpx) |
269 FIELD_PREP(HS_PREP, timing->da_hs_prepare) |
270 FIELD_PREP(HS_ZERO, timing->da_hs_zero) |
271 FIELD_PREP(HS_TRAIL, timing->da_hs_trail);
272
273 timcon1 = FIELD_PREP(TA_GO, timing->ta_go) |
274 FIELD_PREP(TA_SURE, timing->ta_sure) |
275 FIELD_PREP(TA_GET, timing->ta_get) |
276 FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit);
277
278 timcon2 = FIELD_PREP(DA_HS_SYNC, 1) |
279 FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) |
280 FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail);
281
282 timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) |
283 FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) |
284 FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit);
285
286 writel(val: timcon0, addr: dsi->regs + DSI_PHY_TIMECON0);
287 writel(val: timcon1, addr: dsi->regs + DSI_PHY_TIMECON1);
288 writel(val: timcon2, addr: dsi->regs + DSI_PHY_TIMECON2);
289 writel(val: timcon3, addr: dsi->regs + DSI_PHY_TIMECON3);
290}
291
292static void mtk_dsi_enable(struct mtk_dsi *dsi)
293{
294 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
295}
296
297static void mtk_dsi_disable(struct mtk_dsi *dsi)
298{
299 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, data: 0);
300}
301
302static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
303{
304 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
305 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, data: 0);
306}
307
308static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
309{
310 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
311 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, data: 0);
312}
313
314static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
315{
316 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, data: 0);
317 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, data: 0);
318}
319
320static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
321{
322 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, data: 0);
323 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
324 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, data: 0);
325}
326
327static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
328{
329 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, data: 0);
330 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, data: 0);
331}
332
333static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
334{
335 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, data: 0);
336 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
337 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, data: 0);
338}
339
340static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
341{
342 return readl(addr: dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
343}
344
345static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
346{
347 if (enter && !mtk_dsi_clk_hs_state(dsi))
348 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
349 else if (!enter && mtk_dsi_clk_hs_state(dsi))
350 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, data: 0);
351}
352
353static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
354{
355 u32 vid_mode = CMD_MODE;
356
357 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
358 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
359 vid_mode = BURST_MODE;
360 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
361 vid_mode = SYNC_PULSE_MODE;
362 else
363 vid_mode = SYNC_EVENT_MODE;
364 }
365
366 writel(val: vid_mode, addr: dsi->regs + DSI_MODE_CTRL);
367}
368
369static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
370{
371 mtk_dsi_mask(dsi, offset: dsi->driver_data->reg_vm_cmd_off, VM_CMD_EN, VM_CMD_EN);
372 mtk_dsi_mask(dsi, offset: dsi->driver_data->reg_vm_cmd_off, TS_VFP_EN, TS_VFP_EN);
373}
374
375static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
376{
377 u32 regval, tmp_reg = 0;
378 u8 i;
379
380 /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */
381 for (i = 0; i < dsi->lanes; i++)
382 tmp_reg |= BIT(i);
383
384 regval = FIELD_PREP(LANE_NUM, tmp_reg);
385
386 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
387 regval |= HSTX_CKLP_EN;
388
389 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
390 regval |= DIS_EOT;
391
392 writel(val: regval, addr: dsi->regs + DSI_TXRX_CTRL);
393}
394
395static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact)
396{
397 u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl;
398
399 if (dsi->format == MIPI_DSI_FMT_RGB565)
400 dsi_buf_bpp = 2;
401 else
402 dsi_buf_bpp = 3;
403
404 /* Word count */
405 ps_wc = FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp);
406 ps_val = ps_wc;
407
408 /* Pixel Stream type */
409 switch (dsi->format) {
410 default:
411 fallthrough;
412 case MIPI_DSI_FMT_RGB888:
413 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888);
414 break;
415 case MIPI_DSI_FMT_RGB666:
416 ps_val |= FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666);
417 break;
418 case MIPI_DSI_FMT_RGB666_PACKED:
419 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666);
420 break;
421 case MIPI_DSI_FMT_RGB565:
422 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565);
423 break;
424 }
425
426 if (config_vact) {
427 vact_nl = FIELD_PREP(VACT_NL, dsi->vm.vactive);
428 writel(val: vact_nl, addr: dsi->regs + DSI_VACT_NL);
429 writel(val: ps_wc, addr: dsi->regs + DSI_HSTX_CKL_WC);
430 }
431 writel(val: ps_val, addr: dsi->regs + DSI_PSCTRL);
432}
433
434static void mtk_dsi_config_vdo_timing_per_frame_lp(struct mtk_dsi *dsi)
435{
436 u32 horizontal_sync_active_byte;
437 u32 horizontal_backporch_byte;
438 u32 horizontal_frontporch_byte;
439 u32 hfp_byte_adjust, v_active_adjust;
440 u32 cklp_wc_min_adjust, cklp_wc_max_adjust;
441 u32 dsi_tmp_buf_bpp;
442 unsigned int da_hs_trail;
443 unsigned int ps_wc, hs_vb_ps_wc;
444 u32 v_active_roundup, hstx_cklp_wc;
445 u32 hstx_cklp_wc_max, hstx_cklp_wc_min;
446 struct videomode *vm = &dsi->vm;
447
448 if (dsi->format == MIPI_DSI_FMT_RGB565)
449 dsi_tmp_buf_bpp = 2;
450 else
451 dsi_tmp_buf_bpp = 3;
452
453 da_hs_trail = dsi->phy_timing.da_hs_trail;
454 ps_wc = vm->hactive * dsi_tmp_buf_bpp;
455
456 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
457 horizontal_sync_active_byte =
458 vm->hsync_len * dsi_tmp_buf_bpp - 10;
459 horizontal_backporch_byte =
460 vm->hback_porch * dsi_tmp_buf_bpp - 10;
461 hfp_byte_adjust = 12;
462 v_active_adjust = 32 + horizontal_sync_active_byte;
463 cklp_wc_min_adjust = 12 + 2 + 4 + horizontal_sync_active_byte;
464 cklp_wc_max_adjust = 20 + 6 + 4 + horizontal_sync_active_byte;
465 } else {
466 horizontal_sync_active_byte = vm->hsync_len * dsi_tmp_buf_bpp - 4;
467 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
468 dsi_tmp_buf_bpp - 10;
469 cklp_wc_min_adjust = 4;
470 cklp_wc_max_adjust = 12 + 4 + 4;
471 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
472 hfp_byte_adjust = 18;
473 v_active_adjust = 28;
474 } else {
475 hfp_byte_adjust = 12;
476 v_active_adjust = 22;
477 }
478 }
479 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp - hfp_byte_adjust;
480 v_active_roundup = (v_active_adjust + horizontal_backporch_byte + ps_wc +
481 horizontal_frontporch_byte) % dsi->lanes;
482 if (v_active_roundup)
483 horizontal_backporch_byte += dsi->lanes - v_active_roundup;
484 hstx_cklp_wc_min = (DIV_ROUND_UP(cklp_wc_min_adjust, dsi->lanes) + da_hs_trail + 1)
485 * dsi->lanes / 6 - 1;
486 hstx_cklp_wc_max = (DIV_ROUND_UP((cklp_wc_max_adjust + horizontal_backporch_byte +
487 ps_wc), dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1;
488
489 hstx_cklp_wc = FIELD_PREP(HSTX_CKL_WC, (hstx_cklp_wc_min + hstx_cklp_wc_max) / 2);
490 writel(val: hstx_cklp_wc, addr: dsi->regs + DSI_HSTX_CKL_WC);
491
492 hs_vb_ps_wc = ps_wc - (dsi->phy_timing.lpx + dsi->phy_timing.da_hs_exit +
493 dsi->phy_timing.da_hs_prepare + dsi->phy_timing.da_hs_zero + 2) * dsi->lanes;
494 horizontal_frontporch_byte |= FIELD_PREP(HFP_HS_EN, 1) |
495 FIELD_PREP(HFP_HS_VB_PS_WC, hs_vb_ps_wc);
496
497 writel(val: horizontal_sync_active_byte, addr: dsi->regs + DSI_HSA_WC);
498 writel(val: horizontal_backporch_byte, addr: dsi->regs + DSI_HBP_WC);
499 writel(val: horizontal_frontporch_byte, addr: dsi->regs + DSI_HFP_WC);
500}
501
502static void mtk_dsi_config_vdo_timing_per_line_lp(struct mtk_dsi *dsi)
503{
504 u32 horizontal_sync_active_byte;
505 u32 horizontal_backporch_byte;
506 u32 horizontal_frontporch_byte;
507 u32 horizontal_front_back_byte;
508 u32 data_phy_cycles_byte;
509 u32 dsi_tmp_buf_bpp, data_phy_cycles;
510 u32 delta;
511 struct mtk_phy_timing *timing = &dsi->phy_timing;
512 struct videomode *vm = &dsi->vm;
513
514 if (dsi->format == MIPI_DSI_FMT_RGB565)
515 dsi_tmp_buf_bpp = 2;
516 else
517 dsi_tmp_buf_bpp = 3;
518
519 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
520
521 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
522 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10;
523 else
524 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
525 dsi_tmp_buf_bpp - 10;
526
527 data_phy_cycles = timing->lpx + timing->da_hs_prepare +
528 timing->da_hs_zero + timing->da_hs_exit + 3;
529
530 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
531 delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 0 : 2;
532
533 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp;
534 horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte;
535 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;
536
537 if (horizontal_front_back_byte > data_phy_cycles_byte) {
538 horizontal_frontporch_byte -= data_phy_cycles_byte *
539 horizontal_frontporch_byte /
540 horizontal_front_back_byte;
541
542 horizontal_backporch_byte -= data_phy_cycles_byte *
543 horizontal_backporch_byte /
544 horizontal_front_back_byte;
545 } else {
546 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
547 }
548
549 if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
550 (dsi->lanes == 4)) {
551 horizontal_sync_active_byte =
552 roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
553 horizontal_frontporch_byte =
554 roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
555 horizontal_backporch_byte =
556 roundup(horizontal_backporch_byte, dsi->lanes) - 2;
557 horizontal_backporch_byte -=
558 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
559 }
560
561 writel(val: horizontal_sync_active_byte, addr: dsi->regs + DSI_HSA_WC);
562 writel(val: horizontal_backporch_byte, addr: dsi->regs + DSI_HBP_WC);
563 writel(val: horizontal_frontporch_byte, addr: dsi->regs + DSI_HFP_WC);
564}
565
566static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
567{
568 struct videomode *vm = &dsi->vm;
569
570 writel(val: vm->vsync_len, addr: dsi->regs + DSI_VSA_NL);
571 writel(val: vm->vback_porch, addr: dsi->regs + DSI_VBP_NL);
572 writel(val: vm->vfront_porch, addr: dsi->regs + DSI_VFP_NL);
573 writel(val: vm->vactive, addr: dsi->regs + DSI_VACT_NL);
574
575 if (dsi->driver_data->has_size_ctl)
576 writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) |
577 FIELD_PREP(DSI_WIDTH, vm->hactive),
578 addr: dsi->regs + DSI_SIZE_CON);
579
580 if (dsi->driver_data->support_per_frame_lp)
581 mtk_dsi_config_vdo_timing_per_frame_lp(dsi);
582 else
583 mtk_dsi_config_vdo_timing_per_line_lp(dsi);
584
585 mtk_dsi_ps_control(dsi, config_vact: false);
586}
587
588static void mtk_dsi_start(struct mtk_dsi *dsi)
589{
590 writel(val: 0, addr: dsi->regs + DSI_START);
591 writel(val: 1, addr: dsi->regs + DSI_START);
592}
593
594static void mtk_dsi_stop(struct mtk_dsi *dsi)
595{
596 writel(val: 0, addr: dsi->regs + DSI_START);
597}
598
599static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
600{
601 writel(CMD_MODE, addr: dsi->regs + DSI_MODE_CTRL);
602}
603
604static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
605{
606 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
607
608 writel(val: inten, addr: dsi->regs + DSI_INTEN);
609}
610
611static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
612{
613 dsi->irq_data |= irq_bit;
614}
615
616static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
617{
618 dsi->irq_data &= ~irq_bit;
619}
620
621static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
622 unsigned int timeout)
623{
624 s32 ret = 0;
625 unsigned long jiffies = msecs_to_jiffies(m: timeout);
626
627 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
628 dsi->irq_data & irq_flag,
629 jiffies);
630 if (ret == 0) {
631 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
632
633 mtk_dsi_enable(dsi);
634 mtk_dsi_reset_engine(dsi);
635 }
636
637 return ret;
638}
639
640static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
641{
642 struct mtk_dsi *dsi = dev_id;
643 u32 status, tmp;
644 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
645
646 status = readl(addr: dsi->regs + DSI_INTSTA) & flag;
647
648 if (status) {
649 do {
650 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
651 tmp = readl(addr: dsi->regs + DSI_INTSTA);
652 } while (tmp & DSI_BUSY);
653
654 mtk_dsi_mask(dsi, DSI_INTSTA, mask: status, data: 0);
655 mtk_dsi_irq_data_set(dsi, irq_bit: status);
656 wake_up_interruptible(&dsi->irq_wait_queue);
657 }
658
659 return IRQ_HANDLED;
660}
661
662static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
663{
664 mtk_dsi_irq_data_clear(dsi, irq_bit: irq_flag);
665 mtk_dsi_set_cmd_mode(dsi);
666
667 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, timeout: t)) {
668 DRM_ERROR("failed to switch cmd mode\n");
669 return -ETIME;
670 } else {
671 return 0;
672 }
673}
674
675static int mtk_dsi_poweron(struct mtk_dsi *dsi)
676{
677 struct device *dev = dsi->host.dev;
678 int ret;
679 u32 bit_per_pixel;
680
681 if (++dsi->refcount != 1)
682 return 0;
683
684 ret = mipi_dsi_pixel_format_to_bpp(fmt: dsi->format);
685 if (ret < 0) {
686 dev_err(dev, "Unknown MIPI DSI format %d\n", dsi->format);
687 return ret;
688 }
689 bit_per_pixel = ret;
690
691 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
692 dsi->lanes);
693
694 ret = clk_set_rate(clk: dsi->hs_clk, rate: dsi->data_rate);
695 if (ret < 0) {
696 dev_err(dev, "Failed to set data rate: %d\n", ret);
697 goto err_refcount;
698 }
699
700 phy_power_on(phy: dsi->phy);
701
702 ret = clk_prepare_enable(clk: dsi->engine_clk);
703 if (ret < 0) {
704 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
705 goto err_phy_power_off;
706 }
707
708 ret = clk_prepare_enable(clk: dsi->digital_clk);
709 if (ret < 0) {
710 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
711 goto err_disable_engine_clk;
712 }
713
714 mtk_dsi_enable(dsi);
715
716 if (dsi->driver_data->has_shadow_ctl)
717 writel(FORCE_COMMIT | BYPASS_SHADOW,
718 addr: dsi->regs + dsi->driver_data->reg_shadow_dbg_off);
719
720 mtk_dsi_reset_engine(dsi);
721 mtk_dsi_phy_timconfig(dsi);
722
723 mtk_dsi_ps_control(dsi, config_vact: true);
724 mtk_dsi_set_vm_cmd(dsi);
725 mtk_dsi_config_vdo_timing(dsi);
726 mtk_dsi_set_interrupt_enable(dsi);
727
728 return 0;
729err_disable_engine_clk:
730 clk_disable_unprepare(clk: dsi->engine_clk);
731err_phy_power_off:
732 phy_power_off(phy: dsi->phy);
733err_refcount:
734 dsi->refcount--;
735 return ret;
736}
737
738static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
739{
740 if (WARN_ON(dsi->refcount == 0))
741 return;
742
743 if (--dsi->refcount != 0)
744 return;
745
746 /*
747 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
748 * mtk_dsi_stop() should be called after mtk_crtc_atomic_disable(),
749 * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
750 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
751 * after dsi is fully set.
752 */
753 mtk_dsi_stop(dsi);
754
755 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, t: 500);
756 mtk_dsi_reset_engine(dsi);
757 mtk_dsi_lane0_ulp_mode_enter(dsi);
758 mtk_dsi_clk_ulp_mode_enter(dsi);
759 /* set the lane number as 0 to pull down mipi */
760 writel(val: 0, addr: dsi->regs + DSI_TXRX_CTRL);
761
762 mtk_dsi_disable(dsi);
763
764 clk_disable_unprepare(clk: dsi->engine_clk);
765 clk_disable_unprepare(clk: dsi->digital_clk);
766
767 phy_power_off(phy: dsi->phy);
768
769 dsi->lanes_ready = false;
770}
771
772static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
773{
774 if (!dsi->lanes_ready) {
775 dsi->lanes_ready = true;
776 mtk_dsi_rxtx_control(dsi);
777 usleep_range(min: 30, max: 100);
778 mtk_dsi_reset_dphy(dsi);
779 mtk_dsi_clk_ulp_mode_leave(dsi);
780 mtk_dsi_lane0_ulp_mode_leave(dsi);
781 mtk_dsi_clk_hs_mode(dsi, enter: 0);
782 usleep_range(min: 1000, max: 3000);
783 /* The reaction time after pulling up the mipi signal for dsi_rx */
784 }
785}
786
787static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
788{
789 if (dsi->enabled)
790 return;
791
792 mtk_dsi_lane_ready(dsi);
793 mtk_dsi_set_mode(dsi);
794 mtk_dsi_clk_hs_mode(dsi, enter: 1);
795
796 mtk_dsi_start(dsi);
797
798 dsi->enabled = true;
799}
800
801static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
802{
803 if (!dsi->enabled)
804 return;
805
806 dsi->enabled = false;
807}
808
809static int mtk_dsi_bridge_attach(struct drm_bridge *bridge,
810 struct drm_encoder *encoder,
811 enum drm_bridge_attach_flags flags)
812{
813 struct mtk_dsi *dsi = bridge_to_dsi(b: bridge);
814
815 /* Attach the panel or bridge to the dsi bridge */
816 return drm_bridge_attach(encoder, bridge: dsi->next_bridge,
817 previous: &dsi->bridge, flags);
818}
819
820static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge,
821 const struct drm_display_mode *mode,
822 const struct drm_display_mode *adjusted)
823{
824 struct mtk_dsi *dsi = bridge_to_dsi(b: bridge);
825
826 drm_display_mode_to_videomode(dmode: adjusted, vm: &dsi->vm);
827}
828
829static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
830 struct drm_atomic_state *state)
831{
832 struct mtk_dsi *dsi = bridge_to_dsi(b: bridge);
833
834 mtk_output_dsi_disable(dsi);
835}
836
837static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
838 struct drm_atomic_state *state)
839{
840 struct mtk_dsi *dsi = bridge_to_dsi(b: bridge);
841
842 if (dsi->refcount == 0)
843 return;
844
845 mtk_output_dsi_enable(dsi);
846}
847
848static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
849 struct drm_atomic_state *state)
850{
851 struct mtk_dsi *dsi = bridge_to_dsi(b: bridge);
852 int ret;
853
854 ret = mtk_dsi_poweron(dsi);
855 if (ret < 0)
856 DRM_ERROR("failed to power on dsi\n");
857}
858
859static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
860 struct drm_atomic_state *state)
861{
862 struct mtk_dsi *dsi = bridge_to_dsi(b: bridge);
863
864 mtk_dsi_poweroff(dsi);
865}
866
867static enum drm_mode_status
868mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge,
869 const struct drm_display_info *info,
870 const struct drm_display_mode *mode)
871{
872 struct mtk_dsi *dsi = bridge_to_dsi(b: bridge);
873 int bpp;
874
875 bpp = mipi_dsi_pixel_format_to_bpp(fmt: dsi->format);
876 if (bpp < 0)
877 return MODE_ERROR;
878
879 if (mode->clock * bpp / dsi->lanes > 1500000)
880 return MODE_CLOCK_HIGH;
881
882 return MODE_OK;
883}
884
885static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
886 .attach = mtk_dsi_bridge_attach,
887 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
888 .atomic_disable = mtk_dsi_bridge_atomic_disable,
889 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
890 .atomic_enable = mtk_dsi_bridge_atomic_enable,
891 .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
892 .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,
893 .atomic_reset = drm_atomic_helper_bridge_reset,
894 .mode_valid = mtk_dsi_bridge_mode_valid,
895 .mode_set = mtk_dsi_bridge_mode_set,
896};
897
898void mtk_dsi_ddp_start(struct device *dev)
899{
900 struct mtk_dsi *dsi = dev_get_drvdata(dev);
901
902 mtk_dsi_poweron(dsi);
903}
904
905void mtk_dsi_ddp_stop(struct device *dev)
906{
907 struct mtk_dsi *dsi = dev_get_drvdata(dev);
908
909 mtk_dsi_poweroff(dsi);
910}
911
912static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
913{
914 int ret;
915
916 ret = drm_simple_encoder_init(dev: drm, encoder: &dsi->encoder,
917 DRM_MODE_ENCODER_DSI);
918 if (ret) {
919 DRM_ERROR("Failed to encoder init to drm\n");
920 return ret;
921 }
922
923 ret = mtk_find_possible_crtcs(drm, dev: dsi->host.dev);
924 if (ret < 0)
925 goto err_cleanup_encoder;
926 dsi->encoder.possible_crtcs = ret;
927
928 ret = drm_bridge_attach(encoder: &dsi->encoder, bridge: &dsi->bridge, NULL,
929 flags: DRM_BRIDGE_ATTACH_NO_CONNECTOR);
930 if (ret)
931 goto err_cleanup_encoder;
932
933 dsi->connector = drm_bridge_connector_init(drm, encoder: &dsi->encoder);
934 if (IS_ERR(ptr: dsi->connector)) {
935 DRM_ERROR("Unable to create bridge connector\n");
936 ret = PTR_ERR(ptr: dsi->connector);
937 goto err_cleanup_encoder;
938 }
939 drm_connector_attach_encoder(connector: dsi->connector, encoder: &dsi->encoder);
940
941 return 0;
942
943err_cleanup_encoder:
944 drm_encoder_cleanup(encoder: &dsi->encoder);
945 return ret;
946}
947
948unsigned int mtk_dsi_encoder_index(struct device *dev)
949{
950 struct mtk_dsi *dsi = dev_get_drvdata(dev);
951 unsigned int encoder_index = drm_encoder_index(encoder: &dsi->encoder);
952
953 dev_dbg(dev, "encoder index:%d\n", encoder_index);
954 return encoder_index;
955}
956
957static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
958{
959 int ret;
960 struct drm_device *drm = data;
961 struct mtk_dsi *dsi = dev_get_drvdata(dev);
962
963 ret = mtk_dsi_encoder_init(drm, dsi);
964 if (ret)
965 return ret;
966
967 return device_reset_optional(dev);
968}
969
970static void mtk_dsi_unbind(struct device *dev, struct device *master,
971 void *data)
972{
973 struct mtk_dsi *dsi = dev_get_drvdata(dev);
974
975 drm_encoder_cleanup(encoder: &dsi->encoder);
976}
977
978static const struct component_ops mtk_dsi_component_ops = {
979 .bind = mtk_dsi_bind,
980 .unbind = mtk_dsi_unbind,
981};
982
983static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
984 struct mipi_dsi_device *device)
985{
986 struct mtk_dsi *dsi = host_to_dsi(h: host);
987 struct device *dev = host->dev;
988 int ret;
989
990 dsi->lanes = device->lanes;
991 dsi->format = device->format;
992 dsi->mode_flags = device->mode_flags;
993 dsi->next_bridge = devm_drm_of_get_bridge(dev, node: dev->of_node, port: 1, endpoint: 0);
994 if (IS_ERR(ptr: dsi->next_bridge)) {
995 ret = PTR_ERR(ptr: dsi->next_bridge);
996 if (ret == -EPROBE_DEFER)
997 return ret;
998
999 /* Old devicetree has only one endpoint */
1000 dsi->next_bridge = devm_drm_of_get_bridge(dev, node: dev->of_node, port: 0, endpoint: 0);
1001 if (IS_ERR(ptr: dsi->next_bridge))
1002 return PTR_ERR(ptr: dsi->next_bridge);
1003 }
1004
1005 drm_bridge_add(bridge: &dsi->bridge);
1006
1007 ret = component_add(host->dev, &mtk_dsi_component_ops);
1008 if (ret) {
1009 DRM_ERROR("failed to add dsi_host component: %d\n", ret);
1010 drm_bridge_remove(bridge: &dsi->bridge);
1011 return ret;
1012 }
1013
1014 return 0;
1015}
1016
1017static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
1018 struct mipi_dsi_device *device)
1019{
1020 struct mtk_dsi *dsi = host_to_dsi(h: host);
1021
1022 component_del(host->dev, &mtk_dsi_component_ops);
1023 drm_bridge_remove(bridge: &dsi->bridge);
1024 return 0;
1025}
1026
1027static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
1028{
1029 int ret;
1030 u32 val;
1031
1032 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
1033 4, 2000000);
1034 if (ret) {
1035 DRM_WARN("polling dsi wait not busy timeout!\n");
1036
1037 mtk_dsi_enable(dsi);
1038 mtk_dsi_reset_engine(dsi);
1039 }
1040}
1041
1042static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
1043{
1044 switch (type) {
1045 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1046 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1047 return 1;
1048 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1049 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1050 return 2;
1051 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1052 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1053 return read_data[1] + read_data[2] * 16;
1054 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1055 DRM_INFO("type is 0x02, try again\n");
1056 break;
1057 default:
1058 DRM_INFO("type(0x%x) not recognized\n", type);
1059 break;
1060 }
1061
1062 return 0;
1063}
1064
1065static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
1066{
1067 const char *tx_buf = msg->tx_buf;
1068 u8 config, cmdq_size, cmdq_off, type = msg->type;
1069 u32 reg_val, cmdq_mask, i;
1070 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
1071
1072 if (MTK_DSI_HOST_IS_READ(type))
1073 config = BTA;
1074 else
1075 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
1076
1077 if (msg->tx_len > 2) {
1078 cmdq_size = 1 + (msg->tx_len + 3) / 4;
1079 cmdq_off = 4;
1080 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
1081 reg_val = (msg->tx_len << 16) | (type << 8) | config;
1082 } else {
1083 cmdq_size = 1;
1084 cmdq_off = 2;
1085 cmdq_mask = CONFIG | DATA_ID;
1086 reg_val = (type << 8) | config;
1087 }
1088
1089 for (i = 0; i < msg->tx_len; i++)
1090 mtk_dsi_mask(dsi, offset: (reg_cmdq_off + cmdq_off + i) & (~0x3U),
1091 mask: (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
1092 data: tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
1093
1094 mtk_dsi_mask(dsi, offset: reg_cmdq_off, mask: cmdq_mask, data: reg_val);
1095 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, data: cmdq_size);
1096 if (dsi->driver_data->cmdq_long_packet_ctl) {
1097 /* Disable setting cmdq_size automatically for long packets */
1098 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);
1099 }
1100}
1101
1102static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
1103 const struct mipi_dsi_msg *msg, u8 flag)
1104{
1105 mtk_dsi_wait_for_idle(dsi);
1106 mtk_dsi_irq_data_clear(dsi, irq_bit: flag);
1107 mtk_dsi_cmdq(dsi, msg);
1108 mtk_dsi_start(dsi);
1109
1110 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag: flag, timeout: 2000))
1111 return -ETIME;
1112 else
1113 return 0;
1114}
1115
1116static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
1117 const struct mipi_dsi_msg *msg)
1118{
1119 struct mtk_dsi *dsi = host_to_dsi(h: host);
1120 ssize_t recv_cnt;
1121 u8 read_data[16];
1122 void *src_addr;
1123 u8 irq_flag = CMD_DONE_INT_FLAG;
1124 u32 dsi_mode;
1125 int ret, i;
1126
1127 dsi_mode = readl(addr: dsi->regs + DSI_MODE_CTRL);
1128 if (dsi_mode & MODE) {
1129 mtk_dsi_stop(dsi);
1130 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, t: 500);
1131 if (ret)
1132 goto restore_dsi_mode;
1133 }
1134
1135 if (MTK_DSI_HOST_IS_READ(msg->type))
1136 irq_flag |= LPRX_RD_RDY_INT_FLAG;
1137
1138 mtk_dsi_lane_ready(dsi);
1139
1140 ret = mtk_dsi_host_send_cmd(dsi, msg, flag: irq_flag);
1141 if (ret)
1142 goto restore_dsi_mode;
1143
1144 if (!MTK_DSI_HOST_IS_READ(msg->type)) {
1145 recv_cnt = 0;
1146 goto restore_dsi_mode;
1147 }
1148
1149 if (!msg->rx_buf) {
1150 DRM_ERROR("dsi receive buffer size may be NULL\n");
1151 ret = -EINVAL;
1152 goto restore_dsi_mode;
1153 }
1154
1155 for (i = 0; i < 16; i++)
1156 *(read_data + i) = readb(addr: dsi->regs + DSI_RX_DATA0 + i);
1157
1158 recv_cnt = mtk_dsi_recv_cnt(type: read_data[0], read_data);
1159
1160 if (recv_cnt > 2)
1161 src_addr = &read_data[4];
1162 else
1163 src_addr = &read_data[1];
1164
1165 if (recv_cnt > 10)
1166 recv_cnt = 10;
1167
1168 if (recv_cnt > msg->rx_len)
1169 recv_cnt = msg->rx_len;
1170
1171 if (recv_cnt)
1172 memcpy(msg->rx_buf, src_addr, recv_cnt);
1173
1174 DRM_INFO("dsi get %zd byte data from the panel address(0x%x)\n",
1175 recv_cnt, *((u8 *)(msg->tx_buf)));
1176
1177restore_dsi_mode:
1178 if (dsi_mode & MODE) {
1179 mtk_dsi_set_mode(dsi);
1180 mtk_dsi_start(dsi);
1181 }
1182
1183 return ret < 0 ? ret : recv_cnt;
1184}
1185
1186static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1187 .attach = mtk_dsi_host_attach,
1188 .detach = mtk_dsi_host_detach,
1189 .transfer = mtk_dsi_host_transfer,
1190};
1191
1192static int mtk_dsi_probe(struct platform_device *pdev)
1193{
1194 struct mtk_dsi *dsi;
1195 struct device *dev = &pdev->dev;
1196 int irq_num;
1197 int ret;
1198
1199 dsi = devm_drm_bridge_alloc(dev, struct mtk_dsi, bridge,
1200 &mtk_dsi_bridge_funcs);
1201 if (IS_ERR(ptr: dsi))
1202 return PTR_ERR(ptr: dsi);
1203
1204 dsi->driver_data = of_device_get_match_data(dev);
1205
1206 dsi->engine_clk = devm_clk_get(dev, id: "engine");
1207 if (IS_ERR(ptr: dsi->engine_clk))
1208 return dev_err_probe(dev, err: PTR_ERR(ptr: dsi->engine_clk),
1209 fmt: "Failed to get engine clock\n");
1210
1211
1212 dsi->digital_clk = devm_clk_get(dev, id: "digital");
1213 if (IS_ERR(ptr: dsi->digital_clk))
1214 return dev_err_probe(dev, err: PTR_ERR(ptr: dsi->digital_clk),
1215 fmt: "Failed to get digital clock\n");
1216
1217 dsi->hs_clk = devm_clk_get(dev, id: "hs");
1218 if (IS_ERR(ptr: dsi->hs_clk))
1219 return dev_err_probe(dev, err: PTR_ERR(ptr: dsi->hs_clk), fmt: "Failed to get hs clock\n");
1220
1221 dsi->regs = devm_platform_ioremap_resource(pdev, index: 0);
1222 if (IS_ERR(ptr: dsi->regs))
1223 return dev_err_probe(dev, err: PTR_ERR(ptr: dsi->regs), fmt: "Failed to ioremap memory\n");
1224
1225 dsi->phy = devm_phy_get(dev, string: "dphy");
1226 if (IS_ERR(ptr: dsi->phy))
1227 return dev_err_probe(dev, err: PTR_ERR(ptr: dsi->phy), fmt: "Failed to get MIPI-DPHY\n");
1228
1229 irq_num = platform_get_irq(pdev, 0);
1230 if (irq_num < 0)
1231 return irq_num;
1232
1233 dsi->host.ops = &mtk_dsi_ops;
1234 dsi->host.dev = dev;
1235 ret = mipi_dsi_host_register(host: &dsi->host);
1236 if (ret < 0)
1237 return dev_err_probe(dev, err: ret, fmt: "Failed to register DSI host\n");
1238
1239 ret = devm_request_irq(dev: &pdev->dev, irq: irq_num, handler: mtk_dsi_irq,
1240 IRQF_TRIGGER_NONE, devname: dev_name(dev: &pdev->dev), dev_id: dsi);
1241 if (ret) {
1242 mipi_dsi_host_unregister(host: &dsi->host);
1243 return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "Failed to request DSI irq\n");
1244 }
1245
1246 init_waitqueue_head(&dsi->irq_wait_queue);
1247
1248 platform_set_drvdata(pdev, data: dsi);
1249
1250 dsi->bridge.of_node = dev->of_node;
1251 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1252
1253 return 0;
1254}
1255
1256static void mtk_dsi_remove(struct platform_device *pdev)
1257{
1258 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1259
1260 mtk_output_dsi_disable(dsi);
1261 mipi_dsi_host_unregister(host: &dsi->host);
1262}
1263
1264static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
1265 .reg_cmdq_off = 0x200,
1266 .reg_vm_cmd_off = 0x130,
1267 .reg_shadow_dbg_off = 0x190
1268};
1269
1270static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
1271 .reg_cmdq_off = 0x180,
1272 .reg_vm_cmd_off = 0x130,
1273 .reg_shadow_dbg_off = 0x190
1274};
1275
1276static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
1277 .reg_cmdq_off = 0x200,
1278 .reg_vm_cmd_off = 0x130,
1279 .reg_shadow_dbg_off = 0x190,
1280 .has_shadow_ctl = true,
1281 .has_size_ctl = true,
1282};
1283
1284static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
1285 .reg_cmdq_off = 0xd00,
1286 .reg_vm_cmd_off = 0x200,
1287 .reg_shadow_dbg_off = 0xc00,
1288 .has_shadow_ctl = true,
1289 .has_size_ctl = true,
1290};
1291
1292static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
1293 .reg_cmdq_off = 0xd00,
1294 .reg_vm_cmd_off = 0x200,
1295 .reg_shadow_dbg_off = 0xc00,
1296 .has_shadow_ctl = true,
1297 .has_size_ctl = true,
1298 .cmdq_long_packet_ctl = true,
1299 .support_per_frame_lp = true,
1300};
1301
1302static const struct of_device_id mtk_dsi_of_match[] = {
1303 { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data },
1304 { .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data },
1305 { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data },
1306 { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data },
1307 { .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data },
1308 { /* sentinel */ }
1309};
1310MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
1311
1312struct platform_driver mtk_dsi_driver = {
1313 .probe = mtk_dsi_probe,
1314 .remove = mtk_dsi_remove,
1315 .driver = {
1316 .name = "mtk-dsi",
1317 .of_match_table = mtk_dsi_of_match,
1318 },
1319};
1320

source code of linux/drivers/gpu/drm/mediatek/mtk_dsi.c