| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2019-2022 MediaTek Inc. |
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| 4 | * Copyright (c) 2022 BayLibre |
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| 5 | */ |
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| 6 | #ifndef _MTK_DP_REG_H_ |
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| 7 | #define _MTK_DP_REG_H_ |
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| 8 | |
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| 9 | #define SEC_OFFSET 0x4000 |
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| 10 | |
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| 11 | #define MTK_DP_HPD_DISCONNECT BIT(1) |
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| 12 | #define MTK_DP_HPD_CONNECT BIT(2) |
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| 13 | #define MTK_DP_HPD_INTERRUPT BIT(3) |
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| 14 | |
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| 15 | /* offset: 0x0 */ |
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| 16 | #define DP_PHY_GLB_BIAS_GEN_00 0x0 |
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| 17 | #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(20, 16) |
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| 18 | #define DP_PHY_GLB_DPAUX_TX 0x8 |
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| 19 | #define RG_CKM_PT0_CKTX_IMPSEL GENMASK(23, 20) |
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| 20 | #define MTK_DP_0034 0x34 |
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| 21 | #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15) |
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| 22 | #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14) |
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| 23 | #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13) |
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| 24 | #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12) |
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| 25 | #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11) |
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| 26 | #define DA_CKM_CKTX0_EN_FORCE_EN BIT(10) |
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| 27 | #define DA_CKM_XTAL_CK_FORCE_VAL BIT(9) |
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| 28 | #define DA_CKM_XTAL_CK_FORCE_EN BIT(8) |
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| 29 | #define DA_CKM_BIAS_LPF_EN_FORCE_VAL BIT(7) |
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| 30 | #define DA_CKM_BIAS_LPF_EN_FORCE_EN BIT(6) |
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| 31 | #define DA_CKM_BIAS_EN_FORCE_VAL BIT(5) |
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| 32 | #define DA_CKM_BIAS_EN_FORCE_EN BIT(4) |
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| 33 | #define DA_XTP_GLB_AVD10_ON_FORCE_VAL BIT(3) |
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| 34 | #define DA_XTP_GLB_AVD10_ON_FORCE BIT(2) |
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| 35 | #define DA_XTP_GLB_LDO_EN_FORCE_VAL BIT(1) |
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| 36 | #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0) |
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| 37 | #define DP_PHY_LANE_TX_0 0x104 |
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| 38 | #define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12) |
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| 39 | #define RG_XTP_LN0_TX_IMPSEL_NMOS GENMASK(19, 16) |
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| 40 | #define DP_PHY_LANE_TX_1 0x204 |
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| 41 | #define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12) |
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| 42 | #define RG_XTP_LN1_TX_IMPSEL_NMOS GENMASK(19, 16) |
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| 43 | #define DP_PHY_LANE_TX_2 0x304 |
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| 44 | #define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12) |
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| 45 | #define RG_XTP_LN2_TX_IMPSEL_NMOS GENMASK(19, 16) |
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| 46 | #define DP_PHY_LANE_TX_3 0x404 |
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| 47 | #define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12) |
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| 48 | #define RG_XTP_LN3_TX_IMPSEL_NMOS GENMASK(19, 16) |
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| 49 | #define MTK_DP_1040 0x1040 |
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| 50 | #define RG_DPAUX_RX_VALID_DEGLITCH_EN BIT(2) |
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| 51 | #define RG_XTP_GLB_CKDET_EN BIT(1) |
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| 52 | #define RG_DPAUX_RX_EN BIT(0) |
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| 53 | |
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| 54 | /* offset: TOP_OFFSET (0x2000) */ |
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| 55 | #define MTK_DP_TOP_PWR_STATE 0x2000 |
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| 56 | #define DP_PWR_STATE_MASK GENMASK(1, 0) |
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| 57 | #define DP_PWR_STATE_BANDGAP BIT(0) |
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| 58 | #define DP_PWR_STATE_BANDGAP_TPLL BIT(1) |
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| 59 | #define DP_PWR_STATE_BANDGAP_TPLL_LANE GENMASK(1, 0) |
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| 60 | #define MTK_DP_TOP_SWING_EMP 0x2004 |
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| 61 | #define DP_TX0_VOLT_SWING_MASK GENMASK(1, 0) |
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| 62 | #define DP_TX0_VOLT_SWING_SHIFT 0 |
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| 63 | #define DP_TX0_PRE_EMPH_MASK GENMASK(3, 2) |
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| 64 | #define DP_TX0_PRE_EMPH_SHIFT 2 |
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| 65 | #define DP_TX1_VOLT_SWING_MASK GENMASK(9, 8) |
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| 66 | #define DP_TX1_VOLT_SWING_SHIFT 8 |
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| 67 | #define DP_TX1_PRE_EMPH_MASK GENMASK(11, 10) |
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| 68 | #define DP_TX2_VOLT_SWING_MASK GENMASK(17, 16) |
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| 69 | #define DP_TX2_PRE_EMPH_MASK GENMASK(19, 18) |
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| 70 | #define DP_TX3_VOLT_SWING_MASK GENMASK(25, 24) |
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| 71 | #define DP_TX3_PRE_EMPH_MASK GENMASK(27, 26) |
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| 72 | #define MTK_DP_TOP_RESET_AND_PROBE 0x2020 |
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| 73 | #define SW_RST_B_PHYD BIT(4) |
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| 74 | #define MTK_DP_TOP_IRQ_MASK 0x202c |
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| 75 | #define IRQ_MASK_AUX_TOP_IRQ BIT(2) |
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| 76 | #define MTK_DP_TOP_MEM_PD 0x2038 |
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| 77 | #define MEM_ISO_EN BIT(0) |
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| 78 | #define FUSE_SEL BIT(2) |
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| 79 | |
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| 80 | /* offset: ENC0_OFFSET (0x3000) */ |
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| 81 | #define MTK_DP_ENC0_P0_3000 0x3000 |
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| 82 | #define LANE_NUM_DP_ENC0_P0_MASK GENMASK(1, 0) |
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| 83 | #define VIDEO_MUTE_SW_DP_ENC0_P0 BIT(2) |
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| 84 | #define VIDEO_MUTE_SEL_DP_ENC0_P0 BIT(3) |
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| 85 | #define ENHANCED_FRAME_EN_DP_ENC0_P0 BIT(4) |
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| 86 | #define MTK_DP_ENC0_P0_3004 0x3004 |
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| 87 | #define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK BIT(8) |
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| 88 | #define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0 BIT(9) |
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| 89 | #define SDP_RESET_SW_DP_ENC0_P0 BIT(13) |
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| 90 | #define MTK_DP_ENC0_P0_3010 0x3010 |
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| 91 | #define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0) |
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| 92 | #define MTK_DP_ENC0_P0_3014 0x3014 |
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| 93 | #define VTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0) |
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| 94 | #define MTK_DP_ENC0_P0_3018 0x3018 |
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| 95 | #define HSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0) |
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| 96 | #define MTK_DP_ENC0_P0_301C 0x301c |
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| 97 | #define VSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0) |
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| 98 | #define MTK_DP_ENC0_P0_3020 0x3020 |
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| 99 | #define HWIDTH_SW_DP_ENC0_P0_MASK GENMASK(15, 0) |
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| 100 | #define MTK_DP_ENC0_P0_3024 0x3024 |
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| 101 | #define VHEIGHT_SW_DP_ENC0_P0_MASK GENMASK(15, 0) |
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| 102 | #define MTK_DP_ENC0_P0_3028 0x3028 |
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| 103 | #define HSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0) |
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| 104 | #define HSP_SW_DP_ENC0_P0_MASK BIT(15) |
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| 105 | #define MTK_DP_ENC0_P0_302C 0x302c |
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| 106 | #define VSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0) |
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| 107 | #define VSP_SW_DP_ENC0_P0_MASK BIT(15) |
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| 108 | #define MTK_DP_ENC0_P0_3030 0x3030 |
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| 109 | #define HTOTAL_SEL_DP_ENC0_P0 BIT(0) |
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| 110 | #define VTOTAL_SEL_DP_ENC0_P0 BIT(1) |
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| 111 | #define HSTART_SEL_DP_ENC0_P0 BIT(2) |
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| 112 | #define VSTART_SEL_DP_ENC0_P0 BIT(3) |
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| 113 | #define HWIDTH_SEL_DP_ENC0_P0 BIT(4) |
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| 114 | #define VHEIGHT_SEL_DP_ENC0_P0 BIT(5) |
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| 115 | #define HSP_SEL_DP_ENC0_P0 BIT(6) |
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| 116 | #define HSW_SEL_DP_ENC0_P0 BIT(7) |
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| 117 | #define VSP_SEL_DP_ENC0_P0 BIT(8) |
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| 118 | #define VSW_SEL_DP_ENC0_P0 BIT(9) |
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| 119 | #define VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0 BIT(11) |
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| 120 | #define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0 BIT(12) |
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| 121 | #define MTK_DP_ENC0_P0_3034 0x3034 |
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| 122 | #define MTK_DP_ENC0_P0_3038 0x3038 |
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| 123 | #define VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK BIT(11) |
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| 124 | #define MTK_DP_ENC0_P0_303C 0x303c |
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| 125 | #define SRAM_START_READ_THRD_DP_ENC0_P0_MASK GENMASK(5, 0) |
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| 126 | #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK GENMASK(10, 8) |
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| 127 | #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT (0 << 8) |
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| 128 | #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT (1 << 8) |
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| 129 | #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_10BIT (2 << 8) |
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| 130 | #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT (3 << 8) |
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| 131 | #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT (4 << 8) |
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| 132 | #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK GENMASK(14, 12) |
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| 133 | #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB (0 << 12) |
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| 134 | #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422 (1 << 12) |
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| 135 | #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR420 (2 << 12) |
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| 136 | #define VIDEO_MN_GEN_EN_DP_ENC0_P0 BIT(15) |
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| 137 | #define MTK_DP_ENC0_P0_3040 0x3040 |
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| 138 | #define SDP_DOWN_CNT_DP_ENC0_P0_VAL 0x20 |
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| 139 | #define SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK GENMASK(11, 0) |
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| 140 | #define MTK_DP_ENC0_P0_304C 0x304c |
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| 141 | #define VBID_VIDEO_MUTE_DP_ENC0_P0_MASK BIT(2) |
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| 142 | #define SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK BIT(8) |
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| 143 | #define MTK_DP_ENC0_P0_3064 0x3064 |
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| 144 | #define HDE_NUM_LAST_DP_ENC0_P0_MASK GENMASK(15, 0) |
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| 145 | #define MTK_DP_ENC0_P0_3088 0x3088 |
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| 146 | #define AU_EN_DP_ENC0_P0 BIT(6) |
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| 147 | #define AUDIO_8CH_EN_DP_ENC0_P0_MASK BIT(7) |
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| 148 | #define AUDIO_8CH_SEL_DP_ENC0_P0_MASK BIT(8) |
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| 149 | #define AUDIO_2CH_EN_DP_ENC0_P0_MASK BIT(14) |
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| 150 | #define AUDIO_2CH_SEL_DP_ENC0_P0_MASK BIT(15) |
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| 151 | #define MTK_DP_ENC0_P0_308C 0x308c |
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| 152 | #define CH_STATUS_0_DP_ENC0_P0_MASK GENMASK(15, 0) |
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| 153 | #define MTK_DP_ENC0_P0_3090 0x3090 |
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| 154 | #define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0) |
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| 155 | #define MTK_DP_ENC0_P0_3094 0x3094 |
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| 156 | #define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0) |
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| 157 | #define MTK_DP_ENC0_P0_30A4 0x30a4 |
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| 158 | #define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0) |
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| 159 | #define MTK_DP_ENC0_P0_30A8 0x30a8 |
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| 160 | #define MTK_DP_ENC0_P0_30BC 0x30bc |
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| 161 | #define ISRC_CONT_DP_ENC0_P0 BIT(0) |
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| 162 | #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8) |
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| 163 | #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8) |
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| 164 | #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8) |
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| 165 | #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8) |
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| 166 | #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8) |
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| 167 | #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8) |
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| 168 | #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8) |
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| 169 | #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8) |
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| 170 | #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8) |
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| 171 | #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8) |
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| 172 | #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (4 << 8) |
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| 173 | #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (5 << 8) |
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| 174 | #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8) |
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| 175 | #define MTK_DP_ENC0_P0_30D8 0x30d8 |
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| 176 | #define MTK_DP_ENC0_P0_312C 0x312c |
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| 177 | #define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0) |
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| 178 | #define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8) |
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| 179 | #define MTK_DP_ENC0_P0_3154 0x3154 |
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| 180 | #define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0) |
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| 181 | #define MTK_DP_ENC0_P0_3158 0x3158 |
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| 182 | #define PGEN_HSYNC_RISING_DP_ENC0_P0_MASK GENMASK(13, 0) |
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| 183 | #define MTK_DP_ENC0_P0_315C 0x315c |
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| 184 | #define PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0) |
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| 185 | #define MTK_DP_ENC0_P0_3160 0x3160 |
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| 186 | #define PGEN_HFDE_START_DP_ENC0_P0_MASK GENMASK(13, 0) |
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| 187 | #define MTK_DP_ENC0_P0_3164 0x3164 |
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| 188 | #define PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0) |
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| 189 | #define MTK_DP_ENC0_P0_3168 0x3168 |
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| 190 | #define PGEN_VTOTAL_DP_ENC0_P0_MASK GENMASK(12, 0) |
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| 191 | #define MTK_DP_ENC0_P0_316C 0x316c |
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| 192 | #define PGEN_VSYNC_RISING_DP_ENC0_P0_MASK GENMASK(12, 0) |
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| 193 | #define MTK_DP_ENC0_P0_3170 0x3170 |
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| 194 | #define PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0) |
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| 195 | #define MTK_DP_ENC0_P0_3174 0x3174 |
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| 196 | #define PGEN_VFDE_START_DP_ENC0_P0_MASK GENMASK(12, 0) |
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| 197 | #define MTK_DP_ENC0_P0_3178 0x3178 |
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| 198 | #define PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0) |
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| 199 | #define MTK_DP_ENC0_P0_31B0 0x31b0 |
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| 200 | #define PGEN_PATTERN_SEL_VAL 4 |
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| 201 | #define PGEN_PATTERN_SEL_MASK GENMASK(6, 4) |
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| 202 | #define MTK_DP_ENC0_P0_31EC 0x31ec |
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| 203 | #define AUDIO_CH_SRC_SEL_DP_ENC0_P0 BIT(4) |
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| 204 | #define ISRC1_HB3_DP_ENC0_P0_MASK GENMASK(15, 8) |
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| 205 | |
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| 206 | /* offset: ENC1_OFFSET (0x3200) */ |
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| 207 | #define MTK_DP_ENC1_P0_3200 0x3200 |
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| 208 | #define MTK_DP_ENC1_P0_3280 0x3280 |
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| 209 | #define SDP_PACKET_TYPE_DP_ENC1_P0_MASK GENMASK(4, 0) |
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| 210 | #define SDP_PACKET_W_DP_ENC1_P0 BIT(5) |
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| 211 | #define SDP_PACKET_W_DP_ENC1_P0_MASK BIT(5) |
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| 212 | #define MTK_DP_ENC1_P0_3300 0x3300 |
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| 213 | #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_VAL 2 |
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| 214 | #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK GENMASK(9, 8) |
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| 215 | #define MTK_DP_ENC1_P0_3304 0x3304 |
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| 216 | #define AU_PRTY_REGEN_DP_ENC1_P0_MASK BIT(8) |
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| 217 | #define AU_CH_STS_REGEN_DP_ENC1_P0_MASK BIT(9) |
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| 218 | #define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK BIT(12) |
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| 219 | #define MTK_DP_ENC1_P0_3324 0x3324 |
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| 220 | #define AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK GENMASK(9, 8) |
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| 221 | #define AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX 0 |
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| 222 | #define MTK_DP_ENC1_P0_3364 0x3364 |
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| 223 | #define SDP_DOWN_CNT_IN_HBLANK_DP_ENC1_P0_VAL 0x20 |
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| 224 | #define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK GENMASK(11, 0) |
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| 225 | #define FIFO_READ_START_POINT_DP_ENC1_P0_VAL 4 |
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| 226 | #define FIFO_READ_START_POINT_DP_ENC1_P0_MASK GENMASK(15, 12) |
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| 227 | #define MTK_DP_ENC1_P0_3368 0x3368 |
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| 228 | #define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 BIT(0) |
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| 229 | #define VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 BIT(4) |
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| 230 | #define SDP_DP13_EN_DP_ENC1_P0 BIT(8) |
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| 231 | #define BS2BS_MODE_DP_ENC1_P0 BIT(12) |
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| 232 | #define BS2BS_MODE_DP_ENC1_P0_MASK GENMASK(13, 12) |
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| 233 | #define BS2BS_MODE_DP_ENC1_P0_VAL 1 |
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| 234 | #define DP_ENC1_P0_3368_VAL (VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 | \ |
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| 235 | VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 | \ |
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| 236 | SDP_DP13_EN_DP_ENC1_P0 | \ |
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| 237 | BS2BS_MODE_DP_ENC1_P0) |
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| 238 | |
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| 239 | #define MTK_DP_ENC1_P0_3374 0x3374 |
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| 240 | #define SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASK BIT(12) |
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| 241 | #define SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK GENMASK(11, 0) |
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| 242 | |
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| 243 | #define MTK_DP_ENC1_P0_33F4 0x33f4 |
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| 244 | #define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN BIT(0) |
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| 245 | #define DP_ENC_DUMMY_RW_1 BIT(9) |
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| 246 | |
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| 247 | /* offset: TRANS_OFFSET (0x3400) */ |
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| 248 | #define MTK_DP_TRANS_P0_3400 0x3400 |
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| 249 | #define PATTERN1_EN_DP_TRANS_P0_MASK BIT(12) |
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| 250 | #define PATTERN2_EN_DP_TRANS_P0_MASK BIT(13) |
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| 251 | #define PATTERN3_EN_DP_TRANS_P0_MASK BIT(14) |
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| 252 | #define PATTERN4_EN_DP_TRANS_P0_MASK BIT(15) |
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| 253 | #define MTK_DP_TRANS_P0_3404 0x3404 |
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| 254 | #define DP_SCR_EN_DP_TRANS_P0_MASK BIT(0) |
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| 255 | #define MTK_DP_TRANS_P0_340C 0x340c |
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| 256 | #define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0 BIT(13) |
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| 257 | #define MTK_DP_TRANS_P0_3410 0x3410 |
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| 258 | #define HPD_DEB_THD_DP_TRANS_P0_MASK GENMASK(3, 0) |
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| 259 | #define HPD_INT_THD_DP_TRANS_P0_MASK GENMASK(7, 4) |
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| 260 | #define HPD_INT_THD_DP_TRANS_P0_LOWER_500US (2 << 4) |
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| 261 | #define HPD_INT_THD_DP_TRANS_P0_UPPER_1100US (2 << 6) |
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| 262 | #define HPD_DISC_THD_DP_TRANS_P0_MASK GENMASK(11, 8) |
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| 263 | #define HPD_CONN_THD_DP_TRANS_P0_MASK GENMASK(15, 12) |
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| 264 | #define MTK_DP_TRANS_P0_3414 0x3414 |
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| 265 | #define HPD_DB_DP_TRANS_P0_MASK BIT(2) |
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| 266 | #define MTK_DP_TRANS_P0_3418 0x3418 |
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| 267 | #define IRQ_CLR_DP_TRANS_P0_MASK GENMASK(3, 0) |
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| 268 | #define IRQ_MASK_DP_TRANS_P0_MASK GENMASK(7, 4) |
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| 269 | #define IRQ_MASK_DP_TRANS_P0_DISC_IRQ (BIT(1) << 4) |
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| 270 | #define IRQ_MASK_DP_TRANS_P0_CONN_IRQ (BIT(2) << 4) |
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| 271 | #define IRQ_MASK_DP_TRANS_P0_INT_IRQ (BIT(3) << 4) |
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| 272 | #define IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 12) |
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| 273 | #define MTK_DP_TRANS_P0_342C 0x342c |
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| 274 | #define XTAL_FREQ_DP_TRANS_P0_DEFAULT (BIT(0) | BIT(3) | BIT(5) | BIT(6)) |
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| 275 | #define XTAL_FREQ_DP_TRANS_P0_MASK GENMASK(7, 0) |
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| 276 | #define MTK_DP_TRANS_P0_3430 0x3430 |
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| 277 | #define HPD_INT_THD_ECO_DP_TRANS_P0_MASK GENMASK(1, 0) |
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| 278 | #define HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT BIT(1) |
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| 279 | #define MTK_DP_TRANS_P0_34A4 0x34a4 |
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| 280 | #define LANE_NUM_DP_TRANS_P0_MASK GENMASK(3, 2) |
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| 281 | #define MTK_DP_TRANS_P0_3540 0x3540 |
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| 282 | #define FEC_EN_DP_TRANS_P0_MASK BIT(0) |
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| 283 | #define FEC_CLOCK_EN_MODE_DP_TRANS_P0 BIT(3) |
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| 284 | #define MTK_DP_TRANS_P0_3580 0x3580 |
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| 285 | #define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK BIT(8) |
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| 286 | #define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK BIT(9) |
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| 287 | #define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK BIT(10) |
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| 288 | #define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK BIT(11) |
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| 289 | #define MTK_DP_TRANS_P0_35C8 0x35c8 |
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| 290 | #define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0) |
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| 291 | #define SW_IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0) |
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| 292 | #define MTK_DP_TRANS_P0_35D0 0x35d0 |
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| 293 | #define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0) |
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| 294 | #define MTK_DP_TRANS_P0_35F0 0x35f0 |
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| 295 | #define DP_TRANS_DUMMY_RW_0 BIT(3) |
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| 296 | #define DP_TRANS_DUMMY_RW_0_MASK GENMASK(3, 2) |
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| 297 | |
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| 298 | /* offset: AUX_OFFSET (0x3600) */ |
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| 299 | #define MTK_DP_AUX_P0_360C 0x360c |
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| 300 | #define AUX_TIMEOUT_THR_AUX_TX_P0_MASK GENMASK(12, 0) |
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| 301 | #define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595 |
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| 302 | #define MTK_DP_AUX_P0_3614 0x3614 |
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| 303 | #define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0) |
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| 304 | #define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13 |
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| 305 | #define MTK_DP_AUX_P0_3618 0x3618 |
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| 306 | #define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9) |
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| 307 | #define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0) |
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| 308 | #define MTK_DP_AUX_P0_3620 0x3620 |
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| 309 | #define AUX_RD_MODE_AUX_TX_P0_MASK BIT(9) |
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| 310 | #define AUX_RX_FIFO_READ_PULSE_TX_P0 BIT(8) |
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| 311 | #define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK GENMASK(7, 0) |
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| 312 | #define MTK_DP_AUX_P0_3624 0x3624 |
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| 313 | #define AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0) |
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| 314 | #define MTK_DP_AUX_P0_3628 0x3628 |
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| 315 | #define AUX_RX_PHY_STATE_AUX_TX_P0_MASK GENMASK(9, 0) |
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| 316 | #define AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE BIT(0) |
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| 317 | #define MTK_DP_AUX_P0_362C 0x362c |
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| 318 | #define AUX_NO_LENGTH_AUX_TX_P0 BIT(0) |
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| 319 | #define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK BIT(1) |
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| 320 | #define AUX_RESERVED_RW_0_AUX_TX_P0_MASK GENMASK(15, 2) |
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| 321 | #define MTK_DP_AUX_P0_3630 0x3630 |
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| 322 | #define AUX_TX_REQUEST_READY_AUX_TX_P0 BIT(3) |
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| 323 | #define MTK_DP_AUX_P0_3634 0x3634 |
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| 324 | #define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK GENMASK(15, 8) |
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| 325 | #define AUX_TX_OVER_SAMPLE_RATE_FOR_26M 25 |
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| 326 | #define MTK_DP_AUX_P0_3640 0x3640 |
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| 327 | #define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(6) |
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| 328 | #define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(5) |
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| 329 | #define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(4) |
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| 330 | #define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0 BIT(3) |
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| 331 | #define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0 BIT(2) |
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| 332 | #define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0 BIT(1) |
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| 333 | #define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0 BIT(0) |
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| 334 | #define DP_AUX_P0_3640_VAL (AUX_400US_TIMEOUT_IRQ_AUX_TX_P0 | \ |
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| 335 | AUX_RX_DATA_RECV_IRQ_AUX_TX_P0 | \ |
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| 336 | AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0 | \ |
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| 337 | AUX_RX_CMD_RECV_IRQ_AUX_TX_P0 | \ |
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| 338 | AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0 | \ |
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| 339 | AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0 | \ |
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| 340 | AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0) |
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| 341 | #define MTK_DP_AUX_P0_3644 0x3644 |
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| 342 | #define MCU_REQUEST_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0) |
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| 343 | #define MTK_DP_AUX_P0_3648 0x3648 |
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| 344 | #define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK GENMASK(15, 0) |
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| 345 | #define MTK_DP_AUX_P0_364C 0x364c |
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| 346 | #define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK GENMASK(3, 0) |
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| 347 | #define MTK_DP_AUX_P0_3650 0x3650 |
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| 348 | #define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK GENMASK(15, 12) |
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| 349 | #define PHY_FIFO_RST_AUX_TX_P0_MASK BIT(9) |
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| 350 | #define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0 BIT(8) |
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| 351 | #define MTK_DP_AUX_P0_3658 0x3658 |
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| 352 | #define AUX_TX_OV_EN_AUX_TX_P0_MASK BIT(0) |
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| 353 | #define MTK_DP_AUX_P0_3690 0x3690 |
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| 354 | #define RX_REPLY_COMPLETE_MODE_AUX_TX_P0 BIT(8) |
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| 355 | #define MTK_DP_AUX_P0_3704 0x3704 |
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| 356 | #define AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK BIT(1) |
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| 357 | #define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0 BIT(2) |
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| 358 | #define MTK_DP_AUX_P0_3708 0x3708 |
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| 359 | #define MTK_DP_AUX_P0_37C8 0x37c8 |
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| 360 | #define MTK_ATOP_EN_AUX_TX_P0 BIT(0) |
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| 361 | |
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| 362 | #endif /*_MTK_DP_REG_H_*/ |
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| 363 | |
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