1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Authors:
5 * YT Shen <yt.shen@mediatek.com>
6 * CK Hu <ck.hu@mediatek.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/soc/mediatek/mtk-cmdq.h>
15#include <drm/drm_print.h>
16
17#include "mtk_crtc.h"
18#include "mtk_ddp_comp.h"
19#include "mtk_disp_drv.h"
20#include "mtk_drm_drv.h"
21#include "mtk_plane.h"
22
23
24#define DISP_REG_DITHER_EN 0x0000
25#define DITHER_EN BIT(0)
26#define DISP_REG_DITHER_CFG 0x0020
27#define DITHER_RELAY_MODE BIT(0)
28#define DITHER_ENGINE_EN BIT(1)
29#define DISP_DITHERING BIT(2)
30#define DISP_REG_DITHER_SIZE 0x0030
31#define DISP_REG_DITHER_5 0x0114
32#define DISP_REG_DITHER_7 0x011c
33#define DISP_REG_DITHER_15 0x013c
34#define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
35#define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
36#define DITHER_NEW_BIT_MODE BIT(0)
37#define DISP_REG_DITHER_16 0x0140
38#define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
39#define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
40#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
41#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
42
43#define DISP_REG_DSC_CON 0x0000
44#define DSC_EN BIT(0)
45#define DSC_DUAL_INOUT BIT(2)
46#define DSC_BYPASS BIT(4)
47#define DSC_UFOE_SEL BIT(16)
48
49#define DISP_REG_OD_EN 0x0000
50#define DISP_REG_OD_CFG 0x0020
51#define OD_RELAYMODE BIT(0)
52#define DISP_REG_OD_SIZE 0x0030
53
54#define DISP_REG_POSTMASK_EN 0x0000
55#define POSTMASK_EN BIT(0)
56#define DISP_REG_POSTMASK_CFG 0x0020
57#define POSTMASK_RELAY_MODE BIT(0)
58#define DISP_REG_POSTMASK_SIZE 0x0030
59
60#define DISP_REG_UFO_START 0x0000
61#define UFO_BYPASS BIT(2)
62
63struct mtk_ddp_comp_dev {
64 struct clk *clk;
65 void __iomem *regs;
66 struct cmdq_client_reg cmdq_reg;
67};
68
69void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
70 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
71 unsigned int offset)
72{
73#if IS_REACHABLE(CONFIG_MTK_CMDQ)
74 if (cmdq_pkt)
75 cmdq_pkt_write(pkt: cmdq_pkt, subsys: cmdq_reg->subsys,
76 offset: cmdq_reg->offset + offset, value);
77 else
78#endif
79 writel(val: value, addr: regs + offset);
80}
81
82void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
83 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
84 unsigned int offset)
85{
86#if IS_REACHABLE(CONFIG_MTK_CMDQ)
87 if (cmdq_pkt)
88 cmdq_pkt_write(pkt: cmdq_pkt, subsys: cmdq_reg->subsys,
89 offset: cmdq_reg->offset + offset, value);
90 else
91#endif
92 writel_relaxed(value, regs + offset);
93}
94
95void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
96 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
97 unsigned int offset, unsigned int mask)
98{
99#if IS_REACHABLE(CONFIG_MTK_CMDQ)
100 if (cmdq_pkt) {
101 cmdq_pkt_write_mask(pkt: cmdq_pkt, subsys: cmdq_reg->subsys,
102 offset: cmdq_reg->offset + offset, value, mask);
103 } else {
104#endif
105 u32 tmp = readl(addr: regs + offset);
106
107 tmp = (tmp & ~mask) | (value & mask);
108 writel(val: tmp, addr: regs + offset);
109#if IS_REACHABLE(CONFIG_MTK_CMDQ)
110 }
111#endif
112}
113
114static int mtk_ddp_clk_enable(struct device *dev)
115{
116 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
117
118 return clk_prepare_enable(clk: priv->clk);
119}
120
121static void mtk_ddp_clk_disable(struct device *dev)
122{
123 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
124
125 clk_disable_unprepare(clk: priv->clk);
126}
127
128void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
129 unsigned int bpc, unsigned int cfg,
130 unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
131{
132 /* If bpc equal to 0, the dithering function didn't be enabled */
133 if (bpc == 0)
134 return;
135
136 if (bpc >= MTK_MIN_BPC) {
137 mtk_ddp_write(cmdq_pkt, value: 0, cmdq_reg, regs, DISP_REG_DITHER_5);
138 mtk_ddp_write(cmdq_pkt, value: 0, cmdq_reg, regs, DISP_REG_DITHER_7);
139 mtk_ddp_write(cmdq_pkt,
140 DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
141 DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
142 DITHER_NEW_BIT_MODE,
143 cmdq_reg, regs, DISP_REG_DITHER_15);
144 mtk_ddp_write(cmdq_pkt,
145 DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
146 DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
147 DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
148 DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
149 cmdq_reg, regs, DISP_REG_DITHER_16);
150 mtk_ddp_write(cmdq_pkt, value: dither_en, cmdq_reg, regs, offset: cfg);
151 }
152}
153
154static void mtk_dither_config(struct device *dev, unsigned int w,
155 unsigned int h, unsigned int vrefresh,
156 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
157{
158 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
159
160 mtk_ddp_write(cmdq_pkt, value: w << 16 | h, cmdq_reg: &priv->cmdq_reg, regs: priv->regs, DISP_REG_DITHER_SIZE);
161 mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, cmdq_reg: &priv->cmdq_reg, regs: priv->regs,
162 DISP_REG_DITHER_CFG);
163 mtk_dither_set_common(regs: priv->regs, cmdq_reg: &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
164 DITHER_ENGINE_EN, cmdq_pkt);
165}
166
167static void mtk_dither_start(struct device *dev)
168{
169 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
170
171 writel(DITHER_EN, addr: priv->regs + DISP_REG_DITHER_EN);
172}
173
174static void mtk_dither_stop(struct device *dev)
175{
176 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
177
178 writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
179}
180
181static void mtk_dither_set(struct device *dev, unsigned int bpc,
182 unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
183{
184 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
185
186 mtk_dither_set_common(regs: priv->regs, cmdq_reg: &priv->cmdq_reg, bpc, cfg,
187 DISP_DITHERING, cmdq_pkt);
188}
189
190static void mtk_dsc_config(struct device *dev, unsigned int w,
191 unsigned int h, unsigned int vrefresh,
192 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
193{
194 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
195
196 /* dsc bypass mode */
197 mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, cmdq_reg: &priv->cmdq_reg, regs: priv->regs,
198 DISP_REG_DSC_CON, DSC_BYPASS);
199 mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, cmdq_reg: &priv->cmdq_reg, regs: priv->regs,
200 DISP_REG_DSC_CON, DSC_UFOE_SEL);
201 mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, cmdq_reg: &priv->cmdq_reg, regs: priv->regs,
202 DISP_REG_DSC_CON, DSC_DUAL_INOUT);
203}
204
205static void mtk_dsc_start(struct device *dev)
206{
207 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
208
209 /* write with mask to reserve the value set in mtk_dsc_config */
210 mtk_ddp_write_mask(NULL, DSC_EN, cmdq_reg: &priv->cmdq_reg, regs: priv->regs, DISP_REG_DSC_CON, DSC_EN);
211}
212
213static void mtk_dsc_stop(struct device *dev)
214{
215 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
216
217 writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
218}
219
220static void mtk_od_config(struct device *dev, unsigned int w,
221 unsigned int h, unsigned int vrefresh,
222 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
223{
224 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
225
226 mtk_ddp_write(cmdq_pkt, value: w << 16 | h, cmdq_reg: &priv->cmdq_reg, regs: priv->regs, DISP_REG_OD_SIZE);
227 mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, cmdq_reg: &priv->cmdq_reg, regs: priv->regs, DISP_REG_OD_CFG);
228 mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
229}
230
231static void mtk_od_start(struct device *dev)
232{
233 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
234
235 writel(val: 1, addr: priv->regs + DISP_REG_OD_EN);
236}
237
238static void mtk_postmask_config(struct device *dev, unsigned int w,
239 unsigned int h, unsigned int vrefresh,
240 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
241{
242 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
243
244 mtk_ddp_write(cmdq_pkt, value: w << 16 | h, cmdq_reg: &priv->cmdq_reg, regs: priv->regs,
245 DISP_REG_POSTMASK_SIZE);
246 mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, cmdq_reg: &priv->cmdq_reg,
247 regs: priv->regs, DISP_REG_POSTMASK_CFG);
248}
249
250static void mtk_postmask_start(struct device *dev)
251{
252 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
253
254 writel(POSTMASK_EN, addr: priv->regs + DISP_REG_POSTMASK_EN);
255}
256
257static void mtk_postmask_stop(struct device *dev)
258{
259 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
260
261 writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
262}
263
264static void mtk_ufoe_start(struct device *dev)
265{
266 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
267
268 writel(UFO_BYPASS, addr: priv->regs + DISP_REG_UFO_START);
269}
270
271static const struct mtk_ddp_comp_funcs ddp_aal = {
272 .clk_enable = mtk_aal_clk_enable,
273 .clk_disable = mtk_aal_clk_disable,
274 .gamma_get_lut_size = mtk_aal_gamma_get_lut_size,
275 .gamma_set = mtk_aal_gamma_set,
276 .config = mtk_aal_config,
277 .start = mtk_aal_start,
278 .stop = mtk_aal_stop,
279};
280
281static const struct mtk_ddp_comp_funcs ddp_ccorr = {
282 .clk_enable = mtk_ccorr_clk_enable,
283 .clk_disable = mtk_ccorr_clk_disable,
284 .config = mtk_ccorr_config,
285 .start = mtk_ccorr_start,
286 .stop = mtk_ccorr_stop,
287 .ctm_set = mtk_ccorr_ctm_set,
288};
289
290static const struct mtk_ddp_comp_funcs ddp_color = {
291 .clk_enable = mtk_color_clk_enable,
292 .clk_disable = mtk_color_clk_disable,
293 .config = mtk_color_config,
294 .start = mtk_color_start,
295};
296
297static const struct mtk_ddp_comp_funcs ddp_dither = {
298 .clk_enable = mtk_ddp_clk_enable,
299 .clk_disable = mtk_ddp_clk_disable,
300 .config = mtk_dither_config,
301 .start = mtk_dither_start,
302 .stop = mtk_dither_stop,
303};
304
305static const struct mtk_ddp_comp_funcs ddp_dpi = {
306 .start = mtk_dpi_start,
307 .stop = mtk_dpi_stop,
308 .encoder_index = mtk_dpi_encoder_index,
309};
310
311static const struct mtk_ddp_comp_funcs ddp_dsc = {
312 .clk_enable = mtk_ddp_clk_enable,
313 .clk_disable = mtk_ddp_clk_disable,
314 .config = mtk_dsc_config,
315 .start = mtk_dsc_start,
316 .stop = mtk_dsc_stop,
317};
318
319static const struct mtk_ddp_comp_funcs ddp_dsi = {
320 .start = mtk_dsi_ddp_start,
321 .stop = mtk_dsi_ddp_stop,
322 .encoder_index = mtk_dsi_encoder_index,
323};
324
325static const struct mtk_ddp_comp_funcs ddp_gamma = {
326 .clk_enable = mtk_gamma_clk_enable,
327 .clk_disable = mtk_gamma_clk_disable,
328 .gamma_get_lut_size = mtk_gamma_get_lut_size,
329 .gamma_set = mtk_gamma_set,
330 .config = mtk_gamma_config,
331 .start = mtk_gamma_start,
332 .stop = mtk_gamma_stop,
333};
334
335static const struct mtk_ddp_comp_funcs ddp_merge = {
336 .clk_enable = mtk_merge_clk_enable,
337 .clk_disable = mtk_merge_clk_disable,
338 .start = mtk_merge_start,
339 .stop = mtk_merge_stop,
340 .config = mtk_merge_config,
341};
342
343static const struct mtk_ddp_comp_funcs ddp_od = {
344 .clk_enable = mtk_ddp_clk_enable,
345 .clk_disable = mtk_ddp_clk_disable,
346 .config = mtk_od_config,
347 .start = mtk_od_start,
348};
349
350static const struct mtk_ddp_comp_funcs ddp_ovl = {
351 .clk_enable = mtk_ovl_clk_enable,
352 .clk_disable = mtk_ovl_clk_disable,
353 .config = mtk_ovl_config,
354 .start = mtk_ovl_start,
355 .stop = mtk_ovl_stop,
356 .register_vblank_cb = mtk_ovl_register_vblank_cb,
357 .unregister_vblank_cb = mtk_ovl_unregister_vblank_cb,
358 .enable_vblank = mtk_ovl_enable_vblank,
359 .disable_vblank = mtk_ovl_disable_vblank,
360 .supported_rotations = mtk_ovl_supported_rotations,
361 .layer_nr = mtk_ovl_layer_nr,
362 .layer_check = mtk_ovl_layer_check,
363 .layer_config = mtk_ovl_layer_config,
364 .bgclr_in_on = mtk_ovl_bgclr_in_on,
365 .bgclr_in_off = mtk_ovl_bgclr_in_off,
366 .get_blend_modes = mtk_ovl_get_blend_modes,
367 .get_formats = mtk_ovl_get_formats,
368 .get_num_formats = mtk_ovl_get_num_formats,
369 .is_afbc_supported = mtk_ovl_is_afbc_supported,
370};
371
372static const struct mtk_ddp_comp_funcs ddp_postmask = {
373 .clk_enable = mtk_ddp_clk_enable,
374 .clk_disable = mtk_ddp_clk_disable,
375 .config = mtk_postmask_config,
376 .start = mtk_postmask_start,
377 .stop = mtk_postmask_stop,
378};
379
380static const struct mtk_ddp_comp_funcs ddp_rdma = {
381 .clk_enable = mtk_rdma_clk_enable,
382 .clk_disable = mtk_rdma_clk_disable,
383 .config = mtk_rdma_config,
384 .start = mtk_rdma_start,
385 .stop = mtk_rdma_stop,
386 .register_vblank_cb = mtk_rdma_register_vblank_cb,
387 .unregister_vblank_cb = mtk_rdma_unregister_vblank_cb,
388 .enable_vblank = mtk_rdma_enable_vblank,
389 .disable_vblank = mtk_rdma_disable_vblank,
390 .layer_nr = mtk_rdma_layer_nr,
391 .layer_config = mtk_rdma_layer_config,
392 .get_formats = mtk_rdma_get_formats,
393 .get_num_formats = mtk_rdma_get_num_formats,
394};
395
396static const struct mtk_ddp_comp_funcs ddp_ufoe = {
397 .clk_enable = mtk_ddp_clk_enable,
398 .clk_disable = mtk_ddp_clk_disable,
399 .start = mtk_ufoe_start,
400};
401
402static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
403 .power_on = mtk_ovl_adaptor_power_on,
404 .power_off = mtk_ovl_adaptor_power_off,
405 .clk_enable = mtk_ovl_adaptor_clk_enable,
406 .clk_disable = mtk_ovl_adaptor_clk_disable,
407 .config = mtk_ovl_adaptor_config,
408 .start = mtk_ovl_adaptor_start,
409 .stop = mtk_ovl_adaptor_stop,
410 .layer_nr = mtk_ovl_adaptor_layer_nr,
411 .layer_config = mtk_ovl_adaptor_layer_config,
412 .register_vblank_cb = mtk_ovl_adaptor_register_vblank_cb,
413 .unregister_vblank_cb = mtk_ovl_adaptor_unregister_vblank_cb,
414 .enable_vblank = mtk_ovl_adaptor_enable_vblank,
415 .disable_vblank = mtk_ovl_adaptor_disable_vblank,
416 .dma_dev_get = mtk_ovl_adaptor_dma_dev_get,
417 .connect = mtk_ovl_adaptor_connect,
418 .disconnect = mtk_ovl_adaptor_disconnect,
419 .add = mtk_ovl_adaptor_add_comp,
420 .remove = mtk_ovl_adaptor_remove_comp,
421 .get_blend_modes = mtk_ovl_adaptor_get_blend_modes,
422 .get_formats = mtk_ovl_adaptor_get_formats,
423 .get_num_formats = mtk_ovl_adaptor_get_num_formats,
424 .mode_valid = mtk_ovl_adaptor_mode_valid,
425};
426
427static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
428 [MTK_DISP_AAL] = "aal",
429 [MTK_DISP_BLS] = "bls",
430 [MTK_DISP_CCORR] = "ccorr",
431 [MTK_DISP_COLOR] = "color",
432 [MTK_DISP_DITHER] = "dither",
433 [MTK_DISP_DSC] = "dsc",
434 [MTK_DISP_GAMMA] = "gamma",
435 [MTK_DISP_MERGE] = "merge",
436 [MTK_DISP_MUTEX] = "mutex",
437 [MTK_DISP_OD] = "od",
438 [MTK_DISP_OVL] = "ovl",
439 [MTK_DISP_OVL_2L] = "ovl-2l",
440 [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
441 [MTK_DISP_POSTMASK] = "postmask",
442 [MTK_DISP_PWM] = "pwm",
443 [MTK_DISP_RDMA] = "rdma",
444 [MTK_DISP_UFOE] = "ufoe",
445 [MTK_DISP_WDMA] = "wdma",
446 [MTK_DP_INTF] = "dp-intf",
447 [MTK_DPI] = "dpi",
448 [MTK_DSI] = "dsi",
449};
450
451struct mtk_ddp_comp_match {
452 enum mtk_ddp_comp_type type;
453 int alias_id;
454 const struct mtk_ddp_comp_funcs *funcs;
455};
456
457static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] = {
458 [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
459 [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
460 [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
461 [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
462 [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
463 [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
464 [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
465 [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi },
466 [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi },
467 [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
468 [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
469 [DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
470 [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
471 [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
472 [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
473 [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
474 [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
475 [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
476 [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
477 [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
478 [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
479 [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
480 [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
481 [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
482 [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
483 [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
484 [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
485 [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
486 [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
487 [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
488 [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
489 [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
490 [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
491 [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
492 [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
493 [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
494 [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
495 [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
496 [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
497 [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma },
498 [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
499 [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
500 [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
501};
502
503static bool mtk_ddp_comp_find(struct device *dev,
504 const unsigned int *path,
505 unsigned int path_len,
506 struct mtk_ddp_comp *ddp_comp)
507{
508 unsigned int i;
509
510 if (path == NULL)
511 return false;
512
513 for (i = 0U; i < path_len; i++)
514 if (dev == ddp_comp[path[i]].dev)
515 return true;
516
517 return false;
518}
519
520static int mtk_ddp_comp_find_in_route(struct device *dev,
521 const struct mtk_drm_route *routes,
522 unsigned int num_routes,
523 struct mtk_ddp_comp *ddp_comp)
524{
525 unsigned int i;
526
527 if (!routes)
528 return -EINVAL;
529
530 for (i = 0; i < num_routes; i++)
531 if (dev == ddp_comp[routes[i].route_ddp].dev)
532 return BIT(routes[i].crtc_id);
533
534 return -ENODEV;
535}
536
537static bool mtk_ddp_path_available(const unsigned int *path,
538 unsigned int path_len,
539 struct device_node **comp_node)
540{
541 unsigned int i;
542
543 if (!path || !path_len)
544 return false;
545
546 for (i = 0U; i < path_len; i++) {
547 /* OVL_ADAPTOR doesn't have a device node */
548 if (path[i] == DDP_COMPONENT_DRM_OVL_ADAPTOR)
549 continue;
550
551 if (!comp_node[path[i]])
552 return false;
553 }
554
555 return true;
556}
557
558int mtk_ddp_comp_get_id(struct device_node *node,
559 enum mtk_ddp_comp_type comp_type)
560{
561 int id = of_alias_get_id(np: node, stem: mtk_ddp_comp_stem[comp_type]);
562 int i;
563
564 for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
565 if (comp_type == mtk_ddp_matches[i].type &&
566 (id < 0 || id == mtk_ddp_matches[i].alias_id))
567 return i;
568 }
569
570 return -EINVAL;
571}
572
573int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
574{
575 struct mtk_drm_private *private = drm->dev_private;
576 const struct mtk_mmsys_driver_data *data;
577 struct mtk_drm_private *priv_n;
578 int i = 0, j;
579 int ret;
580
581 for (j = 0; j < private->data->mmsys_dev_num; j++) {
582 priv_n = private->all_drm_private[j];
583 data = priv_n->data;
584
585 if (mtk_ddp_path_available(path: data->main_path, path_len: data->main_len,
586 comp_node: priv_n->comp_node)) {
587 if (mtk_ddp_comp_find(dev, path: data->main_path,
588 path_len: data->main_len,
589 ddp_comp: priv_n->ddp_comp))
590 return BIT(i);
591 i++;
592 }
593
594 if (mtk_ddp_path_available(path: data->ext_path, path_len: data->ext_len,
595 comp_node: priv_n->comp_node)) {
596 if (mtk_ddp_comp_find(dev, path: data->ext_path,
597 path_len: data->ext_len,
598 ddp_comp: priv_n->ddp_comp))
599 return BIT(i);
600 i++;
601 }
602
603 if (mtk_ddp_path_available(path: data->third_path, path_len: data->third_len,
604 comp_node: priv_n->comp_node)) {
605 if (mtk_ddp_comp_find(dev, path: data->third_path,
606 path_len: data->third_len,
607 ddp_comp: priv_n->ddp_comp))
608 return BIT(i);
609 i++;
610 }
611 }
612
613 ret = mtk_ddp_comp_find_in_route(dev,
614 routes: private->data->conn_routes,
615 num_routes: private->data->num_conn_routes,
616 ddp_comp: private->ddp_comp);
617
618 if (ret < 0)
619 DRM_INFO("Failed to find comp in ddp table, ret = %d\n", ret);
620
621 return ret;
622}
623
624static void mtk_ddp_comp_put_device(void *_dev)
625{
626 struct device *dev = _dev;
627
628 put_device(dev);
629}
630
631static void mtk_ddp_comp_clk_put(void *_clk)
632{
633 struct clk *clk = _clk;
634
635 clk_put(clk);
636}
637
638int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_ddp_comp *comp,
639 unsigned int comp_id)
640{
641 struct platform_device *comp_pdev;
642 enum mtk_ddp_comp_type type;
643 struct mtk_ddp_comp_dev *priv;
644 int ret;
645
646 if (comp_id >= DDP_COMPONENT_DRM_ID_MAX)
647 return -EINVAL;
648
649 type = mtk_ddp_matches[comp_id].type;
650
651 comp->id = comp_id;
652 comp->funcs = mtk_ddp_matches[comp_id].funcs;
653 /* Not all drm components have a DTS device node, such as ovl_adaptor,
654 * which is the drm bring up sub driver
655 */
656 if (!node)
657 return 0;
658
659 comp_pdev = of_find_device_by_node(np: node);
660 if (!comp_pdev) {
661 DRM_INFO("Waiting for device %s\n", node->full_name);
662 return -EPROBE_DEFER;
663 }
664 comp->dev = &comp_pdev->dev;
665
666 ret = devm_add_action_or_reset(dev, mtk_ddp_comp_put_device, comp->dev);
667 if (ret)
668 return ret;
669
670 if (type == MTK_DISP_AAL ||
671 type == MTK_DISP_BLS ||
672 type == MTK_DISP_CCORR ||
673 type == MTK_DISP_COLOR ||
674 type == MTK_DISP_GAMMA ||
675 type == MTK_DISP_MERGE ||
676 type == MTK_DISP_OVL ||
677 type == MTK_DISP_OVL_2L ||
678 type == MTK_DISP_PWM ||
679 type == MTK_DISP_RDMA ||
680 type == MTK_DPI ||
681 type == MTK_DP_INTF ||
682 type == MTK_DSI)
683 return 0;
684
685 priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL);
686 if (!priv)
687 return -ENOMEM;
688
689 priv->regs = devm_of_iomap(dev, node, index: 0, NULL);
690 if (IS_ERR(ptr: priv->regs))
691 return PTR_ERR(ptr: priv->regs);
692
693 priv->clk = of_clk_get(np: node, index: 0);
694 if (IS_ERR(ptr: priv->clk))
695 return PTR_ERR(ptr: priv->clk);
696
697 ret = devm_add_action_or_reset(dev, mtk_ddp_comp_clk_put, priv->clk);
698 if (ret)
699 return ret;
700
701#if IS_REACHABLE(CONFIG_MTK_CMDQ)
702 ret = cmdq_dev_get_client_reg(dev: comp->dev, client_reg: &priv->cmdq_reg, idx: 0);
703 if (ret)
704 dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
705#endif
706
707 platform_set_drvdata(pdev: comp_pdev, data: priv);
708
709 return 0;
710}
711

source code of linux/drivers/gpu/drm/mediatek/mtk_ddp_comp.c