1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/dma-mapping.h>
8#include <linux/mailbox_controller.h>
9#include <linux/of.h>
10#include <linux/pm_runtime.h>
11#include <linux/soc/mediatek/mtk-cmdq.h>
12#include <linux/soc/mediatek/mtk-mmsys.h>
13#include <linux/soc/mediatek/mtk-mutex.h>
14
15#include <asm/barrier.h>
16
17#include <drm/drm_atomic.h>
18#include <drm/drm_atomic_helper.h>
19#include <drm/drm_print.h>
20#include <drm/drm_probe_helper.h>
21#include <drm/drm_vblank.h>
22
23#include "mtk_crtc.h"
24#include "mtk_ddp_comp.h"
25#include "mtk_drm_drv.h"
26#include "mtk_gem.h"
27#include "mtk_plane.h"
28
29/*
30 * struct mtk_crtc - MediaTek specific crtc structure.
31 * @base: crtc object.
32 * @enabled: records whether crtc_enable succeeded
33 * @planes: array of 4 drm_plane structures, one for each overlay plane
34 * @pending_planes: whether any plane has pending changes to be applied
35 * @mmsys_dev: pointer to the mmsys device for configuration registers
36 * @mutex: handle to one of the ten disp_mutex streams
37 * @ddp_comp_nr: number of components in ddp_comp
38 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
39 *
40 * TODO: Needs update: this header is missing a bunch of member descriptions.
41 */
42struct mtk_crtc {
43 struct drm_crtc base;
44 bool enabled;
45
46 bool pending_needs_vblank;
47 struct drm_pending_vblank_event *event;
48
49 struct drm_plane *planes;
50 unsigned int layer_nr;
51 bool pending_planes;
52 bool pending_async_planes;
53
54#if IS_REACHABLE(CONFIG_MTK_CMDQ)
55 struct cmdq_client cmdq_client;
56 struct cmdq_pkt cmdq_handle;
57 u32 cmdq_event;
58 u32 cmdq_vblank_cnt;
59 wait_queue_head_t cb_blocking_queue;
60#endif
61
62 struct device *mmsys_dev;
63 struct device *dma_dev;
64 struct mtk_mutex *mutex;
65 unsigned int ddp_comp_nr;
66 struct mtk_ddp_comp **ddp_comp;
67 unsigned int num_conn_routes;
68 const struct mtk_drm_route *conn_routes;
69
70 /* lock for display hardware access */
71 struct mutex hw_lock;
72 bool config_updating;
73 /* lock for config_updating to cmd buffer */
74 spinlock_t config_lock;
75};
76
77struct mtk_crtc_state {
78 struct drm_crtc_state base;
79
80 bool pending_config;
81 unsigned int pending_width;
82 unsigned int pending_height;
83 unsigned int pending_vrefresh;
84};
85
86static inline struct mtk_crtc *to_mtk_crtc(struct drm_crtc *c)
87{
88 return container_of(c, struct mtk_crtc, base);
89}
90
91static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
92{
93 return container_of(s, struct mtk_crtc_state, base);
94}
95
96static void mtk_crtc_finish_page_flip(struct mtk_crtc *mtk_crtc)
97{
98 struct drm_crtc *crtc = &mtk_crtc->base;
99 unsigned long flags;
100
101 if (mtk_crtc->event) {
102 spin_lock_irqsave(&crtc->dev->event_lock, flags);
103 drm_crtc_send_vblank_event(crtc, e: mtk_crtc->event);
104 drm_crtc_vblank_put(crtc);
105 mtk_crtc->event = NULL;
106 spin_unlock_irqrestore(lock: &crtc->dev->event_lock, flags);
107 }
108}
109
110static void mtk_drm_finish_page_flip(struct mtk_crtc *mtk_crtc)
111{
112 unsigned long flags;
113
114 drm_crtc_handle_vblank(crtc: &mtk_crtc->base);
115
116#if IS_REACHABLE(CONFIG_MTK_CMDQ)
117 if (mtk_crtc->cmdq_client.chan)
118 return;
119#endif
120
121 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
122 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
123 mtk_crtc_finish_page_flip(mtk_crtc);
124 mtk_crtc->pending_needs_vblank = false;
125 }
126 spin_unlock_irqrestore(lock: &mtk_crtc->config_lock, flags);
127}
128
129static void mtk_crtc_destroy(struct drm_crtc *crtc)
130{
131 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
132 int i;
133
134 mtk_mutex_put(mutex: mtk_crtc->mutex);
135#if IS_REACHABLE(CONFIG_MTK_CMDQ)
136 if (mtk_crtc->cmdq_client.chan) {
137 cmdq_pkt_destroy(client: &mtk_crtc->cmdq_client, pkt: &mtk_crtc->cmdq_handle);
138 mbox_free_channel(chan: mtk_crtc->cmdq_client.chan);
139 mtk_crtc->cmdq_client.chan = NULL;
140 }
141#endif
142
143 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
144 struct mtk_ddp_comp *comp;
145
146 comp = mtk_crtc->ddp_comp[i];
147 mtk_ddp_comp_unregister_vblank_cb(comp);
148 }
149
150 drm_crtc_cleanup(crtc);
151}
152
153static void mtk_crtc_reset(struct drm_crtc *crtc)
154{
155 struct mtk_crtc_state *state;
156
157 if (crtc->state)
158 __drm_atomic_helper_crtc_destroy_state(state: crtc->state);
159
160 kfree(objp: to_mtk_crtc_state(s: crtc->state));
161 crtc->state = NULL;
162
163 state = kzalloc(sizeof(*state), GFP_KERNEL);
164 if (state)
165 __drm_atomic_helper_crtc_reset(crtc, state: &state->base);
166}
167
168static struct drm_crtc_state *mtk_crtc_duplicate_state(struct drm_crtc *crtc)
169{
170 struct mtk_crtc_state *state;
171
172 state = kmalloc(sizeof(*state), GFP_KERNEL);
173 if (!state)
174 return NULL;
175
176 __drm_atomic_helper_crtc_duplicate_state(crtc, state: &state->base);
177
178 WARN_ON(state->base.crtc != crtc);
179 state->base.crtc = crtc;
180 state->pending_config = false;
181
182 return &state->base;
183}
184
185static void mtk_crtc_destroy_state(struct drm_crtc *crtc,
186 struct drm_crtc_state *state)
187{
188 __drm_atomic_helper_crtc_destroy_state(state);
189 kfree(objp: to_mtk_crtc_state(s: state));
190}
191
192static enum drm_mode_status
193mtk_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
194{
195 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
196 enum drm_mode_status status = MODE_OK;
197 int i;
198
199 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
200 status = mtk_ddp_comp_mode_valid(comp: mtk_crtc->ddp_comp[i], mode);
201 if (status != MODE_OK)
202 break;
203 }
204 return status;
205}
206
207static bool mtk_crtc_mode_fixup(struct drm_crtc *crtc,
208 const struct drm_display_mode *mode,
209 struct drm_display_mode *adjusted_mode)
210{
211 /* Nothing to do here, but this callback is mandatory. */
212 return true;
213}
214
215static void mtk_crtc_mode_set_nofb(struct drm_crtc *crtc)
216{
217 struct mtk_crtc_state *state = to_mtk_crtc_state(s: crtc->state);
218
219 state->pending_width = crtc->mode.hdisplay;
220 state->pending_height = crtc->mode.vdisplay;
221 state->pending_vrefresh = drm_mode_vrefresh(mode: &crtc->mode);
222 wmb(); /* Make sure the above parameters are set before update */
223 state->pending_config = true;
224}
225
226static int mtk_crtc_ddp_clk_enable(struct mtk_crtc *mtk_crtc)
227{
228 int ret;
229 int i;
230
231 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
232 ret = mtk_ddp_comp_clk_enable(comp: mtk_crtc->ddp_comp[i]);
233 if (ret) {
234 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
235 goto err;
236 }
237 }
238
239 return 0;
240err:
241 while (--i >= 0)
242 mtk_ddp_comp_clk_disable(comp: mtk_crtc->ddp_comp[i]);
243 return ret;
244}
245
246static void mtk_crtc_ddp_clk_disable(struct mtk_crtc *mtk_crtc)
247{
248 int i;
249
250 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
251 mtk_ddp_comp_clk_disable(comp: mtk_crtc->ddp_comp[i]);
252}
253
254static
255struct mtk_ddp_comp *mtk_ddp_comp_for_plane(struct drm_crtc *crtc,
256 struct drm_plane *plane,
257 unsigned int *local_layer)
258{
259 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
260 struct mtk_ddp_comp *comp;
261 int i, count = 0;
262 unsigned int local_index = plane - mtk_crtc->planes;
263
264 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
265 comp = mtk_crtc->ddp_comp[i];
266 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
267 *local_layer = local_index - count;
268 return comp;
269 }
270 count += mtk_ddp_comp_layer_nr(comp);
271 }
272
273 WARN(1, "Failed to find component for plane %d\n", plane->index);
274 return NULL;
275}
276
277#if IS_REACHABLE(CONFIG_MTK_CMDQ)
278static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
279{
280 struct cmdq_cb_data *data = mssg;
281 struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client);
282 struct mtk_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_crtc, cmdq_client);
283 struct mtk_crtc_state *state;
284 unsigned int i;
285 unsigned long flags;
286
287 /* release GCE HW usage and start autosuspend */
288 pm_runtime_mark_last_busy(dev: cmdq_cl->chan->mbox->dev);
289 pm_runtime_put_autosuspend(dev: cmdq_cl->chan->mbox->dev);
290
291 if (data->sta < 0)
292 return;
293
294 state = to_mtk_crtc_state(s: mtk_crtc->base.state);
295
296 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
297 if (mtk_crtc->config_updating)
298 goto ddp_cmdq_cb_out;
299
300 state->pending_config = false;
301
302 if (mtk_crtc->pending_planes) {
303 for (i = 0; i < mtk_crtc->layer_nr; i++) {
304 struct drm_plane *plane = &mtk_crtc->planes[i];
305 struct mtk_plane_state *plane_state;
306
307 plane_state = to_mtk_plane_state(state: plane->state);
308
309 plane_state->pending.config = false;
310 }
311 mtk_crtc->pending_planes = false;
312 }
313
314 if (mtk_crtc->pending_async_planes) {
315 for (i = 0; i < mtk_crtc->layer_nr; i++) {
316 struct drm_plane *plane = &mtk_crtc->planes[i];
317 struct mtk_plane_state *plane_state;
318
319 plane_state = to_mtk_plane_state(state: plane->state);
320
321 plane_state->pending.async_config = false;
322 }
323 mtk_crtc->pending_async_planes = false;
324 }
325
326ddp_cmdq_cb_out:
327
328 if (mtk_crtc->pending_needs_vblank) {
329 mtk_crtc_finish_page_flip(mtk_crtc);
330 mtk_crtc->pending_needs_vblank = false;
331 }
332
333 spin_unlock_irqrestore(lock: &mtk_crtc->config_lock, flags);
334
335 mtk_crtc->cmdq_vblank_cnt = 0;
336 wake_up(&mtk_crtc->cb_blocking_queue);
337}
338#endif
339
340static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
341{
342 struct drm_crtc *crtc = &mtk_crtc->base;
343 struct drm_connector *connector;
344 struct drm_encoder *encoder;
345 struct drm_connector_list_iter conn_iter;
346 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
347 int ret;
348 int i;
349
350 if (WARN_ON(!crtc->state))
351 return -EINVAL;
352
353 width = crtc->state->adjusted_mode.hdisplay;
354 height = crtc->state->adjusted_mode.vdisplay;
355 vrefresh = drm_mode_vrefresh(mode: &crtc->state->adjusted_mode);
356
357 drm_for_each_encoder(encoder, crtc->dev) {
358 if (encoder->crtc != crtc)
359 continue;
360
361 drm_connector_list_iter_begin(dev: crtc->dev, iter: &conn_iter);
362 drm_for_each_connector_iter(connector, &conn_iter) {
363 if (connector->encoder != encoder)
364 continue;
365 if (connector->display_info.bpc != 0 &&
366 bpc > connector->display_info.bpc)
367 bpc = connector->display_info.bpc;
368 }
369 drm_connector_list_iter_end(iter: &conn_iter);
370 }
371
372 ret = pm_runtime_resume_and_get(dev: crtc->dev->dev);
373 if (ret < 0) {
374 DRM_ERROR("Failed to enable power domain: %d\n", ret);
375 return ret;
376 }
377
378 ret = mtk_mutex_prepare(mutex: mtk_crtc->mutex);
379 if (ret < 0) {
380 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
381 goto err_pm_runtime_put;
382 }
383
384 ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
385 if (ret < 0) {
386 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
387 goto err_mutex_unprepare;
388 }
389
390 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
391 if (!mtk_ddp_comp_connect(comp: mtk_crtc->ddp_comp[i], mmsys_dev: mtk_crtc->mmsys_dev,
392 next: mtk_crtc->ddp_comp[i + 1]->id))
393 mtk_mmsys_ddp_connect(dev: mtk_crtc->mmsys_dev,
394 cur: mtk_crtc->ddp_comp[i]->id,
395 next: mtk_crtc->ddp_comp[i + 1]->id);
396 if (!mtk_ddp_comp_add(comp: mtk_crtc->ddp_comp[i], mutex: mtk_crtc->mutex))
397 mtk_mutex_add_comp(mutex: mtk_crtc->mutex,
398 id: mtk_crtc->ddp_comp[i]->id);
399 }
400 if (!mtk_ddp_comp_add(comp: mtk_crtc->ddp_comp[i], mutex: mtk_crtc->mutex))
401 mtk_mutex_add_comp(mutex: mtk_crtc->mutex, id: mtk_crtc->ddp_comp[i]->id);
402 mtk_mutex_enable(mutex: mtk_crtc->mutex);
403
404 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
405 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
406
407 if (i == 1)
408 mtk_ddp_comp_bgclr_in_on(comp);
409
410 mtk_ddp_comp_config(comp, w: width, h: height, vrefresh, bpc, NULL);
411 mtk_ddp_comp_start(comp);
412 }
413
414 /* Initially configure all planes */
415 for (i = 0; i < mtk_crtc->layer_nr; i++) {
416 struct drm_plane *plane = &mtk_crtc->planes[i];
417 struct mtk_plane_state *plane_state;
418 struct mtk_ddp_comp *comp;
419 unsigned int local_layer;
420
421 plane_state = to_mtk_plane_state(state: plane->state);
422
423 /* should not enable layer before crtc enabled */
424 plane_state->pending.enable = false;
425 comp = mtk_ddp_comp_for_plane(crtc, plane, local_layer: &local_layer);
426 if (comp)
427 mtk_ddp_comp_layer_config(comp, idx: local_layer,
428 state: plane_state, NULL);
429 }
430
431 return 0;
432
433err_mutex_unprepare:
434 mtk_mutex_unprepare(mutex: mtk_crtc->mutex);
435err_pm_runtime_put:
436 pm_runtime_put(dev: crtc->dev->dev);
437 return ret;
438}
439
440static void mtk_crtc_ddp_hw_fini(struct mtk_crtc *mtk_crtc)
441{
442 struct drm_device *drm = mtk_crtc->base.dev;
443 struct drm_crtc *crtc = &mtk_crtc->base;
444 unsigned long flags;
445 int i;
446
447 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
448 mtk_ddp_comp_stop(comp: mtk_crtc->ddp_comp[i]);
449 if (i == 1)
450 mtk_ddp_comp_bgclr_in_off(comp: mtk_crtc->ddp_comp[i]);
451 }
452
453 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
454 if (!mtk_ddp_comp_remove(comp: mtk_crtc->ddp_comp[i], mutex: mtk_crtc->mutex))
455 mtk_mutex_remove_comp(mutex: mtk_crtc->mutex,
456 id: mtk_crtc->ddp_comp[i]->id);
457 mtk_mutex_disable(mutex: mtk_crtc->mutex);
458 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
459 if (!mtk_ddp_comp_disconnect(comp: mtk_crtc->ddp_comp[i], mmsys_dev: mtk_crtc->mmsys_dev,
460 next: mtk_crtc->ddp_comp[i + 1]->id))
461 mtk_mmsys_ddp_disconnect(dev: mtk_crtc->mmsys_dev,
462 cur: mtk_crtc->ddp_comp[i]->id,
463 next: mtk_crtc->ddp_comp[i + 1]->id);
464 if (!mtk_ddp_comp_remove(comp: mtk_crtc->ddp_comp[i], mutex: mtk_crtc->mutex))
465 mtk_mutex_remove_comp(mutex: mtk_crtc->mutex,
466 id: mtk_crtc->ddp_comp[i]->id);
467 }
468 if (!mtk_ddp_comp_remove(comp: mtk_crtc->ddp_comp[i], mutex: mtk_crtc->mutex))
469 mtk_mutex_remove_comp(mutex: mtk_crtc->mutex, id: mtk_crtc->ddp_comp[i]->id);
470 mtk_crtc_ddp_clk_disable(mtk_crtc);
471 mtk_mutex_unprepare(mutex: mtk_crtc->mutex);
472
473 pm_runtime_put(dev: drm->dev);
474
475 if (crtc->state->event && !crtc->state->active) {
476 spin_lock_irqsave(&crtc->dev->event_lock, flags);
477 drm_crtc_send_vblank_event(crtc, e: crtc->state->event);
478 crtc->state->event = NULL;
479 spin_unlock_irqrestore(lock: &crtc->dev->event_lock, flags);
480 }
481}
482
483static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
484 struct cmdq_pkt *cmdq_handle)
485{
486 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
487 struct mtk_crtc_state *state = to_mtk_crtc_state(s: mtk_crtc->base.state);
488 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
489 unsigned int i;
490 unsigned int local_layer;
491
492 /*
493 * TODO: instead of updating the registers here, we should prepare
494 * working registers in atomic_commit and let the hardware command
495 * queue update module registers on vblank.
496 */
497 if (state->pending_config) {
498 mtk_ddp_comp_config(comp, w: state->pending_width,
499 h: state->pending_height,
500 vrefresh: state->pending_vrefresh, bpc: 0,
501 cmdq_pkt: cmdq_handle);
502
503 if (!cmdq_handle)
504 state->pending_config = false;
505 }
506
507 if (mtk_crtc->pending_planes) {
508 for (i = 0; i < mtk_crtc->layer_nr; i++) {
509 struct drm_plane *plane = &mtk_crtc->planes[i];
510 struct mtk_plane_state *plane_state;
511
512 plane_state = to_mtk_plane_state(state: plane->state);
513
514 if (!plane_state->pending.config)
515 continue;
516
517 comp = mtk_ddp_comp_for_plane(crtc, plane, local_layer: &local_layer);
518
519 if (comp)
520 mtk_ddp_comp_layer_config(comp, idx: local_layer,
521 state: plane_state,
522 cmdq_pkt: cmdq_handle);
523 if (!cmdq_handle)
524 plane_state->pending.config = false;
525 }
526
527 if (!cmdq_handle)
528 mtk_crtc->pending_planes = false;
529 }
530
531 if (mtk_crtc->pending_async_planes) {
532 for (i = 0; i < mtk_crtc->layer_nr; i++) {
533 struct drm_plane *plane = &mtk_crtc->planes[i];
534 struct mtk_plane_state *plane_state;
535
536 plane_state = to_mtk_plane_state(state: plane->state);
537
538 if (!plane_state->pending.async_config)
539 continue;
540
541 comp = mtk_ddp_comp_for_plane(crtc, plane, local_layer: &local_layer);
542
543 if (comp)
544 mtk_ddp_comp_layer_config(comp, idx: local_layer,
545 state: plane_state,
546 cmdq_pkt: cmdq_handle);
547 if (!cmdq_handle)
548 plane_state->pending.async_config = false;
549 }
550
551 if (!cmdq_handle)
552 mtk_crtc->pending_async_planes = false;
553 }
554}
555
556static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)
557{
558#if IS_REACHABLE(CONFIG_MTK_CMDQ)
559 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
560#endif
561 struct drm_crtc *crtc = &mtk_crtc->base;
562 struct mtk_drm_private *priv = crtc->dev->dev_private;
563 unsigned int pending_planes = 0, pending_async_planes = 0;
564 int i;
565 unsigned long flags;
566
567 mutex_lock(&mtk_crtc->hw_lock);
568
569 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
570 mtk_crtc->config_updating = true;
571 spin_unlock_irqrestore(lock: &mtk_crtc->config_lock, flags);
572
573 if (needs_vblank)
574 mtk_crtc->pending_needs_vblank = true;
575
576 for (i = 0; i < mtk_crtc->layer_nr; i++) {
577 struct drm_plane *plane = &mtk_crtc->planes[i];
578 struct mtk_plane_state *plane_state;
579
580 plane_state = to_mtk_plane_state(state: plane->state);
581 if (plane_state->pending.dirty) {
582 plane_state->pending.config = true;
583 plane_state->pending.dirty = false;
584 pending_planes |= BIT(i);
585 } else if (plane_state->pending.async_dirty) {
586 plane_state->pending.async_config = true;
587 plane_state->pending.async_dirty = false;
588 pending_async_planes |= BIT(i);
589 }
590 }
591 if (pending_planes)
592 mtk_crtc->pending_planes = true;
593 if (pending_async_planes)
594 mtk_crtc->pending_async_planes = true;
595
596 if (priv->data->shadow_register) {
597 mtk_mutex_acquire(mutex: mtk_crtc->mutex);
598 mtk_crtc_ddp_config(crtc, NULL);
599 mtk_mutex_release(mutex: mtk_crtc->mutex);
600 }
601#if IS_REACHABLE(CONFIG_MTK_CMDQ)
602 if (mtk_crtc->cmdq_client.chan) {
603 mbox_flush(chan: mtk_crtc->cmdq_client.chan, timeout: 2000);
604 cmdq_handle->cmd_buf_size = 0;
605 cmdq_pkt_clear_event(pkt: cmdq_handle, event: mtk_crtc->cmdq_event);
606 cmdq_pkt_wfe(pkt: cmdq_handle, event: mtk_crtc->cmdq_event, clear: false);
607 mtk_crtc_ddp_config(crtc, cmdq_handle);
608 cmdq_pkt_eoc(pkt: cmdq_handle);
609 dma_sync_single_for_device(dev: mtk_crtc->cmdq_client.chan->mbox->dev,
610 addr: cmdq_handle->pa_base,
611 size: cmdq_handle->cmd_buf_size,
612 dir: DMA_TO_DEVICE);
613 /*
614 * CMDQ command should execute in next 3 vblank.
615 * One vblank interrupt before send message (occasionally)
616 * and one vblank interrupt after cmdq done,
617 * so it's timeout after 3 vblank interrupt.
618 * If it fail to execute in next 3 vblank, timeout happen.
619 */
620 mtk_crtc->cmdq_vblank_cnt = 3;
621
622 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
623 mtk_crtc->config_updating = false;
624 spin_unlock_irqrestore(lock: &mtk_crtc->config_lock, flags);
625
626 if (pm_runtime_resume_and_get(dev: mtk_crtc->cmdq_client.chan->mbox->dev) < 0)
627 goto update_config_out;
628
629 mbox_send_message(chan: mtk_crtc->cmdq_client.chan, mssg: cmdq_handle);
630 mbox_client_txdone(chan: mtk_crtc->cmdq_client.chan, r: 0);
631 goto update_config_out;
632 }
633#endif
634 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
635 mtk_crtc->config_updating = false;
636 spin_unlock_irqrestore(lock: &mtk_crtc->config_lock, flags);
637
638#if IS_REACHABLE(CONFIG_MTK_CMDQ)
639update_config_out:
640#endif
641 mutex_unlock(lock: &mtk_crtc->hw_lock);
642}
643
644static void mtk_crtc_ddp_irq(void *data)
645{
646 struct drm_crtc *crtc = data;
647 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
648 struct mtk_drm_private *priv = crtc->dev->dev_private;
649
650#if IS_REACHABLE(CONFIG_MTK_CMDQ)
651 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan)
652 mtk_crtc_ddp_config(crtc, NULL);
653 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
654 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",
655 drm_crtc_index(&mtk_crtc->base));
656#else
657 if (!priv->data->shadow_register)
658 mtk_crtc_ddp_config(crtc, NULL);
659#endif
660 mtk_drm_finish_page_flip(mtk_crtc);
661}
662
663static int mtk_crtc_enable_vblank(struct drm_crtc *crtc)
664{
665 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
666 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
667
668 mtk_ddp_comp_enable_vblank(comp);
669
670 return 0;
671}
672
673static void mtk_crtc_disable_vblank(struct drm_crtc *crtc)
674{
675 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
676 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
677
678 mtk_ddp_comp_disable_vblank(comp);
679}
680
681static void mtk_crtc_update_output(struct drm_crtc *crtc,
682 struct drm_atomic_state *state)
683{
684 int crtc_index = drm_crtc_index(crtc);
685 int i;
686 struct device *dev;
687 struct drm_crtc_state *crtc_state = state->crtcs[crtc_index].new_state;
688 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
689 struct mtk_drm_private *priv;
690 unsigned int encoder_mask = crtc_state->encoder_mask;
691
692 if (!crtc_state->connectors_changed)
693 return;
694
695 if (!mtk_crtc->num_conn_routes)
696 return;
697
698 priv = ((struct mtk_drm_private *)crtc->dev->dev_private)->all_drm_private[crtc_index];
699 dev = priv->dev;
700
701 dev_dbg(dev, "connector change:%d, encoder mask:0x%x for crtc:%d\n",
702 crtc_state->connectors_changed, encoder_mask, crtc_index);
703
704 for (i = 0; i < mtk_crtc->num_conn_routes; i++) {
705 unsigned int comp_id = mtk_crtc->conn_routes[i].route_ddp;
706 struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
707
708 if (comp->encoder_index >= 0 &&
709 (encoder_mask & BIT(comp->encoder_index))) {
710 mtk_crtc->ddp_comp[mtk_crtc->ddp_comp_nr - 1] = comp;
711 dev_dbg(dev, "Add comp_id: %d at path index %d\n",
712 comp->id, mtk_crtc->ddp_comp_nr - 1);
713 break;
714 }
715 }
716}
717
718int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
719 struct mtk_plane_state *state)
720{
721 unsigned int local_layer;
722 struct mtk_ddp_comp *comp;
723
724 comp = mtk_ddp_comp_for_plane(crtc, plane, local_layer: &local_layer);
725 if (comp)
726 return mtk_ddp_comp_layer_check(comp, idx: local_layer, state);
727 return 0;
728}
729
730void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane)
731{
732#if IS_REACHABLE(CONFIG_MTK_CMDQ)
733 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
734 struct mtk_plane_state *plane_state = to_mtk_plane_state(state: plane->state);
735 int i;
736
737 /* no need to wait for disabling the plane by CPU */
738 if (!mtk_crtc->cmdq_client.chan)
739 return;
740
741 if (!mtk_crtc->enabled)
742 return;
743
744 /* set pending plane state to disabled */
745 for (i = 0; i < mtk_crtc->layer_nr; i++) {
746 struct drm_plane *mtk_plane = &mtk_crtc->planes[i];
747 struct mtk_plane_state *mtk_plane_state = to_mtk_plane_state(state: mtk_plane->state);
748
749 if (mtk_plane->index == plane->index) {
750 memcpy(mtk_plane_state, plane_state, sizeof(*plane_state));
751 break;
752 }
753 }
754 mtk_crtc_update_config(mtk_crtc, needs_vblank: false);
755
756 /* wait for planes to be disabled by CMDQ */
757 wait_event_timeout(mtk_crtc->cb_blocking_queue,
758 mtk_crtc->cmdq_vblank_cnt == 0,
759 msecs_to_jiffies(500));
760#endif
761}
762
763void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
764 struct drm_atomic_state *state)
765{
766 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
767
768 if (!mtk_crtc->enabled)
769 return;
770
771 mtk_crtc_update_config(mtk_crtc, needs_vblank: false);
772}
773
774static void mtk_crtc_atomic_enable(struct drm_crtc *crtc,
775 struct drm_atomic_state *state)
776{
777 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
778 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
779 int ret;
780
781 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
782
783 ret = mtk_ddp_comp_power_on(comp);
784 if (ret < 0) {
785 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret);
786 return;
787 }
788
789 mtk_crtc_update_output(crtc, state);
790
791 ret = mtk_crtc_ddp_hw_init(mtk_crtc);
792 if (ret) {
793 mtk_ddp_comp_power_off(comp);
794 return;
795 }
796
797 drm_crtc_vblank_on(crtc);
798 mtk_crtc->enabled = true;
799}
800
801static void mtk_crtc_atomic_disable(struct drm_crtc *crtc,
802 struct drm_atomic_state *state)
803{
804 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
805 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
806 int i;
807
808 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
809 if (!mtk_crtc->enabled)
810 return;
811
812 /* Set all pending plane state to disabled */
813 for (i = 0; i < mtk_crtc->layer_nr; i++) {
814 struct drm_plane *plane = &mtk_crtc->planes[i];
815 struct mtk_plane_state *plane_state;
816
817 plane_state = to_mtk_plane_state(state: plane->state);
818 plane_state->pending.enable = false;
819 plane_state->pending.config = true;
820 }
821 mtk_crtc->pending_planes = true;
822
823 mtk_crtc_update_config(mtk_crtc, needs_vblank: false);
824#if IS_REACHABLE(CONFIG_MTK_CMDQ)
825 /* Wait for planes to be disabled by cmdq */
826 if (mtk_crtc->cmdq_client.chan)
827 wait_event_timeout(mtk_crtc->cb_blocking_queue,
828 mtk_crtc->cmdq_vblank_cnt == 0,
829 msecs_to_jiffies(500));
830#endif
831 /* Wait for planes to be disabled */
832 drm_crtc_wait_one_vblank(crtc);
833
834 drm_crtc_vblank_off(crtc);
835 mtk_crtc_ddp_hw_fini(mtk_crtc);
836 mtk_ddp_comp_power_off(comp);
837
838 mtk_crtc->enabled = false;
839}
840
841static void mtk_crtc_atomic_begin(struct drm_crtc *crtc,
842 struct drm_atomic_state *state)
843{
844 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
845 crtc);
846 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(s: crtc_state);
847 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
848 unsigned long flags;
849
850 if (mtk_crtc->event && mtk_crtc_state->base.event)
851 DRM_ERROR("new event while there is still a pending event\n");
852
853 if (mtk_crtc_state->base.event) {
854 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
855 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
856
857 spin_lock_irqsave(&crtc->dev->event_lock, flags);
858 mtk_crtc->event = mtk_crtc_state->base.event;
859 spin_unlock_irqrestore(lock: &crtc->dev->event_lock, flags);
860
861 mtk_crtc_state->base.event = NULL;
862 }
863}
864
865static void mtk_crtc_atomic_flush(struct drm_crtc *crtc,
866 struct drm_atomic_state *state)
867{
868 struct mtk_crtc *mtk_crtc = to_mtk_crtc(c: crtc);
869 int i;
870
871 if (crtc->state->color_mgmt_changed)
872 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
873 mtk_ddp_gamma_set(comp: mtk_crtc->ddp_comp[i], state: crtc->state);
874 mtk_ddp_ctm_set(comp: mtk_crtc->ddp_comp[i], state: crtc->state);
875 }
876 mtk_crtc_update_config(mtk_crtc, needs_vblank: !!mtk_crtc->event);
877}
878
879static const struct drm_crtc_funcs mtk_crtc_funcs = {
880 .set_config = drm_atomic_helper_set_config,
881 .page_flip = drm_atomic_helper_page_flip,
882 .destroy = mtk_crtc_destroy,
883 .reset = mtk_crtc_reset,
884 .atomic_duplicate_state = mtk_crtc_duplicate_state,
885 .atomic_destroy_state = mtk_crtc_destroy_state,
886 .enable_vblank = mtk_crtc_enable_vblank,
887 .disable_vblank = mtk_crtc_disable_vblank,
888};
889
890static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
891 .mode_fixup = mtk_crtc_mode_fixup,
892 .mode_set_nofb = mtk_crtc_mode_set_nofb,
893 .mode_valid = mtk_crtc_mode_valid,
894 .atomic_begin = mtk_crtc_atomic_begin,
895 .atomic_flush = mtk_crtc_atomic_flush,
896 .atomic_enable = mtk_crtc_atomic_enable,
897 .atomic_disable = mtk_crtc_atomic_disable,
898};
899
900static int mtk_crtc_init(struct drm_device *drm, struct mtk_crtc *mtk_crtc,
901 unsigned int pipe)
902{
903 struct drm_plane *primary = NULL;
904 struct drm_plane *cursor = NULL;
905 int i, ret;
906
907 for (i = 0; i < mtk_crtc->layer_nr; i++) {
908 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
909 primary = &mtk_crtc->planes[i];
910 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
911 cursor = &mtk_crtc->planes[i];
912 }
913
914 ret = drm_crtc_init_with_planes(dev: drm, crtc: &mtk_crtc->base, primary, cursor,
915 funcs: &mtk_crtc_funcs, NULL);
916 if (ret)
917 goto err_cleanup_crtc;
918
919 drm_crtc_helper_add(crtc: &mtk_crtc->base, funcs: &mtk_crtc_helper_funcs);
920
921 return 0;
922
923err_cleanup_crtc:
924 drm_crtc_cleanup(crtc: &mtk_crtc->base);
925 return ret;
926}
927
928static int mtk_crtc_num_comp_planes(struct mtk_crtc *mtk_crtc, int comp_idx)
929{
930 struct mtk_ddp_comp *comp;
931
932 if (comp_idx > 1)
933 return 0;
934
935 comp = mtk_crtc->ddp_comp[comp_idx];
936 if (!comp->funcs)
937 return 0;
938
939 if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
940 return 0;
941
942 return mtk_ddp_comp_layer_nr(comp);
943}
944
945static inline
946enum drm_plane_type mtk_crtc_plane_type(unsigned int plane_idx,
947 unsigned int num_planes)
948{
949 if (plane_idx == 0)
950 return DRM_PLANE_TYPE_PRIMARY;
951 else if (plane_idx == (num_planes - 1))
952 return DRM_PLANE_TYPE_CURSOR;
953 else
954 return DRM_PLANE_TYPE_OVERLAY;
955
956}
957
958static int mtk_crtc_init_comp_planes(struct drm_device *drm_dev,
959 struct mtk_crtc *mtk_crtc,
960 int comp_idx, int pipe)
961{
962 int num_planes = mtk_crtc_num_comp_planes(mtk_crtc, comp_idx);
963 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
964 int i, ret;
965
966 for (i = 0; i < num_planes; i++) {
967 ret = mtk_plane_init(dev: drm_dev,
968 plane: &mtk_crtc->planes[mtk_crtc->layer_nr],
969 BIT(pipe),
970 type: mtk_crtc_plane_type(plane_idx: mtk_crtc->layer_nr, num_planes),
971 supported_rotations: mtk_ddp_comp_supported_rotations(comp),
972 blend_modes: mtk_ddp_comp_get_blend_modes(comp),
973 formats: mtk_ddp_comp_get_formats(comp),
974 num_formats: mtk_ddp_comp_get_num_formats(comp),
975 supports_afbc: mtk_ddp_comp_is_afbc_supported(comp), plane_idx: i);
976 if (ret)
977 return ret;
978
979 mtk_crtc->layer_nr++;
980 }
981 return 0;
982}
983
984struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc)
985{
986 struct mtk_crtc *mtk_crtc = NULL;
987
988 if (!crtc)
989 return NULL;
990
991 mtk_crtc = to_mtk_crtc(c: crtc);
992 if (!mtk_crtc)
993 return NULL;
994
995 return mtk_crtc->dma_dev;
996}
997
998int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
999 unsigned int path_len, int priv_data_index,
1000 const struct mtk_drm_route *conn_routes,
1001 unsigned int num_conn_routes)
1002{
1003 struct mtk_drm_private *priv = drm_dev->dev_private;
1004 struct device *dev = drm_dev->dev;
1005 struct mtk_crtc *mtk_crtc;
1006 unsigned int num_comp_planes = 0;
1007 int ret;
1008 int i;
1009 bool has_ctm = false;
1010 uint gamma_lut_size = 0;
1011 struct drm_crtc *tmp;
1012 int crtc_i = 0;
1013
1014 if (!path)
1015 return 0;
1016
1017 priv = priv->all_drm_private[priv_data_index];
1018
1019 drm_for_each_crtc(tmp, drm_dev)
1020 crtc_i++;
1021
1022 for (i = 0; i < path_len; i++) {
1023 enum mtk_ddp_comp_id comp_id = path[i];
1024 struct device_node *node;
1025 struct mtk_ddp_comp *comp;
1026
1027 node = priv->comp_node[comp_id];
1028 comp = &priv->ddp_comp[comp_id];
1029
1030 /* Not all drm components have a DTS device node, such as ovl_adaptor,
1031 * which is the drm bring up sub driver
1032 */
1033 if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) {
1034 dev_info(dev,
1035 "Not creating crtc %d because component %d is disabled or missing\n",
1036 crtc_i, comp_id);
1037 return 0;
1038 }
1039
1040 if (!comp->dev) {
1041 dev_err(dev, "Component %pOF not initialized\n", node);
1042 return -ENODEV;
1043 }
1044 }
1045
1046 mtk_crtc = devm_kzalloc(dev, size: sizeof(*mtk_crtc), GFP_KERNEL);
1047 if (!mtk_crtc)
1048 return -ENOMEM;
1049
1050 mtk_crtc->mmsys_dev = priv->mmsys_dev;
1051 mtk_crtc->ddp_comp_nr = path_len;
1052 mtk_crtc->ddp_comp = devm_kcalloc(dev,
1053 n: mtk_crtc->ddp_comp_nr + (conn_routes ? 1 : 0),
1054 size: sizeof(*mtk_crtc->ddp_comp),
1055 GFP_KERNEL);
1056 if (!mtk_crtc->ddp_comp)
1057 return -ENOMEM;
1058
1059 mtk_crtc->mutex = mtk_mutex_get(dev: priv->mutex_dev);
1060 if (IS_ERR(ptr: mtk_crtc->mutex)) {
1061 ret = PTR_ERR(ptr: mtk_crtc->mutex);
1062 dev_err(dev, "Failed to get mutex: %d\n", ret);
1063 return ret;
1064 }
1065
1066 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1067 unsigned int comp_id = path[i];
1068 struct mtk_ddp_comp *comp;
1069
1070 comp = &priv->ddp_comp[comp_id];
1071 mtk_crtc->ddp_comp[i] = comp;
1072
1073 if (comp->funcs) {
1074 if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) {
1075 unsigned int lut_sz = mtk_ddp_gamma_get_lut_size(comp);
1076
1077 if (lut_sz)
1078 gamma_lut_size = lut_sz;
1079 }
1080
1081 if (comp->funcs->ctm_set)
1082 has_ctm = true;
1083 }
1084
1085 mtk_ddp_comp_register_vblank_cb(comp, vblank_cb: mtk_crtc_ddp_irq,
1086 vblank_cb_data: &mtk_crtc->base);
1087 }
1088
1089 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
1090 num_comp_planes += mtk_crtc_num_comp_planes(mtk_crtc, comp_idx: i);
1091
1092 mtk_crtc->planes = devm_kcalloc(dev, n: num_comp_planes,
1093 size: sizeof(struct drm_plane), GFP_KERNEL);
1094 if (!mtk_crtc->planes)
1095 return -ENOMEM;
1096
1097 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1098 ret = mtk_crtc_init_comp_planes(drm_dev, mtk_crtc, comp_idx: i, pipe: crtc_i);
1099 if (ret)
1100 return ret;
1101 }
1102
1103 /*
1104 * Default to use the first component as the dma dev.
1105 * In the case of ovl_adaptor sub driver, it needs to use the
1106 * dma_dev_get function to get representative dma dev.
1107 */
1108 mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(comp: &priv->ddp_comp[path[0]]);
1109
1110 ret = mtk_crtc_init(drm: drm_dev, mtk_crtc, pipe: crtc_i);
1111 if (ret < 0)
1112 return ret;
1113
1114 if (gamma_lut_size)
1115 drm_mode_crtc_set_gamma_size(crtc: &mtk_crtc->base, gamma_size: gamma_lut_size);
1116 drm_crtc_enable_color_mgmt(crtc: &mtk_crtc->base, degamma_lut_size: 0, has_ctm, gamma_lut_size);
1117 mutex_init(&mtk_crtc->hw_lock);
1118 spin_lock_init(&mtk_crtc->config_lock);
1119
1120#if IS_REACHABLE(CONFIG_MTK_CMDQ)
1121 i = priv->mbox_index++;
1122 mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;
1123 mtk_crtc->cmdq_client.client.tx_block = false;
1124 mtk_crtc->cmdq_client.client.knows_txdone = true;
1125 mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;
1126 mtk_crtc->cmdq_client.chan =
1127 mbox_request_channel(cl: &mtk_crtc->cmdq_client.client, index: i);
1128 if (IS_ERR(ptr: mtk_crtc->cmdq_client.chan)) {
1129 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
1130 drm_crtc_index(&mtk_crtc->base));
1131 mtk_crtc->cmdq_client.chan = NULL;
1132 }
1133
1134 if (mtk_crtc->cmdq_client.chan) {
1135 ret = of_property_read_u32_index(np: priv->mutex_node,
1136 propname: "mediatek,gce-events",
1137 index: i,
1138 out_value: &mtk_crtc->cmdq_event);
1139 if (ret) {
1140 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
1141 drm_crtc_index(&mtk_crtc->base));
1142 mbox_free_channel(chan: mtk_crtc->cmdq_client.chan);
1143 mtk_crtc->cmdq_client.chan = NULL;
1144 } else {
1145 ret = cmdq_pkt_create(client: &mtk_crtc->cmdq_client,
1146 pkt: &mtk_crtc->cmdq_handle,
1147 PAGE_SIZE);
1148 if (ret) {
1149 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
1150 drm_crtc_index(&mtk_crtc->base));
1151 mbox_free_channel(chan: mtk_crtc->cmdq_client.chan);
1152 mtk_crtc->cmdq_client.chan = NULL;
1153 }
1154 }
1155
1156 /* for sending blocking cmd in crtc disable */
1157 init_waitqueue_head(&mtk_crtc->cb_blocking_queue);
1158 }
1159#endif
1160
1161 if (conn_routes) {
1162 for (i = 0; i < num_conn_routes; i++) {
1163 unsigned int comp_id = conn_routes[i].route_ddp;
1164 struct device_node *node = priv->comp_node[comp_id];
1165 struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
1166
1167 if (!comp->dev) {
1168 dev_dbg(dev, "comp_id:%d, Component %pOF not initialized\n",
1169 comp_id, node);
1170 /* mark encoder_index to -1, if route comp device is not enabled */
1171 comp->encoder_index = -1;
1172 continue;
1173 }
1174
1175 mtk_ddp_comp_encoder_index_set(comp: &priv->ddp_comp[comp_id]);
1176 }
1177
1178 mtk_crtc->num_conn_routes = num_conn_routes;
1179 mtk_crtc->conn_routes = conn_routes;
1180
1181 /* increase ddp_comp_nr at the end of mtk_crtc_create */
1182 mtk_crtc->ddp_comp_nr++;
1183 }
1184
1185 return 0;
1186}
1187

source code of linux/drivers/gpu/drm/mediatek/mtk_crtc.c