| 1 | /* SPDX-License-Identifier: GPL-2.0-only |
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| 2 | * |
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| 3 | * Copyright © 2018-2020 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __KMB_REGS_H__ |
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| 7 | #define __KMB_REGS_H__ |
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| 8 | |
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| 9 | /*************************************************************************** |
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| 10 | * LCD controller control register defines |
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| 11 | ***************************************************************************/ |
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| 12 | #define LCD_CONTROL (0x4 * 0x000) |
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| 13 | #define LCD_CTRL_PROGRESSIVE (0 << 0) |
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| 14 | #define LCD_CTRL_INTERLACED BIT(0) |
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| 15 | #define LCD_CTRL_ENABLE BIT(1) |
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| 16 | #define LCD_CTRL_VL1_ENABLE BIT(2) |
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| 17 | #define LCD_CTRL_VL2_ENABLE BIT(3) |
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| 18 | #define LCD_CTRL_GL1_ENABLE BIT(4) |
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| 19 | #define LCD_CTRL_GL2_ENABLE BIT(5) |
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| 20 | #define LCD_CTRL_ALPHA_BLEND_VL1 (0 << 6) |
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| 21 | #define LCD_CTRL_ALPHA_BLEND_VL2 BIT(6) |
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| 22 | #define LCD_CTRL_ALPHA_BLEND_GL1 (2 << 6) |
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| 23 | #define LCD_CTRL_ALPHA_BLEND_GL2 (3 << 6) |
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| 24 | #define LCD_CTRL_ALPHA_TOP_VL1 (0 << 8) |
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| 25 | #define LCD_CTRL_ALPHA_TOP_VL2 BIT(8) |
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| 26 | #define LCD_CTRL_ALPHA_TOP_GL1 (2 << 8) |
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| 27 | #define LCD_CTRL_ALPHA_TOP_GL2 (3 << 8) |
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| 28 | #define LCD_CTRL_ALPHA_MIDDLE_VL1 (0 << 10) |
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| 29 | #define LCD_CTRL_ALPHA_MIDDLE_VL2 BIT(10) |
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| 30 | #define LCD_CTRL_ALPHA_MIDDLE_GL1 (2 << 10) |
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| 31 | #define LCD_CTRL_ALPHA_MIDDLE_GL2 (3 << 10) |
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| 32 | #define LCD_CTRL_ALPHA_BOTTOM_VL1 (0 << 12) |
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| 33 | #define LCD_CTRL_ALPHA_BOTTOM_VL2 BIT(12) |
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| 34 | #define LCD_CTRL_ALPHA_BOTTOM_GL1 (2 << 12) |
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| 35 | #define LCD_CTRL_ALPHA_BOTTOM_GL2 (3 << 12) |
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| 36 | #define LCD_CTRL_TIM_GEN_ENABLE BIT(14) |
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| 37 | #define LCD_CTRL_CONTINUOUS (0 << 15) |
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| 38 | #define LCD_CTRL_ONE_SHOT BIT(15) |
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| 39 | #define LCD_CTRL_PWM0_EN BIT(16) |
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| 40 | #define LCD_CTRL_PWM1_EN BIT(17) |
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| 41 | #define LCD_CTRL_PWM2_EN BIT(18) |
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| 42 | #define LCD_CTRL_OUTPUT_DISABLED (0 << 19) |
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| 43 | #define LCD_CTRL_OUTPUT_ENABLED BIT(19) |
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| 44 | #define LCD_CTRL_BPORCH_ENABLE BIT(21) |
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| 45 | #define LCD_CTRL_FPORCH_ENABLE BIT(22) |
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| 46 | #define LCD_CTRL_ALPHA_BLEND_BKGND_DISABLE BIT(23) |
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| 47 | #define LCD_CTRL_PIPELINE_DMA BIT(28) |
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| 48 | #define LCD_CTRL_VHSYNC_IDLE_LVL BIT(31) |
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| 49 | #define LCD_CTRL_ALPHA_ALL (0xff << 6) |
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| 50 | |
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| 51 | /* interrupts */ |
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| 52 | #define LCD_INT_STATUS (0x4 * 0x001) |
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| 53 | #define LCD_INT_EOF BIT(0) |
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| 54 | #define LCD_INT_LINE_CMP BIT(1) |
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| 55 | #define LCD_INT_VERT_COMP BIT(2) |
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| 56 | #define LAYER0_DMA_DONE BIT(3) |
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| 57 | #define LAYER0_DMA_IDLE BIT(4) |
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| 58 | #define LAYER0_DMA_FIFO_OVERFLOW BIT(5) |
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| 59 | #define LAYER0_DMA_FIFO_UNDERFLOW BIT(6) |
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| 60 | #define LAYER0_DMA_CB_FIFO_OVERFLOW BIT(7) |
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| 61 | #define LAYER0_DMA_CB_FIFO_UNDERFLOW BIT(8) |
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| 62 | #define LAYER0_DMA_CR_FIFO_OVERFLOW BIT(9) |
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| 63 | #define LAYER0_DMA_CR_FIFO_UNDERFLOW BIT(10) |
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| 64 | #define LAYER1_DMA_DONE BIT(11) |
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| 65 | #define LAYER1_DMA_IDLE BIT(12) |
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| 66 | #define LAYER1_DMA_FIFO_OVERFLOW BIT(13) |
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| 67 | #define LAYER1_DMA_FIFO_UNDERFLOW BIT(14) |
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| 68 | #define LAYER1_DMA_CB_FIFO_OVERFLOW BIT(15) |
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| 69 | #define LAYER1_DMA_CB_FIFO_UNDERFLOW BIT(16) |
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| 70 | #define LAYER1_DMA_CR_FIFO_OVERFLOW BIT(17) |
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| 71 | #define LAYER1_DMA_CR_FIFO_UNDERFLOW BIT(18) |
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| 72 | #define LAYER2_DMA_DONE BIT(19) |
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| 73 | #define LAYER2_DMA_IDLE BIT(20) |
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| 74 | #define LAYER2_DMA_FIFO_OVERFLOW BIT(21) |
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| 75 | #define LAYER2_DMA_FIFO_UNDERFLOW BIT(22) |
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| 76 | #define LAYER3_DMA_DONE BIT(23) |
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| 77 | #define LAYER3_DMA_IDLE BIT(24) |
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| 78 | #define LAYER3_DMA_FIFO_OVERFLOW BIT(25) |
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| 79 | #define LAYER3_DMA_FIFO_UNDERFLOW BIT(26) |
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| 80 | #define LCD_INT_LAYER (0x07fffff8) |
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| 81 | #define LCD_INT_ENABLE (0x4 * 0x002) |
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| 82 | #define LCD_INT_CLEAR (0x4 * 0x003) |
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| 83 | #define LCD_LINE_COUNT (0x4 * 0x004) |
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| 84 | #define LCD_LINE_COMPARE (0x4 * 0x005) |
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| 85 | #define LCD_VSTATUS (0x4 * 0x006) |
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| 86 | |
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| 87 | /*LCD_VSTATUS_COMPARE Vertcal interval in which to generate vertcal |
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| 88 | * interval interrupt |
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| 89 | */ |
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| 90 | /* BITS 13 and 14 */ |
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| 91 | #define LCD_VSTATUS_COMPARE (0x4 * 0x007) |
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| 92 | #define LCD_VSTATUS_VERTICAL_STATUS_MASK (3 << 13) |
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| 93 | #define LCD_VSTATUS_COMPARE_VSYNC (0 << 13) |
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| 94 | #define LCD_VSTATUS_COMPARE_BACKPORCH BIT(13) |
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| 95 | #define LCD_VSTATUS_COMPARE_ACTIVE (2 << 13) |
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| 96 | #define LCD_VSTATUS_COMPARE_FRONT_PORCH (3 << 13) |
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| 97 | |
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| 98 | #define LCD_SCREEN_WIDTH (0x4 * 0x008) |
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| 99 | #define LCD_SCREEN_HEIGHT (0x4 * 0x009) |
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| 100 | #define LCD_FIELD_INT_CFG (0x4 * 0x00a) |
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| 101 | #define LCD_FIFO_FLUSH (0x4 * 0x00b) |
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| 102 | #define LCD_BG_COLOUR_LS (0x4 * 0x00c) |
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| 103 | #define LCD_BG_COLOUR_MS (0x4 * 0x00d) |
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| 104 | #define LCD_RAM_CFG (0x4 * 0x00e) |
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| 105 | |
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| 106 | /**************************************************************************** |
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| 107 | * LCD controller Layer config register |
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| 108 | ***************************************************************************/ |
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| 109 | #define LCD_LAYER0_CFG (0x4 * 0x100) |
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| 110 | #define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400 * (N))) |
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| 111 | #define LCD_LAYER_SCALE_H BIT(1) |
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| 112 | #define LCD_LAYER_SCALE_V BIT(2) |
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| 113 | #define LCD_LAYER_SCALE_H_V (LCD_LAYER_SCALE_H | \ |
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| 114 | LCD_LAYER_SCALE_V) |
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| 115 | #define LCD_LAYER_CSC_EN BIT(3) |
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| 116 | #define LCD_LAYER_ALPHA_STATIC BIT(4) |
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| 117 | #define LCD_LAYER_ALPHA_EMBED BIT(5) |
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| 118 | #define LCD_LAYER_ALPHA_COMBI (LCD_LAYER_ALPHA_STATIC | \ |
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| 119 | LCD_LAYER_ALPHA_EMBED) |
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| 120 | #define LCD_LAYER_ALPHA_DISABLED ~(LCD_LAYER_ALPHA_COMBI) |
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| 121 | /* RGB multiplied with alpha */ |
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| 122 | #define LCD_LAYER_ALPHA_PREMULT BIT(6) |
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| 123 | #define LCD_LAYER_INVERT_COL BIT(7) |
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| 124 | #define LCD_LAYER_TRANSPARENT_EN BIT(8) |
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| 125 | #define LCD_LAYER_FORMAT_YCBCR444PLAN (0 << 9) |
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| 126 | #define LCD_LAYER_FORMAT_YCBCR422PLAN BIT(9) |
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| 127 | #define LCD_LAYER_FORMAT_YCBCR420PLAN (2 << 9) |
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| 128 | #define LCD_LAYER_FORMAT_RGB888PLAN (3 << 9) |
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| 129 | #define LCD_LAYER_FORMAT_YCBCR444LIN (4 << 9) |
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| 130 | #define LCD_LAYER_FORMAT_YCBCR422LIN (5 << 9) |
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| 131 | #define LCD_LAYER_FORMAT_RGB888 (6 << 9) |
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| 132 | #define LCD_LAYER_FORMAT_RGBA8888 (7 << 9) |
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| 133 | #define LCD_LAYER_FORMAT_RGBX8888 (8 << 9) |
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| 134 | #define LCD_LAYER_FORMAT_RGB565 (9 << 9) |
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| 135 | #define LCD_LAYER_FORMAT_RGBA1555 (0xa << 9) |
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| 136 | #define LCD_LAYER_FORMAT_XRGB1555 (0xb << 9) |
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| 137 | #define LCD_LAYER_FORMAT_RGB444 (0xc << 9) |
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| 138 | #define LCD_LAYER_FORMAT_RGBA4444 (0xd << 9) |
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| 139 | #define LCD_LAYER_FORMAT_RGBX4444 (0xe << 9) |
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| 140 | #define LCD_LAYER_FORMAT_RGB332 (0xf << 9) |
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| 141 | #define LCD_LAYER_FORMAT_RGBA3328 (0x10 << 9) |
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| 142 | #define LCD_LAYER_FORMAT_RGBX3328 (0x11 << 9) |
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| 143 | #define LCD_LAYER_FORMAT_CLUT (0x12 << 9) |
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| 144 | #define LCD_LAYER_FORMAT_NV12 (0x1c << 9) |
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| 145 | #define LCD_LAYER_PLANAR_STORAGE BIT(14) |
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| 146 | #define LCD_LAYER_8BPP (0 << 15) |
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| 147 | #define LCD_LAYER_16BPP BIT(15) |
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| 148 | #define LCD_LAYER_24BPP (2 << 15) |
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| 149 | #define LCD_LAYER_32BPP (3 << 15) |
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| 150 | #define LCD_LAYER_Y_ORDER BIT(17) |
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| 151 | #define LCD_LAYER_CRCB_ORDER BIT(18) |
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| 152 | #define LCD_LAYER_BGR_ORDER BIT(19) |
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| 153 | #define LCD_LAYER_LUT_2ENT (0 << 20) |
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| 154 | #define LCD_LAYER_LUT_4ENT BIT(20) |
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| 155 | #define LCD_LAYER_LUT_16ENT (2 << 20) |
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| 156 | #define LCD_LAYER_NO_FLIP (0 << 22) |
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| 157 | #define LCD_LAYER_FLIP_V BIT(22) |
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| 158 | #define LCD_LAYER_FLIP_H (2 << 22) |
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| 159 | #define LCD_LAYER_ROT_R90 (3 << 22) |
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| 160 | #define LCD_LAYER_ROT_L90 (4 << 22) |
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| 161 | #define LCD_LAYER_ROT_180 (5 << 22) |
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| 162 | #define LCD_LAYER_FIFO_00 (0 << 25) |
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| 163 | #define LCD_LAYER_FIFO_25 BIT(25) |
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| 164 | #define LCD_LAYER_FIFO_50 (2 << 25) |
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| 165 | #define LCD_LAYER_FIFO_100 (3 << 25) |
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| 166 | #define LCD_LAYER_INTERLEAVE_DIS (0 << 27) |
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| 167 | #define LCD_LAYER_INTERLEAVE_V BIT(27) |
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| 168 | #define LCD_LAYER_INTERLEAVE_H (2 << 27) |
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| 169 | #define LCD_LAYER_INTERLEAVE_CH (3 << 27) |
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| 170 | #define LCD_LAYER_INTERLEAVE_V_SUB (4 << 27) |
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| 171 | #define LCD_LAYER_INTERLEAVE_H_SUB (5 << 27) |
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| 172 | #define LCD_LAYER_INTERLEAVE_CH_SUB (6 << 27) |
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| 173 | #define LCD_LAYER_INTER_POS_EVEN (0 << 30) |
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| 174 | #define LCD_LAYER_INTER_POS_ODD BIT(30) |
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| 175 | |
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| 176 | #define LCD_LAYER0_COL_START (0x4 * 0x101) |
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| 177 | #define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400 * (N))) |
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| 178 | #define LCD_LAYER0_ROW_START (0x4 * 0x102) |
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| 179 | #define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400 * (N))) |
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| 180 | #define LCD_LAYER0_WIDTH (0x4 * 0x103) |
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| 181 | #define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400 * (N))) |
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| 182 | #define LCD_LAYER0_HEIGHT (0x4 * 0x104) |
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| 183 | #define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400 * (N))) |
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| 184 | #define LCD_LAYER0_SCALE_CFG (0x4 * 0x105) |
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| 185 | #define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400 * (N))) |
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| 186 | #define LCD_LAYER0_ALPHA (0x4 * 0x106) |
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| 187 | #define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400 * (N))) |
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| 188 | #define LCD_LAYER0_INV_COLOUR_LS (0x4 * 0x107) |
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| 189 | #define LCD_LAYERn_INV_COLOUR_LS(N) (LCD_LAYER0_INV_COLOUR_LS + \ |
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| 190 | (0x400 * (N))) |
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| 191 | #define LCD_LAYER0_INV_COLOUR_MS (0x4 * 0x108) |
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| 192 | #define LCD_LAYERn_INV_COLOUR_MS(N) (LCD_LAYER0_INV_COLOUR_MS + \ |
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| 193 | (0x400 * (N))) |
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| 194 | #define LCD_LAYER0_TRANS_COLOUR_LS (0x4 * 0x109) |
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| 195 | #define LCD_LAYERn_TRANS_COLOUR_LS(N) (LCD_LAYER0_TRANS_COLOUR_LS + \ |
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| 196 | (0x400 * (N))) |
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| 197 | #define LCD_LAYER0_TRANS_COLOUR_MS (0x4 * 0x10a) |
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| 198 | #define LCD_LAYERn_TRANS_COLOUR_MS(N) (LCD_LAYER0_TRANS_COLOUR_MS + \ |
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| 199 | (0x400 * (N))) |
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| 200 | #define LCD_LAYER0_CSC_COEFF11 (0x4 * 0x10b) |
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| 201 | #define LCD_LAYERn_CSC_COEFF11(N) (LCD_LAYER0_CSC_COEFF11 + (0x400 * (N))) |
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| 202 | #define LCD_LAYER0_CSC_COEFF12 (0x4 * 0x10c) |
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| 203 | #define LCD_LAYERn_CSC_COEFF12(N) (LCD_LAYER0_CSC_COEFF12 + (0x400 * (N))) |
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| 204 | #define LCD_LAYER0_CSC_COEFF13 (0x4 * 0x10d) |
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| 205 | #define LCD_LAYERn_CSC_COEFF13(N) (LCD_LAYER0_CSC_COEFF13 + (0x400 * (N))) |
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| 206 | #define LCD_LAYER0_CSC_COEFF21 (0x4 * 0x10e) |
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| 207 | #define LCD_LAYERn_CSC_COEFF21(N) (LCD_LAYER0_CSC_COEFF21 + (0x400 * (N))) |
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| 208 | #define LCD_LAYER0_CSC_COEFF22 (0x4 * 0x10f) |
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| 209 | #define LCD_LAYERn_CSC_COEFF22(N) (LCD_LAYER0_CSC_COEFF22 + (0x400 * (N))) |
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| 210 | #define LCD_LAYER0_CSC_COEFF23 (0x4 * 0x110) |
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| 211 | #define LCD_LAYERn_CSC_COEFF23(N) (LCD_LAYER0_CSC_COEFF23 + (0x400 * (N))) |
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| 212 | #define LCD_LAYER0_CSC_COEFF31 (0x4 * 0x111) |
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| 213 | #define LCD_LAYERn_CSC_COEFF31(N) (LCD_LAYER0_CSC_COEFF31 + (0x400 * (N))) |
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| 214 | #define LCD_LAYER0_CSC_COEFF32 (0x4 * 0x112) |
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| 215 | #define LCD_LAYERn_CSC_COEFF32(N) (LCD_LAYER0_CSC_COEFF32 + (0x400 * (N))) |
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| 216 | #define LCD_LAYER0_CSC_COEFF33 (0x4 * 0x113) |
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| 217 | #define LCD_LAYERn_CSC_COEFF33(N) (LCD_LAYER0_CSC_COEFF33 + (0x400 * (N))) |
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| 218 | #define LCD_LAYER0_CSC_OFF1 (0x4 * 0x114) |
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| 219 | #define LCD_LAYERn_CSC_OFF1(N) (LCD_LAYER0_CSC_OFF1 + (0x400 * (N))) |
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| 220 | #define LCD_LAYER0_CSC_OFF2 (0x4 * 0x115) |
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| 221 | #define LCD_LAYERn_CSC_OFF2(N) (LCD_LAYER0_CSC_OFF2 + (0x400 * (N))) |
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| 222 | #define LCD_LAYER0_CSC_OFF3 (0x4 * 0x116) |
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| 223 | #define LCD_LAYERn_CSC_OFF3(N) (LCD_LAYER0_CSC_OFF3 + (0x400 * (N))) |
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| 224 | |
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| 225 | /* LCD controller Layer DMA config register */ |
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| 226 | #define LCD_LAYER0_DMA_CFG (0x4 * 0x117) |
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| 227 | #define LCD_LAYERn_DMA_CFG(N) (LCD_LAYER0_DMA_CFG + \ |
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| 228 | (0x400 * (N))) |
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| 229 | #define LCD_DMA_LAYER_ENABLE BIT(0) |
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| 230 | #define LCD_DMA_LAYER_STATUS BIT(1) |
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| 231 | #define LCD_DMA_LAYER_AUTO_UPDATE BIT(2) |
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| 232 | #define LCD_DMA_LAYER_CONT_UPDATE BIT(3) |
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| 233 | #define LCD_DMA_LAYER_CONT_PING_PONG_UPDATE (LCD_DMA_LAYER_AUTO_UPDATE \ |
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| 234 | | LCD_DMA_LAYER_CONT_UPDATE) |
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| 235 | #define LCD_DMA_LAYER_FIFO_ADR_MODE BIT(4) |
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| 236 | #define LCD_DMA_LAYER_AXI_BURST_1 BIT(5) |
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| 237 | #define LCD_DMA_LAYER_AXI_BURST_2 (2 << 5) |
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| 238 | #define LCD_DMA_LAYER_AXI_BURST_3 (3 << 5) |
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| 239 | #define LCD_DMA_LAYER_AXI_BURST_4 (4 << 5) |
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| 240 | #define LCD_DMA_LAYER_AXI_BURST_5 (5 << 5) |
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| 241 | #define LCD_DMA_LAYER_AXI_BURST_6 (6 << 5) |
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| 242 | #define LCD_DMA_LAYER_AXI_BURST_7 (7 << 5) |
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| 243 | #define LCD_DMA_LAYER_AXI_BURST_8 (8 << 5) |
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| 244 | #define LCD_DMA_LAYER_AXI_BURST_9 (9 << 5) |
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| 245 | #define LCD_DMA_LAYER_AXI_BURST_10 (0xa << 5) |
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| 246 | #define LCD_DMA_LAYER_AXI_BURST_11 (0xb << 5) |
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| 247 | #define LCD_DMA_LAYER_AXI_BURST_12 (0xc << 5) |
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| 248 | #define LCD_DMA_LAYER_AXI_BURST_13 (0xd << 5) |
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| 249 | #define LCD_DMA_LAYER_AXI_BURST_14 (0xe << 5) |
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| 250 | #define LCD_DMA_LAYER_AXI_BURST_15 (0xf << 5) |
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| 251 | #define LCD_DMA_LAYER_AXI_BURST_16 (0x10 << 5) |
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| 252 | #define LCD_DMA_LAYER_VSTRIDE_EN BIT(10) |
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| 253 | |
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| 254 | #define LCD_LAYER0_DMA_START_ADR (0x4 * 0x118) |
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| 255 | #define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR \ |
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| 256 | + (0x400 * (N))) |
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| 257 | #define LCD_LAYER0_DMA_START_SHADOW (0x4 * 0x119) |
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| 258 | #define LCD_LAYERn_DMA_START_SHADOW(N) (LCD_LAYER0_DMA_START_SHADOW \ |
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| 259 | + (0x400 * (N))) |
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| 260 | #define LCD_LAYER0_DMA_LEN (0x4 * 0x11a) |
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| 261 | #define LCD_LAYERn_DMA_LEN(N) (LCD_LAYER0_DMA_LEN + \ |
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| 262 | (0x400 * (N))) |
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| 263 | #define LCD_LAYER0_DMA_LEN_SHADOW (0x4 * 0x11b) |
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| 264 | #define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + \ |
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| 265 | (0x400 * (N))) |
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| 266 | #define LCD_LAYER0_DMA_STATUS (0x4 * 0x11c) |
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| 267 | #define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + \ |
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| 268 | (0x400 * (N))) |
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| 269 | #define LCD_LAYER0_DMA_LINE_WIDTH (0x4 * 0x11d) |
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| 270 | #define LCD_LAYERn_DMA_LINE_WIDTH(N) (LCD_LAYER0_DMA_LINE_WIDTH + \ |
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| 271 | (0x400 * (N))) |
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| 272 | #define LCD_LAYER0_DMA_LINE_VSTRIDE (0x4 * 0x11e) |
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| 273 | #define LCD_LAYERn_DMA_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_LINE_VSTRIDE +\ |
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| 274 | (0x400 * (N))) |
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| 275 | #define LCD_LAYER0_DMA_FIFO_STATUS (0x4 * 0x11f) |
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| 276 | #define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + \ |
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| 277 | (0x400 * (N))) |
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| 278 | #define LCD_LAYER0_CFG2 (0x4 * 0x120) |
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| 279 | #define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400 * (N))) |
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| 280 | #define LCD_LAYER0_DMA_START_CB_ADR (0x4 * 0x700) |
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| 281 | #define LCD_LAYERn_DMA_START_CB_ADR(N) (LCD_LAYER0_DMA_START_CB_ADR + \ |
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| 282 | (0x20 * (N))) |
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| 283 | #define LCD_LAYER0_DMA_START_CB_SHADOW (0x4 * 0x701) |
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| 284 | #define LCD_LAYERn_DMA_START_CB_SHADOW(N) (LCD_LAYER0_DMA_START_CB_SHADOW\ |
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| 285 | + (0x20 * (N))) |
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| 286 | #define LCD_LAYER0_DMA_CB_LINE_WIDTH (0x4 * 0x702) |
|---|
| 287 | #define LCD_LAYERn_DMA_CB_LINE_WIDTH(N) (LCD_LAYER0_DMA_CB_LINE_WIDTH +\ |
|---|
| 288 | (0x20 * (N))) |
|---|
| 289 | #define LCD_LAYER0_DMA_CB_LINE_VSTRIDE (0x4 * 0x703) |
|---|
| 290 | #define LCD_LAYERn_DMA_CB_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_CB_LINE_VSTRIDE\ |
|---|
| 291 | + (0x20 * (N))) |
|---|
| 292 | #define LCD_LAYER0_DMA_START_CR_ADR (0x4 * 0x704) |
|---|
| 293 | #define LCD_LAYERn_DMA_START_CR_ADR(N) (LCD_LAYER0_DMA_START_CR_ADR + \ |
|---|
| 294 | (0x20 * (N))) |
|---|
| 295 | #define LCD_LAYER0_DMA_START_CR_SHADOW (0x4 * 0x705) |
|---|
| 296 | #define LCD_LAYERn_DMA_START_CR_SHADOW(N) \ |
|---|
| 297 | (LCD_LAYER0_DMA_START_CR_SHADOW\ |
|---|
| 298 | + (0x20 * (N))) |
|---|
| 299 | #define LCD_LAYER0_DMA_CR_LINE_WIDTH (0x4 * 0x706) |
|---|
| 300 | #define LCD_LAYERn_DMA_CR_LINE_WIDTH(N) (LCD_LAYER0_DMA_CR_LINE_WIDTH +\ |
|---|
| 301 | (0x20 * (N))) |
|---|
| 302 | #define LCD_LAYER0_DMA_CR_LINE_VSTRIDE (0x4 * 0x707) |
|---|
| 303 | #define LCD_LAYERn_DMA_CR_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_CR_LINE_VSTRIDE\ |
|---|
| 304 | + (0x20 * (N))) |
|---|
| 305 | #define LCD_LAYER1_DMA_START_CB_ADR (0x4 * 0x708) |
|---|
| 306 | #define LCD_LAYER1_DMA_START_CB_SHADOW (0x4 * 0x709) |
|---|
| 307 | #define LCD_LAYER1_DMA_CB_LINE_WIDTH (0x4 * 0x70a) |
|---|
| 308 | #define LCD_LAYER1_DMA_CB_LINE_VSTRIDE (0x4 * 0x70b) |
|---|
| 309 | #define LCD_LAYER1_DMA_START_CR_ADR (0x4 * 0x70c) |
|---|
| 310 | #define LCD_LAYER1_DMA_START_CR_SHADOW (0x4 * 0x70d) |
|---|
| 311 | #define LCD_LAYER1_DMA_CR_LINE_WIDTH (0x4 * 0x70e) |
|---|
| 312 | #define LCD_LAYER1_DMA_CR_LINE_VSTRIDE (0x4 * 0x70f) |
|---|
| 313 | |
|---|
| 314 | /**************************************************************************** |
|---|
| 315 | * LCD controller output format register defines |
|---|
| 316 | ***************************************************************************/ |
|---|
| 317 | #define LCD_OUT_FORMAT_CFG (0x4 * 0x800) |
|---|
| 318 | #define LCD_OUTF_FORMAT_RGB121212 (0x00) |
|---|
| 319 | #define LCD_OUTF_FORMAT_RGB101010 (0x01) |
|---|
| 320 | #define LCD_OUTF_FORMAT_RGB888 (0x02) |
|---|
| 321 | #define LCD_OUTF_FORMAT_RGB666 (0x03) |
|---|
| 322 | #define LCD_OUTF_FORMAT_RGB565 (0x04) |
|---|
| 323 | #define LCD_OUTF_FORMAT_RGB444 (0x05) |
|---|
| 324 | #define LCD_OUTF_FORMAT_MRGB121212 (0x10) |
|---|
| 325 | #define LCD_OUTF_FORMAT_MRGB101010 (0x11) |
|---|
| 326 | #define LCD_OUTF_FORMAT_MRGB888 (0x12) |
|---|
| 327 | #define LCD_OUTF_FORMAT_MRGB666 (0x13) |
|---|
| 328 | #define LCD_OUTF_FORMAT_MRGB565 (0x14) |
|---|
| 329 | #define LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08) |
|---|
| 330 | #define LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09) |
|---|
| 331 | #define LCD_OUTF_FORMAT_YCBCR420_8B (0x0A) |
|---|
| 332 | #define LCD_OUTF_FORMAT_YCBCR420_10B (0x0B) |
|---|
| 333 | #define LCD_OUTF_FORMAT_YCBCR420_12B (0x0C) |
|---|
| 334 | #define LCD_OUTF_FORMAT_YCBCR422_8B (0x0D) |
|---|
| 335 | #define LCD_OUTF_FORMAT_YCBCR422_10B (0x0E) |
|---|
| 336 | #define LCD_OUTF_FORMAT_YCBCR444 (0x0F) |
|---|
| 337 | #define LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18) |
|---|
| 338 | #define LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19) |
|---|
| 339 | #define LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A) |
|---|
| 340 | #define LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B) |
|---|
| 341 | #define LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C) |
|---|
| 342 | #define LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D) |
|---|
| 343 | #define LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E) |
|---|
| 344 | #define LCD_OUTF_FORMAT_MYCBCR444 (0x1F) |
|---|
| 345 | #define LCD_OUTF_BGR_ORDER BIT(5) |
|---|
| 346 | #define LCD_OUTF_Y_ORDER BIT(6) |
|---|
| 347 | #define LCD_OUTF_CRCB_ORDER BIT(7) |
|---|
| 348 | #define LCD_OUTF_SYNC_MODE BIT(11) |
|---|
| 349 | #define LCD_OUTF_RGB_CONV_MODE BIT(14) |
|---|
| 350 | #define LCD_OUTF_MIPI_RGB_MODE BIT(18) |
|---|
| 351 | |
|---|
| 352 | #define LCD_HSYNC_WIDTH (0x4 * 0x801) |
|---|
| 353 | #define LCD_H_BACKPORCH (0x4 * 0x802) |
|---|
| 354 | #define LCD_H_ACTIVEWIDTH (0x4 * 0x803) |
|---|
| 355 | #define LCD_H_FRONTPORCH (0x4 * 0x804) |
|---|
| 356 | #define LCD_VSYNC_WIDTH (0x4 * 0x805) |
|---|
| 357 | #define LCD_V_BACKPORCH (0x4 * 0x806) |
|---|
| 358 | #define LCD_V_ACTIVEHEIGHT (0x4 * 0x807) |
|---|
| 359 | #define LCD_V_FRONTPORCH (0x4 * 0x808) |
|---|
| 360 | #define LCD_VSYNC_START (0x4 * 0x809) |
|---|
| 361 | #define LCD_VSYNC_END (0x4 * 0x80a) |
|---|
| 362 | #define LCD_V_BACKPORCH_EVEN (0x4 * 0x80b) |
|---|
| 363 | #define LCD_VSYNC_WIDTH_EVEN (0x4 * 0x80c) |
|---|
| 364 | #define LCD_V_ACTIVEHEIGHT_EVEN (0x4 * 0x80d) |
|---|
| 365 | #define LCD_V_FRONTPORCH_EVEN (0x4 * 0x80e) |
|---|
| 366 | #define LCD_VSYNC_START_EVEN (0x4 * 0x80f) |
|---|
| 367 | #define LCD_VSYNC_END_EVEN (0x4 * 0x810) |
|---|
| 368 | #define LCD_TIMING_GEN_TRIG (0x4 * 0x811) |
|---|
| 369 | #define LCD_PWM0_CTRL (0x4 * 0x812) |
|---|
| 370 | #define LCD_PWM0_RPT_LEADIN (0x4 * 0x813) |
|---|
| 371 | #define LCD_PWM0_HIGH_LOW (0x4 * 0x814) |
|---|
| 372 | #define LCD_PWM1_CTRL (0x4 * 0x815) |
|---|
| 373 | #define LCD_PWM1_RPT_LEADIN (0x4 * 0x816) |
|---|
| 374 | #define LCD_PWM1_HIGH_LOW (0x4 * 0x817) |
|---|
| 375 | #define LCD_PWM2_CTRL (0x4 * 0x818) |
|---|
| 376 | #define LCD_PWM2_RPT_LEADIN (0x4 * 0x819) |
|---|
| 377 | #define LCD_PWM2_HIGH_LOW (0x4 * 0x81a) |
|---|
| 378 | #define LCD_VIDEO0_DMA0_BYTES (0x4 * 0xb00) |
|---|
| 379 | #define LCD_VIDEO0_DMA0_STATE (0x4 * 0xb01) |
|---|
| 380 | #define LCD_DMA_STATE_ACTIVE BIT(3) |
|---|
| 381 | #define LCD_VIDEO0_DMA1_BYTES (0x4 * 0xb02) |
|---|
| 382 | #define LCD_VIDEO0_DMA1_STATE (0x4 * 0xb03) |
|---|
| 383 | #define LCD_VIDEO0_DMA2_BYTES (0x4 * 0xb04) |
|---|
| 384 | #define LCD_VIDEO0_DMA2_STATE (0x4 * 0xb05) |
|---|
| 385 | #define LCD_VIDEO1_DMA0_BYTES (0x4 * 0xb06) |
|---|
| 386 | #define LCD_VIDEO1_DMA0_STATE (0x4 * 0xb07) |
|---|
| 387 | #define LCD_VIDEO1_DMA1_BYTES (0x4 * 0xb08) |
|---|
| 388 | #define LCD_VIDEO1_DMA1_STATE (0x4 * 0xb09) |
|---|
| 389 | #define LCD_VIDEO1_DMA2_BYTES (0x4 * 0xb0a) |
|---|
| 390 | #define LCD_VIDEO1_DMA2_STATE (0x4 * 0xb0b) |
|---|
| 391 | #define LCD_GRAPHIC0_DMA_BYTES (0x4 * 0xb0c) |
|---|
| 392 | #define LCD_GRAPHIC0_DMA_STATE (0x4 * 0xb0d) |
|---|
| 393 | #define LCD_GRAPHIC1_DMA_BYTES (0x4 * 0xb0e) |
|---|
| 394 | #define LCD_GRAPHIC1_DMA_STATE (0x4 * 0xb0f) |
|---|
| 395 | |
|---|
| 396 | /*************************************************************************** |
|---|
| 397 | * MIPI controller control register defines |
|---|
| 398 | *************************************************************************/ |
|---|
| 399 | #define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400) |
|---|
| 400 | #define HS_OFFSET(M) (((M) + 1) * 0x400) |
|---|
| 401 | |
|---|
| 402 | #define MIPI_TX_HS_CTRL (0x0) |
|---|
| 403 | #define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M)) |
|---|
| 404 | #define HS_CTRL_EN BIT(0) |
|---|
| 405 | /* 1:CSI 0:DSI */ |
|---|
| 406 | #define HS_CTRL_CSIDSIN BIT(2) |
|---|
| 407 | /* 1:LCD, 0:DMA */ |
|---|
| 408 | #define TX_SOURCE BIT(3) |
|---|
| 409 | #define ACTIVE_LANES(n) ((n) << 4) |
|---|
| 410 | #define LCD_VC(ch) ((ch) << 8) |
|---|
| 411 | #define DSI_EOTP_EN BIT(11) |
|---|
| 412 | #define DSI_CMD_HFP_EN BIT(12) |
|---|
| 413 | #define CRC_EN BIT(14) |
|---|
| 414 | #define HSEXIT_CNT(n) ((n) << 16) |
|---|
| 415 | #define HSCLKIDLE_CNT BIT(24) |
|---|
| 416 | #define MIPI_TX_HS_SYNC_CFG (0x8) |
|---|
| 417 | #define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \ |
|---|
| 418 | + HS_OFFSET(M)) |
|---|
| 419 | #define LINE_SYNC_PKT_ENABLE BIT(0) |
|---|
| 420 | #define FRAME_COUNTER_ACTIVE BIT(1) |
|---|
| 421 | #define LINE_COUNTER_ACTIVE BIT(2) |
|---|
| 422 | #define DSI_V_BLANKING BIT(4) |
|---|
| 423 | #define DSI_HSA_BLANKING BIT(5) |
|---|
| 424 | #define DSI_HBP_BLANKING BIT(6) |
|---|
| 425 | #define DSI_HFP_BLANKING BIT(7) |
|---|
| 426 | #define DSI_SYNC_PULSE_EVENTN BIT(8) |
|---|
| 427 | #define DSI_LPM_FIRST_VSA_LINE BIT(9) |
|---|
| 428 | #define DSI_LPM_LAST_VFP_LINE BIT(10) |
|---|
| 429 | #define WAIT_ALL_SECT BIT(11) |
|---|
| 430 | #define WAIT_TRIG_POS BIT(15) |
|---|
| 431 | #define ALWAYS_USE_HACT(f) ((f) << 19) |
|---|
| 432 | #define FRAME_GEN_EN(f) ((f) << 23) |
|---|
| 433 | #define HACT_WAIT_STOP(f) ((f) << 28) |
|---|
| 434 | #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) |
|---|
| 435 | #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ |
|---|
| 436 | HS_OFFSET(M) + (0x2C * (N)) \ |
|---|
| 437 | + (8 * (O))) |
|---|
| 438 | #define MIPI_TX_SECT_WC_MASK (0xffff) |
|---|
| 439 | #define MIPI_TX_SECT_VC_MASK (3) |
|---|
| 440 | #define MIPI_TX_SECT_VC_SHIFT (22) |
|---|
| 441 | #define MIPI_TX_SECT_DT_MASK (0x3f) |
|---|
| 442 | #define MIPI_TX_SECT_DT_SHIFT (16) |
|---|
| 443 | #define MIPI_TX_SECT_DM_MASK (3) |
|---|
| 444 | #define MIPI_TX_SECT_DM_SHIFT (24) |
|---|
| 445 | #define MIPI_TX_SECT_DMA_PACKED BIT(26) |
|---|
| 446 | #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60) |
|---|
| 447 | #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64) |
|---|
| 448 | #define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ |
|---|
| 449 | (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 \ |
|---|
| 450 | + HS_OFFSET(M) + (0x2C * (N))) |
|---|
| 451 | #define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44) |
|---|
| 452 | #define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \ |
|---|
| 453 | (MIPI_TX_HS_FG0_SECT0_LINE_CFG + HS_OFFSET(M) \ |
|---|
| 454 | + (0x2C * (N)) + (8 * (O))) |
|---|
| 455 | |
|---|
| 456 | #define MIPI_TX_HS_FG0_NUM_LINES (0x68) |
|---|
| 457 | #define MIPI_TXm_HS_FGn_NUM_LINES(M, N) \ |
|---|
| 458 | (MIPI_TX_HS_FG0_NUM_LINES + HS_OFFSET(M) \ |
|---|
| 459 | + (0x2C * (N))) |
|---|
| 460 | #define MIPI_TX_HS_VSYNC_WIDTHS0 (0x104) |
|---|
| 461 | #define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) \ |
|---|
| 462 | (MIPI_TX_HS_VSYNC_WIDTHS0 + HS_OFFSET(M) \ |
|---|
| 463 | + (0x4 * (N))) |
|---|
| 464 | #define MIPI_TX_HS_V_BACKPORCHES0 (0x16c) |
|---|
| 465 | #define MIPI_TXm_HS_V_BACKPORCHESn(M, N) \ |
|---|
| 466 | (MIPI_TX_HS_V_BACKPORCHES0 + HS_OFFSET(M) \ |
|---|
| 467 | + (0x4 * (N))) |
|---|
| 468 | #define MIPI_TX_HS_V_FRONTPORCHES0 (0x174) |
|---|
| 469 | #define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) \ |
|---|
| 470 | (MIPI_TX_HS_V_FRONTPORCHES0 + HS_OFFSET(M) \ |
|---|
| 471 | + (0x4 * (N))) |
|---|
| 472 | #define MIPI_TX_HS_V_ACTIVE0 (0x17c) |
|---|
| 473 | #define MIPI_TXm_HS_V_ACTIVEn(M, N) \ |
|---|
| 474 | (MIPI_TX_HS_V_ACTIVE0 + HS_OFFSET(M) \ |
|---|
| 475 | + (0x4 * (N))) |
|---|
| 476 | #define MIPI_TX_HS_HSYNC_WIDTH0 (0x10c) |
|---|
| 477 | #define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) \ |
|---|
| 478 | (MIPI_TX_HS_HSYNC_WIDTH0 + HS_OFFSET(M) \ |
|---|
| 479 | + (0x4 * (N))) |
|---|
| 480 | #define MIPI_TX_HS_H_BACKPORCH0 (0x11c) |
|---|
| 481 | #define MIPI_TXm_HS_H_BACKPORCHn(M, N) \ |
|---|
| 482 | (MIPI_TX_HS_H_BACKPORCH0 + HS_OFFSET(M) \ |
|---|
| 483 | + (0x4 * (N))) |
|---|
| 484 | #define MIPI_TX_HS_H_FRONTPORCH0 (0x12c) |
|---|
| 485 | #define MIPI_TXm_HS_H_FRONTPORCHn(M, N) \ |
|---|
| 486 | (MIPI_TX_HS_H_FRONTPORCH0 + HS_OFFSET(M) \ |
|---|
| 487 | + (0x4 * (N))) |
|---|
| 488 | #define MIPI_TX_HS_H_ACTIVE0 (0x184) |
|---|
| 489 | #define MIPI_TXm_HS_H_ACTIVEn(M, N) \ |
|---|
| 490 | (MIPI_TX_HS_H_ACTIVE0 + HS_OFFSET(M) \ |
|---|
| 491 | + (0x4 * (N))) |
|---|
| 492 | #define MIPI_TX_HS_LLP_HSYNC_WIDTH0 (0x13c) |
|---|
| 493 | #define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) \ |
|---|
| 494 | (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + HS_OFFSET(M) \ |
|---|
| 495 | + (0x4 * (N))) |
|---|
| 496 | #define MIPI_TX_HS_LLP_H_BACKPORCH0 (0x14c) |
|---|
| 497 | #define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) \ |
|---|
| 498 | (MIPI_TX_HS_LLP_H_BACKPORCH0 + HS_OFFSET(M) \ |
|---|
| 499 | + (0x4 * (N))) |
|---|
| 500 | #define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c) |
|---|
| 501 | #define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) \ |
|---|
| 502 | (MIPI_TX_HS_LLP_H_FRONTPORCH0 + HS_OFFSET(M) \ |
|---|
| 503 | + (0x4 * (N))) |
|---|
| 504 | |
|---|
| 505 | #define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194) |
|---|
| 506 | #define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) \ |
|---|
| 507 | (MIPI_TX_HS_MC_FIFO_CTRL_EN + HS_OFFSET(M)) |
|---|
| 508 | |
|---|
| 509 | #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198) |
|---|
| 510 | #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c) |
|---|
| 511 | #define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \ |
|---|
| 512 | (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \ |
|---|
| 513 | + (0x4 * (N))) |
|---|
| 514 | #define SET_MC_FIFO_CHAN_ALLOC(dev, ctrl, vc, sz) \ |
|---|
| 515 | kmb_write_bits_mipi(dev, \ |
|---|
| 516 | MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, \ |
|---|
| 517 | (vc) / 2), ((vc) % 2) * 16, 16, sz) |
|---|
| 518 | #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0) |
|---|
| 519 | #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4) |
|---|
| 520 | #define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \ |
|---|
| 521 | (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + HS_OFFSET(M) \ |
|---|
| 522 | + (0x4 * (N))) |
|---|
| 523 | #define SET_MC_FIFO_RTHRESHOLD(dev, ctrl, vc, th) \ |
|---|
| 524 | kmb_write_bits_mipi(dev, MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, \ |
|---|
| 525 | (vc) / 2), ((vc) % 2) * 16, 16, th) |
|---|
| 526 | #define MIPI_TX_HS_DMA_CFG (0x1a8) |
|---|
| 527 | #define MIPI_TX_HS_DMA_START_ADR_CHAN0 (0x1ac) |
|---|
| 528 | #define MIPI_TX_HS_DMA_LEN_CHAN0 (0x1b4) |
|---|
| 529 | |
|---|
| 530 | /* MIPI IRQ */ |
|---|
| 531 | #define MIPI_CTRL_IRQ_STATUS0 (0x00) |
|---|
| 532 | #define MIPI_DPHY_ERR_IRQ 1 |
|---|
| 533 | #define MIPI_DPHY_ERR_MASK 0x7FE /*bits 1-10 */ |
|---|
| 534 | #define MIPI_HS_IRQ 13 |
|---|
| 535 | /* bits 13-22 */ |
|---|
| 536 | #define MIPI_HS_IRQ_MASK 0x7FE000 |
|---|
| 537 | #define MIPI_LP_EVENT_IRQ 25 |
|---|
| 538 | #define MIPI_GET_IRQ_STAT0(dev) kmb_read_mipi(dev, \ |
|---|
| 539 | MIPI_CTRL_IRQ_STATUS0) |
|---|
| 540 | #define MIPI_CTRL_IRQ_STATUS1 (0x04) |
|---|
| 541 | #define MIPI_HS_RX_EVENT_IRQ 0 |
|---|
| 542 | #define MIPI_GET_IRQ_STAT1(dev) kmb_read_mipi(dev, \ |
|---|
| 543 | MIPI_CTRL_IRQ_STATUS1) |
|---|
| 544 | #define MIPI_CTRL_IRQ_ENABLE0 (0x08) |
|---|
| 545 | #define SET_MIPI_CTRL_IRQ_ENABLE0(dev, M, N) kmb_set_bit_mipi(dev, \ |
|---|
| 546 | MIPI_CTRL_IRQ_ENABLE0, \ |
|---|
| 547 | (M) + (N)) |
|---|
| 548 | #define MIPI_GET_IRQ_ENABLED0(dev) kmb_read_mipi(dev, \ |
|---|
| 549 | MIPI_CTRL_IRQ_ENABLE0) |
|---|
| 550 | #define MIPI_CTRL_IRQ_ENABLE1 (0x0c) |
|---|
| 551 | #define MIPI_GET_IRQ_ENABLED1(dev) kmb_read_mipi(dev, \ |
|---|
| 552 | MIPI_CTRL_IRQ_ENABLE1) |
|---|
| 553 | #define MIPI_CTRL_IRQ_CLEAR0 (0x010) |
|---|
| 554 | #define SET_MIPI_CTRL_IRQ_CLEAR0(dev, M, N) \ |
|---|
| 555 | kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR0, (M) + (N)) |
|---|
| 556 | #define MIPI_CTRL_IRQ_CLEAR1 (0x014) |
|---|
| 557 | #define SET_MIPI_CTRL_IRQ_CLEAR1(dev, M, N) \ |
|---|
| 558 | kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR1, (M) + (N)) |
|---|
| 559 | #define MIPI_CTRL_DIG_LOOPBACK (0x018) |
|---|
| 560 | #define MIPI_TX_HS_IRQ_STATUS (0x01c) |
|---|
| 561 | #define MIPI_TX_HS_IRQ_STATUSm(M) (MIPI_TX_HS_IRQ_STATUS + \ |
|---|
| 562 | HS_OFFSET(M)) |
|---|
| 563 | #define GET_MIPI_TX_HS_IRQ_STATUS(dev, M) kmb_read_mipi(dev, \ |
|---|
| 564 | MIPI_TX_HS_IRQ_STATUSm(M)) |
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| 565 | #define MIPI_TX_HS_IRQ_LINE_COMPARE BIT(1) |
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| 566 | #define MIPI_TX_HS_IRQ_FRAME_DONE_0 BIT(2) |
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| 567 | #define MIPI_TX_HS_IRQ_FRAME_DONE_1 BIT(3) |
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| 568 | #define MIPI_TX_HS_IRQ_FRAME_DONE_2 BIT(4) |
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| 569 | #define MIPI_TX_HS_IRQ_FRAME_DONE_3 BIT(5) |
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| 570 | #define MIPI_TX_HS_IRQ_DMA_DONE_0 BIT(6) |
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| 571 | #define MIPI_TX_HS_IRQ_DMA_IDLE_0 BIT(7) |
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| 572 | #define MIPI_TX_HS_IRQ_DMA_DONE_1 BIT(8) |
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| 573 | #define MIPI_TX_HS_IRQ_DMA_IDLE_1 BIT(9) |
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| 574 | #define MIPI_TX_HS_IRQ_DMA_DONE_2 BIT(10) |
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| 575 | #define MIPI_TX_HS_IRQ_DMA_IDLE_2 BIT(11) |
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| 576 | #define MIPI_TX_HS_IRQ_DMA_DONE_3 BIT(12) |
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| 577 | #define MIPI_TX_HS_IRQ_DMA_IDLE_3 BIT(13) |
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| 578 | #define MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW BIT(14) |
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| 579 | #define MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW BIT(15) |
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| 580 | #define MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY BIT(16) |
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| 581 | #define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL BIT(17) |
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| 582 | #define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR BIT(18) |
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| 583 | #define MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR BIT(20) |
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| 584 | #define MIPI_TX_HS_IRQ_FRAME_DONE \ |
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| 585 | (MIPI_TX_HS_IRQ_FRAME_DONE_0 | \ |
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| 586 | MIPI_TX_HS_IRQ_FRAME_DONE_1 | \ |
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| 587 | MIPI_TX_HS_IRQ_FRAME_DONE_2 | \ |
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| 588 | MIPI_TX_HS_IRQ_FRAME_DONE_3) |
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| 589 | |
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| 590 | #define MIPI_TX_HS_IRQ_DMA_DONE \ |
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| 591 | (MIPI_TX_HS_IRQ_DMA_DONE_0 | \ |
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| 592 | MIPI_TX_HS_IRQ_DMA_DONE_1 | \ |
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| 593 | MIPI_TX_HS_IRQ_DMA_DONE_2 | \ |
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| 594 | MIPI_TX_HS_IRQ_DMA_DONE_3) |
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| 595 | |
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| 596 | #define MIPI_TX_HS_IRQ_DMA_IDLE \ |
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| 597 | (MIPI_TX_HS_IRQ_DMA_IDLE_0 | \ |
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| 598 | MIPI_TX_HS_IRQ_DMA_IDLE_1 | \ |
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| 599 | MIPI_TX_HS_IRQ_DMA_IDLE_2 | \ |
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| 600 | MIPI_TX_HS_IRQ_DMA_IDLE_3) |
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| 601 | |
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| 602 | #define MIPI_TX_HS_IRQ_ERROR \ |
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| 603 | (MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW | \ |
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| 604 | MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW | \ |
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| 605 | MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY | \ |
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| 606 | MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL | \ |
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| 607 | MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR | \ |
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| 608 | MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR) |
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| 609 | |
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| 610 | #define MIPI_TX_HS_IRQ_ALL \ |
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| 611 | (MIPI_TX_HS_IRQ_FRAME_DONE | \ |
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| 612 | MIPI_TX_HS_IRQ_DMA_DONE | \ |
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| 613 | MIPI_TX_HS_IRQ_DMA_IDLE | \ |
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| 614 | MIPI_TX_HS_IRQ_LINE_COMPARE | \ |
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| 615 | MIPI_TX_HS_IRQ_ERROR) |
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| 616 | |
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| 617 | #define MIPI_TX_HS_IRQ_ENABLE (0x020) |
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| 618 | #define GET_HS_IRQ_ENABLE(dev, M) kmb_read_mipi(dev, \ |
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| 619 | MIPI_TX_HS_IRQ_ENABLE \ |
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| 620 | + HS_OFFSET(M)) |
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| 621 | #define MIPI_TX_HS_IRQ_CLEAR (0x024) |
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| 622 | |
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| 623 | /* MIPI Test Pattern Generation */ |
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| 624 | #define MIPI_TX_HS_TEST_PAT_CTRL (0x230) |
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| 625 | #define MIPI_TXm_HS_TEST_PAT_CTRL(M) \ |
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| 626 | (MIPI_TX_HS_TEST_PAT_CTRL + HS_OFFSET(M)) |
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| 627 | #define TP_EN_VCm(M) (1 << ((M) * 0x04)) |
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| 628 | #define TP_SEL_VCm(M, N) \ |
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| 629 | ((N) << (((M) * 0x04) + 1)) |
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| 630 | #define TP_STRIPE_WIDTH(M) ((M) << 16) |
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| 631 | #define MIPI_TX_HS_TEST_PAT_COLOR0 (0x234) |
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| 632 | #define MIPI_TXm_HS_TEST_PAT_COLOR0(M) \ |
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| 633 | (MIPI_TX_HS_TEST_PAT_COLOR0 + HS_OFFSET(M)) |
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| 634 | #define MIPI_TX_HS_TEST_PAT_COLOR1 (0x238) |
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| 635 | #define MIPI_TXm_HS_TEST_PAT_COLOR1(M) \ |
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| 636 | (MIPI_TX_HS_TEST_PAT_COLOR1 + HS_OFFSET(M)) |
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| 637 | |
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| 638 | /* D-PHY regs */ |
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| 639 | #define DPHY_ENABLE (0x100) |
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| 640 | #define DPHY_INIT_CTRL0 (0x104) |
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| 641 | #define SHUTDOWNZ 0 |
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| 642 | #define RESETZ 12 |
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| 643 | #define DPHY_INIT_CTRL1 (0x108) |
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| 644 | #define PLL_CLKSEL_0 18 |
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| 645 | #define PLL_SHADOW_CTRL 16 |
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| 646 | #define DPHY_INIT_CTRL2 (0x10c) |
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| 647 | #define SET_DPHY_INIT_CTRL0(dev, dphy, offset) \ |
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| 648 | kmb_set_bit_mipi(dev, DPHY_INIT_CTRL0, \ |
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| 649 | ((dphy) + (offset))) |
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| 650 | #define CLR_DPHY_INIT_CTRL0(dev, dphy, offset) \ |
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| 651 | kmb_clr_bit_mipi(dev, DPHY_INIT_CTRL0, \ |
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| 652 | ((dphy) + (offset))) |
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| 653 | #define DPHY_INIT_CTRL2 (0x10c) |
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| 654 | #define DPHY_PLL_OBS0 (0x110) |
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| 655 | #define DPHY_PLL_OBS1 (0x114) |
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| 656 | #define DPHY_PLL_OBS2 (0x118) |
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| 657 | #define DPHY_FREQ_CTRL0_3 (0x11c) |
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| 658 | #define DPHY_FREQ_CTRL4_7 (0x120) |
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| 659 | #define SET_DPHY_FREQ_CTRL0_3(dev, dphy, val) \ |
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| 660 | kmb_write_bits_mipi(dev, DPHY_FREQ_CTRL0_3 \ |
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| 661 | + (((dphy) / 4) * 4), (dphy % 4) * 8, 6, val) |
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| 662 | |
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| 663 | #define DPHY_FORCE_CTRL0 (0x128) |
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| 664 | #define DPHY_FORCE_CTRL1 (0x12C) |
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| 665 | #define MIPI_DPHY_STAT0_3 (0x134) |
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| 666 | #define MIPI_DPHY_STAT4_7 (0x138) |
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| 667 | #define GET_STOPSTATE_DATA(dev, dphy) \ |
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| 668 | (((kmb_read_mipi(dev, MIPI_DPHY_STAT0_3 + \ |
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| 669 | ((dphy) / 4) * 4)) >> \ |
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| 670 | (((dphy % 4) * 8) + 4)) & 0x03) |
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| 671 | |
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| 672 | #define MIPI_DPHY_ERR_STAT6_7 (0x14C) |
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| 673 | |
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| 674 | #define DPHY_TEST_CTRL0 (0x154) |
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| 675 | #define SET_DPHY_TEST_CTRL0(dev, dphy) \ |
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| 676 | kmb_set_bit_mipi(dev, DPHY_TEST_CTRL0, (dphy)) |
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| 677 | #define CLR_DPHY_TEST_CTRL0(dev, dphy) \ |
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| 678 | kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL0, \ |
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| 679 | (dphy)) |
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| 680 | #define DPHY_TEST_CTRL1 (0x158) |
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| 681 | #define SET_DPHY_TEST_CTRL1_CLK(dev, dphy) \ |
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| 682 | kmb_set_bit_mipi(dev, DPHY_TEST_CTRL1, (dphy)) |
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| 683 | #define CLR_DPHY_TEST_CTRL1_CLK(dev, dphy) \ |
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| 684 | kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL1, (dphy)) |
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| 685 | #define SET_DPHY_TEST_CTRL1_EN(dev, dphy) \ |
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| 686 | kmb_set_bit_mipi(dev, DPHY_TEST_CTRL1, ((dphy) + 12)) |
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| 687 | #define CLR_DPHY_TEST_CTRL1_EN(dev, dphy) \ |
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| 688 | kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL1, ((dphy) + 12)) |
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| 689 | #define DPHY_TEST_DIN0_3 (0x15c) |
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| 690 | #define SET_TEST_DIN0_3(dev, dphy, val) \ |
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| 691 | kmb_write_mipi(dev, DPHY_TEST_DIN0_3 + \ |
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| 692 | 4, ((val) << (((dphy) % 4) * 8))) |
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| 693 | #define DPHY_TEST_DOUT0_3 (0x168) |
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| 694 | #define GET_TEST_DOUT0_3(dev, dphy) \ |
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| 695 | (kmb_read_mipi(dev, DPHY_TEST_DOUT0_3) \ |
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| 696 | >> (((dphy) % 4) * 8) & 0xff) |
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| 697 | #define DPHY_TEST_DOUT4_7 (0x16C) |
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| 698 | #define GET_TEST_DOUT4_7(dev, dphy) \ |
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| 699 | (kmb_read_mipi(dev, DPHY_TEST_DOUT4_7) \ |
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| 700 | >> (((dphy) % 4) * 8) & 0xff) |
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| 701 | #define DPHY_TEST_DOUT8_9 (0x170) |
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| 702 | #define DPHY_TEST_DIN4_7 (0x160) |
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| 703 | #define DPHY_TEST_DIN8_9 (0x164) |
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| 704 | #define DPHY_PLL_LOCK (0x188) |
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| 705 | #define GET_PLL_LOCK(dev, dphy) \ |
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| 706 | (kmb_read_mipi(dev, DPHY_PLL_LOCK) \ |
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| 707 | & (1 << ((dphy) - MIPI_DPHY6))) |
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| 708 | #define DPHY_CFG_CLK_EN (0x18c) |
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| 709 | |
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| 710 | #define MSS_MIPI_CIF_CFG (0x00) |
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| 711 | #define MSS_LCD_MIPI_CFG (0x04) |
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| 712 | #define MSS_CAM_CLK_CTRL (0x10) |
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| 713 | #define MSS_LOOPBACK_CFG (0x0C) |
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| 714 | #define LCD BIT(1) |
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| 715 | #define MIPI_COMMON BIT(2) |
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| 716 | #define MIPI_TX0 BIT(9) |
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| 717 | #define MSS_CAM_RSTN_CTRL (0x14) |
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| 718 | #define MSS_CAM_RSTN_SET (0x20) |
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| 719 | #define MSS_CAM_RSTN_CLR (0x24) |
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| 720 | |
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| 721 | #define MSSCPU_CPR_CLK_EN (0x0) |
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| 722 | #define MSSCPU_CPR_RST_EN (0x10) |
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| 723 | #define BIT_MASK_16 (0xffff) |
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| 724 | /* icam lcd qos */ |
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| 725 | #define LCD_QOS_PRIORITY (0x8) |
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| 726 | #define LCD_QOS_MODE (0xC) |
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| 727 | #define LCD_QOS_BW (0x10) |
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| 728 | #endif /* __KMB_REGS_H__ */ |
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| 729 | |
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