| 1 | /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ |
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| 2 | /* Copyright (c) 2023 Imagination Technologies Ltd. */ |
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| 3 | |
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| 4 | #ifndef PVR_ROGUE_FWIF_COMMON_H |
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| 5 | #define PVR_ROGUE_FWIF_COMMON_H |
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| 6 | |
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| 7 | #include <linux/build_bug.h> |
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| 8 | |
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| 9 | /* |
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| 10 | * This macro represents a mask of LSBs that must be zero on data structure |
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| 11 | * sizes and offsets to ensure they are 8-byte granular on types shared between |
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| 12 | * the FW and host driver. |
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| 13 | */ |
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| 14 | #define PVR_FW_ALIGNMENT_LSB 7U |
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| 15 | |
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| 16 | /* Macro to test structure size alignment. */ |
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| 17 | #define PVR_FW_STRUCT_SIZE_ASSERT(_a) \ |
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| 18 | static_assert((sizeof(_a) & PVR_FW_ALIGNMENT_LSB) == 0U, \ |
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| 19 | "Size of " #_a " is not properly aligned") |
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| 20 | |
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| 21 | /* The master definition for data masters known to the firmware. */ |
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| 22 | |
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| 23 | #define PVR_FWIF_DM_GP (0) |
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| 24 | /* Either TDM or 2D DM is present. */ |
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| 25 | /* When the 'tla' feature is present in the hw (as per @pvr_device_features). */ |
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| 26 | #define PVR_FWIF_DM_2D (1) |
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| 27 | /* |
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| 28 | * When the 'fastrender_dm' feature is present in the hw (as per |
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| 29 | * @pvr_device_features). |
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| 30 | */ |
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| 31 | #define PVR_FWIF_DM_TDM (1) |
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| 32 | |
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| 33 | #define PVR_FWIF_DM_GEOM (2) |
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| 34 | #define PVR_FWIF_DM_FRAG (3) |
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| 35 | #define PVR_FWIF_DM_CDM (4) |
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| 36 | #define PVR_FWIF_DM_RAY (5) |
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| 37 | #define PVR_FWIF_DM_GEOM2 (6) |
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| 38 | #define PVR_FWIF_DM_GEOM3 (7) |
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| 39 | #define PVR_FWIF_DM_GEOM4 (8) |
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| 40 | |
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| 41 | #define PVR_FWIF_DM_LAST PVR_FWIF_DM_GEOM4 |
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| 42 | |
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| 43 | /* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RAY, GEOM2, GEOM3, GEOM4 */ |
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| 44 | #define PVR_FWIF_DM_MAX (PVR_FWIF_DM_LAST + 1U) |
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| 45 | |
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| 46 | /* GPU Utilisation states */ |
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| 47 | #define PVR_FWIF_GPU_UTIL_STATE_IDLE 0U |
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| 48 | #define PVR_FWIF_GPU_UTIL_STATE_ACTIVE 1U |
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| 49 | #define PVR_FWIF_GPU_UTIL_STATE_BLOCKED 2U |
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| 50 | #define PVR_FWIF_GPU_UTIL_STATE_NUM 3U |
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| 51 | #define PVR_FWIF_GPU_UTIL_STATE_MASK 0x3ULL |
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| 52 | |
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| 53 | /* |
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| 54 | * Maximum amount of register writes that can be done by the register |
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| 55 | * programmer (FW or META DMA). This is not a HW limitation, it is only |
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| 56 | * a protection against malformed inputs to the register programmer. |
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| 57 | */ |
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| 58 | #define PVR_MAX_NUM_REGISTER_PROGRAMMER_WRITES 128U |
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| 59 | |
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| 60 | #endif /* PVR_ROGUE_FWIF_COMMON_H */ |
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| 61 | |
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