| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_MCHBAR_REGS__ |
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| 7 | #define __INTEL_MCHBAR_REGS__ |
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| 8 | |
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| 9 | #include "i915_reg_defs.h" |
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| 10 | |
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| 11 | /* |
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| 12 | * MCHBAR mirror. |
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| 13 | * |
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| 14 | * This mirrors the MCHBAR MMIO space whose location is determined by |
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| 15 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in |
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| 16 | * every way. It is not accessible from the CP register read instructions. |
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| 17 | * |
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| 18 | * Starting from Haswell, you can't write registers using the MCHBAR mirror, |
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| 19 | * just read. |
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| 20 | */ |
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| 21 | |
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| 22 | #define MCHBAR_MIRROR_BASE 0x10000 |
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| 23 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
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| 24 | |
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| 25 | #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) |
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| 26 | #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) |
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| 27 | #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) |
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| 28 | #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) |
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| 29 | #define G4X_STOLEN_RESERVED_ENABLE (1 << 0) |
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| 30 | |
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| 31 | /* Pineview MCH register contains DDR3 setting */ |
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| 32 | #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) |
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| 33 | #define CSHRDDR3CTL_DDR3 (1 << 2) |
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| 34 | |
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| 35 | /* 915-945 and GM965 MCH register controlling DRAM channel access */ |
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| 36 | #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) |
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| 37 | #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) |
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| 38 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) |
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| 39 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) |
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| 40 | #define DCC_ADDRESSING_MODE_MASK (3 << 0) |
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| 41 | #define DCC_CHANNEL_XOR_DISABLE (1 << 10) |
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| 42 | #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
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| 43 | #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) |
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| 44 | #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) |
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| 45 | |
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| 46 | /* 965 MCH register controlling DRAM channel configuration */ |
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| 47 | #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206) |
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| 48 | #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606) |
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| 49 | |
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| 50 | /* Clocking configuration register */ |
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| 51 | #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) |
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| 52 | #define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */ |
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| 53 | #define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */ |
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| 54 | #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ |
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| 55 | #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ |
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| 56 | #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ |
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| 57 | #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ |
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| 58 | #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ |
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| 59 | #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ |
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| 60 | #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ |
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| 61 | #define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */ |
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| 62 | #define CLKCFG_FSB_MASK (7 << 0) |
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| 63 | #define CLKCFG_MEM_533 (1 << 4) |
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| 64 | #define CLKCFG_MEM_667 (2 << 4) |
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| 65 | #define CLKCFG_MEM_800 (3 << 4) |
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| 66 | #define CLKCFG_MEM_MASK (7 << 4) |
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| 67 | |
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| 68 | #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) |
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| 69 | #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) |
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| 70 | |
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| 71 | #define TSC1 _MMIO(MCHBAR_MIRROR_BASE + 0x1001) |
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| 72 | #define TSE (1 << 0) |
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| 73 | #define TR1 _MMIO(MCHBAR_MIRROR_BASE + 0x1006) |
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| 74 | #define TSFS _MMIO(MCHBAR_MIRROR_BASE + 0x1020) |
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| 75 | #define TSFS_SLOPE_MASK 0x0000ff00 |
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| 76 | #define TSFS_SLOPE_SHIFT 8 |
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| 77 | #define TSFS_INTR_MASK 0x000000ff |
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| 78 | |
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| 79 | /* Memory latency timer register */ |
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| 80 | #define MLTR_ILK _MMIO(MCHBAR_MIRROR_BASE + 0x1222) |
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| 81 | /* the unit of memory self-refresh latency time is 0.5us */ |
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| 82 | #define MLTR_WM2_MASK REG_GENMASK(13, 8) |
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| 83 | #define MLTR_WM1_MASK REG_GENMASK(5, 0) |
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| 84 | |
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| 85 | #define CSIPLL0 _MMIO(MCHBAR_MIRROR_BASE + 0x2c10) |
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| 86 | #define DDRMPLL1 _MMIO(MCHBAR_MIRROR_BASE + 0x2c20) |
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| 87 | |
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| 88 | #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) |
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| 89 | #define ILK_GRDOM_FULL (0 << 1) |
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| 90 | #define ILK_GRDOM_RENDER (1 << 1) |
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| 91 | #define ILK_GRDOM_MEDIA (3 << 1) |
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| 92 | #define ILK_GRDOM_MASK (3 << 1) |
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| 93 | #define ILK_GRDOM_RESET_ENABLE (1 << 0) |
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| 94 | |
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| 95 | #define BXT_D_CR_DRP0_DUNIT8 0x1000 |
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| 96 | #define BXT_D_CR_DRP0_DUNIT9 0x1200 |
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| 97 | #define BXT_D_CR_DRP0_DUNIT_START 8 |
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| 98 | #define BXT_D_CR_DRP0_DUNIT_END 11 |
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| 99 | #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \ |
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| 100 | _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\ |
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| 101 | BXT_D_CR_DRP0_DUNIT9)) |
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| 102 | #define BXT_DRAM_RANK_MASK 0x3 |
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| 103 | #define BXT_DRAM_RANK_SINGLE 0x1 |
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| 104 | #define BXT_DRAM_RANK_DUAL 0x3 |
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| 105 | #define BXT_DRAM_WIDTH_MASK (0x3 << 4) |
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| 106 | #define BXT_DRAM_WIDTH_SHIFT 4 |
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| 107 | #define BXT_DRAM_WIDTH_X8 (0x0 << 4) |
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| 108 | #define BXT_DRAM_WIDTH_X16 (0x1 << 4) |
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| 109 | #define BXT_DRAM_WIDTH_X32 (0x2 << 4) |
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| 110 | #define BXT_DRAM_WIDTH_X64 (0x3 << 4) |
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| 111 | #define BXT_DRAM_SIZE_MASK (0x7 << 6) |
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| 112 | #define BXT_DRAM_SIZE_SHIFT 6 |
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| 113 | #define BXT_DRAM_SIZE_4GBIT (0x0 << 6) |
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| 114 | #define BXT_DRAM_SIZE_6GBIT (0x1 << 6) |
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| 115 | #define BXT_DRAM_SIZE_8GBIT (0x2 << 6) |
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| 116 | #define BXT_DRAM_SIZE_12GBIT (0x3 << 6) |
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| 117 | #define BXT_DRAM_SIZE_16GBIT (0x4 << 6) |
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| 118 | #define BXT_DRAM_TYPE_MASK (0x7 << 22) |
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| 119 | #define BXT_DRAM_TYPE_SHIFT 22 |
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| 120 | #define BXT_DRAM_TYPE_DDR3 (0x0 << 22) |
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| 121 | #define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22) |
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| 122 | #define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22) |
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| 123 | #define BXT_DRAM_TYPE_DDR4 (0x4 << 22) |
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| 124 | |
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| 125 | #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000) |
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| 126 | #define DG1_DRAM_T_RDPRE_MASK REG_GENMASK(16, 11) |
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| 127 | #define DG1_DRAM_T_RP_MASK REG_GENMASK(6, 0) |
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| 128 | #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004) |
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| 129 | #define DG1_DRAM_T_RCD_MASK REG_GENMASK(15, 9) |
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| 130 | #define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1) |
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| 131 | |
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| 132 | #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000) |
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| 133 | #define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0) |
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| 134 | #define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0) |
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| 135 | #define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0) |
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| 136 | #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0) |
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| 137 | #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0) |
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| 138 | |
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| 139 | /* snb MCH registers for reading the DRAM channel configuration */ |
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| 140 | #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) |
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| 141 | #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) |
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| 142 | #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) |
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| 143 | #define MAD_DIMM_ECC_MASK (0x3 << 24) |
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| 144 | #define MAD_DIMM_ECC_OFF (0x0 << 24) |
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| 145 | #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) |
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| 146 | #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) |
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| 147 | #define MAD_DIMM_ECC_ON (0x3 << 24) |
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| 148 | #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) |
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| 149 | #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) |
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| 150 | #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ |
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| 151 | #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ |
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| 152 | #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) |
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| 153 | #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) |
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| 154 | #define MAD_DIMM_A_SELECT (0x1 << 16) |
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| 155 | /* DIMM sizes are in multiples of 256mb. */ |
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| 156 | #define MAD_DIMM_B_SIZE_SHIFT 8 |
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| 157 | #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) |
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| 158 | #define MAD_DIMM_A_SIZE_SHIFT 0 |
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| 159 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) |
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| 160 | |
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| 161 | #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) |
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| 162 | #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) |
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| 163 | #define SKL_DRAM_S_SHIFT 16 |
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| 164 | #define SKL_DRAM_SIZE_MASK 0x3F |
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| 165 | #define SKL_DRAM_WIDTH_MASK (0x3 << 8) |
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| 166 | #define SKL_DRAM_WIDTH_SHIFT 8 |
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| 167 | #define SKL_DRAM_WIDTH_X8 (0x0 << 8) |
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| 168 | #define SKL_DRAM_WIDTH_X16 (0x1 << 8) |
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| 169 | #define SKL_DRAM_WIDTH_X32 (0x2 << 8) |
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| 170 | #define SKL_DRAM_RANK_MASK (0x1 << 10) |
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| 171 | #define SKL_DRAM_RANK_SHIFT 10 |
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| 172 | #define SKL_DRAM_RANK_1 (0x0 << 10) |
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| 173 | #define SKL_DRAM_RANK_2 (0x1 << 10) |
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| 174 | #define SKL_DRAM_RANK_MASK (0x1 << 10) |
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| 175 | #define ICL_DRAM_SIZE_MASK 0x7F |
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| 176 | #define ICL_DRAM_WIDTH_MASK (0x3 << 7) |
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| 177 | #define ICL_DRAM_WIDTH_SHIFT 7 |
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| 178 | #define ICL_DRAM_WIDTH_X8 (0x0 << 7) |
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| 179 | #define ICL_DRAM_WIDTH_X16 (0x1 << 7) |
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| 180 | #define ICL_DRAM_WIDTH_X32 (0x2 << 7) |
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| 181 | #define ICL_DRAM_RANK_MASK (0x3 << 9) |
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| 182 | #define ICL_DRAM_RANK_SHIFT 9 |
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| 183 | #define ICL_DRAM_RANK_1 (0x0 << 9) |
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| 184 | #define ICL_DRAM_RANK_2 (0x1 << 9) |
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| 185 | #define ICL_DRAM_RANK_3 (0x2 << 9) |
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| 186 | #define ICL_DRAM_RANK_4 (0x3 << 9) |
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| 187 | |
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| 188 | #define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918) |
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| 189 | #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2) |
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| 190 | #define DG1_QCLK_REFERENCE REG_BIT(10) |
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| 191 | |
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| 192 | /* |
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| 193 | * *_PACKAGE_POWER_SKU - SKU power and timing parameters. |
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| 194 | */ |
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| 195 | #define PCU_PACKAGE_POWER_SKU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5930) |
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| 196 | #define PKG_PKG_TDP GENMASK_ULL(14, 0) |
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| 197 | #define PKG_MIN_PWR GENMASK_ULL(30, 16) |
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| 198 | #define PKG_MAX_PWR GENMASK_ULL(46, 32) |
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| 199 | #define PKG_MAX_WIN GENMASK_ULL(54, 48) |
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| 200 | #define PKG_MAX_WIN_X GENMASK_ULL(54, 53) |
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| 201 | #define PKG_MAX_WIN_Y GENMASK_ULL(52, 48) |
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| 202 | |
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| 203 | #define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938) |
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| 204 | #define PKG_PWR_UNIT REG_GENMASK(3, 0) |
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| 205 | #define PKG_ENERGY_UNIT REG_GENMASK(12, 8) |
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| 206 | #define PKG_TIME_UNIT REG_GENMASK(19, 16) |
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| 207 | #define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c) |
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| 208 | |
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| 209 | #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) |
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| 210 | |
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| 211 | #define PCU_PACKAGE_TEMPERATURE _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5978) |
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| 212 | #define TEMP_MASK REG_GENMASK(7, 0) |
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| 213 | |
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| 214 | #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) |
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| 215 | #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) |
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| 216 | #define RP0_CAP_MASK REG_GENMASK(7, 0) |
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| 217 | #define RP1_CAP_MASK REG_GENMASK(15, 8) |
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| 218 | #define RPN_CAP_MASK REG_GENMASK(23, 16) |
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| 219 | |
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| 220 | #define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0) |
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| 221 | #define RPE_MASK REG_GENMASK(15, 8) |
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| 222 | #define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0) |
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| 223 | #define PKG_PWR_LIM_1 REG_GENMASK(14, 0) |
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| 224 | #define PKG_PWR_LIM_1_EN REG_BIT(15) |
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| 225 | #define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17) |
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| 226 | #define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22) |
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| 227 | #define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17) |
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| 228 | |
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| 229 | /* snb MCH registers for priority tuning */ |
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| 230 | #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) |
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| 231 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56) |
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| 232 | #define SSKPD_WM4_MASK_HSW REG_GENMASK64(40, 32) |
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| 233 | #define SSKPD_WM3_MASK_HSW REG_GENMASK64(28, 20) |
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| 234 | #define SSKPD_WM2_MASK_HSW REG_GENMASK64(19, 12) |
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| 235 | #define SSKPD_WM1_MASK_HSW REG_GENMASK64(11, 4) |
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| 236 | #define SSKPD_OLD_WM0_MASK_HSW REG_GENMASK64(3, 0) |
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| 237 | #define SSKPD_WM3_MASK_SNB REG_GENMASK(29, 24) |
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| 238 | #define SSKPD_WM2_MASK_SNB REG_GENMASK(21, 16) |
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| 239 | #define SSKPD_WM1_MASK_SNB REG_GENMASK(13, 8) |
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| 240 | #define SSKPD_WM0_MASK_SNB REG_GENMASK(5, 0) |
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| 241 | |
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| 242 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
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| 243 | #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
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| 244 | #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
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| 245 | #define DG1_GEAR_TYPE REG_BIT(16) |
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| 246 | |
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| 247 | /* |
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| 248 | * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
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| 249 | * since on HSW we can't write to it using intel_uncore_write. |
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| 250 | */ |
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| 251 | #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5f0c) |
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| 252 | #define D_COMP_RCOMP_IN_PROGRESS (1 << 9) |
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| 253 | #define D_COMP_COMP_FORCE (1 << 8) |
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| 254 | #define D_COMP_COMP_DISABLE (1 << 0) |
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| 255 | |
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| 256 | #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) |
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| 257 | |
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| 258 | #endif /* __INTEL_MCHBAR_REGS */ |
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| 259 | |
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