1/*
2 * Copyright © 2008-2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef I915_REQUEST_H
26#define I915_REQUEST_H
27
28#include <linux/dma-fence.h>
29#include <linux/hrtimer.h>
30#include <linux/irq_work.h>
31#include <linux/llist.h>
32#include <linux/lockdep.h>
33
34#include <uapi/drm/i915_drm.h>
35
36#include "gem/i915_gem_context_types.h"
37#include "gt/intel_context_types.h"
38#include "gt/intel_engine_types.h"
39#include "gt/intel_timeline_types.h"
40
41#include "i915_gem.h"
42#include "i915_ptr_util.h"
43#include "i915_scheduler.h"
44#include "i915_selftest.h"
45#include "i915_sw_fence.h"
46#include "i915_vma_resource.h"
47
48struct drm_file;
49struct drm_i915_gem_object;
50struct drm_printer;
51struct i915_deps;
52struct i915_request;
53
54#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
55struct i915_capture_list {
56 struct i915_vma_resource *vma_res;
57 struct i915_capture_list *next;
58};
59
60void i915_request_free_capture_list(struct i915_capture_list *capture);
61#else
62#define i915_request_free_capture_list(_a) do {} while (0)
63#endif
64
65#define RQ_TRACE(rq, fmt, ...) do { \
66 const struct i915_request *rq__ = (rq); \
67 ENGINE_TRACE(rq__->engine, "fence %llx:%lld, current %d " fmt, \
68 rq__->fence.context, rq__->fence.seqno, \
69 hwsp_seqno(rq__), ##__VA_ARGS__); \
70} while (0)
71
72enum {
73 /*
74 * I915_FENCE_FLAG_ACTIVE - this request is currently submitted to HW.
75 *
76 * Set by __i915_request_submit() on handing over to HW, and cleared
77 * by __i915_request_unsubmit() if we preempt this request.
78 *
79 * Finally cleared for consistency on retiring the request, when
80 * we know the HW is no longer running this request.
81 *
82 * See i915_request_is_active()
83 */
84 I915_FENCE_FLAG_ACTIVE = DMA_FENCE_FLAG_USER_BITS,
85
86 /*
87 * I915_FENCE_FLAG_PQUEUE - this request is ready for execution
88 *
89 * Using the scheduler, when a request is ready for execution it is put
90 * into the priority queue, and removed from that queue when transferred
91 * to the HW runlists. We want to track its membership within the
92 * priority queue so that we can easily check before rescheduling.
93 *
94 * See i915_request_in_priority_queue()
95 */
96 I915_FENCE_FLAG_PQUEUE,
97
98 /*
99 * I915_FENCE_FLAG_HOLD - this request is currently on hold
100 *
101 * This request has been suspended, pending an ongoing investigation.
102 */
103 I915_FENCE_FLAG_HOLD,
104
105 /*
106 * I915_FENCE_FLAG_INITIAL_BREADCRUMB - this request has the initial
107 * breadcrumb that marks the end of semaphore waits and start of the
108 * user payload.
109 */
110 I915_FENCE_FLAG_INITIAL_BREADCRUMB,
111
112 /*
113 * I915_FENCE_FLAG_SIGNAL - this request is currently on signal_list
114 *
115 * Internal bookkeeping used by the breadcrumb code to track when
116 * a request is on the various signal_list.
117 */
118 I915_FENCE_FLAG_SIGNAL,
119
120 /*
121 * I915_FENCE_FLAG_NOPREEMPT - this request should not be preempted
122 *
123 * The execution of some requests should not be interrupted. This is
124 * a sensitive operation as it makes the request super important,
125 * blocking other higher priority work. Abuse of this flag will
126 * lead to quality of service issues.
127 */
128 I915_FENCE_FLAG_NOPREEMPT,
129
130 /*
131 * I915_FENCE_FLAG_SENTINEL - this request should be last in the queue
132 *
133 * A high priority sentinel request may be submitted to clear the
134 * submission queue. As it will be the only request in-flight, upon
135 * execution all other active requests will have been preempted and
136 * unsubmitted. This preemptive pulse is used to re-evaluate the
137 * in-flight requests, particularly in cases where an active context
138 * is banned and those active requests need to be cancelled.
139 */
140 I915_FENCE_FLAG_SENTINEL,
141
142 /*
143 * I915_FENCE_FLAG_BOOST - upclock the gpu for this request
144 *
145 * Some requests are more important than others! In particular, a
146 * request that the user is waiting on is typically required for
147 * interactive latency, for which we want to minimise by upclocking
148 * the GPU. Here we track such boost requests on a per-request basis.
149 */
150 I915_FENCE_FLAG_BOOST,
151
152 /*
153 * I915_FENCE_FLAG_SUBMIT_PARALLEL - request with a context in a
154 * parent-child relationship (parallel submission, multi-lrc) should
155 * trigger a submission to the GuC rather than just moving the context
156 * tail.
157 */
158 I915_FENCE_FLAG_SUBMIT_PARALLEL,
159
160 /*
161 * I915_FENCE_FLAG_SKIP_PARALLEL - request with a context in a
162 * parent-child relationship (parallel submission, multi-lrc) that
163 * hit an error while generating requests in the execbuf IOCTL.
164 * Indicates this request should be skipped as another request in
165 * submission / relationship encountered an error.
166 */
167 I915_FENCE_FLAG_SKIP_PARALLEL,
168
169 /*
170 * I915_FENCE_FLAG_COMPOSITE - Indicates fence is part of a composite
171 * fence (dma_fence_array) and i915 generated for parallel submission.
172 */
173 I915_FENCE_FLAG_COMPOSITE,
174};
175
176/*
177 * Request queue structure.
178 *
179 * The request queue allows us to note sequence numbers that have been emitted
180 * and may be associated with active buffers to be retired.
181 *
182 * By keeping this list, we can avoid having to do questionable sequence
183 * number comparisons on buffer last_read|write_seqno. It also allows an
184 * emission time to be associated with the request for tracking how far ahead
185 * of the GPU the submission is.
186 *
187 * When modifying this structure be very aware that we perform a lockless
188 * RCU lookup of it that may race against reallocation of the struct
189 * from the slab freelist. We intentionally do not zero the structure on
190 * allocation so that the lookup can use the dangling pointers (and is
191 * cognisant that those pointers may be wrong). Instead, everything that
192 * needs to be initialised must be done so explicitly.
193 *
194 * The requests are reference counted.
195 */
196struct i915_request {
197 struct dma_fence fence;
198 spinlock_t lock;
199
200 struct drm_i915_private *i915;
201
202 /*
203 * Context and ring buffer related to this request
204 * Contexts are refcounted, so when this request is associated with a
205 * context, we must increment the context's refcount, to guarantee that
206 * it persists while any request is linked to it. Requests themselves
207 * are also refcounted, so the request will only be freed when the last
208 * reference to it is dismissed, and the code in
209 * i915_request_free() will then decrement the refcount on the
210 * context.
211 */
212 struct intel_engine_cs *engine;
213 struct intel_context *context;
214 struct intel_ring *ring;
215 struct intel_timeline __rcu *timeline;
216
217 struct list_head signal_link;
218 struct llist_node signal_node;
219
220 /*
221 * The rcu epoch of when this request was allocated. Used to judiciously
222 * apply backpressure on future allocations to ensure that under
223 * mempressure there is sufficient RCU ticks for us to reclaim our
224 * RCU protected slabs.
225 */
226 unsigned long rcustate;
227
228 /*
229 * We pin the timeline->mutex while constructing the request to
230 * ensure that no caller accidentally drops it during construction.
231 * The timeline->mutex must be held to ensure that only this caller
232 * can use the ring and manipulate the associated timeline during
233 * construction.
234 */
235 struct pin_cookie cookie;
236
237 /*
238 * Fences for the various phases in the request's lifetime.
239 *
240 * The submit fence is used to await upon all of the request's
241 * dependencies. When it is signaled, the request is ready to run.
242 * It is used by the driver to then queue the request for execution.
243 */
244 struct i915_sw_fence submit;
245 union {
246 wait_queue_entry_t submitq;
247 struct i915_sw_dma_fence_cb dmaq;
248 struct i915_request_duration_cb {
249 struct dma_fence_cb cb;
250 ktime_t emitted;
251 } duration;
252 };
253 struct llist_head execute_cb;
254 struct i915_sw_fence semaphore;
255 /*
256 * complete submit fence from an IRQ if needed for locking hierarchy
257 * reasons.
258 */
259 struct irq_work submit_work;
260
261 /*
262 * A list of everyone we wait upon, and everyone who waits upon us.
263 * Even though we will not be submitted to the hardware before the
264 * submit fence is signaled (it waits for all external events as well
265 * as our own requests), the scheduler still needs to know the
266 * dependency tree for the lifetime of the request (from execbuf
267 * to retirement), i.e. bidirectional dependency information for the
268 * request not tied to individual fences.
269 */
270 struct i915_sched_node sched;
271 struct i915_dependency dep;
272 intel_engine_mask_t execution_mask;
273
274 /*
275 * A convenience pointer to the current breadcrumb value stored in
276 * the HW status page (or our timeline's local equivalent). The full
277 * path would be rq->hw_context->ring->timeline->hwsp_seqno.
278 */
279 const u32 *hwsp_seqno;
280
281 /* Position in the ring of the start of the request */
282 u32 head;
283
284 /* Position in the ring of the start of the user packets */
285 u32 infix;
286
287 /*
288 * Position in the ring of the start of the postfix.
289 * This is required to calculate the maximum available ring space
290 * without overwriting the postfix.
291 */
292 u32 postfix;
293
294 /* Position in the ring of the end of the whole request */
295 u32 tail;
296
297 /* Position in the ring of the end of any workarounds after the tail */
298 u32 wa_tail;
299
300 /* Preallocate space in the ring for the emitting the request */
301 u32 reserved_space;
302
303 /* Batch buffer pointer for selftest internal use. */
304 I915_SELFTEST_DECLARE(struct i915_vma *batch);
305
306 struct i915_vma_resource *batch_res;
307
308#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
309 /*
310 * Additional buffers requested by userspace to be captured upon
311 * a GPU hang. The vma/obj on this list are protected by their
312 * active reference - all objects on this list must also be
313 * on the active_list (of their final request).
314 */
315 struct i915_capture_list *capture_list;
316#endif
317
318 /* Time at which this request was emitted, in jiffies. */
319 unsigned long emitted_jiffies;
320
321 /* timeline->request entry for this request */
322 struct list_head link;
323
324 /* Watchdog support fields. */
325 struct i915_request_watchdog {
326 struct llist_node link;
327 struct hrtimer timer;
328 } watchdog;
329
330 /*
331 * Requests may need to be stalled when using GuC submission waiting for
332 * certain GuC operations to complete. If that is the case, stalled
333 * requests are added to a per context list of stalled requests. The
334 * below list_head is the link in that list. Protected by
335 * ce->guc_state.lock.
336 */
337 struct list_head guc_fence_link;
338
339 /*
340 * Priority level while the request is in flight. Differs
341 * from i915 scheduler priority. See comment above
342 * I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP for details. Protected by
343 * ce->guc_active.lock. Two special values (GUC_PRIO_INIT and
344 * GUC_PRIO_FINI) outside the GuC priority range are used to indicate
345 * if the priority has not been initialized yet or if no more updates
346 * are possible because the request has completed.
347 */
348#define GUC_PRIO_INIT 0xff
349#define GUC_PRIO_FINI 0xfe
350 u8 guc_prio;
351
352 /*
353 * wait queue entry used to wait on the HuC load to complete
354 */
355 wait_queue_entry_t hucq;
356
357 I915_SELFTEST_DECLARE(struct {
358 struct list_head link;
359 unsigned long delay;
360 } mock;)
361};
362
363#define I915_FENCE_GFP (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
364
365extern const struct dma_fence_ops i915_fence_ops;
366
367static inline bool dma_fence_is_i915(const struct dma_fence *fence)
368{
369 return fence->ops == &i915_fence_ops;
370}
371
372struct kmem_cache *i915_request_slab_cache(void);
373
374struct i915_request * __must_check
375__i915_request_create(struct intel_context *ce, gfp_t gfp);
376struct i915_request * __must_check
377i915_request_create(struct intel_context *ce);
378
379void __i915_request_skip(struct i915_request *rq);
380bool i915_request_set_error_once(struct i915_request *rq, int error);
381struct i915_request *i915_request_mark_eio(struct i915_request *rq);
382
383struct i915_request *__i915_request_commit(struct i915_request *request);
384void __i915_request_queue(struct i915_request *rq,
385 const struct i915_sched_attr *attr);
386void __i915_request_queue_bh(struct i915_request *rq);
387
388bool i915_request_retire(struct i915_request *rq);
389void i915_request_retire_upto(struct i915_request *rq);
390
391static inline struct i915_request *
392to_request(struct dma_fence *fence)
393{
394 /* We assume that NULL fence/request are interoperable */
395 BUILD_BUG_ON(offsetof(struct i915_request, fence) != 0);
396 GEM_BUG_ON(fence && !dma_fence_is_i915(fence));
397 return container_of(fence, struct i915_request, fence);
398}
399
400static inline struct i915_request *
401i915_request_get(struct i915_request *rq)
402{
403 return to_request(fence: dma_fence_get(fence: &rq->fence));
404}
405
406static inline struct i915_request *
407i915_request_get_rcu(struct i915_request *rq)
408{
409 return to_request(fence: dma_fence_get_rcu(fence: &rq->fence));
410}
411
412static inline void
413i915_request_put(struct i915_request *rq)
414{
415 dma_fence_put(fence: &rq->fence);
416}
417
418int i915_request_await_object(struct i915_request *to,
419 struct drm_i915_gem_object *obj,
420 bool write);
421int i915_request_await_dma_fence(struct i915_request *rq,
422 struct dma_fence *fence);
423int i915_request_await_deps(struct i915_request *rq, const struct i915_deps *deps);
424int i915_request_await_execution(struct i915_request *rq,
425 struct dma_fence *fence);
426
427void i915_request_add(struct i915_request *rq);
428
429bool __i915_request_submit(struct i915_request *request);
430void i915_request_submit(struct i915_request *request);
431
432void __i915_request_unsubmit(struct i915_request *request);
433void i915_request_unsubmit(struct i915_request *request);
434
435void i915_request_cancel(struct i915_request *rq, int error);
436
437long i915_request_wait_timeout(struct i915_request *rq,
438 unsigned int flags,
439 long timeout)
440 __attribute__((nonnull(1)));
441
442long i915_request_wait(struct i915_request *rq,
443 unsigned int flags,
444 long timeout)
445 __attribute__((nonnull(1)));
446#define I915_WAIT_INTERRUPTIBLE BIT(0)
447#define I915_WAIT_PRIORITY BIT(1) /* small priority bump for the request */
448#define I915_WAIT_ALL BIT(2) /* used by i915_gem_object_wait() */
449
450void i915_request_show(struct drm_printer *m,
451 const struct i915_request *rq,
452 const char *prefix,
453 int indent);
454
455static inline bool i915_request_signaled(const struct i915_request *rq)
456{
457 /* The request may live longer than its HWSP, so check flags first! */
458 return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags);
459}
460
461static inline bool i915_request_is_active(const struct i915_request *rq)
462{
463 return test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
464}
465
466static inline bool i915_request_in_priority_queue(const struct i915_request *rq)
467{
468 return test_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
469}
470
471static inline bool
472i915_request_has_initial_breadcrumb(const struct i915_request *rq)
473{
474 return test_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags);
475}
476
477/*
478 * Returns true if seq1 is later than seq2.
479 */
480static inline bool i915_seqno_passed(u32 seq1, u32 seq2)
481{
482 return (s32)(seq1 - seq2) >= 0;
483}
484
485static inline u32 __hwsp_seqno(const struct i915_request *rq)
486{
487 const u32 *hwsp = READ_ONCE(rq->hwsp_seqno);
488
489 return READ_ONCE(*hwsp);
490}
491
492/**
493 * hwsp_seqno - the current breadcrumb value in the HW status page
494 * @rq: the request, to chase the relevant HW status page
495 *
496 * The emphasis in naming here is that hwsp_seqno() is not a property of the
497 * request, but an indication of the current HW state (associated with this
498 * request). Its value will change as the GPU executes more requests.
499 *
500 * Returns the current breadcrumb value in the associated HW status page (or
501 * the local timeline's equivalent) for this request. The request itself
502 * has the associated breadcrumb value of rq->fence.seqno, when the HW
503 * status page has that breadcrumb or later, this request is complete.
504 */
505static inline u32 hwsp_seqno(const struct i915_request *rq)
506{
507 u32 seqno;
508
509 rcu_read_lock(); /* the HWSP may be freed at runtime */
510 seqno = __hwsp_seqno(rq);
511 rcu_read_unlock();
512
513 return seqno;
514}
515
516static inline bool __i915_request_has_started(const struct i915_request *rq)
517{
518 return i915_seqno_passed(seq1: __hwsp_seqno(rq), seq2: rq->fence.seqno - 1);
519}
520
521/**
522 * i915_request_started - check if the request has begun being executed
523 * @rq: the request
524 *
525 * If the timeline is not using initial breadcrumbs, a request is
526 * considered started if the previous request on its timeline (i.e.
527 * context) has been signaled.
528 *
529 * If the timeline is using semaphores, it will also be emitting an
530 * "initial breadcrumb" after the semaphores are complete and just before
531 * it began executing the user payload. A request can therefore be active
532 * on the HW and not yet started as it is still busywaiting on its
533 * dependencies (via HW semaphores).
534 *
535 * If the request has started, its dependencies will have been signaled
536 * (either by fences or by semaphores) and it will have begun processing
537 * the user payload.
538 *
539 * However, even if a request has started, it may have been preempted and
540 * so no longer active, or it may have already completed.
541 *
542 * See also i915_request_is_active().
543 *
544 * Returns true if the request has begun executing the user payload, or
545 * has completed:
546 */
547static inline bool i915_request_started(const struct i915_request *rq)
548{
549 bool result;
550
551 if (i915_request_signaled(rq))
552 return true;
553
554 result = true;
555 rcu_read_lock(); /* the HWSP may be freed at runtime */
556 if (likely(!i915_request_signaled(rq)))
557 /* Remember: started but may have since been preempted! */
558 result = __i915_request_has_started(rq);
559 rcu_read_unlock();
560
561 return result;
562}
563
564/**
565 * i915_request_is_running - check if the request may actually be executing
566 * @rq: the request
567 *
568 * Returns true if the request is currently submitted to hardware, has passed
569 * its start point (i.e. the context is setup and not busywaiting). Note that
570 * it may no longer be running by the time the function returns!
571 */
572static inline bool i915_request_is_running(const struct i915_request *rq)
573{
574 bool result;
575
576 if (!i915_request_is_active(rq))
577 return false;
578
579 rcu_read_lock();
580 result = __i915_request_has_started(rq) && i915_request_is_active(rq);
581 rcu_read_unlock();
582
583 return result;
584}
585
586/**
587 * i915_request_is_ready - check if the request is ready for execution
588 * @rq: the request
589 *
590 * Upon construction, the request is instructed to wait upon various
591 * signals before it is ready to be executed by the HW. That is, we do
592 * not want to start execution and read data before it is written. In practice,
593 * this is controlled with a mixture of interrupts and semaphores. Once
594 * the submit fence is completed, the backend scheduler will place the
595 * request into its queue and from there submit it for execution. So we
596 * can detect when a request is eligible for execution (and is under control
597 * of the scheduler) by querying where it is in any of the scheduler's lists.
598 *
599 * Returns true if the request is ready for execution (it may be inflight),
600 * false otherwise.
601 */
602static inline bool i915_request_is_ready(const struct i915_request *rq)
603{
604 return !list_empty(head: &rq->sched.link);
605}
606
607static inline bool __i915_request_is_complete(const struct i915_request *rq)
608{
609 return i915_seqno_passed(seq1: __hwsp_seqno(rq), seq2: rq->fence.seqno);
610}
611
612static inline bool i915_request_completed(const struct i915_request *rq)
613{
614 bool result;
615
616 if (i915_request_signaled(rq))
617 return true;
618
619 result = true;
620 rcu_read_lock(); /* the HWSP may be freed at runtime */
621 if (likely(!i915_request_signaled(rq)))
622 result = __i915_request_is_complete(rq);
623 rcu_read_unlock();
624
625 return result;
626}
627
628static inline void i915_request_mark_complete(struct i915_request *rq)
629{
630 WRITE_ONCE(rq->hwsp_seqno, /* decouple from HWSP */
631 (u32 *)&rq->fence.seqno);
632}
633
634static inline bool i915_request_has_waitboost(const struct i915_request *rq)
635{
636 return test_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags);
637}
638
639static inline bool i915_request_has_nopreempt(const struct i915_request *rq)
640{
641 /* Preemption should only be disabled very rarely */
642 return unlikely(test_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags));
643}
644
645static inline bool i915_request_has_sentinel(const struct i915_request *rq)
646{
647 return unlikely(test_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags));
648}
649
650static inline bool i915_request_on_hold(const struct i915_request *rq)
651{
652 return unlikely(test_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags));
653}
654
655static inline void i915_request_set_hold(struct i915_request *rq)
656{
657 set_bit(nr: I915_FENCE_FLAG_HOLD, addr: &rq->fence.flags);
658}
659
660static inline void i915_request_clear_hold(struct i915_request *rq)
661{
662 clear_bit(nr: I915_FENCE_FLAG_HOLD, addr: &rq->fence.flags);
663}
664
665static inline struct intel_timeline *
666i915_request_timeline(const struct i915_request *rq)
667{
668 /* Valid only while the request is being constructed (or retired). */
669 return rcu_dereference_protected(rq->timeline,
670 lockdep_is_held(&rcu_access_pointer(rq->timeline)->mutex) ||
671 test_bit(CONTEXT_IS_PARKING, &rq->context->flags));
672}
673
674static inline struct i915_gem_context *
675i915_request_gem_context(const struct i915_request *rq)
676{
677 /* Valid only while the request is being constructed (or retired). */
678 return rcu_dereference_protected(rq->context->gem_context, true);
679}
680
681static inline struct intel_timeline *
682i915_request_active_timeline(const struct i915_request *rq)
683{
684 /*
685 * When in use during submission, we are protected by a guarantee that
686 * the context/timeline is pinned and must remain pinned until after
687 * this submission.
688 */
689 return rcu_dereference_protected(rq->timeline,
690 lockdep_is_held(&rq->engine->sched_engine->lock));
691}
692
693static inline u32
694i915_request_active_seqno(const struct i915_request *rq)
695{
696 u32 hwsp_phys_base =
697 page_mask_bits(i915_request_active_timeline(rq)->hwsp_offset);
698 u32 hwsp_relative_offset = offset_in_page(rq->hwsp_seqno);
699
700 /*
701 * Because of wraparound, we cannot simply take tl->hwsp_offset,
702 * but instead use the fact that the relative for vaddr is the
703 * offset as for hwsp_offset. Take the top bits from tl->hwsp_offset
704 * and combine them with the relative offset in rq->hwsp_seqno.
705 *
706 * As rw->hwsp_seqno is rewritten when signaled, this only works
707 * when the request isn't signaled yet, but at that point you
708 * no longer need the offset.
709 */
710
711 return hwsp_phys_base + hwsp_relative_offset;
712}
713
714bool
715i915_request_active_engine(struct i915_request *rq,
716 struct intel_engine_cs **active);
717
718void i915_request_notify_execute_cb_imm(struct i915_request *rq);
719
720enum i915_request_state {
721 I915_REQUEST_UNKNOWN = 0,
722 I915_REQUEST_COMPLETE,
723 I915_REQUEST_PENDING,
724 I915_REQUEST_QUEUED,
725 I915_REQUEST_ACTIVE,
726};
727
728enum i915_request_state i915_test_request_state(struct i915_request *rq);
729
730void i915_request_module_exit(void);
731int i915_request_module_init(void);
732
733#endif /* I915_REQUEST_H */
734

source code of linux/drivers/gpu/drm/i915/i915_request.h