1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#ifndef __I915_REG_DEFS__
7#define __I915_REG_DEFS__
8
9#include <linux/bitfield.h>
10#include <linux/bits.h>
11
12/*
13 * Wrappers over the generic fixed width BIT_U*() and GENMASK_U*()
14 * implementations, for compatibility reasons with previous implementation.
15 */
16#define REG_GENMASK(high, low) GENMASK_U32(high, low)
17#define REG_GENMASK64(high, low) GENMASK_U64(high, low)
18#define REG_GENMASK16(high, low) GENMASK_U16(high, low)
19#define REG_GENMASK8(high, low) GENMASK_U8(high, low)
20
21#define REG_BIT(n) BIT_U32(n)
22#define REG_BIT64(n) BIT_U64(n)
23#define REG_BIT16(n) BIT_U16(n)
24#define REG_BIT8(n) BIT_U8(n)
25
26/*
27 * Local integer constant expression version of is_power_of_2().
28 */
29#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
30
31/**
32 * REG_FIELD_PREP() - Prepare a u32 bitfield value
33 * @__mask: shifted mask defining the field's length and position
34 * @__val: value to put in the field
35 *
36 * Local copy of FIELD_PREP() to generate an integer constant expression, force
37 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
38 *
39 * @return: @__val masked and shifted into the field defined by @__mask.
40 */
41#define REG_FIELD_PREP(__mask, __val) \
42 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
43 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
44 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
45 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
46 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
47
48/**
49 * REG_FIELD_PREP8() - Prepare a u8 bitfield value
50 * @__mask: shifted mask defining the field's length and position
51 * @__val: value to put in the field
52 *
53 * Local copy of FIELD_PREP() to generate an integer constant expression, force
54 * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
55 *
56 * @return: @__val masked and shifted into the field defined by @__mask.
57 */
58#define REG_FIELD_PREP8(__mask, __val) \
59 ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
60 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
61 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
62 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
63 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
64
65/**
66 * REG_FIELD_GET() - Extract a u32 bitfield value
67 * @__mask: shifted mask defining the field's length and position
68 * @__val: value to extract the bitfield value from
69 *
70 * Local wrapper for FIELD_GET() to force u32 and for consistency with
71 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
72 *
73 * @return: Masked and shifted value of the field defined by @__mask in @__val.
74 */
75#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
76
77/**
78 * REG_FIELD_GET64() - Extract a u64 bitfield value
79 * @__mask: shifted mask defining the field's length and position
80 * @__val: value to extract the bitfield value from
81 *
82 * Local wrapper for FIELD_GET() to force u64 and for consistency with
83 * REG_GENMASK64().
84 *
85 * @return: Masked and shifted value of the field defined by @__mask in @__val.
86 */
87#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
88
89
90/**
91 * REG_FIELD_PREP16() - Prepare a u16 bitfield value
92 * @__mask: shifted mask defining the field's length and position
93 * @__val: value to put in the field
94 *
95 * Local copy of FIELD_PREP16() to generate an integer constant
96 * expression, force u8 and for consistency with
97 * REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16().
98 *
99 * @return: @__val masked and shifted into the field defined by @__mask.
100 */
101#define REG_FIELD_PREP16(__mask, __val) \
102 ((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
103 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
104 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \
105 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
106 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
107
108#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
109#define _MASKED_FIELD(mask, value) ({ \
110 if (__builtin_constant_p(mask)) \
111 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
112 if (__builtin_constant_p(value)) \
113 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
114 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
115 BUILD_BUG_ON_MSG((value) & ~(mask), \
116 "Incorrect value for mask"); \
117 __MASKED_FIELD(mask, value); })
118#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
119#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
120
121/*
122 * Given the first two numbers __a and __b of arbitrarily many evenly spaced
123 * numbers, pick the 0-based __index'th value.
124 *
125 * Always prefer this over _PICK() if the numbers are evenly spaced.
126 */
127#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
128
129/*
130 * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
131 * @__c_index corresponds to the index in which the second range starts to be
132 * used. Using math interval notation, the first range is used for indexes [ 0,
133 * @__c_index), while the second range is used for [ @__c_index, ... ). Example:
134 *
135 * #define _FOO_A 0xf000
136 * #define _FOO_B 0xf004
137 * #define _FOO_C 0xf008
138 * #define _SUPER_FOO_A 0xa000
139 * #define _SUPER_FOO_B 0xa100
140 * #define FOO(x) _MMIO(_PICK_EVEN_2RANGES(x, 3, \
141 * _FOO_A, _FOO_B, \
142 * _SUPER_FOO_A, _SUPER_FOO_B))
143 *
144 * This expands to:
145 * 0: 0xf000,
146 * 1: 0xf004,
147 * 2: 0xf008,
148 * 3: 0xa000,
149 * 4: 0xa100,
150 * 5: 0xa200,
151 * ...
152 */
153#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d) \
154 (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \
155 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) : \
156 _PICK_EVEN((__index) - (__c_index), __c, __d)))
157
158/*
159 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
160 *
161 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
162 */
163#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
164
165/**
166 * REG_FIELD_GET8() - Extract a u8 bitfield value
167 * @__mask: shifted mask defining the field's length and position
168 * @__val: value to extract the bitfield value from
169 *
170 * Local wrapper for FIELD_GET() to force u8 and for consistency with
171 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
172 *
173 * @return: Masked and shifted value of the field defined by @__mask in @__val.
174 */
175#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
176
177/**
178 * REG_FIELD_MAX() - produce the maximum value representable by a field
179 * @__mask: shifted mask defining the field's length and position
180 *
181 * Local wrapper for FIELD_MAX() to return the maximum bit value that can
182 * be held in the field specified by @_mask, cast to u32 for consistency
183 * with other macros.
184 */
185#define REG_FIELD_MAX(__mask) ((u32)FIELD_MAX(__mask))
186
187typedef struct {
188 u32 reg;
189} i915_reg_t;
190
191#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
192
193typedef struct {
194 u32 reg;
195} i915_mcr_reg_t;
196
197#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
198
199#define INVALID_MMIO_REG _MMIO(0)
200
201/*
202 * These macros can be used on either i915_reg_t or i915_mcr_reg_t since they're
203 * simply operations on the register's offset and don't care about the MCR vs
204 * non-MCR nature of the register.
205 */
206#define i915_mmio_reg_offset(r) \
207 _Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)
208#define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))
209#define i915_mmio_reg_valid(r) (!i915_mmio_reg_equal(r, INVALID_MMIO_REG))
210
211/* A triplet for IMR/IER/IIR registers. */
212struct i915_irq_regs {
213 i915_reg_t imr;
214 i915_reg_t ier;
215 i915_reg_t iir;
216};
217
218#define I915_IRQ_REGS(_imr, _ier, _iir) \
219 ((const struct i915_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) })
220
221struct i915_error_regs {
222 i915_reg_t emr;
223 i915_reg_t eir;
224};
225
226#define I915_ERROR_REGS(_emr, _eir) \
227 ((const struct i915_error_regs){ .emr = (_emr), .eir = (_eir) })
228
229#endif /* __I915_REG_DEFS__ */
230

source code of linux/drivers/gpu/drm/i915/i915_reg_defs.h