1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#ifndef __INTEL_GT_REGS__
7#define __INTEL_GT_REGS__
8
9#include "i915_reg_defs.h"
10
11#define VLV_GUNIT_BASE 0x180000
12
13/*
14 * The perf control registers are technically multicast registers, but the
15 * driver never needs to read/write them directly; we only use them to build
16 * lists of registers (where they're mixed in with other non-MCR registers)
17 * and then operate on the offset directly. For now we'll just define them
18 * as non-multicast so we can place them on the same list, but we may want
19 * to try to come up with a better way to handle heterogeneous lists of
20 * registers in the future.
21 */
22#define PERF_REG(offset) _MMIO(offset)
23
24/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
25#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
26#define MTL_CAGF_MASK REG_GENMASK(8, 0)
27#define MTL_CC0 0x0
28#define MTL_CC6 0x3
29#define MTL_CC_MASK REG_GENMASK(10, 9)
30
31/* RPM unit config (Gen8+) */
32#define RPM_CONFIG0 _MMIO(0xd00)
33#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
34#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
35#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
36#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2)
37#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3)
38#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_BIT(3)
39#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
40#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
41#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
42
43#define RPM_CONFIG1 _MMIO(0xd04)
44#define GEN10_GT_NOA_ENABLE (1 << 9)
45
46/* RCP unit config (Gen8+) */
47#define RCP_CONFIG _MMIO(0xd08)
48
49#define RC6_LOCATION _MMIO(0xd40)
50#define RC6_CTX_IN_DRAM (1 << 0)
51#define RC6_CTX_BASE _MMIO(0xd48)
52#define RC6_CTX_BASE_MASK 0xFFFFFFF0
53
54#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)
55#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)
56#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
57#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
58
59#define FORCEWAKE_ACK_GSC _MMIO(0xdf8)
60#define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc)
61
62#define GMD_ID_GRAPHICS _MMIO(0xd8c)
63#define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)
64
65#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
66#define MTL_STEER_SEMAPHORE _MMIO(0xfd0)
67#define MTL_MCR_SELECTOR _MMIO(0xfd4)
68#define SF_MCR_SELECTOR _MMIO(0xfd8)
69#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
70#define GAM_MCR_SELECTOR _MMIO(0xfe0)
71#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
72#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
73#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
74#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
75#define GEN11_MCR_MULTICAST REG_BIT(31)
76#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
77#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
78#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
79#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
80#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
81#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
82
83#define IPEIR_I965 _MMIO(0x2064)
84#define IPEHR_I965 _MMIO(0x2068)
85
86/*
87 * On GEN4, only the render ring INSTDONE exists and has a different
88 * layout than the GEN7+ version.
89 * The GEN2 counterpart of this register is GEN2_INSTDONE.
90 */
91#define INSTPS _MMIO(0x2070) /* 965+ only */
92#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
93#define ACTHD_I965 _MMIO(0x2074)
94#define HWS_PGA _MMIO(0x2080)
95#define HWS_ADDRESS_MASK 0xfffff000
96#define HWS_START_ADDRESS_SHIFT 4
97
98#define _3D_CHICKEN _MMIO(0x2084)
99#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
100
101#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
102#define PWRCTX_EN (1 << 0)
103
104#define FF_SLICE_CHICKEN _MMIO(0x2088)
105#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
106
107/* GM45+ chicken bits -- debug workaround bits that may be required
108 * for various sorts of correct behavior. The top 16 bits of each are
109 * the enables for writing to the corresponding low bit.
110 */
111#define _3D_CHICKEN2 _MMIO(0x208c)
112/* Disables pipelining of read flushes past the SF-WIZ interface.
113 * Required on all Ironlake steppings according to the B-Spec, but the
114 * particular danger of not doing so is not specified.
115 */
116#define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
117
118#define _3D_CHICKEN3 _MMIO(0x2090)
119#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
120#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
121#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
122#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
123#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */
124#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
125
126#define GEN2_INSTDONE _MMIO(0x2090)
127#define NOPID _MMIO(0x2094)
128#define HWSTAM _MMIO(0x2098)
129
130#define WAIT_FOR_RC6_EXIT _MMIO(0x20cc)
131/* HSW only */
132#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
133#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
134#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
135#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
136/* HSW+ */
137#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
138#define HSW_RCS_CONTEXT_ENABLE (1 << 7)
139#define HSW_RCS_INHIBIT (1 << 8)
140/* Gen8 */
141#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
142#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
143#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
144#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
145#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
146#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
147#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
148#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
149#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
150#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
151
152#define GEN6_GT_MODE _MMIO(0x20d0)
153#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
154#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
155#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
156#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
157#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
158#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
159
160/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
161#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
162#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
163#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
164#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
165#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
166
167#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
168#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
169
170#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
171#define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
172#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
173#define GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
174
175#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
176#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
177#define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON _MMIO(0x20ec)
178#define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
179
180/* WaClearTdlStateAckDirtyBits */
181#define GEN8_STATE_ACK _MMIO(0x20f0)
182#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20f8)
183#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
184#define GEN9_STATE_ACK_TDL0 (1 << 12)
185#define GEN9_STATE_ACK_TDL1 (1 << 13)
186#define GEN9_STATE_ACK_TDL2 (1 << 14)
187#define GEN9_STATE_ACK_TDL3 (1 << 15)
188#define GEN9_SUBSLICE_TDL_ACK_BITS \
189 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
190 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
191
192#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
193#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
194#define CM0_IZ_OPT_DISABLE (1 << 6)
195#define CM0_ZR_OPT_DISABLE (1 << 5)
196#define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
197#define CM0_DEPTH_EVICT_DISABLE (1 << 4)
198#define CM0_COLOR_EVICT_DISABLE (1 << 3)
199#define CM0_DEPTH_WRITE_DISABLE (1 << 1)
200#define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
201
202#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
203
204/*
205 * Logical Context regs
206 */
207/*
208 * Notes on SNB/IVB/VLV context size:
209 * - Power context is saved elsewhere (LLC or stolen)
210 * - Ring/execlist context is saved on SNB, not on IVB
211 * - Extended context size already includes render context size
212 * - We always need to follow the extended context size.
213 * SNB BSpec has comments indicating that we should use the
214 * render context size instead if execlists are disabled, but
215 * based on empirical testing that's just nonsense.
216 * - Pipelined/VF state is saved on SNB/IVB respectively
217 * - GT1 size just indicates how much of render context
218 * doesn't need saving on GT1
219 */
220#define CXT_SIZE _MMIO(0x21a0)
221#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
222#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
223#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
224#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
225#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
226#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
227 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
228 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
229#define GEN7_CXT_SIZE _MMIO(0x21a8)
230#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
231#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
232#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
233#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
234#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
235#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
236#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
237 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
238
239#define HSW_MI_PREDICATE_RESULT_2 _MMIO(0x2214)
240
241#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
242#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
243
244#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
245#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
246
247#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
248#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
249
250#define HS_INVOCATION_COUNT _MMIO(0x2300)
251#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
252#define DS_INVOCATION_COUNT _MMIO(0x2308)
253#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
254#define IA_VERTICES_COUNT _MMIO(0x2310)
255#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
256#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
257#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
258#define VS_INVOCATION_COUNT _MMIO(0x2320)
259#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
260#define GS_INVOCATION_COUNT _MMIO(0x2328)
261#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
262#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
263#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
264#define CL_INVOCATION_COUNT _MMIO(0x2338)
265#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
266#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
267#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
268#define PS_INVOCATION_COUNT _MMIO(0x2348)
269#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
270#define PS_DEPTH_COUNT _MMIO(0x2350)
271#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
272#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
273#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
274#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
275#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
276#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243c)
277#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
278#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
279#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
280#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
281
282#define GFX_MODE _MMIO(0x2520)
283
284#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
285#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
286#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
287#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
288#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
289#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
290#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
291
292#define DRAW_WATERMARK _MMIO(0x26c0)
293#define VERT_WM_VAL REG_GENMASK(9, 0)
294
295#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
296
297#define RENDER_HWS_PGA_GEN7 _MMIO(0x4080)
298
299#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
300#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
301#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
302
303#define GAM_ECOCHK _MMIO(0x4090)
304#define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
305#define ECOCHK_SNB_BIT (1 << 10)
306#define ECOCHK_DIS_TLB (1 << 8)
307#define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
308#define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
309#define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
310#define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
311#define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
312#define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
313#define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
314#define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
315
316#define GEN8_RING_FAULT_REG _MMIO(0x4094)
317#define _RING_FAULT_REG_RCS 0x4094
318#define _RING_FAULT_REG_VCS 0x4194
319#define _RING_FAULT_REG_BCS 0x4294
320#define _RING_FAULT_REG_VECS 0x4394
321#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \
322 _RING_FAULT_REG_RCS, \
323 _RING_FAULT_REG_VCS, \
324 _RING_FAULT_REG_VECS, \
325 _RING_FAULT_REG_BCS))
326#define RING_FAULT_VADDR_MASK REG_GENMASK(31, 12) /* pre-bdw */
327#define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12) /* bdw+ */
328#define RING_FAULT_GTTSEL_MASK REG_BIT(11) /* pre-bdw */
329#define RING_FAULT_SRCID_MASK REG_GENMASK(10, 3)
330#define RING_FAULT_FAULT_TYPE_MASK REG_GENMASK(2, 1) /* ivb+ */
331#define RING_FAULT_VALID REG_BIT(0)
332
333#define ERROR_GEN6 _MMIO(0x40a0)
334
335#define DONE_REG _MMIO(0x40b0)
336#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
337#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
338#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
339#define BSD_HWS_PGA_GEN7 _MMIO(0x4180)
340
341#define GEN12_CCS_AUX_INV _MMIO(0x4208)
342#define GEN12_VD0_AUX_INV _MMIO(0x4218)
343#define GEN12_VE0_AUX_INV _MMIO(0x4238)
344#define GEN12_BCS0_AUX_INV _MMIO(0x4248)
345
346#define GEN8_RTCR _MMIO(0x4260)
347#define GEN8_M1TCR _MMIO(0x4264)
348#define GEN8_M2TCR _MMIO(0x4268)
349#define GEN8_BTCR _MMIO(0x426c)
350#define GEN8_VTCR _MMIO(0x4270)
351
352#define BLT_HWS_PGA_GEN7 _MMIO(0x4280)
353
354#define GEN12_VD2_AUX_INV _MMIO(0x4298)
355#define GEN12_CCS0_AUX_INV _MMIO(0x42c8)
356#define AUX_INV REG_BIT(0)
357
358#define VEBOX_HWS_PGA_GEN7 _MMIO(0x4380)
359
360#define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
361
362#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
363
364#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
365#define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \
366 0x4800, 0x4804, \
367 0x4848, 0x484c)
368#define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index))
369#define XELPMP_PAT_INDEX(index) _MMIO(_PAT_INDEX(index))
370
371#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
372#define XEHP_TILE_LMEM_RANGE_SHIFT 8
373
374#define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
375#define XEHP_CCS_BASE_SHIFT 8
376
377#define GAMTARBMODE _MMIO(0x4a08)
378#define ARB_MODE_BWGTLB_DISABLE (1 << 9)
379#define ARB_MODE_SWIZZLE_BDW (1 << 1)
380
381#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
382#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
383
384#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
385#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
386#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
387#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
388
389#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
390#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
391#define FAULT_GTT_SEL REG_BIT(4)
392#define FAULT_VA_HIGH_BITS REG_GENMASK(3, 0)
393
394#define GEN11_GACB_PERF_CTRL _MMIO(0x4b80)
395#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
396#define GEN11_HASH_CTRL_BIT0 (1 << 0)
397#define GEN11_HASH_CTRL_BIT4 (1 << 12)
398
399/* gamt regs */
400#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
401#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
402#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
403#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
404#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
405
406#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
407#define MMCD_PCLA (1 << 31)
408#define MMCD_HOTSPOT_EN (1 << 27)
409
410/* There are the 4 64-bit counter registers, one for each stream output */
411#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
412#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
413
414#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
415#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
416
417#define GEN8_WM_CHICKEN2 MCR_REG(0x5584)
418#define WAIT_ON_DEPTH_STALL_DONE_DISABLE REG_BIT(5)
419
420#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
421#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
422
423#define XEHP_CULLBIT1 MCR_REG(0x6100)
424
425#define CHICKEN_RASTER_2 MCR_REG(0x6208)
426#define TBIMR_FAST_CLIP REG_BIT(5)
427
428#define VFLSKPD MCR_REG(0x62a8)
429#define VF_PREFETCH_TLB_DIS REG_BIT(5)
430#define DIS_OVER_FETCH_CACHE REG_BIT(1)
431#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
432
433#define GEN12_FF_MODE2 _MMIO(0x6604)
434#define XEHP_FF_MODE2 MCR_REG(0x6604)
435#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
436#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
437#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
438#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
439
440#define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c)
441
442#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
443#define DISABLE_REPACKING_FOR_COMPRESSION REG_BIT(15) /* jsl+ */
444#define RC_OP_FLUSH_ENABLE (1 << 0)
445#define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
446#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
447#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11)
448#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6)
449#define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6)
450#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1)
451
452#define GEN7_GT_MODE _MMIO(0x7008)
453#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
454#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
455
456/* GEN7 chicken */
457#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
458#define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
459#define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
460
461#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
462#define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
463#define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
464#define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
465#define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
466
467#define HIZ_CHICKEN _MMIO(0x7018)
468#define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15)
469#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
470#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13)
471#define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3)
472
473#define XEHP_CULLBIT2 MCR_REG(0x7030)
474
475#define GEN8_L3CNTLREG _MMIO(0x7034)
476#define GEN8_ERRDETBCTRL (1 << 9)
477
478#define XEHP_PSS_MODE2 MCR_REG(0x703c)
479#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
480
481#define XEHP_PSS_CHICKEN MCR_REG(0x7044)
482#define FD_END_COLLECT REG_BIT(5)
483
484#define GEN7_SC_INSTDONE _MMIO(0x7100)
485#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
486#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
487
488/* GEN8 chicken */
489#define HDC_CHICKEN0 _MMIO(0x7300)
490#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
491#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
492#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
493#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
494#define HDC_FORCE_NON_COHERENT (1 << 4)
495#define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
496
497#define COMMON_SLICE_CHICKEN4 _MMIO(0x7300)
498#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6)
499
500#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
501
502#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
503#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
504#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
505#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
506#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
507#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
508
509#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
510#define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c)
511#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
512#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
513
514#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
515#define GEN9_PGCTL_SS_ACK(subslice) REG_BIT(2 + (subslice) * 2)
516#define GEN9_PGCTL_SLICE_ACK REG_BIT(0)
517
518#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
519 ((slice) % 3) * 0x4)
520#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0))
521
522#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
523#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
524 ((slice) % 3) * 0x8)
525#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
526#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
527 ((slice) % 3) * 0x8)
528#define GEN9_PGCTL_SSB_EU311_ACK REG_BIT(14)
529#define GEN9_PGCTL_SSB_EU210_ACK REG_BIT(12)
530#define GEN9_PGCTL_SSB_EU19_ACK REG_BIT(10)
531#define GEN9_PGCTL_SSB_EU08_ACK REG_BIT(8)
532#define GEN9_PGCTL_SSA_EU311_ACK REG_BIT(6)
533#define GEN9_PGCTL_SSA_EU210_ACK REG_BIT(4)
534#define GEN9_PGCTL_SSA_EU19_ACK REG_BIT(2)
535#define GEN9_PGCTL_SSA_EU08_ACK REG_BIT(0)
536
537#define VF_PREEMPTION _MMIO(0x83a4)
538#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
539
540#define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)
541#define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4)
542
543#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
544
545#define GEN12_SQCNT1 _MMIO(0x8718)
546#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
547#define GEN12_SQCNT1_OABPC REG_BIT(29)
548#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
549
550#define XEHP_SQCM MCR_REG(0x8724)
551#define EN_32B_ACCESS REG_BIT(30)
552
553#define MTL_GSCPSMI_BASEADDR_LSB _MMIO(0x880c)
554#define MTL_GSCPSMI_BASEADDR_MSB _MMIO(0x8810)
555
556#define HSW_IDICR _MMIO(0x9008)
557#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
558
559#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
560#define GEN6_MBC_SNPCR_SHIFT 21
561#define GEN6_MBC_SNPCR_MASK (3 << 21)
562#define GEN6_MBC_SNPCR_MAX (0 << 21)
563#define GEN6_MBC_SNPCR_MED (1 << 21)
564#define GEN6_MBC_SNPCR_LOW (2 << 21)
565#define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */
566
567#define VLV_G3DCTL _MMIO(0x9024)
568#define VLV_GSCKGCTL _MMIO(0x9028)
569
570/* WaCatErrorRejectionIssue */
571#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
572#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
573
574#define FBC_LLC_READ_CTRL _MMIO(0x9044)
575#define FBC_LLC_FULLY_OPEN REG_BIT(30)
576
577#define GEN6_MBCTL _MMIO(0x907c)
578#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
579#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
580#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
581#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
582#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
583
584/* Fuse readout registers for GT */
585#define XEHP_FUSE4 _MMIO(0x9114)
586#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
587#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
588#define GEN10_L3BANK_PAIR_COUNT 4
589#define GEN10_L3BANK_MASK 0x0F
590/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
591#define GEN12_MAX_MSLICES 4
592#define GEN12_MEML3_EN_MASK REG_GENMASK(3, 0)
593
594#define HSW_PAVP_FUSE1 _MMIO(0x911c)
595#define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24)
596#define HSW_F1_EU_DIS_MASK REG_GENMASK(17, 16)
597#define HSW_F1_EU_DIS_10EUS 0
598#define HSW_F1_EU_DIS_8EUS 1
599#define HSW_F1_EU_DIS_6EUS 2
600
601#define GEN8_FUSE2 _MMIO(0x9120)
602#define GEN10_F2_S_ENA_MASK REG_GENMASK(27, 22)
603#define GEN10_F2_SS_DIS_MASK REG_GENMASK(21, 18)
604#define GEN8_F2_S_ENA_MASK REG_GENMASK(27, 25)
605#define GEN9_F2_SS_DIS_MASK REG_GENMASK(23, 20)
606#define GEN8_F2_SS_DIS_MASK REG_GENMASK(23, 21)
607
608#define GEN8_EU_DISABLE0 _MMIO(0x9134)
609#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
610#define GEN11_EU_DISABLE _MMIO(0x9134)
611#define GEN8_EU_DIS0_S1_MASK REG_GENMASK(31, 24)
612#define GEN8_EU_DIS0_S0_MASK REG_GENMASK(23, 0)
613#define GEN11_EU_DIS_MASK REG_GENMASK(7, 0)
614#define XEHP_EU_ENABLE _MMIO(0x9134)
615#define XEHP_EU_ENA_MASK REG_GENMASK(7, 0)
616
617#define GEN8_EU_DISABLE1 _MMIO(0x9138)
618#define GEN8_EU_DIS1_S2_MASK REG_GENMASK(31, 16)
619#define GEN8_EU_DIS1_S1_MASK REG_GENMASK(15, 0)
620
621#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
622#define GEN11_GT_S_ENA_MASK REG_GENMASK(7, 0)
623
624#define GEN8_EU_DISABLE2 _MMIO(0x913c)
625#define GEN8_EU_DIS2_S2_MASK REG_GENMASK(7, 0)
626
627#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913c)
628#define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c)
629
630#define GEN10_EU_DISABLE3 _MMIO(0x9140)
631#define GEN10_EU_DIS_SS_MASK 0xff
632#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
633#define GEN11_GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
634#define GEN11_GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
635
636#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
637#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
638
639#define GEN6_UCGCTL1 _MMIO(0x9400)
640#define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
641#define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
642#define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
643#define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
644
645#define GEN6_UCGCTL2 _MMIO(0x9404)
646#define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
647#define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
648#define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
649#define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
650#define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
651#define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
652
653#define GEN6_UCGCTL3 _MMIO(0x9408)
654#define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
655
656#define GEN7_UCGCTL4 _MMIO(0x940c)
657#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
658#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
659
660#define GEN6_RCGCTL1 _MMIO(0x9410)
661#define GEN6_RCGCTL2 _MMIO(0x9414)
662
663#define GEN6_GDRST _MMIO(0x941c)
664#define GEN6_GRDOM_FULL (1 << 0)
665#define GEN6_GRDOM_RENDER (1 << 1)
666#define GEN6_GRDOM_MEDIA (1 << 2)
667#define GEN6_GRDOM_BLT (1 << 3)
668#define GEN6_GRDOM_VECS (1 << 4)
669#define GEN9_GRDOM_GUC (1 << 5)
670#define GEN8_GRDOM_MEDIA2 (1 << 7)
671/* GEN11 changed all bit defs except for FULL & RENDER */
672#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
673#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
674#define XEHPC_GRDOM_BLT8 REG_BIT(31)
675#define XEHPC_GRDOM_BLT7 REG_BIT(30)
676#define XEHPC_GRDOM_BLT6 REG_BIT(29)
677#define XEHPC_GRDOM_BLT5 REG_BIT(28)
678#define XEHPC_GRDOM_BLT4 REG_BIT(27)
679#define XEHPC_GRDOM_BLT3 REG_BIT(26)
680#define XEHPC_GRDOM_BLT2 REG_BIT(25)
681#define XEHPC_GRDOM_BLT1 REG_BIT(24)
682#define GEN12_GRDOM_GSC REG_BIT(21)
683#define GEN11_GRDOM_SFC3 REG_BIT(20)
684#define GEN11_GRDOM_SFC2 REG_BIT(19)
685#define GEN11_GRDOM_SFC1 REG_BIT(18)
686#define GEN11_GRDOM_SFC0 REG_BIT(17)
687#define GEN11_GRDOM_VECS4 REG_BIT(16)
688#define GEN11_GRDOM_VECS3 REG_BIT(15)
689#define GEN11_GRDOM_VECS2 REG_BIT(14)
690#define GEN11_GRDOM_VECS REG_BIT(13)
691#define GEN11_GRDOM_MEDIA8 REG_BIT(12)
692#define GEN11_GRDOM_MEDIA7 REG_BIT(11)
693#define GEN11_GRDOM_MEDIA6 REG_BIT(10)
694#define GEN11_GRDOM_MEDIA5 REG_BIT(9)
695#define GEN11_GRDOM_MEDIA4 REG_BIT(8)
696#define GEN11_GRDOM_MEDIA3 REG_BIT(7)
697#define GEN11_GRDOM_MEDIA2 REG_BIT(6)
698#define GEN11_GRDOM_MEDIA REG_BIT(5)
699#define GEN11_GRDOM_GUC REG_BIT(3)
700#define GEN11_GRDOM_BLT REG_BIT(2)
701#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
702#define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
703
704#define GEN6_RSTCTL _MMIO(0x9420)
705
706#define GEN7_MISCCPCTL _MMIO(0x9424)
707#define GEN7_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
708#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
709#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
710#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
711#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
712
713#define GEN8_UCGCTL6 _MMIO(0x9430)
714#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
715#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
716#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
717
718#define UNSLCGCTL9430 _MMIO(0x9430)
719#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
720
721#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
722#define VFUNIT_CLKGATE_DIS REG_BIT(20)
723#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
724#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
725#define HSUNIT_CLKGATE_DIS REG_BIT(8)
726#define VSUNIT_CLKGATE_DIS REG_BIT(3)
727
728#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
729#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
730#define SARBUNIT_CLKGATE_DIS (1 << 5)
731#define RCCUNIT_CLKGATE_DIS (1 << 7)
732#define MSCUNIT_CLKGATE_DIS (1 << 10)
733#define NODEDSS_CLKGATE_DIS REG_BIT(12)
734#define L3_CLKGATE_DIS REG_BIT(16)
735#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
736
737#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
738#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
739#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
740
741#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
742#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
743#define GWUNIT_CLKGATE_DIS REG_BIT(16)
744
745#define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528)
746#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
747
748#define SSMCGCTL9530 MCR_REG(0x9530)
749#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
750
751#define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
752#define DFR_DISABLE (1 << 9)
753
754#define MICRO_BP0_0 _MMIO(0x9800)
755#define MICRO_BP0_2 _MMIO(0x9804)
756#define MICRO_BP0_1 _MMIO(0x9808)
757#define MICRO_BP1_0 _MMIO(0x980c)
758#define MICRO_BP1_2 _MMIO(0x9810)
759#define MICRO_BP1_1 _MMIO(0x9814)
760#define MICRO_BP2_0 _MMIO(0x9818)
761#define MICRO_BP2_2 _MMIO(0x981c)
762#define MICRO_BP2_1 _MMIO(0x9820)
763#define MICRO_BP3_0 _MMIO(0x9824)
764#define MICRO_BP3_2 _MMIO(0x9828)
765#define MICRO_BP3_1 _MMIO(0x982c)
766#define MICRO_BP_TRIGGER _MMIO(0x9830)
767#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
768#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
769#define MICRO_BP_FIRED_ARMED _MMIO(0x983c)
770
771#define GEN6_GFXPAUSE _MMIO(0xa000)
772#define GEN6_RPNSWREQ _MMIO(0xa008)
773#define GEN6_TURBO_DISABLE (1 << 31)
774#define GEN6_FREQUENCY(x) ((x) << 25)
775#define HSW_FREQUENCY(x) ((x) << 24)
776#define GEN9_FREQUENCY(x) ((x) << 23)
777#define GEN6_OFFSET(x) ((x) << 19)
778#define GEN6_AGGRESSIVE_TURBO (0 << 15)
779#define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 23
780#define GEN9_IGNORE_SLICE_RATIO (0 << 0)
781#define GEN12_MEDIA_FREQ_RATIO REG_BIT(13)
782
783#define GEN6_RC_VIDEO_FREQ _MMIO(0xa00c)
784#define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
785#define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
786#define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
787#define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
788#define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
789#define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
790#define GEN7_RC_CTL_TO_MODE (1 << 28)
791#define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
792#define GEN6_RC_CTL_HW_ENABLE (1 << 31)
793#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xa010)
794#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xa014)
795#define GEN6_RPSTAT1 _MMIO(0xa01c)
796#define GEN6_CAGF_MASK REG_GENMASK(14, 8)
797#define HSW_CAGF_MASK REG_GENMASK(13, 7)
798#define GEN9_CAGF_MASK REG_GENMASK(31, 23)
799#define GEN6_RP_CONTROL _MMIO(0xa024)
800#define GEN6_RP_MEDIA_TURBO (1 << 11)
801#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
802#define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
803#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
804#define GEN6_RP_MEDIA_HW_MODE (1 << 9)
805#define GEN6_RP_MEDIA_SW_MODE (0 << 9)
806#define GEN6_RP_MEDIA_IS_GFX (1 << 8)
807#define GEN6_RP_ENABLE (1 << 7)
808#define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
809#define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
810#define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
811#define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
812#define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
813#define GEN6_RPSWCTL_SHIFT 9
814#define GEN9_RPSWCTL_ENABLE (0x2 << GEN6_RPSWCTL_SHIFT)
815#define GEN9_RPSWCTL_DISABLE (0x0 << GEN6_RPSWCTL_SHIFT)
816#define GEN6_RP_UP_THRESHOLD _MMIO(0xa02c)
817#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xa030)
818#define GEN6_RP_CUR_UP_EI _MMIO(0xa050)
819#define GEN6_RP_EI_MASK 0xffffff
820#define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
821#define GEN6_RP_CUR_UP _MMIO(0xa054)
822#define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
823#define GEN6_RP_PREV_UP _MMIO(0xa058)
824#define GEN6_RP_CUR_DOWN_EI _MMIO(0xa05c)
825#define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
826#define GEN6_RP_CUR_DOWN _MMIO(0xa060)
827#define GEN6_RP_PREV_DOWN _MMIO(0xa064)
828#define GEN6_RP_UP_EI _MMIO(0xa068)
829#define GEN6_RP_DOWN_EI _MMIO(0xa06c)
830#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xa070)
831#define GEN6_RPDEUHWTC _MMIO(0xa080)
832#define GEN6_RPDEUC _MMIO(0xa084)
833#define GEN6_RPDEUCSW _MMIO(0xa088)
834#define GEN6_RC_CONTROL _MMIO(0xa090)
835#define GEN6_RC_STATE _MMIO(0xa094)
836#define RC_SW_TARGET_STATE_SHIFT 16
837#define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
838#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xa098)
839#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xa09c)
840#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xa0a0)
841#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xa0a0)
842#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xa0a8)
843#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xa0ac)
844#define GEN6_RC_SLEEP _MMIO(0xa0b0)
845#define GEN6_RCUBMABDTMR _MMIO(0xa0b0)
846#define GEN6_RC1e_THRESHOLD _MMIO(0xa0b4)
847#define GEN6_RC6_THRESHOLD _MMIO(0xa0b8)
848#define GEN6_RC6p_THRESHOLD _MMIO(0xa0bc)
849#define VLV_RCEDATA _MMIO(0xa0bc)
850#define GEN6_RC6pp_THRESHOLD _MMIO(0xa0c0)
851#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xa0c4)
852#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xa0c8)
853
854#define GEN6_PMINTRMSK _MMIO(0xa168)
855#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
856#define ARAT_EXPIRED_INTRMSK (1 << 9)
857
858#define GEN8_MISC_CTRL0 _MMIO(0xa180)
859
860#define ECOBUS _MMIO(0xa180)
861#define FORCEWAKE_MT_ENABLE (1 << 5)
862
863#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
864#define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
865#define FORCEWAKE _MMIO(0xa18c)
866
867#define VLV_SPAREG2H _MMIO(0xa194)
868
869#define GEN9_PG_ENABLE _MMIO(0xa210)
870#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
871#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
872#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
873#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
874#define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
875
876#define GEN8_PUSHBUS_CONTROL _MMIO(0xa248)
877#define GEN8_PUSHBUS_ENABLE _MMIO(0xa250)
878#define GEN8_PUSHBUS_SHIFT _MMIO(0xa25c)
879
880/* GPM unit config (Gen9+) */
881#define CTC_MODE _MMIO(0xa26c)
882#define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
883#define CTC_SOURCE_PARAMETER_MASK REG_BIT(0)
884#define CTC_SOURCE_CRYSTAL_CLOCK REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 0)
885#define CTC_SOURCE_DIVIDE_LOGIC REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 1)
886
887/* GPM MSG_IDLE */
888#define MSG_IDLE_CS _MMIO(0x8000)
889#define MSG_IDLE_VCS0 _MMIO(0x8004)
890#define MSG_IDLE_VCS1 _MMIO(0x8008)
891#define MSG_IDLE_BCS _MMIO(0x800C)
892#define MSG_IDLE_VECS0 _MMIO(0x8010)
893#define MSG_IDLE_VCS2 _MMIO(0x80C0)
894#define MSG_IDLE_VCS3 _MMIO(0x80C4)
895#define MSG_IDLE_VCS4 _MMIO(0x80C8)
896#define MSG_IDLE_VCS5 _MMIO(0x80CC)
897#define MSG_IDLE_VCS6 _MMIO(0x80D0)
898#define MSG_IDLE_VCS7 _MMIO(0x80D4)
899#define MSG_IDLE_VECS1 _MMIO(0x80D8)
900#define MSG_IDLE_VECS2 _MMIO(0x80DC)
901#define MSG_IDLE_VECS3 _MMIO(0x80E0)
902#define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
903#define MSG_IDLE_FW_SHIFT 9
904
905#define RC_PSMI_CTRL_GSCCS _MMIO(0x11a050)
906#define IDLE_MSG_DISABLE REG_BIT(0)
907#define PWRCTX_MAXCNT_GSCCS _MMIO(0x11a054)
908
909#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
910#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
911
912#define VLV_PWRDWNUPCTL _MMIO(0xa294)
913
914#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xa2a0)
915#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
916#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
917
918#define MISC_STATUS0 _MMIO(0xa500)
919#define MISC_STATUS1 _MMIO(0xa504)
920
921#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
922#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
923
924#define FORCEWAKE_REQ_GSC _MMIO(0xa618)
925
926#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
927#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
928#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
929#define CHV_EU210_PG_ENABLE REG_BIT(25)
930#define CHV_EU19_PG_ENABLE REG_BIT(17)
931#define CHV_EU08_PG_ENABLE REG_BIT(9)
932#define CHV_SS_PG_ENABLE REG_BIT(1)
933#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
934#define CHV_EU311_PG_ENABLE REG_BIT(1)
935
936#define GEN7_SARCHKMD _MMIO(0xb000)
937#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
938#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
939
940#define GEN8_GARBCNTL _MMIO(0xb004)
941#define GEN11_ARBITRATION_PRIO_ORDER_MASK REG_GENMASK(27, 22)
942#define GEN12_BUS_HASH_CTL_BIT_EXC REG_BIT(7)
943#define GEN9_GAPS_TSV_CREDIT_DISABLE REG_BIT(7)
944#define GEN11_HASH_CTRL_EXCL_MASK REG_GENMASK(6, 0)
945#define GEN11_HASH_CTRL_EXCL_BIT0 REG_FIELD_PREP(GEN11_HASH_CTRL_EXCL_MASK, 0x1)
946
947#define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)
948#define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
949
950#define GEN7_L3SQCREG1 _MMIO(0xb010)
951#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
952
953#define GEN7_L3CNTLREG1 _MMIO(0xb01c)
954#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
955#define GEN7_L3AGDIS (1 << 19)
956
957#define GEN7_L3CNTLREG2 _MMIO(0xb020)
958
959/* MOCS (Memory Object Control State) registers */
960#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
961#define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4)
962#define LNCFCMOCS_REG_COUNT 32
963
964#define GEN7_L3CNTLREG3 _MMIO(0xb024)
965
966#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xb030)
967#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
968
969#define GEN7_L3SQCREG4 _MMIO(0xb034)
970#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
971
972#define HSW_SCRATCH1 _MMIO(0xb038)
973#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
974
975#define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
976#define GEN7_L3LOG_SIZE 0x80
977
978#define XEHP_L3NODEARBCFG MCR_REG(0xb0b4)
979#define XEHP_LNESPARE REG_BIT(19)
980
981#define GEN8_L3SQCREG1 MCR_REG(0xb100)
982/*
983 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
984 * Using the formula in BSpec leads to a hang, while the formula here works
985 * fine and matches the formulas for all other platforms. A BSpec change
986 * request has been filed to clarify this.
987 */
988#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
989#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
990#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
991
992#define GEN8_L3SQCREG4 MCR_REG(0xb118)
993#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
994#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
995#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
996#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
997
998#define GEN9_SCRATCH1 MCR_REG(0xb11c)
999#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
1000
1001#define BDW_SCRATCH1 MCR_REG(0xb11c)
1002#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
1003
1004#define GEN11_SCRATCH2 MCR_REG(0xb140)
1005#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
1006
1007#define XEHP_L3SQCREG5 MCR_REG(0xb158)
1008#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
1009
1010#define XEHP_L3SCQREG7 MCR_REG(0xb188)
1011#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
1012
1013#define GEN11_GLBLINVL _MMIO(0xb404)
1014#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
1015#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
1016
1017#define GEN11_LSN_UNSLCVC _MMIO(0xb43c)
1018#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
1019#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
1020
1021#define GUCPMTIMESTAMP _MMIO(0xc3e8)
1022
1023#define __GEN9_RCS0_MOCS0 0xc800
1024#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
1025#define __GEN9_VCS0_MOCS0 0xc900
1026#define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
1027#define __GEN9_VCS1_MOCS0 0xca00
1028#define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
1029#define __GEN9_VECS0_MOCS0 0xcb00
1030#define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
1031#define __GEN9_BCS0_MOCS0 0xcc00
1032#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
1033
1034#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
1035#define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8)
1036#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
1037#define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc)
1038/* see GEN8_FAULT_TLB_DATA0/1 */
1039
1040#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
1041#define XEHP_RING_FAULT_REG MCR_REG(0xcec4)
1042#define XELPMP_RING_FAULT_REG _MMIO(0xcec4)
1043/* see GEN8_RING_FAULT_REG */
1044
1045#define GEN12_GFX_TLB_INV_CR _MMIO(0xced8)
1046#define XEHP_GFX_TLB_INV_CR MCR_REG(0xced8)
1047#define GEN12_VD_TLB_INV_CR _MMIO(0xcedc)
1048#define XEHP_VD_TLB_INV_CR MCR_REG(0xcedc)
1049#define GEN12_VE_TLB_INV_CR _MMIO(0xcee0)
1050#define XEHP_VE_TLB_INV_CR MCR_REG(0xcee0)
1051#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
1052#define XEHP_BLT_TLB_INV_CR MCR_REG(0xcee4)
1053#define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04)
1054#define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
1055#define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */
1056
1057#define RENDER_MOD_CTRL MCR_REG(0xcf2c)
1058#define COMP_MOD_CTRL MCR_REG(0xcf30)
1059#define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */
1060#define XEHP_VDBX_MOD_CTRL MCR_REG(0xcf34)
1061#define XELPMP_VDBX_MOD_CTRL _MMIO(0xcf34)
1062#define XEHP_VEBX_MOD_CTRL MCR_REG(0xcf38)
1063#define XELPMP_VEBX_MOD_CTRL _MMIO(0xcf38)
1064#define FORCE_MISS_FTLB REG_BIT(3)
1065
1066#define XEHP_GAMSTLB_CTRL MCR_REG(0xcf4c)
1067#define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
1068#define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
1069#define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
1070
1071#define XEHP_GAMCNTRL_CTRL MCR_REG(0xcf54)
1072#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
1073#define GLOBAL_INVALIDATION_MODE REG_BIT(2)
1074
1075#define GEN12_GAM_DONE _MMIO(0xcf68)
1076
1077#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
1078#define GEN8_HALF_SLICE_CHICKEN1 MCR_REG(0xe100)
1079#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
1080#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
1081#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
1082#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
1083
1084#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
1085#define GEN8_SAMPLER_INSTDONE MCR_REG(0xe160)
1086#define GEN7_ROW_INSTDONE _MMIO(0xe164)
1087#define GEN8_ROW_INSTDONE MCR_REG(0xe164)
1088
1089#define HALF_SLICE_CHICKEN2 MCR_REG(0xe180)
1090#define GEN8_ST_PO_DISABLE (1 << 13)
1091
1092#define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
1093#define GEN8_HALF_SLICE_CHICKEN3 MCR_REG(0xe184)
1094#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
1095#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
1096#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
1097#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
1098
1099#define GEN9_HALF_SLICE_CHICKEN5 MCR_REG(0xe188)
1100#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
1101#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
1102
1103#define GEN10_SAMPLER_MODE MCR_REG(0xe18c)
1104#define ENABLE_SMALLPL REG_BIT(15)
1105#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
1106#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
1107#define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3)
1108#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
1109
1110#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
1111#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
1112#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8)
1113#define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4)
1114#define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2)
1115
1116#define GEN10_CACHE_MODE_SS MCR_REG(0xe420)
1117#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
1118#define DISABLE_ECC REG_BIT(5)
1119#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
1120/*
1121 * We have both ENABLE and DISABLE defines below using the same bit because the
1122 * meaning depends on the target platform. There are no platform prefix for them
1123 * because different steppings of DG2 pick one or the other semantics.
1124 */
1125#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
1126#define DISABLE_PREFETCH_INTO_IC REG_BIT(3)
1127
1128#define EU_PERF_CNTL0 PERF_REG(0xe458)
1129#define EU_PERF_CNTL4 PERF_REG(0xe45c)
1130
1131#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
1132#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
1133#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
1134#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
1135#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
1136#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
1137#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
1138
1139#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
1140#define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c)
1141#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
1142#define MTL_DISABLE_FIX_FOR_EOT_FLUSH REG_BIT(9)
1143
1144#define GEN8_ROW_CHICKEN MCR_REG(0xe4f0)
1145#define FLOW_CONTROL_ENABLE REG_BIT(15)
1146#define UGM_BACKUP_MODE REG_BIT(13)
1147#define MDQ_ARBITRATION_MODE REG_BIT(12)
1148#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
1149#define STALL_DOP_GATING_DISABLE REG_BIT(5)
1150#define THROTTLE_12_5 REG_GENMASK(4, 2)
1151#define DISABLE_EARLY_EOT REG_BIT(1)
1152
1153#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
1154
1155#define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4)
1156#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
1157#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
1158#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
1159#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
1160#define XELPG_DISABLE_TDL_SVHS_GATING REG_BIT(1)
1161#define GEN12_DISABLE_DOP_GATING REG_BIT(0)
1162
1163#define RT_CTRL MCR_REG(0xe530)
1164#define DIS_NULL_QUERY REG_BIT(10)
1165#define STACKID_CTRL REG_GENMASK(6, 5)
1166#define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2)
1167
1168#define EU_PERF_CNTL1 PERF_REG(0xe558)
1169#define EU_PERF_CNTL5 PERF_REG(0xe55c)
1170
1171#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
1172#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
1173#define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3)
1174
1175#define ICL_HDC_MODE MCR_REG(0xe5f4)
1176
1177#define EU_PERF_CNTL2 PERF_REG(0xe658)
1178#define EU_PERF_CNTL6 PERF_REG(0xe65c)
1179#define EU_PERF_CNTL3 PERF_REG(0xe758)
1180
1181#define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8)
1182#define DISABLE_D8_D16_COASLESCE REG_BIT(30)
1183#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
1184#define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4)
1185#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32)
1186#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
1187#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
1188#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
1189#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
1190#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
1191
1192#define SARB_CHICKEN1 MCR_REG(0xe90c)
1193#define COMP_CKN_IN REG_GENMASK(30, 29)
1194
1195#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
1196#define DOP_CLOCK_GATING_DISABLE (1 << 0)
1197#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
1198#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
1199
1200#define __GEN11_VCS2_MOCS0 0x10000
1201#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
1202
1203#define CRSTANDVID _MMIO(0x11100)
1204#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1205#define PXVFREQ_PX_MASK 0x7f000000
1206#define PXVFREQ_PX_SHIFT 24
1207#define VIDFREQ_BASE _MMIO(0x11110)
1208#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1209#define VIDFREQ2 _MMIO(0x11114)
1210#define VIDFREQ3 _MMIO(0x11118)
1211#define VIDFREQ4 _MMIO(0x1111c)
1212#define VIDFREQ_P0_MASK 0x1f000000
1213#define VIDFREQ_P0_SHIFT 24
1214#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1215#define VIDFREQ_P0_CSCLK_SHIFT 20
1216#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1217#define VIDFREQ_P0_CRCLK_SHIFT 16
1218#define VIDFREQ_P1_MASK 0x00001f00
1219#define VIDFREQ_P1_SHIFT 8
1220#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1221#define VIDFREQ_P1_CSCLK_SHIFT 4
1222#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1223#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
1224#define INTTOEXT_MAP3_SHIFT 24
1225#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1226#define INTTOEXT_MAP2_SHIFT 16
1227#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1228#define INTTOEXT_MAP1_SHIFT 8
1229#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1230#define INTTOEXT_MAP0_SHIFT 0
1231#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1232#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
1233#define MEMCTL_CMD_MASK 0xe000
1234#define MEMCTL_CMD_SHIFT 13
1235#define MEMCTL_CMD_RCLK_OFF 0
1236#define MEMCTL_CMD_RCLK_ON 1
1237#define MEMCTL_CMD_CHFREQ 2
1238#define MEMCTL_CMD_CHVID 3
1239#define MEMCTL_CMD_VMMOFF 4
1240#define MEMCTL_CMD_VMMON 5
1241#define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
1242 when command complete */
1243#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1244#define MEMCTL_FREQ_SHIFT 8
1245#define MEMCTL_SFCAVM (1 << 7)
1246#define MEMCTL_TGT_VID_MASK 0x007f
1247#define MEMIHYST _MMIO(0x1117c)
1248#define MEMINTREN _MMIO(0x11180) /* 16 bits */
1249#define MEMINT_RSEXIT_EN (1 << 8)
1250#define MEMINT_CX_SUPR_EN (1 << 7)
1251#define MEMINT_CONT_BUSY_EN (1 << 6)
1252#define MEMINT_AVG_BUSY_EN (1 << 5)
1253#define MEMINT_EVAL_CHG_EN (1 << 4)
1254#define MEMINT_MON_IDLE_EN (1 << 3)
1255#define MEMINT_UP_EVAL_EN (1 << 2)
1256#define MEMINT_DOWN_EVAL_EN (1 << 1)
1257#define MEMINT_SW_CMD_EN (1 << 0)
1258#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
1259#define MEM_RSEXIT_MASK 0xc000
1260#define MEM_RSEXIT_SHIFT 14
1261#define MEM_CONT_BUSY_MASK 0x3000
1262#define MEM_CONT_BUSY_SHIFT 12
1263#define MEM_AVG_BUSY_MASK 0x0c00
1264#define MEM_AVG_BUSY_SHIFT 10
1265#define MEM_EVAL_CHG_MASK 0x0300
1266#define MEM_EVAL_BUSY_SHIFT 8
1267#define MEM_MON_IDLE_MASK 0x00c0
1268#define MEM_MON_IDLE_SHIFT 6
1269#define MEM_UP_EVAL_MASK 0x0030
1270#define MEM_UP_EVAL_SHIFT 4
1271#define MEM_DOWN_EVAL_MASK 0x000c
1272#define MEM_DOWN_EVAL_SHIFT 2
1273#define MEM_SW_CMD_MASK 0x0003
1274#define MEM_INT_STEER_GFX 0
1275#define MEM_INT_STEER_CMR 1
1276#define MEM_INT_STEER_SMI 2
1277#define MEM_INT_STEER_SCI 3
1278#define MEMINTRSTS _MMIO(0x11184)
1279#define MEMINT_RSEXIT (1 << 7)
1280#define MEMINT_CONT_BUSY (1 << 6)
1281#define MEMINT_AVG_BUSY (1 << 5)
1282#define MEMINT_EVAL_CHG (1 << 4)
1283#define MEMINT_MON_IDLE (1 << 3)
1284#define MEMINT_UP_EVAL (1 << 2)
1285#define MEMINT_DOWN_EVAL (1 << 1)
1286#define MEMINT_SW_CMD (1 << 0)
1287#define MEMMODECTL _MMIO(0x11190)
1288#define MEMMODE_BOOST_EN (1 << 31)
1289#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1290#define MEMMODE_BOOST_FREQ_SHIFT 24
1291#define MEMMODE_IDLE_MODE_MASK 0x00030000
1292#define MEMMODE_IDLE_MODE_SHIFT 16
1293#define MEMMODE_IDLE_MODE_EVAL 0
1294#define MEMMODE_IDLE_MODE_CONT 1
1295#define MEMMODE_HWIDLE_EN (1 << 15)
1296#define MEMMODE_SWMODE_EN (1 << 14)
1297#define MEMMODE_RCLK_GATE (1 << 13)
1298#define MEMMODE_HW_UPDATE (1 << 12)
1299#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1300#define MEMMODE_FSTART_SHIFT 8
1301#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1302#define MEMMODE_FMAX_SHIFT 4
1303#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1304#define RCBMAXAVG _MMIO(0x1119c)
1305#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
1306#define SWMEMCMD_RENDER_OFF (0 << 13)
1307#define SWMEMCMD_RENDER_ON (1 << 13)
1308#define SWMEMCMD_SWFREQ (2 << 13)
1309#define SWMEMCMD_TARVID (3 << 13)
1310#define SWMEMCMD_VRM_OFF (4 << 13)
1311#define SWMEMCMD_VRM_ON (5 << 13)
1312#define CMDSTS (1 << 12)
1313#define SFCAVM (1 << 11)
1314#define SWFREQ_MASK 0x0380 /* P0-7 */
1315#define SWFREQ_SHIFT 7
1316#define TARVID_MASK 0x001f
1317#define MEMSTAT_CTG _MMIO(0x111a0)
1318#define RCBMINAVG _MMIO(0x111a0)
1319#define RCUPEI _MMIO(0x111b0)
1320#define RCDNEI _MMIO(0x111b4)
1321#define RSTDBYCTL _MMIO(0x111b8)
1322#define RS1EN (1 << 31)
1323#define RS2EN (1 << 30)
1324#define RS3EN (1 << 29)
1325#define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */
1326#define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */
1327#define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */
1328#define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */
1329#define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */
1330#define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
1331#define RSX_STATUS_MASK (7 << 20)
1332#define RSX_STATUS_ON (0 << 20)
1333#define RSX_STATUS_RC1 (1 << 20)
1334#define RSX_STATUS_RC1E (2 << 20)
1335#define RSX_STATUS_RS1 (3 << 20)
1336#define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */
1337#define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */
1338#define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */
1339#define RSX_STATUS_RSVD2 (7 << 20)
1340#define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */
1341#define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */
1342#define JRSC (1 << 17) /* rsx coupled to cpu c-state */
1343#define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */
1344#define RS1CONTSAV_MASK (3 << 14)
1345#define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */
1346#define RS1CONTSAV_RSVD (1 << 14)
1347#define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */
1348#define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */
1349#define NORMSLEXLAT_MASK (3 << 12)
1350#define SLOW_RS123 (0 << 12)
1351#define SLOW_RS23 (1 << 12)
1352#define SLOW_RS3 (2 << 12)
1353#define NORMAL_RS123 (3 << 12)
1354#define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */
1355#define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1356#define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
1357#define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
1358#define RS_CSTATE_MASK (3 << 4)
1359#define RS_CSTATE_C367_RS1 (0 << 4)
1360#define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
1361#define RS_CSTATE_RSVD (2 << 4)
1362#define RS_CSTATE_C367_RS2 (3 << 4)
1363#define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
1364#define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
1365#define VIDCTL _MMIO(0x111c0)
1366#define VIDSTS _MMIO(0x111c8)
1367#define VIDSTART _MMIO(0x111cc) /* 8 bits */
1368#define MEMSTAT_ILK _MMIO(0x111f8)
1369#define MEMSTAT_VID_MASK 0x7f00
1370#define MEMSTAT_VID_SHIFT 8
1371#define MEMSTAT_PSTATE_MASK REG_GENMASK(7, 3)
1372#define MEMSTAT_MON_ACTV (1 << 2)
1373#define MEMSTAT_SRC_CTL_MASK 0x0003
1374#define MEMSTAT_SRC_CTL_CORE 0
1375#define MEMSTAT_SRC_CTL_TRB 1
1376#define MEMSTAT_SRC_CTL_THM 2
1377#define MEMSTAT_SRC_CTL_STDBY 3
1378#define PMMISC _MMIO(0x11214)
1379#define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
1380#define SDEW _MMIO(0x1124c)
1381#define CSIEW0 _MMIO(0x11250)
1382#define CSIEW1 _MMIO(0x11254)
1383#define CSIEW2 _MMIO(0x11258)
1384#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
1385#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
1386#define MCHAFE _MMIO(0x112c0)
1387#define CSIEC _MMIO(0x112e0)
1388#define DMIEC _MMIO(0x112e4)
1389#define DDREC _MMIO(0x112e8)
1390#define PEG0EC _MMIO(0x112ec)
1391#define PEG1EC _MMIO(0x112f0)
1392#define GFXEC _MMIO(0x112f4)
1393#define INTTOEXT_BASE_ILK _MMIO(0x11300)
1394#define RPPREVBSYTUPAVG _MMIO(0x113b8)
1395#define RCPREVBSYTUPAVG _MMIO(0x113b8)
1396#define RCPREVBSYTDNAVG _MMIO(0x113bc)
1397#define RPPREVBSYTDNAVG _MMIO(0x113bc)
1398#define ECR _MMIO(0x11600)
1399#define ECR_GPFE (1 << 31)
1400#define ECR_IMONE (1 << 30)
1401#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1402#define OGW0 _MMIO(0x11608)
1403#define OGW1 _MMIO(0x1160c)
1404#define EG0 _MMIO(0x11610)
1405#define EG1 _MMIO(0x11614)
1406#define EG2 _MMIO(0x11618)
1407#define EG3 _MMIO(0x1161c)
1408#define EG4 _MMIO(0x11620)
1409#define EG5 _MMIO(0x11624)
1410#define EG6 _MMIO(0x11628)
1411#define EG7 _MMIO(0x1162c)
1412#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
1413#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
1414#define LCFUSE02 _MMIO(0x116c0)
1415#define LCFUSE_HIV_MASK 0x000000ff
1416
1417#define GAC_ECO_BITS _MMIO(0x14090)
1418#define ECOBITS_SNB_BIT (1 << 13)
1419#define ECOBITS_PPGTT_CACHE64B (3 << 8)
1420#define ECOBITS_PPGTT_CACHE4B (0 << 8)
1421
1422#define GEN12_RCU_MODE _MMIO(0x14800)
1423#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
1424#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
1425
1426#define XEHP_CCS_MODE _MMIO(0x14804)
1427#define XEHP_CCS_MODE_CSLICE_MASK REG_GENMASK(2, 0) /* CCS0-3 + rsvd */
1428#define XEHP_CCS_MODE_CSLICE_WIDTH ilog2(XEHP_CCS_MODE_CSLICE_MASK + 1)
1429#define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH))
1430
1431#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
1432#define CHV_FGT_EU_DIS_SS1_R1_MASK REG_GENMASK(31, 28)
1433#define CHV_FGT_EU_DIS_SS1_R0_MASK REG_GENMASK(27, 24)
1434#define CHV_FGT_EU_DIS_SS0_R1_MASK REG_GENMASK(23, 20)
1435#define CHV_FGT_EU_DIS_SS0_R0_MASK REG_GENMASK(19, 16)
1436#define CHV_FGT_DISABLE_SS1 REG_BIT(11)
1437#define CHV_FGT_DISABLE_SS0 REG_BIT(10)
1438
1439#define BCS_SWCTRL _MMIO(0x22200)
1440#define BCS_SRC_Y REG_BIT(0)
1441#define BCS_DST_Y REG_BIT(1)
1442
1443#define GAB_CTL _MMIO(0x24000)
1444#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
1445
1446#define GEN6_PMISR _MMIO(0x44020)
1447#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
1448#define GEN6_PMIIR _MMIO(0x44028)
1449#define GEN6_PMIER _MMIO(0x4402c)
1450#define GEN6_PM_MBOX_EVENT (1 << 25)
1451#define GEN6_PM_THERMAL_EVENT (1 << 24)
1452/*
1453 * For Gen11 these are in the upper word of the GPM_WGBOXPERF
1454 * registers. Shifting is handled on accessing the imr and ier.
1455 */
1456#define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
1457#define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
1458#define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
1459#define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
1460#define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
1461#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
1462 GEN6_PM_RP_UP_THRESHOLD | \
1463 GEN6_PM_RP_DOWN_EI_EXPIRED | \
1464 GEN6_PM_RP_DOWN_THRESHOLD | \
1465 GEN6_PM_RP_DOWN_TIMEOUT)
1466
1467#define GEN6_PM_IRQ_REGS I915_IRQ_REGS(GEN6_PMIMR, \
1468 GEN6_PMIER, \
1469 GEN6_PMIIR)
1470
1471#define GEN7_GT_SCRATCH(i) _MMIO(0x4f100 + (i) * 4)
1472#define GEN7_GT_SCRATCH_REG_NUM 8
1473
1474#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
1475#define GFX_FLSH_CNTL_EN (1 << 0)
1476
1477#define GTFIFODBG _MMIO(0x120000)
1478#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
1479#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
1480#define GT_FIFO_SBDROPERR (1 << 6)
1481#define GT_FIFO_BLOBDROPERR (1 << 5)
1482#define GT_FIFO_SB_READ_ABORTERR (1 << 4)
1483#define GT_FIFO_DROPERR (1 << 3)
1484#define GT_FIFO_OVFERR (1 << 2)
1485#define GT_FIFO_IAWRERR (1 << 1)
1486#define GT_FIFO_IARDERR (1 << 0)
1487
1488#define GTFIFOCTL _MMIO(0x120008)
1489#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
1490#define GT_FIFO_NUM_RESERVED_ENTRIES 20
1491#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
1492#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
1493
1494#define FORCEWAKE_MT_ACK _MMIO(0x130040)
1495#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
1496#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
1497#define FORCEWAKE_KERNEL BIT(0)
1498#define FORCEWAKE_USER BIT(1)
1499#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
1500#define FORCEWAKE_ACK _MMIO(0x130090)
1501#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
1502#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
1503#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
1504#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
1505#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
1506#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
1507#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
1508#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
1509#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
1510#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
1511#define VLV_GFX_CLK_STATUS_BIT (1 << 3)
1512#define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
1513#define FORCEWAKE_VLV _MMIO(0x1300b0)
1514#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
1515#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
1516#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
1517
1518#define MTL_MEDIA_MC6 _MMIO(0x138048)
1519
1520#define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010)
1521#define MTL_GT_L3_EXC_MASK REG_GENMASK(5, 3)
1522
1523#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
1524#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1525
1526#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
1527#define GEN6_CORE_CPD_STATE_MASK (7 << 4)
1528#define GEN6_RCn_MASK 7
1529#define GEN6_RC0 0
1530#define GEN6_RC3 2
1531#define GEN6_RC6 3
1532#define GEN6_RC7 4
1533
1534#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
1535#define GEN8_LSLICESTAT_MASK 0x7
1536
1537#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
1538#define VLV_COUNTER_CONTROL _MMIO(0x138104)
1539#define VLV_COUNT_RANGE_HIGH (1 << 15)
1540#define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
1541#define VLV_RENDER_RC0_COUNT_EN (1 << 4)
1542#define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
1543#define VLV_RENDER_RC6_COUNT_EN (1 << 0)
1544#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
1545#define VLV_GT_MEDIA_RC6 _MMIO(0x13810c)
1546
1547#define GEN6_GT_GFX_RC6p _MMIO(0x13810c)
1548#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
1549#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
1550#define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
1551
1552#define PCU_PWM_FAN_SPEED _MMIO(0x138140)
1553
1554#define GEN12_RPSTAT1 _MMIO(0x1381b4)
1555#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
1556#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
1557
1558#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
1559#define GEN11_CSME (31)
1560#define GEN12_HECI_2 (30)
1561#define GEN11_GUNIT (28)
1562#define GEN11_GUC (25)
1563#define MTL_MGUC (24)
1564#define GEN11_WDPERF (20)
1565#define GEN11_KCR (19)
1566#define GEN11_GTPM (16)
1567#define GEN11_BCS (15)
1568#define XEHPC_BCS1 (14)
1569#define XEHPC_BCS2 (13)
1570#define XEHPC_BCS3 (12)
1571#define XEHPC_BCS4 (11)
1572#define XEHPC_BCS5 (10)
1573#define XEHPC_BCS6 (9)
1574#define XEHPC_BCS7 (8)
1575#define XEHPC_BCS8 (23)
1576#define GEN12_CCS3 (7)
1577#define GEN12_CCS2 (6)
1578#define GEN12_CCS1 (5)
1579#define GEN12_CCS0 (4)
1580#define GEN11_RCS0 (0)
1581#define GEN11_VECS(x) (31 - (x))
1582#define GEN11_VCS(x) (x)
1583
1584#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
1585#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
1586#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
1587#define ENGINE1_MASK REG_GENMASK(31, 16)
1588#define ENGINE0_MASK REG_GENMASK(15, 0)
1589#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
1590#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
1591#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
1592#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
1593
1594#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
1595#define GEN11_INTR_DATA_VALID (1 << 31)
1596#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
1597#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
1598#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
1599/* irq instances for OTHER_CLASS */
1600#define OTHER_GUC_INSTANCE 0
1601#define OTHER_GTPM_INSTANCE 1
1602#define OTHER_GSC_HECI_2_INSTANCE 3
1603#define OTHER_KCR_INSTANCE 4
1604#define OTHER_GSC_INSTANCE 6
1605#define OTHER_MEDIA_GUC_INSTANCE 16
1606#define OTHER_MEDIA_GTPM_INSTANCE 17
1607
1608#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
1609
1610#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
1611#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
1612#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
1613#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
1614#define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0)
1615#define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)
1616#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
1617#define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)
1618#define GEN12_HECI2_RSVD_INTR_MASK _MMIO(0x1900e4)
1619#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
1620#define MTL_GUC_MGUC_INTR_MASK _MMIO(0x1900e8) /* MTL+ */
1621#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
1622#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
1623#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
1624#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
1625#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
1626#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110)
1627#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114)
1628#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118)
1629#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c)
1630
1631#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
1632
1633/*
1634 * Standalone Media's non-engine GT registers are located at their regular GT
1635 * offsets plus 0x380000. This extra offset is stored inside the intel_uncore
1636 * structure so that the existing code can be used for both GTs without
1637 * modification.
1638 */
1639#define MTL_MEDIA_GSI_BASE 0x380000
1640
1641#endif /* __INTEL_GT_REGS__ */
1642

source code of linux/drivers/gpu/drm/i915/gt/intel_gt_regs.h