| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __VLV_DPIO_PHY_REGS_H__ |
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| 7 | #define __VLV_DPIO_PHY_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | #define _VLV_CMN(dw) (0x8100 + (dw) * 4) |
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| 12 | #define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4) |
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| 13 | #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */ |
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| 14 | #define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4) |
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| 15 | #define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */ |
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| 16 | #define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4) |
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| 17 | #define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4) |
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| 18 | #define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4) |
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| 19 | #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) |
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| 20 | #define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4) |
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| 21 | #define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4) |
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| 22 | |
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| 23 | /* |
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| 24 | * Per pipe/PLL DPIO regs |
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| 25 | */ |
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| 26 | #define VLV_PLL_DW3(ch) _VLV_PLL((ch), 3) |
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| 27 | #define DPIO_S1_DIV_MASK REG_GENMASK(30, 28) |
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| 28 | #define DPIO_S1_DIV(s1) REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1)) |
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| 29 | #define DPIO_S1_DIV_DAC 0 /* 10, DAC 25-225M rate */ |
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| 30 | #define DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */ |
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| 31 | #define DPIO_S1_DIV_LVDS1 2 /* 14 */ |
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| 32 | #define DPIO_S1_DIV_LVDS2 3 /* 7 */ |
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| 33 | #define DPIO_K_DIV_MASK REG_GENMASK(27, 24) |
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| 34 | #define DPIO_K_DIV(k) REG_FIELD_PREP(DPIO_K_DIV_MASK, (k)) |
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| 35 | #define DPIO_P1_DIV_MASK REG_GENMASK(23, 21) |
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| 36 | #define DPIO_P1_DIV(p1) REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1)) |
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| 37 | #define DPIO_P2_DIV_MASK REG_GENMASK(20, 16) |
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| 38 | #define DPIO_P2_DIV(p2) REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2)) |
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| 39 | #define DPIO_N_DIV_MASK REG_GENMASK(15, 12) |
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| 40 | #define DPIO_N_DIV(n) REG_FIELD_PREP(DPIO_N_DIV_MASK, (n)) |
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| 41 | #define DPIO_ENABLE_CALIBRATION REG_BIT(11) |
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| 42 | #define DPIO_M1_DIV_MASK REG_GENMASK(10, 8) |
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| 43 | #define DPIO_M1_DIV(m1) REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1)) |
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| 44 | #define DPIO_M2_DIV_MASK REG_GENMASK(7, 0) |
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| 45 | #define DPIO_M2_DIV(m2) REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2)) |
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| 46 | |
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| 47 | #define VLV_PLL_DW5(ch) _VLV_PLL((ch), 5) |
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| 48 | #define DPIO_REFSEL_OVERRIDE REG_BIT(27) |
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| 49 | #define DPIO_PLL_MODESEL_MASK REG_GENMASK(26, 24) |
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| 50 | #define DPIO_BIAS_CURRENT_CTL_MASK REG_GENMASK(22, 20) /* always 0x7 */ |
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| 51 | #define DPIO_PLL_REFCLK_SEL_MASK REG_GENMASK(17, 16) |
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| 52 | #define DPIO_DRIVER_CTL_MASK REG_GENMASK(15, 12) /* always set to 0x8 */ |
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| 53 | #define DPIO_CLK_BIAS_CTL_MASK REG_GENMASK(11, 8) /* always set to 0x5 */ |
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| 54 | |
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| 55 | #define VLV_PLL_DW7(ch) _VLV_PLL((ch), 7) |
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| 56 | |
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| 57 | #define VLV_PLL_DW16(ch) _VLV_PLL((ch), 16) |
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| 58 | |
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| 59 | #define VLV_PLL_DW17(ch) _VLV_PLL((ch), 17) |
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| 60 | |
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| 61 | #define VLV_PLL_DW18(ch) _VLV_PLL((ch), 18) |
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| 62 | |
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| 63 | #define VLV_PLL_DW19(ch) _VLV_PLL((ch), 19) |
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| 64 | |
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| 65 | #define VLV_REF_DW11 _VLV_REF(11) |
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| 66 | |
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| 67 | #define VLV_CMN_DW0 _VLV_CMN(0) |
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| 68 | |
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| 69 | /* |
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| 70 | * Per DDI channel DPIO regs |
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| 71 | */ |
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| 72 | #define VLV_PCS_DW0_GRP(ch) _VLV_PCS_GRP((ch), 0) |
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| 73 | #define VLV_PCS01_DW0(ch) _VLV_PCS((ch), 0, 0) |
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| 74 | #define VLV_PCS23_DW0(ch) _VLV_PCS((ch), 1, 0) |
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| 75 | #define DPIO_PCS_TX_LANE2_RESET REG_BIT(16) |
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| 76 | #define DPIO_PCS_TX_LANE1_RESET REG_BIT(7) |
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| 77 | #define DPIO_LEFT_TXFIFO_RST_MASTER2 REG_BIT(4) |
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| 78 | #define DPIO_RIGHT_TXFIFO_RST_MASTER2 REG_BIT(3) |
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| 79 | |
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| 80 | #define VLV_PCS_DW1_GRP(ch) _VLV_PCS_GRP((ch), 1) |
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| 81 | #define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1) |
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| 82 | #define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1) |
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| 83 | #define CHV_PCS_REQ_SOFTRESET_EN REG_BIT(23) |
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| 84 | #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN REG_BIT(22) |
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| 85 | #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN REG_BIT(21) |
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| 86 | #define DPIO_PCS_CLK_DATAWIDTH_MASK REG_GENMASK(7, 6) |
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| 87 | #define DPIO_PCS_CLK_DATAWIDTH_8_10 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1) |
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| 88 | #define DPIO_PCS_CLK_DATAWIDTH_16_20 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2) |
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| 89 | #define DPIO_PCS_CLK_DATAWIDTH_32_40 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3) |
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| 90 | #define DPIO_PCS_CLK_SOFT_RESET REG_BIT(5) |
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| 91 | |
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| 92 | #define VLV_PCS_DW8_GRP(ch) _VLV_PCS_GRP((ch), 8) |
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| 93 | #define VLV_PCS01_DW8(ch) _VLV_PCS((ch), 0, 8) |
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| 94 | #define VLV_PCS23_DW8(ch) _VLV_PCS((ch), 1, 8) |
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| 95 | #define DPIO_PCS_USEDCLKCHANNEL REG_BIT(21) |
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| 96 | #define DPIO_PCS_USEDCLKCHANNEL_OVRRIDE REG_BIT(20) |
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| 97 | |
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| 98 | #define VLV_PCS_DW9_GRP(ch) _VLV_PCS_GRP((ch), 9) |
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| 99 | #define VLV_PCS01_DW9(ch) _VLV_PCS((ch), 0, 9) |
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| 100 | #define VLV_PCS23_DW9(ch) _VLV_PCS((ch), 1, 9) |
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| 101 | #define DPIO_PCS_TX2MARGIN_MASK REG_GENMASK(15, 13) |
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| 102 | #define DPIO_PCS_TX2MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0) |
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| 103 | #define DPIO_PCS_TX2MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1) |
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| 104 | #define DPIO_PCS_TX1MARGIN_MASK REG_GENMASK(12, 10) |
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| 105 | #define DPIO_PCS_TX1MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0) |
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| 106 | #define DPIO_PCS_TX1MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1) |
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| 107 | |
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| 108 | #define VLV_PCS_DW10_GRP(ch) _VLV_PCS_GRP((ch), 10) |
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| 109 | #define VLV_PCS01_DW10(ch) _VLV_PCS((ch), 0, 10) |
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| 110 | #define VLV_PCS23_DW10(ch) _VLV_PCS((ch), 1, 10) |
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| 111 | #define DPIO_PCS_SWING_CALC_TX1_TX3 REG_BIT(31) |
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| 112 | #define DPIO_PCS_SWING_CALC_TX0_TX2 REG_BIT(30) |
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| 113 | #define DPIO_PCS_TX2DEEMP_MASK REG_GENMASK(27, 24) |
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| 114 | #define DPIO_PCS_TX2DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0) |
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| 115 | #define DPIO_PCS_TX2DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2) |
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| 116 | #define DPIO_PCS_TX1DEEMP_MASK REG_GENMASK(19, 16) |
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| 117 | #define DPIO_PCS_TX1DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0) |
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| 118 | #define DPIO_PCS_TX1DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2) |
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| 119 | |
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| 120 | #define VLV_PCS_DW11_GRP(ch) _VLV_PCS_GRP((ch), 11) |
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| 121 | #define VLV_PCS01_DW11(ch) _VLV_PCS((ch), 0, 11) |
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| 122 | #define VLV_PCS23_DW11(ch) _VLV_PCS((ch), 1, 11) |
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| 123 | #define DPIO_TX2_STAGGER_MASK_MASK REG_GENMASK(28, 24) |
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| 124 | #define DPIO_TX2_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x)) |
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| 125 | #define DPIO_LANEDESKEW_STRAP_OVRD REG_BIT(3) |
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| 126 | #define DPIO_LEFT_TXFIFO_RST_MASTER REG_BIT(1) |
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| 127 | #define DPIO_RIGHT_TXFIFO_RST_MASTER REG_BIT(0) |
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| 128 | |
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| 129 | #define VLV_PCS_DW12_GRP(ch) _VLV_PCS_GRP((ch), 12) |
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| 130 | #define VLV_PCS01_DW12(ch) _VLV_PCS((ch), 0, 12) |
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| 131 | #define VLV_PCS23_DW12(ch) _VLV_PCS((ch), 1, 12) |
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| 132 | #define DPIO_TX2_STAGGER_MULT_MASK REG_GENMASK(22, 20) |
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| 133 | #define DPIO_TX2_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x)) |
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| 134 | #define DPIO_TX1_STAGGER_MULT_MASK REG_GENMASK(20, 16) |
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| 135 | #define DPIO_TX1_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x)) |
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| 136 | #define DPIO_TX1_STAGGER_MASK_MASK REG_GENMASK(12, 8) |
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| 137 | #define DPIO_TX1_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x)) |
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| 138 | #define DPIO_LANESTAGGER_STRAP_OVRD REG_BIT(6) |
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| 139 | #define DPIO_LANESTAGGER_STRAP_MASK REG_GENMASK(4, 0) |
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| 140 | #define DPIO_LANESTAGGER_STRAP(x) REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x)) |
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| 141 | |
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| 142 | #define VLV_PCS_DW14_GRP(ch) _VLV_PCS_GRP((ch), 14) |
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| 143 | #define VLV_PCS01_DW14(ch) _VLV_PCS((ch), 0, 14) |
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| 144 | #define VLV_PCS23_DW14(ch) _VLV_PCS((ch), 1, 14) |
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| 145 | |
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| 146 | #define VLV_PCS_DW17_BCAST _VLV_PCS_BCAST(17) |
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| 147 | #define VLV_PCS_DW17_GRP(ch) _VLV_PCS_GRP((ch), 17) |
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| 148 | #define VLV_PCS01_DW17(ch) _VLV_PCS((ch), 0, 17) |
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| 149 | #define VLV_PCS23_DW17(ch) _VLV_PCS((ch), 1, 17) |
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| 150 | |
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| 151 | #define VLV_PCS_DW23_GRP(ch) _VLV_PCS_GRP((ch), 23) |
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| 152 | #define VLV_PCS01_DW23(ch) _VLV_PCS((ch), 0, 23) |
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| 153 | #define VLV_PCS23_DW23(ch) _VLV_PCS((ch), 1, 23) |
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| 154 | |
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| 155 | #define VLV_TX_DW2_GRP(ch) _VLV_TX_GRP((ch), 2) |
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| 156 | #define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) |
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| 157 | #define DPIO_SWING_MARGIN000_MASK REG_GENMASK(23, 16) |
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| 158 | #define DPIO_SWING_MARGIN000(x) REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x)) |
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| 159 | #define DPIO_UNIQ_TRANS_SCALE_MASK REG_GENMASK(15, 8) |
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| 160 | #define DPIO_UNIQ_TRANS_SCALE(x) REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x)) |
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| 161 | |
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| 162 | #define VLV_TX_DW3_GRP(ch) _VLV_TX_GRP((ch), 3) |
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| 163 | #define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) |
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| 164 | /* The following bit for CHV phy */ |
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| 165 | #define DPIO_TX_UNIQ_TRANS_SCALE_EN REG_BIT(27) |
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| 166 | #define DPIO_SWING_MARGIN101_MASK REG_GENMASK(23, 16) |
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| 167 | #define DPIO_SWING_MARGIN101(x) REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x)) |
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| 168 | |
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| 169 | #define VLV_TX_DW4_GRP(ch) _VLV_TX_GRP((ch), 4) |
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| 170 | #define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) |
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| 171 | #define DPIO_SWING_DEEMPH9P5_MASK REG_GENMASK(31, 24) |
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| 172 | #define DPIO_SWING_DEEMPH9P5(x) REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x)) |
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| 173 | #define DPIO_SWING_DEEMPH6P0_MASK REG_GENMASK(23, 16) |
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| 174 | #define DPIO_SWING_DEEMPH6P0_SHIFT REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x)) |
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| 175 | |
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| 176 | #define VLV_TX_DW5_GRP(ch) _VLV_TX_GRP((ch), 5) |
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| 177 | #define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) |
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| 178 | #define DPIO_TX_OCALINIT_EN REG_BIT(31) |
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| 179 | |
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| 180 | #define VLV_TX_DW11_GRP(ch) _VLV_TX_GRP((ch), 11) |
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| 181 | #define VLV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) |
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| 182 | |
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| 183 | #define VLV_TX_DW14_GRP(ch) _VLV_TX_GRP((ch), 14) |
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| 184 | #define VLV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) |
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| 185 | |
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| 186 | /* CHV dpPhy registers */ |
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| 187 | #define CHV_PLL_DW0(ch) _CHV_PLL((ch), 0) |
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| 188 | #define DPIO_CHV_M2_DIV_MASK REG_GENMASK(7, 0) |
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| 189 | #define DPIO_CHV_M2_DIV(m2) REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2)) |
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| 190 | |
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| 191 | #define CHV_PLL_DW1(ch) _CHV_PLL((ch), 1) |
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| 192 | #define DPIO_CHV_N_DIV_MASK REG_GENMASK(11, 8) |
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| 193 | #define DPIO_CHV_N_DIV(n) REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n)) |
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| 194 | #define DPIO_CHV_M1_DIV_MASK REG_GENMASK(2, 0) |
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| 195 | #define DPIO_CHV_M1_DIV(m1) REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1)) |
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| 196 | #define DPIO_CHV_M1_DIV_BY_2 0 |
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| 197 | |
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| 198 | #define CHV_PLL_DW2(ch) _CHV_PLL((ch), 2) |
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| 199 | #define DPIO_CHV_M2_FRAC_DIV_MASK REG_GENMASK(21, 0) |
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| 200 | #define DPIO_CHV_M2_FRAC_DIV(m2_frac) REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac)) |
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| 201 | |
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| 202 | #define CHV_PLL_DW3(ch) _CHV_PLL((ch), 3) |
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| 203 | #define DPIO_CHV_FRAC_DIV_EN REG_BIT(16) |
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| 204 | #define DPIO_CHV_SECOND_MOD REG_BIT(8) |
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| 205 | #define DPIO_CHV_FEEDFWD_GAIN_MASK REG_GENMASK(3, 0) |
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| 206 | #define DPIO_CHV_FEEDFWD_GAIN(x) REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x)) |
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| 207 | |
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| 208 | #define CHV_PLL_DW6(ch) _CHV_PLL((ch), 6) |
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| 209 | #define DPIO_CHV_GAIN_CTRL_MASK REG_GENMASK(18, 16) |
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| 210 | #define DPIO_CHV_GAIN_CTRL(x) REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x)) |
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| 211 | #define DPIO_CHV_INT_COEFF_MASK REG_GENMASK(12, 8) |
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| 212 | #define DPIO_CHV_INT_COEFF(x) REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x)) |
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| 213 | #define DPIO_CHV_PROP_COEFF_MASK REG_GENMASK(3, 0) |
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| 214 | #define DPIO_CHV_PROP_COEFF(x) REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x)) |
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| 215 | |
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| 216 | #define CHV_PLL_DW8(ch) _CHV_PLL((ch), 8) |
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| 217 | #define DPIO_CHV_TDC_TARGET_CNT_MASK REG_GENMASK(9, 0) |
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| 218 | #define DPIO_CHV_TDC_TARGET_CNT(x) REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x)) |
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| 219 | |
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| 220 | #define CHV_PLL_DW9(ch) _CHV_PLL((ch), 9) |
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| 221 | #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) |
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| 222 | #define DPIO_CHV_INT_LOCK_THRESHOLD(x) REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x)) |
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| 223 | #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE REG_BIT(0) /* 1: coarse & 0 : fine */ |
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| 224 | |
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| 225 | #define CHV_CMN_DW0_CH0 _CHV_CMN(0, 0) |
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| 226 | #define DPIO_ALLDL_POWERDOWN_CH0 REG_BIT(19) |
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| 227 | #define DPIO_ANYDL_POWERDOWN_CH0 REG_BIT(18) |
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| 228 | #define DPIO_ALLDL_POWERDOWN BIT(1) |
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| 229 | #define DPIO_ANYDL_POWERDOWN BIT(0) |
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| 230 | |
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| 231 | #define CHV_CMN_DW5_CH0 _CHV_CMN(0, 5) |
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| 232 | #define CHV_BUFRIGHTENA1_MASK REG_GENMASK(21, 20) |
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| 233 | #define CHV_BUFRIGHTENA1_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0) |
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| 234 | #define CHV_BUFRIGHTENA1_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1) |
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| 235 | #define CHV_BUFRIGHTENA1_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3) |
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| 236 | #define CHV_BUFLEFTENA1_MASK REG_GENMASK(23, 22) |
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| 237 | #define CHV_BUFLEFTENA1_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0) |
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| 238 | #define CHV_BUFLEFTENA1_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1) |
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| 239 | #define CHV_BUFLEFTENA1_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3) |
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| 240 | |
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| 241 | #define CHV_CMN_DW13_CH0 _CHV_CMN(0, 13) |
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| 242 | #define CHV_CMN_DW0_CH1 _CHV_CMN(1, 0) |
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| 243 | #define DPIO_CHV_S1_DIV_MASK REG_GENMASK(23, 21) |
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| 244 | #define DPIO_CHV_S1_DIV(s1) REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1)) |
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| 245 | #define DPIO_CHV_P1_DIV_MASK REG_GENMASK(15, 13) |
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| 246 | #define DPIO_CHV_P1_DIV(p1) REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1)) |
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| 247 | #define DPIO_CHV_P2_DIV_MASK REG_GENMASK(12, 8) |
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| 248 | #define DPIO_CHV_P2_DIV(p2) REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2)) |
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| 249 | #define DPIO_CHV_K_DIV_MASK REG_GENMASK(7, 4) |
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| 250 | #define DPIO_CHV_K_DIV(k) REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k)) |
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| 251 | #define DPIO_PLL_FREQLOCK REG_BIT(1) |
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| 252 | #define DPIO_PLL_LOCK REG_BIT(0) |
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| 253 | #define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1) |
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| 254 | |
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| 255 | #define CHV_CMN_DW14_CH0 _CHV_CMN(0, 14) |
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| 256 | #define CHV_CMN_DW1_CH1 _CHV_CMN(1, 1) |
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| 257 | #define DPIO_AFC_RECAL REG_BIT(14) |
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| 258 | #define DPIO_DCLKP_EN REG_BIT(13) |
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| 259 | #define CHV_BUFLEFTENA2_MASK REG_GENMASK(18, 17) /* CL2 DW1 only */ |
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| 260 | #define CHV_BUFLEFTENA2_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0) |
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| 261 | #define CHV_BUFLEFTENA2_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1) |
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| 262 | #define CHV_BUFLEFTENA2_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3) |
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| 263 | #define CHV_BUFRIGHTENA2_MASK REG_GENMASK(20, 19) /* CL2 DW1 only */ |
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| 264 | #define CHV_BUFRIGHTENA2_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0) |
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| 265 | #define CHV_BUFRIGHTENA2_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1) |
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| 266 | #define CHV_BUFRIGHTENA2_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3) |
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| 267 | #define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1) |
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| 268 | |
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| 269 | #define CHV_CMN_DW19_CH0 _CHV_CMN(0, 19) |
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| 270 | #define CHV_CMN_DW6_CH1 _CHV_CMN(1, 6) |
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| 271 | #define DPIO_ALLDL_POWERDOWN_CH1 REG_BIT(30) /* CL2 DW6 only */ |
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| 272 | #define DPIO_ANYDL_POWERDOWN_CH1 REG_BIT(29) /* CL2 DW6 only */ |
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| 273 | #define DPIO_DYNPWRDOWNEN_CH1 REG_BIT(28) /* CL2 DW6 only */ |
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| 274 | #define CHV_CMN_USEDCLKCHANNEL REG_BIT(13) |
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| 275 | #define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1) |
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| 276 | |
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| 277 | #define CHV_CMN_DW28 _CHV_CMN(0, 28) |
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| 278 | #define DPIO_CL1POWERDOWNEN REG_BIT(23) |
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| 279 | #define DPIO_DYNPWRDOWNEN_CH0 REG_BIT(22) |
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| 280 | #define DPIO_SUS_CLK_CONFIG_MASK REG_GENMASK(1, 0) |
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| 281 | #define DPIO_SUS_CLK_CONFIG_ON REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0) |
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| 282 | #define DPIO_SUS_CLK_CONFIG_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1) |
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| 283 | #define DPIO_SUS_CLK_CONFIG_GATE REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2) |
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| 284 | #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3) |
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| 285 | |
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| 286 | #define CHV_CMN_DW30 _CHV_CMN(0, 30) |
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| 287 | #define DPIO_CL2_LDOFUSE_PWRENB REG_BIT(6) |
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| 288 | #define DPIO_LRC_BYPASS REG_BIT(3) |
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| 289 | |
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| 290 | #define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) |
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| 291 | #define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) |
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| 292 | #define CHV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) |
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| 293 | #define CHV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) |
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| 294 | #define CHV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) |
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| 295 | #define CHV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) |
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| 296 | #define CHV_TX_DW6(ch, lane) _VLV_TX((ch), (lane), 6) |
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| 297 | #define CHV_TX_DW7(ch, lane) _VLV_TX((ch), (lane), 7) |
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| 298 | #define CHV_TX_DW8(ch, lane) _VLV_TX((ch), (lane), 8) |
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| 299 | #define CHV_TX_DW9(ch, lane) _VLV_TX((ch), (lane), 9) |
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| 300 | #define CHV_TX_DW10(ch, lane) _VLV_TX((ch), (lane), 10) |
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| 301 | |
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| 302 | #define CHV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) |
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| 303 | #define DPIO_FRC_LATENCY_MASK REG_GENMASK(10, 8) |
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| 304 | #define DPIO_FRC_LATENCY(x) REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x)) |
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| 305 | |
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| 306 | #define CHV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) |
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| 307 | #define DPIO_UPAR REG_BIT(30) |
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| 308 | |
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| 309 | #endif /* __VLV_DPIO_PHY_REGS_H__ */ |
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| 310 | |
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