| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __SKL_WATERMARK_H__ |
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| 7 | #define __SKL_WATERMARK_H__ |
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| 8 | |
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| 9 | #include <linux/types.h> |
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| 10 | |
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| 11 | enum plane_id; |
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| 12 | struct intel_atomic_state; |
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| 13 | struct intel_crtc; |
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| 14 | struct intel_crtc_state; |
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| 15 | struct intel_dbuf_state; |
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| 16 | struct intel_display; |
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| 17 | struct intel_plane; |
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| 18 | struct intel_plane_state; |
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| 19 | struct skl_ddb_entry; |
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| 20 | struct skl_pipe_wm; |
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| 21 | struct skl_wm_level; |
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| 22 | |
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| 23 | u8 intel_enabled_dbuf_slices_mask(struct intel_display *display); |
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| 24 | |
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| 25 | void intel_sagv_pre_plane_update(struct intel_atomic_state *state); |
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| 26 | void intel_sagv_post_plane_update(struct intel_atomic_state *state); |
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| 27 | bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state); |
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| 28 | bool intel_has_sagv(struct intel_display *display); |
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| 29 | |
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| 30 | u32 skl_ddb_dbuf_slice_mask(struct intel_display *display, |
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| 31 | const struct skl_ddb_entry *entry); |
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| 32 | |
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| 33 | bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, |
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| 34 | const struct skl_ddb_entry *entries, |
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| 35 | int num_entries, int ignore_idx); |
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| 36 | |
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| 37 | void intel_wm_state_verify(struct intel_atomic_state *state, |
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| 38 | struct intel_crtc *crtc); |
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| 39 | |
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| 40 | void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc); |
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| 41 | void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc, |
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| 42 | struct intel_plane *plane); |
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| 43 | |
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| 44 | void skl_watermark_ipc_init(struct intel_display *display); |
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| 45 | void skl_watermark_ipc_update(struct intel_display *display); |
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| 46 | bool skl_watermark_ipc_enabled(struct intel_display *display); |
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| 47 | void skl_watermark_debugfs_register(struct intel_display *display); |
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| 48 | |
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| 49 | unsigned int skl_watermark_max_latency(struct intel_display *display, |
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| 50 | int initial_wm_level); |
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| 51 | void skl_wm_init(struct intel_display *display); |
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| 52 | |
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| 53 | const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, |
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| 54 | enum plane_id plane_id, |
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| 55 | int level); |
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| 56 | const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, |
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| 57 | enum plane_id plane_id); |
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| 58 | unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, |
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| 59 | struct intel_plane *plane, int width, |
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| 60 | int height, int cpp); |
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| 61 | |
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| 62 | struct intel_dbuf_state * |
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| 63 | intel_atomic_get_dbuf_state(struct intel_atomic_state *state); |
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| 64 | |
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| 65 | int intel_dbuf_num_enabled_slices(const struct intel_dbuf_state *dbuf_state); |
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| 66 | int intel_dbuf_num_active_pipes(const struct intel_dbuf_state *dbuf_state); |
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| 67 | |
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| 68 | int intel_dbuf_init(struct intel_display *display); |
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| 69 | int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, |
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| 70 | int ratio); |
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| 71 | |
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| 72 | void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); |
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| 73 | void intel_dbuf_post_plane_update(struct intel_atomic_state *state); |
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| 74 | void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display, |
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| 75 | int ratio, bool joined_mbus); |
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| 76 | void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state); |
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| 77 | void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state); |
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| 78 | void intel_program_dpkgc_latency(struct intel_atomic_state *state); |
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| 79 | |
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| 80 | bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state); |
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| 81 | |
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| 82 | unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state); |
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| 83 | unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state); |
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| 84 | |
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| 85 | #endif /* __SKL_WATERMARK_H__ */ |
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| 86 | |
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| 87 | |
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