| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2024 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __SKL_UNIVERSAL_PLANE_REGS_H__ |
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| 7 | #define __SKL_UNIVERSAL_PLANE_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | #define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ |
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| 12 | _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b))) |
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| 13 | #define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ |
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| 14 | (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4) |
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| 15 | #define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ |
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| 16 | _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) |
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| 17 | #define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ |
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| 18 | _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) |
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| 19 | |
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| 20 | #define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ |
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| 21 | _PICK_EVEN_2RANGES((plane), PLANE_5, \ |
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| 22 | _PIPE((pipe), (reg_1_a), (reg_1_b)), \ |
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| 23 | _PIPE((pipe), (reg_2_a), (reg_2_b)), \ |
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| 24 | _PIPE((pipe), (reg_5_a), (reg_5_b)), \ |
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| 25 | _PIPE((pipe), (reg_6_a), (reg_6_b))) |
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| 26 | #define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ |
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| 27 | _MMIO(_SEL_FETCH((pipe), (plane), \ |
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| 28 | (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b), \ |
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| 29 | (reg_5_a), (reg_5_b), (reg_6_a), (reg_6_b))) |
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| 30 | |
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| 31 | #define _PLANE_CTL_1_A 0x70180 |
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| 32 | #define _PLANE_CTL_2_A 0x70280 |
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| 33 | #define _PLANE_CTL_1_B 0x71180 |
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| 34 | #define _PLANE_CTL_2_B 0x71280 |
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| 35 | #define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 36 | _PLANE_CTL_1_A, _PLANE_CTL_1_B, \ |
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| 37 | _PLANE_CTL_2_A, _PLANE_CTL_2_B) |
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| 38 | #define PLANE_CTL_ENABLE REG_BIT(31) |
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| 39 | #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ |
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| 40 | #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ |
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| 41 | #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ |
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| 42 | #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) |
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| 43 | /* |
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| 44 | * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition |
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| 45 | * expanded to include bit 23 as well. However, the shift-24 based values |
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| 46 | * correctly map to the same formats in ICL, as long as bit 23 is set to 0 |
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| 47 | */ |
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| 48 | #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ |
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| 49 | #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ |
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| 50 | #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) |
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| 51 | #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) |
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| 52 | #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) |
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| 53 | #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) |
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| 54 | #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) |
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| 55 | #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) |
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| 56 | #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) |
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| 57 | #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) |
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| 58 | #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) |
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| 59 | #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) |
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| 60 | #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) |
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| 61 | #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) |
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| 62 | #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) |
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| 63 | #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) |
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| 64 | #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) |
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| 65 | #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) |
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| 66 | #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) |
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| 67 | #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ |
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| 68 | #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) |
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| 69 | #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) |
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| 70 | #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) |
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| 71 | #define PLANE_CTL_ORDER_RGBX REG_BIT(20) |
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| 72 | #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) |
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| 73 | #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) |
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| 74 | #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) |
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| 75 | #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) |
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| 76 | #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) |
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| 77 | #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) |
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| 78 | #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) |
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| 79 | #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) |
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| 80 | #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) |
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| 81 | #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ |
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| 82 | #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ |
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| 83 | #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) |
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| 84 | #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) |
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| 85 | #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) |
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| 86 | #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) |
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| 87 | #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) |
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| 88 | #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) |
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| 89 | #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) |
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| 90 | #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) |
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| 91 | #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ |
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| 92 | #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ |
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| 93 | #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) |
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| 94 | #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) |
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| 95 | #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) |
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| 96 | #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) |
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| 97 | #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) |
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| 98 | #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) |
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| 99 | #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) |
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| 100 | #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) |
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| 101 | |
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| 102 | #define _PLANE_STRIDE_1_A 0x70188 |
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| 103 | #define _PLANE_STRIDE_2_A 0x70288 |
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| 104 | #define _PLANE_STRIDE_1_B 0x71188 |
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| 105 | #define _PLANE_STRIDE_2_B 0x71288 |
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| 106 | #define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 107 | _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B, \ |
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| 108 | _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) |
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| 109 | #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) |
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| 110 | #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) |
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| 111 | |
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| 112 | #define _PLANE_POS_1_A 0x7018c |
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| 113 | #define _PLANE_POS_2_A 0x7028c |
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| 114 | #define _PLANE_POS_1_B 0x7118c |
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| 115 | #define _PLANE_POS_2_B 0x7128c |
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| 116 | #define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 117 | _PLANE_POS_1_A, _PLANE_POS_1_B, \ |
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| 118 | _PLANE_POS_2_A, _PLANE_POS_2_B) |
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| 119 | #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) |
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| 120 | #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) |
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| 121 | #define PLANE_POS_X_MASK REG_GENMASK(15, 0) |
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| 122 | #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) |
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| 123 | |
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| 124 | #define _PLANE_SIZE_1_A 0x70190 |
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| 125 | #define _PLANE_SIZE_2_A 0x70290 |
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| 126 | #define _PLANE_SIZE_1_B 0x71190 |
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| 127 | #define _PLANE_SIZE_2_B 0x71290 |
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| 128 | #define PLANE_SIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 129 | _PLANE_SIZE_1_A, _PLANE_SIZE_1_B, \ |
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| 130 | _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) |
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| 131 | #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) |
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| 132 | #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) |
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| 133 | #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) |
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| 134 | #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) |
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| 135 | |
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| 136 | #define _PLANE_KEYVAL_1_A 0x70194 |
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| 137 | #define _PLANE_KEYVAL_2_A 0x70294 |
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| 138 | #define _PLANE_KEYVAL_1_B 0x71194 |
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| 139 | #define _PLANE_KEYVAL_2_B 0x71294 |
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| 140 | #define PLANE_KEYVAL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane),\ |
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| 141 | _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B, \ |
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| 142 | _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) |
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| 143 | |
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| 144 | #define _PLANE_KEYMSK_1_A 0x70198 |
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| 145 | #define _PLANE_KEYMSK_2_A 0x70298 |
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| 146 | #define _PLANE_KEYMSK_1_B 0x71198 |
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| 147 | #define _PLANE_KEYMSK_2_B 0x71298 |
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| 148 | #define PLANE_KEYMSK(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 149 | _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B, \ |
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| 150 | _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) |
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| 151 | #define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) |
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| 152 | |
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| 153 | #define _PLANE_SURF_1_A 0x7019c |
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| 154 | #define _PLANE_SURF_2_A 0x7029c |
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| 155 | #define _PLANE_SURF_1_B 0x7119c |
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| 156 | #define _PLANE_SURF_2_B 0x7129c |
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| 157 | #define PLANE_SURF(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 158 | _PLANE_SURF_1_A, _PLANE_SURF_1_B, \ |
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| 159 | _PLANE_SURF_2_A, _PLANE_SURF_2_B) |
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| 160 | #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) |
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| 161 | #define PLANE_SURF_DECRYPT REG_BIT(2) |
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| 162 | #define PLANE_SURF_ASYNC_UPDATE REG_BIT(0) |
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| 163 | |
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| 164 | #define _PLANE_KEYMAX_1_A 0x701a0 |
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| 165 | #define _PLANE_KEYMAX_2_A 0x702a0 |
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| 166 | #define _PLANE_KEYMAX_1_B 0x711a0 |
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| 167 | #define _PLANE_KEYMAX_2_B 0x712a0 |
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| 168 | #define PLANE_KEYMAX(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 169 | _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B, \ |
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| 170 | _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) |
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| 171 | #define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) |
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| 172 | #define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) |
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| 173 | |
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| 174 | #define _PLANE_OFFSET_1_A 0x701a4 |
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| 175 | #define _PLANE_OFFSET_2_A 0x702a4 |
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| 176 | #define _PLANE_OFFSET_1_B 0x711a4 |
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| 177 | #define _PLANE_OFFSET_2_B 0x712a4 |
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| 178 | #define PLANE_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 179 | _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B, \ |
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| 180 | _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) |
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| 181 | #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) |
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| 182 | #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) |
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| 183 | #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) |
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| 184 | #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) |
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| 185 | |
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| 186 | #define _PLANE_SURFLIVE_1_A 0x701ac |
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| 187 | #define _PLANE_SURFLIVE_2_A 0x702ac |
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| 188 | #define _PLANE_SURFLIVE_1_B 0x711ac |
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| 189 | #define _PLANE_SURFLIVE_2_B 0x712ac |
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| 190 | #define PLANE_SURFLIVE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 191 | _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B, \ |
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| 192 | _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) |
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| 193 | |
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| 194 | #define _PLANE_CC_VAL_1_A 0x701b4 |
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| 195 | #define _PLANE_CC_VAL_2_A 0x702b4 |
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| 196 | #define _PLANE_CC_VAL_1_B 0x711b4 |
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| 197 | #define _PLANE_CC_VAL_2_B 0x712b4 |
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| 198 | #define PLANE_CC_VAL(pipe, plane, dw) _MMIO_SKL_PLANE_DW((pipe), (plane), (dw), \ |
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| 199 | _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B, \ |
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| 200 | _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) |
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| 201 | |
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| 202 | #define _PLANE_AUX_DIST_1_A 0x701c0 |
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| 203 | #define _PLANE_AUX_DIST_2_A 0x702c0 |
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| 204 | #define _PLANE_AUX_DIST_1_B 0x711c0 |
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| 205 | #define _PLANE_AUX_DIST_2_B 0x712c0 |
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| 206 | #define PLANE_AUX_DIST(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 207 | _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B, \ |
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| 208 | _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) |
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| 209 | #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) |
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| 210 | #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) |
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| 211 | #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) |
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| 212 | |
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| 213 | #define _PLANE_AUX_OFFSET_1_A 0x701c4 |
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| 214 | #define _PLANE_AUX_OFFSET_2_A 0x702c4 |
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| 215 | #define _PLANE_AUX_OFFSET_1_B 0x711c4 |
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| 216 | #define _PLANE_AUX_OFFSET_2_B 0x712c4 |
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| 217 | #define PLANE_AUX_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 218 | _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B, \ |
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| 219 | _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) |
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| 220 | |
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| 221 | #define _PLANE_CUS_CTL_1_A 0x701c8 |
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| 222 | #define _PLANE_CUS_CTL_2_A 0x702c8 |
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| 223 | #define _PLANE_CUS_CTL_1_B 0x711c8 |
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| 224 | #define _PLANE_CUS_CTL_2_B 0x712c8 |
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| 225 | #define PLANE_CUS_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 226 | _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B, \ |
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| 227 | _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) |
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| 228 | #define PLANE_CUS_ENABLE REG_BIT(31) |
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| 229 | #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) |
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| 230 | #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) |
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| 231 | #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) |
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| 232 | #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) |
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| 233 | #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) |
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| 234 | #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) |
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| 235 | #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) |
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| 236 | #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) |
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| 237 | #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) |
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| 238 | #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) |
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| 239 | #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) |
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| 240 | #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) |
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| 241 | #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) |
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| 242 | #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) |
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| 243 | #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) |
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| 244 | |
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| 245 | #define _PLANE_COLOR_CTL_1_A 0x701cc /* GLK+ */ |
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| 246 | #define _PLANE_COLOR_CTL_2_A 0x702cc |
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| 247 | #define _PLANE_COLOR_CTL_1_B 0x711cc |
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| 248 | #define _PLANE_COLOR_CTL_2_B 0x712cc |
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| 249 | #define PLANE_COLOR_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 250 | _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B, \ |
|---|
| 251 | _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) |
|---|
| 252 | #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ |
|---|
| 253 | #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) |
|---|
| 254 | #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ |
|---|
| 255 | #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ |
|---|
| 256 | #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ |
|---|
| 257 | #define PLANE_COLOR_POST_CSC_GAMMA_MULTSEG_ENABLE REG_BIT(15) /* TGL+ */ |
|---|
| 258 | #define PLANE_COLOR_PRE_CSC_GAMMA_ENABLE REG_BIT(14) |
|---|
| 259 | #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) |
|---|
| 260 | #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) |
|---|
| 261 | #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) |
|---|
| 262 | #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) |
|---|
| 263 | #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) |
|---|
| 264 | #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) |
|---|
| 265 | #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) |
|---|
| 266 | #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) |
|---|
| 267 | #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) |
|---|
| 268 | #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) |
|---|
| 269 | #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) |
|---|
| 270 | |
|---|
| 271 | #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701e0 |
|---|
| 272 | #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0 |
|---|
| 273 | #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0 |
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| 274 | #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0 |
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| 275 | #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ |
|---|
| 276 | _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B, \ |
|---|
| 277 | _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B) |
|---|
| 278 | |
|---|
| 279 | #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8 |
|---|
| 280 | #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8 |
|---|
| 281 | #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8 |
|---|
| 282 | #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8 |
|---|
| 283 | #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ |
|---|
| 284 | _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B, \ |
|---|
| 285 | _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B) |
|---|
| 286 | |
|---|
| 287 | #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 |
|---|
| 288 | #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 |
|---|
| 289 | #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 |
|---|
| 290 | #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 |
|---|
| 291 | #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ |
|---|
| 292 | _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \ |
|---|
| 293 | _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B) |
|---|
| 294 | |
|---|
| 295 | #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) |
|---|
| 296 | |
|---|
| 297 | #define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A 0x70160 |
|---|
| 298 | #define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B 0x71160 |
|---|
| 299 | #define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A 0x70260 |
|---|
| 300 | #define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B 0x71260 |
|---|
| 301 | #define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \ |
|---|
| 302 | _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B) |
|---|
| 303 | #define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \ |
|---|
| 304 | _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B) |
|---|
| 305 | #define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \ |
|---|
| 306 | _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe)) |
|---|
| 307 | |
|---|
| 308 | #define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A 0x70164 |
|---|
| 309 | #define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B 0x71164 |
|---|
| 310 | #define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A 0x70264 |
|---|
| 311 | #define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B 0x71264 |
|---|
| 312 | #define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \ |
|---|
| 313 | _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B) |
|---|
| 314 | #define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \ |
|---|
| 315 | _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B) |
|---|
| 316 | #define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \ |
|---|
| 317 | _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe)) |
|---|
| 318 | |
|---|
| 319 | #define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701d8 |
|---|
| 320 | #define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711d8 |
|---|
| 321 | #define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702d8 |
|---|
| 322 | #define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712d8 |
|---|
| 323 | #define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \ |
|---|
| 324 | _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B) |
|---|
| 325 | #define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \ |
|---|
| 326 | _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B) |
|---|
| 327 | #define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \ |
|---|
| 328 | _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe)) |
|---|
| 329 | |
|---|
| 330 | #define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701dc |
|---|
| 331 | #define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711dc |
|---|
| 332 | #define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702dc |
|---|
| 333 | #define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712dc |
|---|
| 334 | #define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \ |
|---|
| 335 | _PLANE_POST_CSC_GAMC_DATA_ENH_1_B) |
|---|
| 336 | #define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \ |
|---|
| 337 | _PLANE_POST_CSC_GAMC_DATA_ENH_2_B) |
|---|
| 338 | #define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \ |
|---|
| 339 | _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe)) |
|---|
| 340 | |
|---|
| 341 | #define _PLANE_POST_CSC_GAMC_INDEX_1_A 0x704d8 |
|---|
| 342 | #define _PLANE_POST_CSC_GAMC_INDEX_1_B 0x714d8 |
|---|
| 343 | #define _PLANE_POST_CSC_GAMC_INDEX_2_A 0x705d8 |
|---|
| 344 | #define _PLANE_POST_CSC_GAMC_INDEX_2_B 0x715d8 |
|---|
| 345 | #define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_1_A, \ |
|---|
| 346 | _PLANE_POST_CSC_GAMC_INDEX_1_B) |
|---|
| 347 | #define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_2_A, \ |
|---|
| 348 | _PLANE_POST_CSC_GAMC_INDEX_2_B) |
|---|
| 349 | #define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \ |
|---|
| 350 | _PLANE_POST_CSC_GAMC_INDEX_2(pipe)) |
|---|
| 351 | |
|---|
| 352 | #define _PLANE_POST_CSC_GAMC_DATA_1_A 0x704dc |
|---|
| 353 | #define _PLANE_POST_CSC_GAMC_DATA_1_B 0x714dc |
|---|
| 354 | #define _PLANE_POST_CSC_GAMC_DATA_2_A 0x705dc |
|---|
| 355 | #define _PLANE_POST_CSC_GAMC_DATA_2_B 0x715dc |
|---|
| 356 | #define _PLANE_POST_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_1_A, \ |
|---|
| 357 | _PLANE_POST_CSC_GAMC_DATA_1_B) |
|---|
| 358 | #define _PLANE_POST_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_2_A, \ |
|---|
| 359 | _PLANE_POST_CSC_GAMC_DATA_2_B) |
|---|
| 360 | #define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_1(pipe), \ |
|---|
| 361 | _PLANE_POST_CSC_GAMC_DATA_2(pipe)) |
|---|
| 362 | |
|---|
| 363 | #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0 |
|---|
| 364 | #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0 |
|---|
| 365 | #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702d0 |
|---|
| 366 | #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x712d0 |
|---|
| 367 | #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \ |
|---|
| 368 | _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B) |
|---|
| 369 | #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \ |
|---|
| 370 | _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B) |
|---|
| 371 | #define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \ |
|---|
| 372 | _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) |
|---|
| 373 | #define PLANE_PAL_PREC_AUTO_INCREMENT REG_BIT(10) |
|---|
| 374 | |
|---|
| 375 | #define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701d4 |
|---|
| 376 | #define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711d4 |
|---|
| 377 | #define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702d4 |
|---|
| 378 | #define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712d4 |
|---|
| 379 | #define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \ |
|---|
| 380 | _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B) |
|---|
| 381 | #define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \ |
|---|
| 382 | _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B) |
|---|
| 383 | #define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \ |
|---|
| 384 | _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)) |
|---|
| 385 | |
|---|
| 386 | #define _PLANE_PRE_CSC_GAMC_INDEX_1_A 0x704d0 |
|---|
| 387 | #define _PLANE_PRE_CSC_GAMC_INDEX_1_B 0x714d0 |
|---|
| 388 | #define _PLANE_PRE_CSC_GAMC_INDEX_2_A 0x705d0 |
|---|
| 389 | #define _PLANE_PRE_CSC_GAMC_INDEX_2_B 0x715d0 |
|---|
| 390 | #define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_1_A, \ |
|---|
| 391 | _PLANE_PRE_CSC_GAMC_INDEX_1_B) |
|---|
| 392 | #define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_2_A, \ |
|---|
| 393 | _PLANE_PRE_CSC_GAMC_INDEX_2_B) |
|---|
| 394 | #define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \ |
|---|
| 395 | _PLANE_PRE_CSC_GAMC_INDEX_2(pipe)) |
|---|
| 396 | |
|---|
| 397 | #define _PLANE_PRE_CSC_GAMC_DATA_1_A 0x704d4 |
|---|
| 398 | #define _PLANE_PRE_CSC_GAMC_DATA_1_B 0x714d4 |
|---|
| 399 | #define _PLANE_PRE_CSC_GAMC_DATA_2_A 0x705d4 |
|---|
| 400 | #define _PLANE_PRE_CSC_GAMC_DATA_2_B 0x715d4 |
|---|
| 401 | #define _PLANE_PRE_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_1_A, \ |
|---|
| 402 | _PLANE_PRE_CSC_GAMC_DATA_1_B) |
|---|
| 403 | #define _PLANE_PRE_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_2_A, \ |
|---|
| 404 | _PLANE_PRE_CSC_GAMC_DATA_2_B) |
|---|
| 405 | #define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \ |
|---|
| 406 | _PLANE_PRE_CSC_GAMC_DATA_2(pipe)) |
|---|
| 407 | |
|---|
| 408 | #define _PLANE_CSC_RY_GY_1_A 0x70210 |
|---|
| 409 | #define _PLANE_CSC_RY_GY_2_A 0x70310 |
|---|
| 410 | #define _PLANE_CSC_RY_GY_1_B 0x71210 |
|---|
| 411 | #define _PLANE_CSC_RY_GY_2_B 0x71310 |
|---|
| 412 | #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ |
|---|
| 413 | _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B, \ |
|---|
| 414 | _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B) |
|---|
| 415 | |
|---|
| 416 | #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 |
|---|
| 417 | #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 |
|---|
| 418 | #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 |
|---|
| 419 | #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 |
|---|
| 420 | #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ |
|---|
| 421 | _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B, \ |
|---|
| 422 | _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B) |
|---|
| 423 | |
|---|
| 424 | #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 |
|---|
| 425 | #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 |
|---|
| 426 | #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 |
|---|
| 427 | #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 |
|---|
| 428 | #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ |
|---|
| 429 | _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B, \ |
|---|
| 430 | _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B) |
|---|
| 431 | #define _PLANE_WM_1_A_0 0x70240 |
|---|
| 432 | #define _PLANE_WM_1_B_0 0x71240 |
|---|
| 433 | #define _PLANE_WM_2_A_0 0x70340 |
|---|
| 434 | #define _PLANE_WM_2_B_0 0x71340 |
|---|
| 435 | #define PLANE_WM(pipe, plane, level) _MMIO_SKL_PLANE_DW((pipe), (plane), (level), \ |
|---|
| 436 | _PLANE_WM_1_A_0, _PLANE_WM_1_B_0, \ |
|---|
| 437 | _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) |
|---|
| 438 | #define PLANE_WM_EN REG_BIT(31) |
|---|
| 439 | #define PLANE_WM_IGNORE_LINES REG_BIT(30) |
|---|
| 440 | #define PLANE_WM_AUTO_MIN_ALLOC_EN REG_BIT(29) |
|---|
| 441 | #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) |
|---|
| 442 | #define PLANE_WM_BLOCKS_MASK REG_GENMASK(12, 0) |
|---|
| 443 | |
|---|
| 444 | #define _PLANE_WM_SAGV_1_A 0x70258 |
|---|
| 445 | #define _PLANE_WM_SAGV_1_B 0x71258 |
|---|
| 446 | #define _PLANE_WM_SAGV_2_A 0x70358 |
|---|
| 447 | #define _PLANE_WM_SAGV_2_B 0x71358 |
|---|
| 448 | #define PLANE_WM_SAGV(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
|---|
| 449 | _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B, \ |
|---|
| 450 | _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) |
|---|
| 451 | |
|---|
| 452 | #define _PLANE_WM_SAGV_TRANS_1_A 0x7025c |
|---|
| 453 | #define _PLANE_WM_SAGV_TRANS_1_B 0x7125c |
|---|
| 454 | #define _PLANE_WM_SAGV_TRANS_2_A 0x7035c |
|---|
| 455 | #define _PLANE_WM_SAGV_TRANS_2_B 0x7135c |
|---|
| 456 | #define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
|---|
| 457 | _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B, \ |
|---|
| 458 | _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) |
|---|
| 459 | |
|---|
| 460 | #define _PLANE_WM_TRANS_1_A 0x70268 |
|---|
| 461 | #define _PLANE_WM_TRANS_1_B 0x71268 |
|---|
| 462 | #define _PLANE_WM_TRANS_2_A 0x70368 |
|---|
| 463 | #define _PLANE_WM_TRANS_2_B 0x71368 |
|---|
| 464 | #define PLANE_WM_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
|---|
| 465 | _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B, \ |
|---|
| 466 | _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) |
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| 467 | |
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| 468 | #define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */ |
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| 469 | #define _PLANE_CHICKEN_2_A 0x7036c |
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| 470 | #define _PLANE_CHICKEN_1_B 0x7126c |
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| 471 | #define _PLANE_CHICKEN_2_B 0x7136c |
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| 472 | #define PLANE_CHICKEN(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 473 | _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B, \ |
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| 474 | _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) |
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| 475 | #define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ |
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| 476 | |
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| 477 | #define _PLANE_NV12_BUF_CFG_1_A 0x70278 |
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| 478 | #define _PLANE_NV12_BUF_CFG_2_A 0x70378 |
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| 479 | #define _PLANE_NV12_BUF_CFG_1_B 0x71278 |
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| 480 | #define _PLANE_NV12_BUF_CFG_2_B 0x71378 |
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| 481 | #define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 482 | _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B, \ |
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| 483 | _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) |
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| 484 | |
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| 485 | #define _PLANE_BUF_CFG_1_A 0x7027c |
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| 486 | #define _PLANE_BUF_CFG_2_A 0x7037c |
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| 487 | #define _PLANE_BUF_CFG_1_B 0x7127c |
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| 488 | #define _PLANE_BUF_CFG_2_B 0x7137c |
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| 489 | #define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 490 | _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \ |
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| 491 | _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) |
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| 492 | |
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| 493 | /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits, xe3p_lpd 13 bits */ |
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| 494 | #define PLANE_BUF_END_MASK REG_GENMASK(28, 16) |
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| 495 | #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) |
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| 496 | #define PLANE_BUF_START_MASK REG_GENMASK(12, 0) |
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| 497 | #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) |
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| 498 | |
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| 499 | #define _PLANE_MIN_BUF_CFG_1_A 0x70274 |
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| 500 | #define _PLANE_MIN_BUF_CFG_2_A 0x70374 |
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| 501 | #define _PLANE_MIN_BUF_CFG_1_B 0x71274 |
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| 502 | #define _PLANE_MIN_BUF_CFG_2_B 0x71374 |
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| 503 | #define PLANE_MIN_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 504 | _PLANE_MIN_BUF_CFG_1_A, _PLANE_MIN_BUF_CFG_1_B, \ |
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| 505 | _PLANE_MIN_BUF_CFG_2_A, _PLANE_MIN_BUF_CFG_2_B) |
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| 506 | #define PLANE_AUTO_MIN_DBUF_EN REG_BIT(31) |
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| 507 | #define PLANE_MIN_DBUF_BLOCKS_MASK REG_GENMASK(28, 16) |
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| 508 | #define PLANE_MIN_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val)) |
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| 509 | #define PLANE_INTERIM_DBUF_BLOCKS_MASK REG_GENMASK(12, 0) |
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| 510 | #define PLANE_INTERIM_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val)) |
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| 511 | |
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| 512 | /* tgl+ */ |
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| 513 | #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 |
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| 514 | #define _SEL_FETCH_PLANE_CTL_2_A 0x708b0 |
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| 515 | #define _SEL_FETCH_PLANE_CTL_5_A 0x70920 |
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| 516 | #define _SEL_FETCH_PLANE_CTL_6_A 0x70940 |
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| 517 | #define _SEL_FETCH_PLANE_CTL_1_B 0x71890 |
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| 518 | #define _SEL_FETCH_PLANE_CTL_2_B 0x718b0 |
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| 519 | #define _SEL_FETCH_PLANE_CTL_5_B 0x71920 |
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| 520 | #define _SEL_FETCH_PLANE_CTL_6_B 0x71940 |
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| 521 | #define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ |
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| 522 | _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \ |
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| 523 | _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \ |
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| 524 | _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \ |
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| 525 | _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B) |
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| 526 | #define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) |
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| 527 | |
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| 528 | /* tgl+ */ |
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| 529 | #define _SEL_FETCH_PLANE_POS_1_A 0x70894 |
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| 530 | #define _SEL_FETCH_PLANE_POS_2_A 0x708b4 |
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| 531 | #define _SEL_FETCH_PLANE_POS_5_A 0x70924 |
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| 532 | #define _SEL_FETCH_PLANE_POS_6_A 0x70944 |
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| 533 | #define _SEL_FETCH_PLANE_POS_1_B 0x71894 |
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| 534 | #define _SEL_FETCH_PLANE_POS_2_B 0x718b4 |
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| 535 | #define _SEL_FETCH_PLANE_POS_5_B 0x71924 |
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| 536 | #define _SEL_FETCH_PLANE_POS_6_B 0x71944 |
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| 537 | #define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ |
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| 538 | _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ |
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| 539 | _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ |
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| 540 | _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ |
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| 541 | _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B) |
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| 542 | |
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| 543 | /* tgl+ */ |
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| 544 | #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 |
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| 545 | #define _SEL_FETCH_PLANE_SIZE_2_A 0x708b8 |
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| 546 | #define _SEL_FETCH_PLANE_SIZE_5_A 0x70928 |
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| 547 | #define _SEL_FETCH_PLANE_SIZE_6_A 0x70948 |
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| 548 | #define _SEL_FETCH_PLANE_SIZE_1_B 0x71898 |
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| 549 | #define _SEL_FETCH_PLANE_SIZE_2_B 0x718b8 |
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| 550 | #define _SEL_FETCH_PLANE_SIZE_5_B 0x71928 |
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| 551 | #define _SEL_FETCH_PLANE_SIZE_6_B 0x71948 |
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| 552 | #define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ |
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| 553 | _SEL_FETCH_PLANE_SIZE_1_A, _SEL_FETCH_PLANE_SIZE_1_B, \ |
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| 554 | _SEL_FETCH_PLANE_SIZE_2_A, _SEL_FETCH_PLANE_SIZE_2_B, \ |
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| 555 | _SEL_FETCH_PLANE_SIZE_5_A, _SEL_FETCH_PLANE_SIZE_5_B, \ |
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| 556 | _SEL_FETCH_PLANE_SIZE_6_A, _SEL_FETCH_PLANE_SIZE_6_B) |
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| 557 | |
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| 558 | /* tgl+ */ |
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| 559 | #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089c |
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| 560 | #define _SEL_FETCH_PLANE_OFFSET_2_A 0x708bc |
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| 561 | #define _SEL_FETCH_PLANE_OFFSET_5_A 0x7092c |
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| 562 | #define _SEL_FETCH_PLANE_OFFSET_6_A 0x7094c |
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| 563 | #define _SEL_FETCH_PLANE_OFFSET_1_B 0x7189c |
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| 564 | #define _SEL_FETCH_PLANE_OFFSET_2_B 0x718bc |
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| 565 | #define _SEL_FETCH_PLANE_OFFSET_5_B 0x7192c |
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| 566 | #define _SEL_FETCH_PLANE_OFFSET_6_B 0x7194c |
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| 567 | #define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ |
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| 568 | _SEL_FETCH_PLANE_OFFSET_1_A, _SEL_FETCH_PLANE_OFFSET_1_B, \ |
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| 569 | _SEL_FETCH_PLANE_OFFSET_2_A, _SEL_FETCH_PLANE_OFFSET_2_B, \ |
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| 570 | _SEL_FETCH_PLANE_OFFSET_5_A, _SEL_FETCH_PLANE_OFFSET_5_B, \ |
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| 571 | _SEL_FETCH_PLANE_OFFSET_6_A, _SEL_FETCH_PLANE_OFFSET_6_B) |
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| 572 | |
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| 573 | #define _PLANE_PIXEL_NORMALIZE_1_A 0x701a8 |
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| 574 | #define _PLANE_PIXEL_NORMALIZE_2_A 0x702a8 |
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| 575 | #define _PLANE_PIXEL_NORMALIZE_1_B 0x711a8 |
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| 576 | #define _PLANE_PIXEL_NORMALIZE_2_B 0x712a8 |
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| 577 | #define PLANE_PIXEL_NORMALIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ |
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| 578 | _PLANE_PIXEL_NORMALIZE_1_A, _PLANE_PIXEL_NORMALIZE_1_B, \ |
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| 579 | _PLANE_PIXEL_NORMALIZE_2_A, _PLANE_PIXEL_NORMALIZE_2_B) |
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| 580 | #define PLANE_PIXEL_NORMALIZE_ENABLE REG_BIT(31) |
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| 581 | #define PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK REG_GENMASK(15, 0) |
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| 582 | #define PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val) REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK, (val)) |
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| 583 | #define PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0 0x3c00 |
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| 584 | |
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| 585 | #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */ |
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| 586 | |
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