| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* Copyright © 2024 Intel Corporation */ |
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| 3 | |
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| 4 | #ifndef __INTEL_SPRITE_REGS__ |
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| 5 | #define __INTEL_SPRITE_REGS__ |
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| 6 | |
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| 7 | #include "intel_display_reg_defs.h" |
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| 8 | |
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| 9 | /* g4x/ilk/snb video sprite */ |
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| 10 | #define _DVSACNTR 0x72180 |
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| 11 | #define _DVSBCNTR 0x73180 |
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| 12 | #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) |
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| 13 | #define DVS_ENABLE REG_BIT(31) |
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| 14 | #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) |
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| 15 | #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) |
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| 16 | #define DVS_FORMAT_MASK REG_GENMASK(26, 25) |
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| 17 | #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) |
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| 18 | #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) |
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| 19 | #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) |
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| 20 | #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) |
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| 21 | #define DVS_PIPE_CSC_ENABLE REG_BIT(24) |
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| 22 | #define DVS_SOURCE_KEY REG_BIT(22) |
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| 23 | #define DVS_RGB_ORDER_XBGR REG_BIT(20) |
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| 24 | #define DVS_YUV_FORMAT_BT709 REG_BIT(18) |
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| 25 | #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) |
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| 26 | #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) |
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| 27 | #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) |
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| 28 | #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) |
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| 29 | #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) |
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| 30 | #define DVS_ROTATE_180 REG_BIT(15) |
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| 31 | #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) |
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| 32 | #define DVS_TILED REG_BIT(10) |
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| 33 | #define DVS_DEST_KEY REG_BIT(2) |
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| 34 | |
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| 35 | #define _DVSALINOFF 0x72184 |
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| 36 | #define _DVSBLINOFF 0x73184 |
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| 37 | #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) |
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| 38 | |
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| 39 | #define _DVSASTRIDE 0x72188 |
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| 40 | #define _DVSBSTRIDE 0x73188 |
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| 41 | #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) |
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| 42 | |
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| 43 | #define _DVSAPOS 0x7218c |
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| 44 | #define _DVSBPOS 0x7318c |
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| 45 | #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) |
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| 46 | #define DVS_POS_Y_MASK REG_GENMASK(31, 16) |
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| 47 | #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) |
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| 48 | #define DVS_POS_X_MASK REG_GENMASK(15, 0) |
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| 49 | #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) |
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| 50 | |
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| 51 | #define _DVSASIZE 0x72190 |
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| 52 | #define _DVSBSIZE 0x73190 |
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| 53 | #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) |
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| 54 | #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) |
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| 55 | #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) |
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| 56 | #define DVS_WIDTH_MASK REG_GENMASK(15, 0) |
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| 57 | #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) |
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| 58 | |
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| 59 | #define _DVSAKEYVAL 0x72194 |
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| 60 | #define _DVSBKEYVAL 0x73194 |
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| 61 | #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) |
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| 62 | |
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| 63 | #define _DVSAKEYMSK 0x72198 |
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| 64 | #define _DVSBKEYMSK 0x73198 |
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| 65 | #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) |
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| 66 | |
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| 67 | #define _DVSASURF 0x7219c |
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| 68 | #define _DVSBSURF 0x7319c |
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| 69 | #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) |
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| 70 | #define DVS_ADDR_MASK REG_GENMASK(31, 12) |
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| 71 | |
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| 72 | #define _DVSAKEYMAXVAL 0x721a0 |
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| 73 | #define _DVSBKEYMAXVAL 0x731a0 |
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| 74 | #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) |
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| 75 | |
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| 76 | #define _DVSATILEOFF 0x721a4 |
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| 77 | #define _DVSBTILEOFF 0x731a4 |
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| 78 | #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) |
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| 79 | #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) |
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| 80 | #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) |
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| 81 | #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) |
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| 82 | #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) |
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| 83 | |
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| 84 | #define _DVSASURFLIVE 0x721ac |
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| 85 | #define _DVSBSURFLIVE 0x731ac |
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| 86 | #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) |
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| 87 | |
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| 88 | #define _DVSAGAMC_G4X 0x721e0 /* g4x */ |
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| 89 | #define _DVSBGAMC_G4X 0x731e0 /* g4x */ |
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| 90 | #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ |
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| 91 | |
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| 92 | #define _DVSASCALE 0x72204 |
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| 93 | #define _DVSBSCALE 0x73204 |
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| 94 | #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) |
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| 95 | #define DVS_SCALE_ENABLE REG_BIT(31) |
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| 96 | #define DVS_FILTER_MASK REG_GENMASK(30, 29) |
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| 97 | #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) |
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| 98 | #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) |
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| 99 | #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) |
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| 100 | #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ |
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| 101 | #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) |
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| 102 | #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) |
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| 103 | #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) |
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| 104 | #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) |
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| 105 | #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) |
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| 106 | |
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| 107 | #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ |
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| 108 | #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ |
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| 109 | #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ |
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| 110 | |
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| 111 | #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ |
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| 112 | #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ |
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| 113 | #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ |
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| 114 | |
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| 115 | /* ivb/hsw/bdw sprite */ |
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| 116 | #define _SPRA_CTL 0x70280 |
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| 117 | #define _SPRB_CTL 0x71280 |
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| 118 | #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) |
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| 119 | #define SPRITE_ENABLE REG_BIT(31) |
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| 120 | #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) |
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| 121 | #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) |
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| 122 | #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) |
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| 123 | #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) |
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| 124 | #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) |
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| 125 | #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) |
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| 126 | #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) |
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| 127 | #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) |
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| 128 | #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ |
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| 129 | #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) |
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| 130 | #define SPRITE_SOURCE_KEY REG_BIT(22) |
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| 131 | #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ |
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| 132 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) |
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| 133 | #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ |
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| 134 | #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) |
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| 135 | #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) |
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| 136 | #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) |
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| 137 | #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) |
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| 138 | #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) |
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| 139 | #define SPRITE_ROTATE_180 REG_BIT(15) |
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| 140 | #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) |
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| 141 | #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) |
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| 142 | #define SPRITE_TILED REG_BIT(10) |
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| 143 | #define SPRITE_DEST_KEY REG_BIT(2) |
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| 144 | |
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| 145 | #define _SPRA_LINOFF 0x70284 /* ivb */ |
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| 146 | #define _SPRB_LINOFF 0x71284 /* ivb */ |
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| 147 | #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) |
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| 148 | |
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| 149 | #define _SPRA_STRIDE 0x70288 |
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| 150 | #define _SPRB_STRIDE 0x71288 |
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| 151 | #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) |
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| 152 | |
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| 153 | #define _SPRA_POS 0x7028c |
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| 154 | #define _SPRB_POS 0x7128c |
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| 155 | #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) |
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| 156 | #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) |
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| 157 | #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) |
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| 158 | #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) |
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| 159 | #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) |
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| 160 | |
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| 161 | #define _SPRA_SIZE 0x70290 |
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| 162 | #define _SPRB_SIZE 0x71290 |
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| 163 | #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) |
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| 164 | #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) |
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| 165 | #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) |
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| 166 | #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) |
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| 167 | #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) |
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| 168 | |
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| 169 | #define _SPRA_KEYVAL 0x70294 |
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| 170 | #define _SPRB_KEYVAL 0x71294 |
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| 171 | #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) |
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| 172 | |
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| 173 | #define _SPRA_KEYMSK 0x70298 |
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| 174 | #define _SPRB_KEYMSK 0x71298 |
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| 175 | #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) |
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| 176 | |
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| 177 | #define _SPRA_SURF 0x7029c |
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| 178 | #define _SPRB_SURF 0x7129c |
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| 179 | #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) |
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| 180 | #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) |
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| 181 | |
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| 182 | #define _SPRA_KEYMAX 0x702a0 |
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| 183 | #define _SPRB_KEYMAX 0x712a0 |
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| 184 | #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) |
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| 185 | |
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| 186 | #define _SPRA_TILEOFF 0x702a4 /* ivb */ |
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| 187 | #define _SPRB_TILEOFF 0x712a4 /* ivb */ |
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| 188 | #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) |
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| 189 | #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) |
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| 190 | #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) |
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| 191 | #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) |
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| 192 | #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) |
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| 193 | |
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| 194 | #define _SPRA_OFFSET 0x702a4 /* hsw/bdw */ |
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| 195 | #define _SPRB_OFFSET 0x712a4 /* hsw/bdw */ |
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| 196 | #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) |
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| 197 | |
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| 198 | #define _SPRA_SURFLIVE 0x702ac |
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| 199 | #define _SPRB_SURFLIVE 0x712ac |
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| 200 | #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) |
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| 201 | |
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| 202 | #define _SPRA_SCALE 0x70304 /* ivb */ |
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| 203 | #define _SPRB_SCALE 0x71304 /* ivb */ |
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| 204 | #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) |
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| 205 | #define SPRITE_SCALE_ENABLE REG_BIT(31) |
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| 206 | #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) |
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| 207 | #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) |
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| 208 | #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) |
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| 209 | #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) |
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| 210 | #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ |
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| 211 | #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) |
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| 212 | #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) |
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| 213 | #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) |
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| 214 | #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) |
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| 215 | #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) |
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| 216 | |
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| 217 | #define _SPRA_GAMC 0x70400 |
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| 218 | #define _SPRB_GAMC 0x71400 |
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| 219 | #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ |
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| 220 | |
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| 221 | #define _SPRA_GAMC16 0x70440 |
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| 222 | #define _SPRB_GAMC16 0x71440 |
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| 223 | #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ |
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| 224 | |
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| 225 | #define _SPRA_GAMC17 0x7044c |
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| 226 | #define _SPRB_GAMC17 0x7144c |
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| 227 | #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ |
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| 228 | |
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| 229 | /* vlv/chv sprite */ |
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| 230 | #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ |
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| 231 | _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) |
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| 232 | #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ |
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| 233 | _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) |
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| 234 | |
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| 235 | #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) |
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| 236 | #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) |
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| 237 | #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) |
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| 238 | #define SP_ENABLE REG_BIT(31) |
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| 239 | #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) |
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| 240 | #define SP_FORMAT_MASK REG_GENMASK(29, 26) |
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| 241 | #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) |
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| 242 | #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) |
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| 243 | #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) |
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| 244 | #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) |
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| 245 | #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) |
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| 246 | #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) |
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| 247 | #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) |
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| 248 | #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ |
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| 249 | #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ |
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| 250 | #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) |
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| 251 | #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) |
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| 252 | #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ |
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| 253 | #define SP_SOURCE_KEY REG_BIT(22) |
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| 254 | #define SP_YUV_FORMAT_BT709 REG_BIT(18) |
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| 255 | #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) |
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| 256 | #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) |
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| 257 | #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) |
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| 258 | #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) |
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| 259 | #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) |
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| 260 | #define SP_ROTATE_180 REG_BIT(15) |
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| 261 | #define SP_TILED REG_BIT(10) |
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| 262 | #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ |
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| 263 | |
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| 264 | #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) |
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| 265 | #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) |
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| 266 | #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) |
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| 267 | |
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| 268 | #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) |
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| 269 | #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) |
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| 270 | #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) |
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| 271 | |
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| 272 | #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) |
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| 273 | #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) |
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| 274 | #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) |
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| 275 | #define SP_POS_Y_MASK REG_GENMASK(31, 16) |
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| 276 | #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) |
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| 277 | #define SP_POS_X_MASK REG_GENMASK(15, 0) |
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| 278 | #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) |
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| 279 | |
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| 280 | #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) |
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| 281 | #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) |
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| 282 | #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) |
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| 283 | #define SP_HEIGHT_MASK REG_GENMASK(31, 16) |
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| 284 | #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) |
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| 285 | #define SP_WIDTH_MASK REG_GENMASK(15, 0) |
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| 286 | #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) |
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| 287 | |
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| 288 | #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) |
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| 289 | #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) |
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| 290 | #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) |
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| 291 | |
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| 292 | #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) |
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| 293 | #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) |
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| 294 | #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) |
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| 295 | |
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| 296 | #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) |
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| 297 | #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) |
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| 298 | #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) |
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| 299 | #define SP_ADDR_MASK REG_GENMASK(31, 12) |
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| 300 | |
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| 301 | #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) |
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| 302 | #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) |
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| 303 | #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) |
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| 304 | |
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| 305 | #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) |
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| 306 | #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) |
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| 307 | #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) |
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| 308 | #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) |
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| 309 | #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) |
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| 310 | #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) |
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| 311 | #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) |
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| 312 | |
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| 313 | #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) |
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| 314 | #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) |
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| 315 | #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) |
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| 316 | #define SP_CONST_ALPHA_ENABLE REG_BIT(31) |
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| 317 | #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) |
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| 318 | #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) |
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| 319 | |
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| 320 | #define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac) |
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| 321 | #define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac) |
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| 322 | #define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE) |
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| 323 | |
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| 324 | #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) |
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| 325 | #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) |
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| 326 | #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) |
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| 327 | #define SP_CONTRAST_MASK REG_GENMASK(26, 18) |
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| 328 | #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ |
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| 329 | #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) |
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| 330 | #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ |
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| 331 | |
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| 332 | #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) |
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| 333 | #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) |
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| 334 | #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) |
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| 335 | #define SP_SH_SIN_MASK REG_GENMASK(26, 16) |
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| 336 | #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ |
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| 337 | #define SP_SH_COS_MASK REG_GENMASK(9, 0) |
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| 338 | #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ |
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| 339 | |
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| 340 | #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) |
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| 341 | #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) |
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| 342 | #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ |
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| 343 | |
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| 344 | /* |
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| 345 | * CHV pipe B sprite CSC |
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| 346 | * |
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| 347 | * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| |
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| 348 | * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| |
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| 349 | * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| |
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| 350 | */ |
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| 351 | #define _MMIO_CHV_SPCSC(plane_id, reg) \ |
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| 352 | _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) |
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| 353 | |
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| 354 | #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) |
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| 355 | #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) |
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| 356 | #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) |
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| 357 | #define SPCSC_OOFF_MASK REG_GENMASK(26, 16) |
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| 358 | #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ |
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| 359 | #define SPCSC_IOFF_MASK REG_GENMASK(10, 0) |
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| 360 | #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ |
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| 361 | |
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| 362 | #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) |
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| 363 | #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) |
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| 364 | #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) |
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| 365 | #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) |
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| 366 | #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) |
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| 367 | #define SPCSC_C1_MASK REG_GENMASK(30, 16) |
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| 368 | #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ |
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| 369 | #define SPCSC_C0_MASK REG_GENMASK(14, 0) |
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| 370 | #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ |
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| 371 | |
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| 372 | #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) |
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| 373 | #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) |
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| 374 | #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) |
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| 375 | #define SPCSC_IMAX_MASK REG_GENMASK(26, 16) |
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| 376 | #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ |
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| 377 | #define SPCSC_IMIN_MASK REG_GENMASK(10, 0) |
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| 378 | #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ |
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| 379 | |
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| 380 | #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) |
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| 381 | #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) |
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| 382 | #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) |
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| 383 | #define SPCSC_OMAX_MASK REG_GENMASK(25, 16) |
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| 384 | #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ |
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| 385 | #define SPCSC_OMIN_MASK REG_GENMASK(9, 0) |
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| 386 | #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ |
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| 387 | |
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| 388 | #endif /* __INTEL_SPRITE_REGS__ */ |
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| 389 | |
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