| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* Copyright © 2025 Intel Corporation */ |
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| 3 | |
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| 4 | #ifndef __INTEL_SBI_REGS_H__ |
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| 5 | #define __INTEL_SBI_REGS_H__ |
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| 6 | |
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| 7 | #include "intel_display_reg_defs.h" |
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| 8 | |
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| 9 | /* |
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| 10 | * Sideband Interface (SBI) is programmed indirectly, via SBI_ADDR, which |
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| 11 | * contains the register offset; and SBI_DATA, which contains the payload. |
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| 12 | */ |
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| 13 | #define SBI_ADDR _MMIO(0xC6000) |
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| 14 | #define SBI_ADDR_MASK REG_GENMASK(31, 16) |
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| 15 | #define SBI_ADDR_VALUE(addr) REG_FIELD_PREP(SBI_ADDR_MASK, (addr)) |
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| 16 | |
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| 17 | #define SBI_DATA _MMIO(0xC6004) |
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| 18 | |
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| 19 | #define SBI_CTL_STAT _MMIO(0xC6008) |
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| 20 | #define SBI_CTL_DEST_MASK REG_GENMASK(16, 16) |
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| 21 | #define SBI_CTL_DEST_ICLK REG_FIELD_PREP(SBI_CTL_DEST_MASK, 0) |
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| 22 | #define SBI_CTL_DEST_MPHY REG_FIELD_PREP(SBI_CTL_DEST_MASK, 1) |
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| 23 | #define SBI_CTL_OP_MASK REG_GENMASK(15, 8) |
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| 24 | #define SBI_CTL_OP_IORD REG_FIELD_PREP(SBI_CTL_OP_MASK, 2) |
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| 25 | #define SBI_CTL_OP_IOWR REG_FIELD_PREP(SBI_CTL_OP_MASK, 3) |
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| 26 | #define SBI_CTL_OP_CRRD REG_FIELD_PREP(SBI_CTL_OP_MASK, 6) |
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| 27 | #define SBI_CTL_OP_CRWR REG_FIELD_PREP(SBI_CTL_OP_MASK, 7) |
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| 28 | #define SBI_CTL_OP_WR REG_BIT(8) |
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| 29 | #define SBI_RESPONSE_MASK REG_GENMASK(2, 1) |
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| 30 | #define SBI_RESPONSE_FAIL REG_FIELD_PREP(SBI_RESPONSE_MASK, 1) |
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| 31 | #define SBI_RESPONSE_SUCCESS REG_FIELD_PREP(SBI_RESPONSE_MASK, 0) |
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| 32 | #define SBI_STATUS_MASK REG_GENMASK(0, 0) |
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| 33 | #define SBI_STATUS_BUSY REG_FIELD_PREP(SBI_STATUS_MASK, 1) |
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| 34 | #define SBI_STATUS_READY REG_FIELD_PREP(SBI_STATUS_MASK, 0) |
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| 35 | |
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| 36 | /* SBI offsets */ |
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| 37 | #define SBI_SSCDIVINTPHASE 0x0200 |
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| 38 | |
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| 39 | #define SBI_SSCDIVINTPHASE6 0x0600 |
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| 40 | #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 |
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| 41 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) |
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| 42 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) |
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| 43 | #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 |
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| 44 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) |
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| 45 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) |
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| 46 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) |
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| 47 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) |
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| 48 | |
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| 49 | #define SBI_SSCDITHPHASE 0x0204 |
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| 50 | #define SBI_SSCCTL 0x020c |
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| 51 | #define SBI_SSCCTL6 0x060C |
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| 52 | #define SBI_SSCCTL_PATHALT (1 << 3) |
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| 53 | #define SBI_SSCCTL_DISABLE (1 << 0) |
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| 54 | |
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| 55 | #define SBI_SSCAUXDIV6 0x0610 |
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| 56 | #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 |
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| 57 | #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) |
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| 58 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) |
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| 59 | |
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| 60 | #define SBI_DBUFF0 0x2a00 |
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| 61 | |
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| 62 | #define SBI_GEN0 0x1f00 |
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| 63 | #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) |
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| 64 | |
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| 65 | #endif /* __INTEL_SBI_REGS_H__ */ |
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| 66 | |
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