1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#ifndef __INTEL_DMC_REGS_H__
7#define __INTEL_DMC_REGS_H__
8
9#include "intel_display_reg_defs.h"
10
11enum dmc_event_id {
12 DMC_EVENT_TRUE = 0x0,
13 DMC_EVENT_FALSE = 0x1,
14};
15
16enum maindmc_event_id {
17 MAINDMC_EVENT_CMP_ZERO = 0x8,
18 MAINDMC_EVENT_CMP_ODD = 0x9,
19 MAINDMC_EVENT_CMP_NEG = 0xa,
20 MAINDMC_EVENT_CMP_CARRY = 0xb,
21
22 MAINDMC_EVENT_TMR0_DONE = 0x14,
23 MAINDMC_EVENT_TMR1_DONE = 0x15,
24 MAINDMC_EVENT_TMR2_DONE = 0x16,
25 MAINDMC_EVENT_COUNT0_DONE = 0x17,
26 MAINDMC_EVENT_COUNT1_DONE = 0x18,
27 MAINDMC_EVENT_PERF_CNTR_DARBF = 0x19,
28
29 MAINDMC_EVENT_SCANLINE_INRANGE_FQ_A_TRIGGER = 0x22,
30 MAINDMC_EVENT_SCANLINE_INRANGE_FQ_B_TRIGGER = 0x23,
31 MAINDMC_EVENT_SCANLINE_INRANGE_FQ_C_TRIGGER = 0x24,
32 MAINDMC_EVENT_SCANLINE_INRANGE_FQ_D_TRIGGER = 0x25,
33 MAINDMC_EVENT_1KHZ_FQ_A_TRIGGER = 0x26,
34 MAINDMC_EVENT_1KHZ_FQ_B_TRIGGER = 0x27,
35 MAINDMC_EVENT_1KHZ_FQ_C_TRIGGER = 0x28,
36 MAINDMC_EVENT_1KHZ_FQ_D_TRIGGER = 0x29,
37 MAINDMC_EVENT_SCANLINE_COMP_A = 0x2a,
38 MAINDMC_EVENT_SCANLINE_COMP_B = 0x2b,
39 MAINDMC_EVENT_SCANLINE_COMP_C = 0x2c,
40 MAINDMC_EVENT_SCANLINE_COMP_D = 0x2d,
41 MAINDMC_EVENT_VBLANK_DELAYED_A = 0x2e,
42 MAINDMC_EVENT_VBLANK_DELAYED_B = 0x2f,
43 MAINDMC_EVENT_VBLANK_DELAYED_C = 0x30,
44 MAINDMC_EVENT_VBLANK_DELAYED_D = 0x31,
45 MAINDMC_EVENT_VBLANK_A = 0x32,
46 MAINDMC_EVENT_VBLANK_B = 0x33,
47 MAINDMC_EVENT_VBLANK_C = 0x34,
48 MAINDMC_EVENT_VBLANK_D = 0x35,
49 MAINDMC_EVENT_HBLANK_A = 0x36,
50 MAINDMC_EVENT_HBLANK_B = 0x37,
51 MAINDMC_EVENT_HBLANK_C = 0x38,
52 MAINDMC_EVENT_HBLANK_D = 0x39,
53 MAINDMC_EVENT_VSYNC_A = 0x3a,
54 MAINDMC_EVENT_VSYNC_B = 0x3b,
55 MAINDMC_EVENT_VSYNC_C = 0x3c,
56 MAINDMC_EVENT_VSYNC_D = 0x3d,
57 MAINDMC_EVENT_SCANLINE_A = 0x3e,
58 MAINDMC_EVENT_SCANLINE_B = 0x3f,
59 MAINDMC_EVENT_SCANLINE_C = 0x40,
60 MAINDMC_EVENT_SCANLINE_D = 0x41,
61
62 MAINDMC_EVENT_PLANE1_FLIP_A = 0x42,
63 MAINDMC_EVENT_PLANE2_FLIP_A = 0x43,
64 MAINDMC_EVENT_PLANE3_FLIP_A = 0x44,
65 MAINDMC_EVENT_PLANE4_FLIP_A = 0x45,
66 MAINDMC_EVENT_PLANE5_FLIP_A = 0x46,
67 MAINDMC_EVENT_PLANE6_FLIP_A = 0x47,
68 MAINDMC_EVENT_PLANE7_FLIP_A = 0x48,
69 MAINDMC_EVENT_PLANE1_FLIP_B = 0x49,
70 MAINDMC_EVENT_PLANE2_FLIP_B = 0x4a,
71 MAINDMC_EVENT_PLANE3_FLIP_B = 0x4b,
72 MAINDMC_EVENT_PLANE4_FLIP_B = 0x4c,
73 MAINDMC_EVENT_PLANE5_FLIP_B = 0x4d,
74 MAINDMC_EVENT_PLANE6_FLIP_B = 0x4e,
75 MAINDMC_EVENT_PLANE7_FLIP_B = 0x4f,
76 MAINDMC_EVENT_PLANE1_FLIP_C = 0x50,
77 MAINDMC_EVENT_PLANE2_FLIP_C = 0x51,
78 MAINDMC_EVENT_PLANE3_FLIP_C = 0x52,
79 MAINDMC_EVENT_PLANE4_FLIP_C = 0x53,
80 MAINDMC_EVENT_PLANE5_FLIP_C = 0x54,
81 MAINDMC_EVENT_PLANE6_FLIP_C = 0x55,
82 MAINDMC_EVENT_PLANE7_FLIP_C = 0x56,
83 MAINDMC_EVENT_PLANE1_FLIP_D = 0x57,
84 MAINDMC_EVENT_PLANE2_FLIP_D = 0x58,
85 MAINDMC_EVENT_PLANE3_FLIP_D = 0x59,
86 MAINDMC_EVENT_PLANE4_FLIP_D = 0x5a,
87 MAINDMC_EVENT_PLANE5_FLIP_D = 0x5b,
88 MAINDMC_EVENT_PLANE6_FLIP_D = 0x5c,
89 MAINDMC_EVENT_PLANE7_FLIP_D = 0x5d,
90 MAINDMC_EVENT_PLANE1_FLIP_DONE_A = 0x5e,
91 MAINDMC_EVENT_PLANE2_FLIP_DONE_A = 0x5f,
92 MAINDMC_EVENT_PLANE3_FLIP_DONE_A = 0x60,
93 MAINDMC_EVENT_PLANE4_FLIP_DONE_A = 0x61,
94 MAINDMC_EVENT_PLANE5_FLIP_DONE_A = 0x62,
95 MAINDMC_EVENT_PLANE6_FLIP_DONE_A = 0x63,
96 MAINDMC_EVENT_PLANE7_FLIP_DONE_A = 0x64,
97 MAINDMC_EVENT_PLANE1_FLIP_DONE_B = 0x65,
98 MAINDMC_EVENT_PLANE2_FLIP_DONE_B = 0x66,
99 MAINDMC_EVENT_PLANE3_FLIP_DONE_B = 0x67,
100 MAINDMC_EVENT_PLANE4_FLIP_DONE_B = 0x68,
101 MAINDMC_EVENT_PLANE5_FLIP_DONE_B = 0x69,
102 MAINDMC_EVENT_PLANE6_FLIP_DONE_B = 0x6a,
103 MAINDMC_EVENT_PLANE7_FLIP_DONE_B = 0x6b,
104 MAINDMC_EVENT_PLANE1_FLIP_DONE_C = 0x6c,
105 MAINDMC_EVENT_PLANE2_FLIP_DONE_C = 0x6d,
106 MAINDMC_EVENT_PLANE3_FLIP_DONE_C = 0x6e,
107 MAINDMC_EVENT_PLANE4_FLIP_DONE_C = 0x6f,
108 MAINDMC_EVENT_PLANE5_FLIP_DONE_C = 0x70,
109 MAINDMC_EVENT_PLANE6_FLIP_DONE_C = 0x71,
110 MAINDMC_EVENT_PLANE7_FLIP_DONE_C = 0x72,
111 MAINDMC_EVENT_PLANE1_FLIP_DONE_D = 0x73,
112 MAINDMC_EVENT_PLANE2_FLIP_DONE_D = 0x74,
113 MAINDMC_EVENT_PLANE3_FLIP_DONE_D = 0x75,
114 MAINDMC_EVENT_PLANE4_FLIP_DONE_D = 0x76,
115 MAINDMC_EVENT_PLANE5_FLIP_DONE_D = 0x77,
116 MAINDMC_EVENT_PLANE6_FLIP_DONE_D = 0x78,
117 MAINDMC_EVENT_PLANE7_FLIP_DONE_D = 0x79,
118
119 MAINDMC_EVENT_WIDI_GTT_FAULT_SL1 = 0x7d,
120 MAINDMC_EVENT_WIDI_GTT_FAULT_SL2 = 0x7e,
121 MAINDMC_EVENT_WIDI_CAP_ACTIVE_SL1 = 0x7f,
122 MAINDMC_EVENT_WIDI_CAP_ACTIVE_SL2 = 0x80,
123
124 MAINDMC_EVENT_RENUKE_A = 0x85,
125 MAINDMC_EVENT_RENUKE_B = 0x86,
126 MAINDMC_EVENT_RENUKE_C = 0x87,
127 MAINDMC_EVENT_RENUKE_D = 0x88,
128 MAINDMC_EVENT_DPFC_FIFO_FULL_A = 0x89,
129 MAINDMC_EVENT_DPFC_FIFO_FULL_B = 0x8a,
130 MAINDMC_EVENT_DPFC_FIFO_FULL_C = 0x8b,
131 MAINDMC_EVENT_DPFC_FIFO_FULL_D = 0x8c,
132 MAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_A = 0x8d,
133 MAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_B = 0x8e,
134 MAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_C = 0x8f,
135 MAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_D = 0x90,
136 MAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_A = 0x91,
137 MAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_B = 0x92,
138 MAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_C = 0x93,
139 MAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_D = 0x94,
140 MAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_A = 0x95,
141 MAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_B = 0x96,
142 MAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_C = 0x97,
143 MAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_D = 0x98,
144 MAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_A = 0x99,
145 MAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_B = 0x9a,
146 MAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_C = 0x9b,
147 MAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_D = 0x9c,
148 MAINDMC_EVENT_DISP_PCH_INT = 0x9d,
149 MAINDMC_EVENT_GTT_ERR = 0x9e,
150 MAINDMC_EVENT_VTD_ERR = 0x9f,
151 MAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_A = 0xa0,
152 MAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_B = 0xa1,
153 MAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_C = 0xa2,
154 MAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_D = 0xa3,
155 MAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_A = 0xa4,
156 MAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_B = 0xa5,
157 MAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_C = 0xa6,
158 MAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_D = 0xa7,
159
160 MAINDMC_EVENT_DC_CLOCK_OFF_START_EDP = 0xb2,
161 MAINDMC_EVENT_DC_CLOCK_OFF_START_DSI = 0xb3,
162 MAINDMC_EVENT_DCPR_DMC_CSR_START = 0xb4,
163 MAINDMC_EVENT_IN_PSR = 0xb5,
164
165 MAINDMC_EVENT_IN_MEMUP = 0xb7,
166 MAINDMC_EVENT_IN_VGA = 0xb8,
167
168 MAINDMC_EVENT_IN_KVM_SESSION = 0xba,
169 MAINDMC_EVENT_DEWAKE = 0xbb,
170
171 MAINDMC_EVENT_TRAP_HIT = 0xbd,
172 MAINDMC_EVENT_CLK_USEC = 0xbe,
173 MAINDMC_EVENT_CLK_MSEC = 0xbf,
174
175 MAINDMC_EVENT_CHICKEN1 = 0xc8,
176 MAINDMC_EVENT_CHICKEN2 = 0xc9,
177 MAINDMC_EVENT_CHICKEN3 = 0xca,
178 MAINDMC_EVENT_DDT_UBP = 0xcb,
179
180 MAINDMC_EVENT_HP_LATENCY = 0xcd,
181 MAINDMC_EVENT_LP_LATENCY = 0xce,
182 MAINDMC_EVENT_WIDI_LP_REQ_SL1 = 0xcf,
183 MAINDMC_EVENT_WIDI_LP_REQ_SL2 = 0xd0,
184
185 MAINDMC_EVENT_DG_DMC_EVT_0 = 0xd3,
186 MAINDMC_EVENT_DG_DMC_EVT_1 = 0xd4,
187 MAINDMC_EVENT_DG_DMC_EVT_2 = 0xd5,
188 MAINDMC_EVENT_DG_DMC_EVT_3 = 0xd6,
189 MAINDMC_EVENT_DG_DMC_EVT_4 = 0xd7,
190 MAINDMC_EVENT_DACFE_CLK_STOP = 0xd8,
191 MAINDMC_EVENT_DACFE_AZILIA_SDI_WAKE = 0xd9,
192 MAINDMC_EVENT_AUDIO_DOUBLE_FUNC_GRP_RST = 0xda,
193 MAINDMC_EVENT_AUDIO_CMD_VALID = 0xdb,
194 MAINDMC_EVENT_AUDIO_FRM_SYNC_BCLK = 0xdc,
195 MAINDMC_EVENT_AUDIO_FRM_SYNC_CDCLK = 0xdd,
196 MAINDMC_EVENT_AUDIO_PRESENCE_DETECT_A = 0xde,
197 MAINDMC_EVENT_AUDIO_PRESENCE_DETECT_B = 0xdf,
198 MAINDMC_EVENT_AUDIO_PRESENCE_DETECT_C = 0xe0,
199 MAINDMC_EVENT_AUDIO_PRESENCE_DETECT_E = 0xe1,
200 MAINDMC_EVENT_CMTG_SCANLINE_IN_GB_DC6v = 0xe2,
201 MAINDMC_EVENT_DCPR_CMTG_SCANLINE_OUTSIDE_GB = 0xe3,
202 MAINDMC_EVENT_DC6v_BACKWARD_COMPAT = 0xe4,
203 MAINDMC_EVENT_DPMA_PM_ABORT = 0xe5,
204
205 MAINDMC_EVENT_STACK_OVF = 0xfc,
206 MAINDMC_EVENT_NO_CLAIM = 0xfd,
207 MAINDMC_EVENT_UNK_CMD = 0xfe,
208 MAINDMC_EVENT_HTP_MOD = 0xff,
209};
210
211enum pipedmc_event_id {
212 PIPEDMC_EVENT_TMR0_DONE = 0x14,
213 PIPEDMC_EVENT_TMR1_DONE = 0x15,
214 PIPEDMC_EVENT_TMR2_DONE = 0x16,
215 PIPEDMC_EVENT_COUNT0_DONE = 0x17,
216 PIPEDMC_EVENT_COUNT1_DONE = 0x18,
217 PIPEDMC_EVENT_PGA_PGB_RESTORE_DONE = 0x19,
218 PIPEDMC_EVENT_PG1_PG2_RESTORE_DONE = 0x1a,
219 PIPEDMC_EVENT_PGA_PGB_SAVE_DONE = 0x1b,
220 PIPEDMC_EVENT_PG1_PG2_SAVE_DONE = 0x1c,
221
222 PIPEDMC_EVENT_FULL_FQ_WAKE_TRIGGER = 0x2b,
223 PIPEDMC_EVENT_1KHZ_FQ_TRIGGER = 0x2c,
224 PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER = 0x2d,
225 PIPEDMC_EVENT_SCANLINE_INRANGE = 0x2e,
226 PIPEDMC_EVENT_SCANLINE_OUTRANGE = 0x2f,
227 PIPEDMC_EVENT_SCANLINE_EQUAL = 0x30,
228 PIPEDMC_EVENT_DELAYED_VBLANK = 0x31,
229 PIPEDMC_EVENT_VBLANK = 0x32,
230 PIPEDMC_EVENT_HBLANK = 0x33,
231 PIPEDMC_EVENT_VSYNC = 0x34,
232 PIPEDMC_EVENT_SCANLINE_FROM_DMUX = 0x35,
233 PIPEDMC_EVENT_PLANE1_FLIP = 0x36,
234 PIPEDMC_EVENT_PLANE2_FLIP = 0x37,
235 PIPEDMC_EVENT_PLANE3_FLIP = 0x38,
236 PIPEDMC_EVENT_PLANE4_FLIP = 0x39,
237 PIPEDMC_EVENT_PLANE5_FLIP = 0x3a,
238 PIPEDMC_EVENT_PLANE6_FLIP = 0x3b,
239 PIPEDMC_EVENT_PLANE7_FLIP = 0x3c,
240 PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER = 0x3d,
241
242 PIPEDMC_EVENT_PLANE1_FLIP_DONE = 0x56,
243 PIPEDMC_EVENT_PLANE2_FLIP_DONE = 0x57,
244 PIPEDMC_EVENT_PLANE3_FLIP_DONE = 0x58,
245 PIPEDMC_EVENT_PLANE4_FLIP_DONE = 0x59,
246 PIPEDMC_EVENT_PLANE5_FLIP_DONE = 0x5a,
247 PIPEDMC_EVENT_PLANE6_FLIP_DONE = 0x5b,
248 PIPEDMC_EVENT_PLANE7_FLIP_DONE = 0x5c,
249
250 PIPEDMC_EVENT_GTT_ERR = 0x9b,
251
252 PIPEDMC_EVENT_IN_PSR = 0xb5,
253 PIPEDMC_EVENT_DSI_DMC_IDLE = 0xb6,
254 PIPEDMC_EVENT_PSR2_DMC_IDLE = 0xb7,
255 PIPEDMC_EVENT_IN_VGA = 0xb8,
256
257 PIPEDMC_EVENT_TRAP_HIT = 0xbd,
258 PIPEDMC_EVENT_CLK_USEC = 0xbe,
259 PIPEDMC_EVENT_CLK_MSEC = 0xbf,
260
261 PIPEDMC_EVENT_CHICKEN1 = 0xc8,
262 PIPEDMC_EVENT_CHICKEN2 = 0xc9,
263 PIPEDMC_EVENT_CHICKEN3 = 0xca,
264 PIPEDMC_EVENT_DDT_UBP = 0xcb,
265
266 PIPEDMC_EVENT_LP_LATENCY = 0xce,
267
268 PIPEDMC_EVENT_LACE_PART_A_HIST_TRIGGER = 0xdf,
269 PIPEDMC_EVENT_LACE_PART_B_HIST_TRIGGER = 0xe0,
270
271 PIPEDMC_EVENT_STACK_OVF = 0xfc,
272 PIPEDMC_EVENT_NO_CLAIM = 0xfd,
273 PIPEDMC_EVENT_UNK_CMD = 0xfe,
274 PIPEDMC_EVENT_HTP_MOD = 0xff,
275};
276
277#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
278#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
279
280#define _PIPEDMC_CONTROL_A 0x45250
281#define _PIPEDMC_CONTROL_B 0x45254
282#define PIPEDMC_CONTROL(pipe) _MMIO_PIPE(pipe, \
283 _PIPEDMC_CONTROL_A, \
284 _PIPEDMC_CONTROL_B)
285#define PIPEDMC_ENABLE REG_BIT(0)
286
287#define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
288#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
289
290#define _PIPEDMC_LOAD_HTP_A 0x5f000
291#define _PIPEDMC_LOAD_HTP_B 0x5f400
292#define PIPEDMC_LOAD_HTP(pipe) _MMIO_PIPE((pipe), _PIPEDMC_LOAD_HTP_A, _PIPEDMC_LOAD_HTP_B)
293
294#define _PIPEDMC_CTL_A 0x5f064
295#define _PIPEDMC_CTL_B 0x5f464
296#define PIPEDMC_CTL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_CTL_A, _PIPEDMC_CTL_B)
297#define PIPEDMC_HALT REG_BIT(31)
298#define PIPEDMC_STEP REG_BIT(27)
299#define PIPEDMC_CLOCKGATE REG_BIT(23)
300
301#define _PIPEDMC_STATUS_A 0x5f06c
302#define _PIPEDMC_STATUS_B 0x5f46c
303#define PIPEDMC_STATUS(pipe) _MMIO_PIPE((pipe), _PIPEDMC_STATUS_A, _PIPEDMC_STATUS_B)
304#define PIPEDMC_SSP REG_GENMASK(31, 16)
305#define PIPEDMC_INT_VECTOR_MASK REG_GENMASK(15, 8)
306/* PIPEDMC_INT_VECTOR values defined by firmware */
307#define PIPEDMC_INT_VECTOR_SCANLINE_COMP_ERROR REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0x1)
308#define PIPEDMC_INT_VECTOR_DC6V_FLIPQ_OVERLAP_ERROR REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0x2)
309#define PIPEDMC_INT_VECTOR_FLIPQ_PROG_DONE REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0xff) /* Wa_16018781658:lnl[a0] */
310#define PIPEDMC_EVT_PENDING REG_GENMASK(7, 0)
311
312#define _PIPEDMC_FQ_CTRL_A 0x5f078
313#define _PIPEDMC_FQ_CTRL_B 0x5f478
314#define PIPEDMC_FQ_CTRL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FQ_CTRL_A, _PIPEDMC_FQ_CTRL_B)
315#define PIPEDMC_FQ_CTRL_ENABLE REG_BIT(31)
316#define PIPEDMC_FQ_CTRL_ASYNC REG_BIT(29)
317#define PIPEDMC_FQ_CTRL_PREEMPT REG_BIT(0)
318
319#define _PIPEDMC_FQ_STATUS_A 0x5f098
320#define _PIPEDMC_FQ_STATUS_B 0x5f498
321#define PIPEDMC_FQ_STATUS(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FQ_STATUS_A, _PIPEDMC_FQ_STATUS_B)
322#define PIPEDMC_FQ_STATUS_BUSY REG_BIT(31)
323#define PIPEDMC_FQ_STATUS_W2_LIVE_STATUS REG_BIT(1)
324#define PIPEDMC_FQ_STATUS_W1_LIVE_STATUS REG_BIT(0)
325
326#define _PIPEDMC_FPQ_ATOMIC_TP_A 0x5f0a0
327#define _PIPEDMC_FPQ_ATOMIC_TP_B 0x5f4a0
328#define PIPEDMC_FPQ_ATOMIC_TP(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_ATOMIC_TP_A, _PIPEDMC_FPQ_ATOMIC_TP_B)
329#define PIPEDMC_FPQ_PLANEQ_3_TP_MASK REG_GENMASK(31, 26)
330#define PIPEDMC_FPQ_PLANEQ_3_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, (tail))
331#define PIPEDMC_FPQ_PLANEQ_2_TP_MASK REG_GENMASK(24, 19)
332#define PIPEDMC_FPQ_PLANEQ_2_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, (tail))
333#define PIPEDMC_FPQ_PLANEQ_1_TP_MASK REG_GENMASK(17, 12)
334#define PIPEDMC_FPQ_PLANEQ_1_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, (tail))
335#define PIPEDMC_FPQ_FASTQ_TP_MASK REG_GENMASK(10, 6)
336#define PIPEDMC_FPQ_FASTQ_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_FASTQ_TP_MASK, (tail))
337#define PIPEDMC_FPQ_GENERALQ_TP_MASK REG_GENMASK(4, 0)
338#define PIPEDMC_FPQ_GENERALQ_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_GENERALQ_TP_MASK, (tail))
339
340#define _PIPEDMC_FPQ_LINES_TO_W1_A 0x5f0a4
341#define _PIPEDMC_FPQ_LINES_TO_W1_B 0x5f4a4
342#define PIPEDMC_FPQ_LINES_TO_W1 _MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W1_A, _PIPEDMC_FPQ_LINES_TO_W1_B)
343
344#define _PIPEDMC_FPQ_LINES_TO_W2_A 0x5f0a8
345#define _PIPEDMC_FPQ_LINES_TO_W2_B 0x5f4a8
346#define PIPEDMC_FPQ_LINES_TO_W2 _MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W2_A, _PIPEDMC_FPQ_LINES_TO_W2_B)
347
348#define _PIPEDMC_SCANLINECMP_A 0x5f11c
349#define _PIPEDMC_SCANLINECMP_B 0x5f51c
350#define PIPEDMC_SCANLINECMP(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMP_A, _PIPEDMC_SCANLINECMP_B)
351#define PIPEDMC_SCANLINECMP_EN REG_BIT(31)
352#define PIPEDMC_SCANLINE_NUMBER REG_GENMASK(20, 0)
353
354#define _PIPEDMC_SCANLINECMPLOWER_A 0x5f120
355#define _PIPEDMC_SCANLINECMPLOWER_B 0x5f520
356#define PIPEDMC_SCANLINECMPLOWER(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPLOWER_A, _PIPEDMC_SCANLINECMPLOWER_B)
357#define PIPEDMC_SCANLINEINRANGECMP_EN REG_BIT(31)
358#define PIPEDMC_SCANLINEOUTRANGECMP_EN REG_BIT(30)
359#define PIPEDMC_SCANLINE_LOWER_MASK REG_GENMASK(20, 0)
360#define PIPEDMC_SCANLINE_LOWER(scanline) REG_FIELD_PREP(PIPEDMC_SCANLINE_LOWER_MASK, (scanline))
361
362#define _PIPEDMC_SCANLINECMPUPPER_A 0x5f124
363#define _PIPEDMC_SCANLINECMPUPPER_B 0x5f524
364#define PIPEDMC_SCANLINECMPUPPER(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPUPPER_A, _PIPEDMC_SCANLINECMPUPPER_B)
365#define PIPEDMC_SCANLINE_UPPER_MASK REG_GENMASK(20, 0)
366#define PIPEDMC_SCANLINE_UPPER(scanline) REG_FIELD_PREP(PIPEDMC_SCANLINE_UPPER_MASK, (scanline))
367
368#define _MMIO_PIPEDMC_FPQ(pipe, fq_id, \
369 reg_fpq1_a, reg_fpq2_a, reg_fpq3_a, reg_fpq4_a, \
370 reg_fpq1_b, reg_fpq2_b, reg_fpq3_b, reg_fpq4_b) \
371 _MMIO(_PICK_EVEN_2RANGES((fq_id), INTEL_FLIPQ_PLANE_3, \
372 _PIPE((pipe), (reg_fpq1_a), (reg_fpq1_b)), \
373 _PIPE((pipe), (reg_fpq2_a), (reg_fpq2_b)), \
374 _PIPE((pipe), (reg_fpq3_a), (reg_fpq3_b)), \
375 _PIPE((pipe), (reg_fpq4_a), (reg_fpq4_b))))
376
377#define _PIPEDMC_FPQ1_HP_A 0x5f128
378#define _PIPEDMC_FPQ2_HP_A 0x5f138
379#define _PIPEDMC_FPQ3_HP_A 0x5f168
380#define _PIPEDMC_FPQ4_HP_A 0x5f174
381#define _PIPEDMC_FPQ5_HP_A 0x5f180
382#define _PIPEDMC_FPQ1_HP_B 0x5f528
383#define _PIPEDMC_FPQ2_HP_B 0x5f538
384#define _PIPEDMC_FPQ3_HP_B 0x5f568
385#define _PIPEDMC_FPQ4_HP_B 0x5f574
386#define _PIPEDMC_FPQ5_HP_B 0x5f580
387#define PIPEDMC_FPQ_HP(pipe, fq_id) _MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
388 _PIPEDMC_FPQ1_HP_A, _PIPEDMC_FPQ2_HP_A, \
389 _PIPEDMC_FPQ3_HP_A, _PIPEDMC_FPQ4_HP_A, \
390 _PIPEDMC_FPQ1_HP_B, _PIPEDMC_FPQ2_HP_B, \
391 _PIPEDMC_FPQ3_HP_B, _PIPEDMC_FPQ4_HP_B)
392
393#define _PIPEDMC_FPQ1_TP_A 0x5f12c
394#define _PIPEDMC_FPQ2_TP_A 0x5f13c
395#define _PIPEDMC_FPQ3_TP_A 0x5f16c
396#define _PIPEDMC_FPQ4_TP_A 0x5f178
397#define _PIPEDMC_FPQ5_TP_A 0x5f184
398#define _PIPEDMC_FPQ1_TP_B 0x5f52c
399#define _PIPEDMC_FPQ2_TP_B 0x5f53c
400#define _PIPEDMC_FPQ3_TP_B 0x5f56c
401#define _PIPEDMC_FPQ4_TP_B 0x5f578
402#define _PIPEDMC_FPQ5_TP_B 0x5f584
403#define PIPEDMC_FPQ_TP(pipe, fq_id) _MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
404 _PIPEDMC_FPQ1_TP_A, _PIPEDMC_FPQ2_TP_A, \
405 _PIPEDMC_FPQ3_TP_A, _PIPEDMC_FPQ4_TP_A, \
406 _PIPEDMC_FPQ1_TP_B, _PIPEDMC_FPQ2_TP_B, \
407 _PIPEDMC_FPQ3_TP_B, _PIPEDMC_FPQ4_TP_B)
408
409#define _PIPEDMC_FPQ1_CHP_A 0x5f130
410#define _PIPEDMC_FPQ2_CHP_A 0x5f140
411#define _PIPEDMC_FPQ3_CHP_A 0x5f170
412#define _PIPEDMC_FPQ4_CHP_A 0x5f17c
413#define _PIPEDMC_FPQ5_CHP_A 0x5f188
414#define _PIPEDMC_FPQ1_CHP_B 0x5f530
415#define _PIPEDMC_FPQ2_CHP_B 0x5f540
416#define _PIPEDMC_FPQ3_CHP_B 0x5f570
417#define _PIPEDMC_FPQ4_CHP_B 0x5f57c
418#define _PIPEDMC_FPQ5_CHP_B 0x5f588
419#define PIPEDMC_FPQ_CHP(pipe, fq_id) _MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
420 _PIPEDMC_FPQ1_CHP_A, _PIPEDMC_FPQ2_CHP_A, \
421 _PIPEDMC_FPQ3_CHP_A, _PIPEDMC_FPQ4_CHP_A, \
422 _PIPEDMC_FPQ1_CHP_B, _PIPEDMC_FPQ2_CHP_B, \
423 _PIPEDMC_FPQ3_CHP_B, _PIPEDMC_FPQ4_CHP_B)
424
425#define _PIPEDMC_FPQ_TS_A 0x5f134
426#define _PIPEDMC_FPQ_TS_B 0x5f534
427#define PIPEDMC_FPQ_TS(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_TS_A, _PIPEDMC_FPQ_TS_B)
428
429#define _PIPEDMC_SCANLINE_RO_A 0x5f144
430#define _PIPEDMC_SCANLINE_RO_B 0x5f544
431#define PIPEDMC_SCANLINE_RO(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINE_RO_A, _PIPEDMC_SCANLINE_RO_B)
432
433#define _PIPEDMC_FPQ_CTL1_A 0x5f160
434#define _PIPEDMC_FPQ_CTL1_B 0x5f560
435#define PIPEDMC_FPQ_CTL1(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_CTL1_A, _PIPEDMC_FPQ_CTL1_B)
436#define PIPEDMC_SW_DMC_WAKE REG_BIT(0)
437
438#define _PIPEDMC_FPQ_CTL2_A 0x5f164
439#define _PIPEDMC_FPQ_CTL2_B 0x5f564
440#define PIPEDMC_FPQ_CTL2(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_CTL2_A, _PIPEDMC_FPQ_CTL2_B)
441#define PIPEDMC_DMC_INT_AT_DELAYED_VBLANK REG_BIT(1)
442#define PIPEDMC_W1_DMC_WAKE REG_BIT(0)
443
444#define _PIPEDMC_INTERRUPT_A 0x5f190 /* lnl+ */
445#define _PIPEDMC_INTERRUPT_B 0x5f590 /* lnl+ */
446#define PIPEDMC_INTERRUPT(pipe) _MMIO_PIPE((pipe), _PIPEDMC_INTERRUPT_A, _PIPEDMC_INTERRUPT_B)
447#define _PIPEDMC_INTERRUPT_MASK_A 0x5f194 /* lnl+ */
448#define _PIPEDMC_INTERRUPT_MASK_B 0x5f594 /* lnl+ */
449#define PIPEDMC_INTERRUPT_MASK(pipe) _MMIO_PIPE((pipe), _PIPEDMC_INTERRUPT_MASK_A, _PIPEDMC_INTERRUPT_MASK_B)
450#define PIPEDMC_FLIPQ_PROG_DONE REG_BIT(3)
451#define PIPEDMC_ERROR REG_BIT(2)
452#define PIPEDMC_GTT_FAULT REG_BIT(1)
453#define PIPEDMC_ATS_FAULT REG_BIT(0)
454
455#define PIPEDMC_BLOCK_PKGC_SW_A 0x5f1d0
456#define PIPEDMC_BLOCK_PKGC_SW_B 0x5F5d0
457#define PIPEDMC_BLOCK_PKGC_SW(pipe) _MMIO_PIPE(pipe, \
458 PIPEDMC_BLOCK_PKGC_SW_A, \
459 PIPEDMC_BLOCK_PKGC_SW_B)
460#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS BIT(31)
461#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_UNTIL_NEXT_FRAMESTART BIT(15)
462
463#define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
464#define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
465
466#define __PIPEDMC_REG_MMIO_BASE(i915, dmc_id) \
467 ((DISPLAY_VER(i915) >= 13 ? _ADLP_PIPEDMC_REG_MMIO_BASE_A : \
468 _TGL_PIPEDMC_REG_MMIO_BASE_A) + \
469 0x400 * ((dmc_id) - 1))
470
471#define __DMC_REG_MMIO_BASE 0x8f000
472
473#define _DMC_REG_MMIO_BASE(i915, dmc_id) \
474 ((dmc_id) == DMC_FW_MAIN ? __DMC_REG_MMIO_BASE : \
475 __PIPEDMC_REG_MMIO_BASE(i915, dmc_id))
476
477#define _DMC_REG(i915, dmc_id, reg) \
478 ((reg) - __DMC_REG_MMIO_BASE + _DMC_REG_MMIO_BASE(i915, dmc_id))
479
480#define DMC_EVENT_HANDLER_COUNT_GEN12 8
481
482#define _DMC_EVT_HTP_0 0x8f004
483
484#define DMC_EVT_HTP(i915, dmc_id, handler) \
485 _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler))
486
487#define _DMC_EVT_CTL_0 0x8f034
488
489#define DMC_EVT_CTL(i915, dmc_id, handler) \
490 _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler))
491
492#define DMC_EVT_CTL_ENABLE REG_BIT(31)
493#define DMC_EVT_CTL_RECURRING REG_BIT(30)
494#define DMC_EVT_CTL_TYPE_MASK REG_GENMASK(17, 16)
495#define DMC_EVT_CTL_TYPE_LEVEL_0 0
496#define DMC_EVT_CTL_TYPE_LEVEL_1 1
497#define DMC_EVT_CTL_TYPE_EDGE_1_0 2
498#define DMC_EVT_CTL_TYPE_EDGE_0_1 3
499#define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8)
500
501#define DMC_HTP_ADDR_SKL 0x00500034
502#define DMC_SSP_BASE _MMIO(0x8F074)
503#define DMC_HTP_SKL _MMIO(0x8F004)
504#define DMC_LAST_WRITE _MMIO(0x8F034)
505#define DMC_LAST_WRITE_VALUE 0xc003b400
506#define DMC_MMIO_START_RANGE 0x80000
507#define DMC_MMIO_END_RANGE 0x8FFFF
508#define DMC_V1_MMIO_START_RANGE 0x80000
509#define TGL_MAIN_MMIO_START 0x8F000
510#define TGL_MAIN_MMIO_END 0x8FFFF
511#define _TGL_PIPEA_MMIO_START 0x92000
512#define _TGL_PIPEA_MMIO_END 0x93FFF
513#define _TGL_PIPEB_MMIO_START 0x96000
514#define _TGL_PIPEB_MMIO_END 0x97FFF
515#define ADLP_PIPE_MMIO_START 0x5F000
516#define ADLP_PIPE_MMIO_END 0x5FFFF
517
518#define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\
519 _TGL_PIPEB_MMIO_START)
520
521#define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\
522 _TGL_PIPEB_MMIO_END)
523
524#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
525#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
526#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
527#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
528#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
529#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
530
531#define TGL_DMC_DEBUG3 _MMIO(0x101090)
532#define DG1_DMC_DEBUG3 _MMIO(0x13415c)
533
534#define DMC_WAKELOCK_CFG _MMIO(0x8F1B0)
535#define DMC_WAKELOCK_CFG_ENABLE REG_BIT(31)
536#define DMC_WAKELOCK1_CTL _MMIO(0x8F140)
537#define DMC_WAKELOCK_CTL_REQ REG_BIT(31)
538#define DMC_WAKELOCK_CTL_ACK REG_BIT(15)
539
540#define DMC_FQ_W2_PTS_CFG_SEL _MMIO(0x8f240)
541#define PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(26, 24)
542#define PIPE_D_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
543#define PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(18, 16)
544#define PIPE_C_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
545#define PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(10, 8)
546#define PIPE_B_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
547#define PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(2, 0)
548#define PIPE_A_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
549
550/* plane/general flip queue entries */
551#define PIPEDMC_FQ_RAM(start_mmioaddr, i) _MMIO((start_mmioaddr) + (i) * 4)
552/* LNL */
553/* DW0 pts */
554/* DW1 head */
555/* DW2 size/etc. */
556#define LNL_FQ_INTERRUPT REG_BIT(31)
557#define LNL_FQ_DSB_ID_MASK REG_GENMASK(30, 29)
558#define LNL_FQ_DSB_ID(dsb_id) REG_FIELD_PREP(LNL_FQ_DSB_ID_MASK, (dsb_id))
559#define LNL_FQ_EXECUTED REG_BIT(28)
560#define LNL_FQ_DSB_SIZE_MASK REG_GENMASK(15, 0)
561#define LNL_FQ_DSB_SIZE(size) REG_FIELD_PREP(LNL_FQ_DSB_SIZE_MASK, (size))
562/* DW3 reserved (plane queues) */
563/* DW3 second DSB head (general queue) */
564/* DW4 second DSB size/etc. (general queue) */
565/* DW5 reserved (general queue) */
566
567/* PTL+ */
568/* DW0 pts */
569/* DW1 reserved */
570/* DW2 size/etc. */
571#define PTL_FQ_INTERRUPT REG_BIT(31)
572#define PTL_FQ_NEED_PUSH REG_BIT(30)
573#define PTL_FQ_BLOCK_PUSH REG_BIT(29)
574#define PTL_FQ_EXECUTED REG_BIT(28)
575#define PTL_FQ_DSB_ID_MASK REG_GENMASK(25, 24)
576#define PTL_FQ_DSB_ID(dsb_id) REG_FIELD_PREP(PTL_FQ_DSB_ID_MASK, (dsb_id))
577#define PTL_FQ_DSB_SIZE_MASK REG_GENMASK(15, 0)
578#define PTL_FQ_DSB_SIZE(size) REG_FIELD_PREP(PTL_FQ_DSB_SIZE_MASK, (size))
579/* DW3 head */
580/* DW4 second DSB size/etc. (general queue) */
581/* DW5 second DSB head (general queue) */
582
583/* undocumented magic DMC variables */
584#define PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6b8)
585#define PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6c0)
586
587#endif /* __INTEL_DMC_REGS_H__ */
588

source code of linux/drivers/gpu/drm/i915/display/intel_dmc_regs.h