1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#ifndef __INTEL_DISPLAY_DEVICE_H__
7#define __INTEL_DISPLAY_DEVICE_H__
8
9#include <linux/bitops.h>
10#include <linux/types.h>
11
12#include "intel_display_limits.h"
13
14struct drm_printer;
15struct intel_display;
16struct intel_display_parent_interface;
17struct pci_dev;
18
19/*
20 * Display platforms and subplatforms. Keep platforms in display version based
21 * order, chronological order within a version, and subplatforms next to the
22 * platform.
23 */
24#define INTEL_DISPLAY_PLATFORMS(func) \
25 /* Platform group aliases */ \
26 func(g4x) /* g45 and gm45 */ \
27 func(mobile) /* mobile platforms */ \
28 func(dgfx) /* discrete graphics */ \
29 /* Display ver 2 */ \
30 func(i830) \
31 func(i845g) \
32 func(i85x) \
33 func(i865g) \
34 /* Display ver 3 */ \
35 func(i915g) \
36 func(i915gm) \
37 func(i945g) \
38 func(i945gm) \
39 func(g33) \
40 func(pineview) \
41 /* Display ver 4 */ \
42 func(i965g) \
43 func(i965gm) \
44 func(g45) \
45 func(gm45) \
46 /* Display ver 5 */ \
47 func(ironlake) \
48 /* Display ver 6 */ \
49 func(sandybridge) \
50 /* Display ver 7 */ \
51 func(ivybridge) \
52 func(valleyview) \
53 func(haswell) \
54 func(haswell_ult) \
55 func(haswell_ulx) \
56 /* Display ver 8 */ \
57 func(broadwell) \
58 func(broadwell_ult) \
59 func(broadwell_ulx) \
60 func(cherryview) \
61 /* Display ver 9 */ \
62 func(skylake) \
63 func(skylake_ult) \
64 func(skylake_ulx) \
65 func(broxton) \
66 func(kabylake) \
67 func(kabylake_ult) \
68 func(kabylake_ulx) \
69 func(geminilake) \
70 func(coffeelake) \
71 func(coffeelake_ult) \
72 func(coffeelake_ulx) \
73 func(cometlake) \
74 func(cometlake_ult) \
75 func(cometlake_ulx) \
76 /* Display ver 11 */ \
77 func(icelake) \
78 func(icelake_port_f) \
79 func(jasperlake) \
80 func(elkhartlake) \
81 /* Display ver 12 */ \
82 func(tigerlake) \
83 func(tigerlake_uy) \
84 func(rocketlake) \
85 func(dg1) \
86 func(alderlake_s) \
87 func(alderlake_s_raptorlake_s) \
88 /* Display ver 13 */ \
89 func(alderlake_p) \
90 func(alderlake_p_alderlake_n) \
91 func(alderlake_p_raptorlake_p) \
92 func(alderlake_p_raptorlake_u) \
93 func(dg2) \
94 func(dg2_g10) \
95 func(dg2_g11) \
96 func(dg2_g12) \
97 /* Display ver 14 (based on GMD ID) */ \
98 func(meteorlake) \
99 func(meteorlake_u) \
100 /* Display ver 20 (based on GMD ID) */ \
101 func(lunarlake) \
102 /* Display ver 14.1 (based on GMD ID) */ \
103 func(battlemage) \
104 /* Display ver 30 (based on GMD ID) */ \
105 func(pantherlake) \
106 func(pantherlake_wildcatlake)
107
108
109#define __MEMBER(name) unsigned long name:1;
110#define __COUNT(x) 1 +
111
112#define __NUM_PLATFORMS (INTEL_DISPLAY_PLATFORMS(__COUNT) 0)
113
114struct intel_display_platforms {
115 union {
116 struct {
117 INTEL_DISPLAY_PLATFORMS(__MEMBER);
118 };
119 DECLARE_BITMAP(bitmap, __NUM_PLATFORMS);
120 };
121};
122
123#undef __MEMBER
124#undef __COUNT
125#undef __NUM_PLATFORMS
126
127#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
128 /* Keep in alphabetical order */ \
129 func(cursor_needs_physical); \
130 func(has_cdclk_crawl); \
131 func(has_cdclk_squash); \
132 func(has_ddi); \
133 func(has_dp_mst); \
134 func(has_dsb); \
135 func(has_fpga_dbg); \
136 func(has_gmch); \
137 func(has_hotplug); \
138 func(has_hti); \
139 func(has_ipc); \
140 func(has_overlay); \
141 func(has_psr); \
142 func(has_psr_hw_tracking); \
143 func(overlay_needs_physical); \
144 func(supports_tv);
145
146#define HAS_128B_Y_TILING(__display) (!(__display)->platform.i915g && !(__display)->platform.i915gm)
147#define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
148#define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5)
149#define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13)
150#define HAS_AUX_CCS(__display) (IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake)
151#define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
152#define HAS_CASF(__display) (DISPLAY_VER(__display) >= 20)
153#define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl)
154#define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash)
155#define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
156#define HAS_CMTG(__display) (!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13)
157#define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
158#define HAS_D12_PLANE_MINIMIZATION(__display) ((__display)->platform.rocketlake || (__display)->platform.alderlake_s)
159#define HAS_DBUF_OVERLAP_DETECTION(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection)
160#define HAS_DDI(__display) (DISPLAY_INFO(__display)->has_ddi)
161#define HAS_DISPLAY(__display) (DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0)
162#define HAS_DMC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dmc)
163#define HAS_DMC_WAKELOCK(__display) (DISPLAY_VER(__display) >= 20)
164#define HAS_DOUBLE_BUFFERED_M_N(__display) (IS_DISPLAY_VER((__display), 9, 14) || (__display)->platform.broadwell)
165#define HAS_DOUBLE_BUFFERED_LUT(__display) (DISPLAY_VER(__display) >= 30)
166#define HAS_DOUBLE_WIDE(__display) (DISPLAY_VER(__display) < 4)
167#define HAS_DP20(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
168#define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13)
169#define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst)
170#define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb)
171#define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc)
172#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display))
173#define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
174#define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
175#define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30)
176#define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg)
177#define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3)
178#define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
179#define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4)
180#define HAS_GMCH(__display) (DISPLAY_INFO(__display)->has_gmch)
181#define HAS_FDI(__display) (IS_DISPLAY_VER((__display), 5, 8) && !HAS_GMCH(__display))
182#define HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug)
183#define HAS_HW_SAGV_WM(__display) (DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx)
184#define HAS_IPC(__display) (DISPLAY_INFO(__display)->has_ipc)
185#define HAS_IPS(__display) ((__display)->platform.haswell_ult || (__display)->platform.broadwell)
186#define HAS_LRR(__display) (DISPLAY_VER(__display) >= 12)
187#define HAS_LSPCON(__display) (IS_DISPLAY_VER(__display, 9, 10))
188#define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
189#define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12)
190#define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay)
191#define HAS_PIPEDMC(__display) (DISPLAY_VER(__display) >= 12)
192#define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr)
193#define HAS_PSR_HW_TRACKING(__display) (DISPLAY_INFO(__display)->has_psr_hw_tracking)
194#define HAS_PSR2_SEL_FETCH(__display) (DISPLAY_VER(__display) >= 12)
195#define HAS_SAGV(__display) (DISPLAY_VER(__display) >= 9 && \
196 !(__display)->platform.broxton && !(__display)->platform.geminilake)
197#define HAS_TRANSCODER(__display, trans) ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \
198 BIT(trans)) != 0)
199#define HAS_UNCOMPRESSED_JOINER(__display) (DISPLAY_VER(__display) >= 13)
200#define HAS_ULTRAJOINER(__display) (((__display)->platform.dgfx && \
201 DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
202#define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11)
203#define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
204#define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical)
205#define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv)
206
207/* Check that device has a display IP version within the specific range. */
208#define IS_DISPLAY_VERx100(__display, from, until) ( \
209 BUILD_BUG_ON_ZERO((from) < 200) + \
210 (DISPLAY_VERx100(__display) >= (from) && \
211 DISPLAY_VERx100(__display) <= (until)))
212
213/*
214 * Check if a device has a specific IP version as well as a stepping within the
215 * specified range [from, until). The lower bound is inclusive, the upper
216 * bound is exclusive. The most common use-case of this macro is for checking
217 * bounds for workarounds, which usually have a stepping ("from") at which the
218 * hardware issue is first present and another stepping ("until") at which a
219 * hardware fix is present and the software workaround is no longer necessary.
220 * E.g.,
221 *
222 * IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B2)
223 * IS_DISPLAY_VERx100_STEP(display, 1400, STEP_C0, STEP_FOREVER)
224 *
225 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
226 * stepping bound for the specified IP version.
227 */
228#define IS_DISPLAY_VERx100_STEP(__display, ipver, from, until) \
229 (IS_DISPLAY_VERx100((__display), (ipver), (ipver)) && \
230 IS_DISPLAY_STEP((__display), (from), (until)))
231
232#define DISPLAY_INFO(__display) ((__display)->info.__device_info)
233#define DISPLAY_RUNTIME_INFO(__display) (&(__display)->info.__runtime_info)
234
235#define DISPLAY_VER(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver)
236#define DISPLAY_VERx100(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver * 100 + \
237 DISPLAY_RUNTIME_INFO(__display)->ip.rel)
238#define IS_DISPLAY_VER(__display, from, until) \
239 (DISPLAY_VER(__display) >= (from) && DISPLAY_VER(__display) <= (until))
240
241#define INTEL_DISPLAY_STEP(__display) (DISPLAY_RUNTIME_INFO(__display)->step)
242
243#define IS_DISPLAY_STEP(__display, since, until) \
244 (drm_WARN_ON((__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \
245 INTEL_DISPLAY_STEP(__display) >= (since) && INTEL_DISPLAY_STEP(__display) < (until))
246
247#define ARLS_HOST_BRIDGE_PCI_ID1 0x7D1C
248#define ARLS_HOST_BRIDGE_PCI_ID2 0x7D2D
249#define ARLS_HOST_BRIDGE_PCI_ID3 0x7D2E
250#define ARLS_HOST_BRIDGE_PCI_ID4 0x7D2F
251
252#define IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(id) \
253 (((id) == ARLS_HOST_BRIDGE_PCI_ID1) || \
254 ((id) == ARLS_HOST_BRIDGE_PCI_ID2) || \
255 ((id) == ARLS_HOST_BRIDGE_PCI_ID3) || \
256 ((id) == ARLS_HOST_BRIDGE_PCI_ID4))
257
258struct intel_display_runtime_info {
259 struct intel_display_ip_ver {
260 u16 ver;
261 u16 rel;
262 u16 step; /* hardware */
263 } ip;
264 int step; /* symbolic */
265
266 u32 rawclk_freq;
267
268 u8 pipe_mask;
269 u8 cpu_transcoder_mask;
270 u16 port_mask;
271
272 u8 num_sprites[I915_MAX_PIPES];
273 u8 num_scalers[I915_MAX_PIPES];
274
275 u8 fbc_mask;
276
277 bool has_hdcp;
278 bool has_dmc;
279 bool has_dsc;
280 bool edp_typec_support;
281 bool has_dbuf_overlap_detection;
282};
283
284struct intel_display_device_info {
285 /* Initial runtime info. */
286 const struct intel_display_runtime_info __runtime_defaults;
287
288 u8 abox_mask;
289
290 struct {
291 u16 size; /* in blocks */
292 u8 slice_mask;
293 } dbuf;
294
295#define DEFINE_FLAG(name) u8 name:1
296 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
297#undef DEFINE_FLAG
298
299 /* Global register offset for the display engine */
300 u32 mmio_offset;
301
302 /* Register offsets for the various display pipes and transcoders */
303 u32 pipe_offsets[I915_MAX_TRANSCODERS];
304 u32 trans_offsets[I915_MAX_TRANSCODERS];
305 u32 cursor_offsets[I915_MAX_PIPES];
306
307 struct {
308 u32 degamma_lut_size;
309 u32 gamma_lut_size;
310 u32 degamma_lut_tests;
311 u32 gamma_lut_tests;
312 } color;
313};
314
315bool intel_display_device_present(struct intel_display *display);
316bool intel_display_device_enabled(struct intel_display *display);
317struct intel_display *intel_display_device_probe(struct pci_dev *pdev,
318 const struct intel_display_parent_interface *parent);
319void intel_display_device_remove(struct intel_display *display);
320void intel_display_device_info_runtime_init(struct intel_display *display);
321
322void intel_display_device_info_print(const struct intel_display_device_info *info,
323 const struct intel_display_runtime_info *runtime,
324 struct drm_printer *p);
325
326#endif
327

source code of linux/drivers/gpu/drm/i915/display/intel_display_device.h