1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#ifndef __INTEL_DISPLAY_CORE_H__
7#define __INTEL_DISPLAY_CORE_H__
8
9#include <linux/list.h>
10#include <linux/llist.h>
11#include <linux/mutex.h>
12#include <linux/types.h>
13#include <linux/wait.h>
14#include <linux/workqueue.h>
15
16#include <drm/drm_connector.h>
17#include <drm/drm_modeset_lock.h>
18
19#include "intel_cdclk.h"
20#include "intel_display_device.h"
21#include "intel_display_limits.h"
22#include "intel_display_params.h"
23#include "intel_display_power.h"
24#include "intel_dmc_wl.h"
25#include "intel_dpll_mgr.h"
26#include "intel_fbc.h"
27#include "intel_global_state.h"
28#include "intel_gmbus.h"
29#include "intel_opregion.h"
30#include "intel_pch.h"
31#include "intel_wm_types.h"
32
33struct drm_property;
34struct drm_property_blob;
35struct i915_audio_component;
36struct i915_hdcp_arbiter;
37struct intel_atomic_state;
38struct intel_audio_funcs;
39struct intel_cdclk_funcs;
40struct intel_cdclk_vals;
41struct intel_color_funcs;
42struct intel_crtc;
43struct intel_crtc_state;
44struct intel_display_parent_interface;
45struct intel_dmc;
46struct intel_dpll_global_funcs;
47struct intel_dpll_mgr;
48struct intel_fbdev;
49struct intel_fdi_funcs;
50struct intel_hotplug_funcs;
51struct intel_initial_plane_config;
52struct intel_opregion;
53struct intel_overlay;
54struct task_struct;
55
56/* Amount of SAGV/QGV points, BSpec precisely defines this */
57#define I915_NUM_QGV_POINTS 8
58
59/* Amount of PSF GV points, BSpec precisely defines this */
60#define I915_NUM_PSF_GV_POINTS 3
61
62struct intel_display_funcs {
63 /*
64 * Returns the active state of the crtc, and if the crtc is active,
65 * fills out the pipe-config with the hw state.
66 */
67 bool (*get_pipe_config)(struct intel_crtc *,
68 struct intel_crtc_state *);
69 void (*get_initial_plane_config)(struct intel_crtc *,
70 struct intel_initial_plane_config *);
71 bool (*fixup_initial_plane_config)(struct intel_crtc *crtc,
72 const struct intel_initial_plane_config *plane_config);
73 void (*crtc_enable)(struct intel_atomic_state *state,
74 struct intel_crtc *crtc);
75 void (*crtc_disable)(struct intel_atomic_state *state,
76 struct intel_crtc *crtc);
77 void (*commit_modeset_enables)(struct intel_atomic_state *state);
78};
79
80/* functions used for watermark calcs for display. */
81struct intel_wm_funcs {
82 /* update_wm is for legacy wm management */
83 void (*update_wm)(struct intel_display *display);
84 int (*compute_watermarks)(struct intel_atomic_state *state,
85 struct intel_crtc *crtc);
86 void (*initial_watermarks)(struct intel_atomic_state *state,
87 struct intel_crtc *crtc);
88 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
89 struct intel_crtc *crtc);
90 void (*optimize_watermarks)(struct intel_atomic_state *state,
91 struct intel_crtc *crtc);
92 int (*compute_global_watermarks)(struct intel_atomic_state *state);
93 void (*get_hw_state)(struct intel_display *display);
94 void (*sanitize)(struct intel_display *display);
95};
96
97struct intel_audio_state {
98 struct intel_encoder *encoder;
99 u8 eld[MAX_ELD_BYTES];
100};
101
102struct intel_audio {
103 /* hda/i915 audio component */
104 struct i915_audio_component *component;
105 bool component_registered;
106 /* mutex for audio/video sync */
107 struct mutex mutex;
108 int power_refcount;
109 u32 freq_cntrl;
110
111 /* current audio state for the audio component hooks */
112 struct intel_audio_state state[I915_MAX_TRANSCODERS];
113
114 /* necessary resource sharing with HDMI LPE audio driver. */
115 struct {
116 struct platform_device *platdev;
117 int irq;
118 } lpe;
119};
120
121/*
122 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
123 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
124 * dpll, because on some platforms plls share registers.
125 */
126struct intel_dpll_global {
127 struct mutex lock;
128
129 int num_dpll;
130 struct intel_dpll dplls[I915_NUM_PLLS];
131 const struct intel_dpll_mgr *mgr;
132
133 struct {
134 int nssc;
135 int ssc;
136 } ref_clks;
137
138 /*
139 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id.
140 */
141 u8 pch_ssc_use;
142};
143
144struct intel_frontbuffer_tracking {
145 /* protects busy_bits */
146 spinlock_t lock;
147
148 /*
149 * Tracking bits for delayed frontbuffer flushing due to gpu activity.
150 */
151 unsigned busy_bits;
152};
153
154struct intel_hotplug {
155 struct delayed_work hotplug_work;
156
157 const u32 *hpd, *pch_hpd;
158
159 struct {
160 unsigned long last_jiffies;
161 int count;
162 int blocked_count;
163 enum {
164 HPD_ENABLED = 0,
165 HPD_DISABLED = 1,
166 HPD_MARK_DISABLED = 2
167 } state;
168 } stats[HPD_NUM_PINS];
169 u32 event_bits;
170 u32 retry_bits;
171 struct delayed_work reenable_work;
172
173 u32 long_hpd_pin_mask;
174 u32 short_hpd_pin_mask;
175 struct work_struct dig_port_work;
176
177 struct work_struct poll_init_work;
178 bool poll_enabled;
179
180 /*
181 * Queuing of hotplug_work, reenable_work and poll_init_work is
182 * enabled. Protected by intel_display::irq::lock.
183 */
184 bool detection_work_enabled;
185
186 unsigned int hpd_storm_threshold;
187 /* Whether or not to count short HPD IRQs in HPD storms */
188 u8 hpd_short_storm_enabled;
189
190 /* Last state reported by oob_hotplug_event for each encoder */
191 unsigned long oob_hotplug_last_state;
192
193 /*
194 * if we get a HPD irq from DP and a HPD irq from non-DP
195 * the non-DP HPD could block the workqueue on a mode config
196 * mutex getting, that userspace may have taken. However
197 * userspace is waiting on the DP workqueue to run which is
198 * blocked behind the non-DP one.
199 */
200 struct workqueue_struct *dp_wq;
201
202 /*
203 * Flag to track if long HPDs need not to be processed
204 *
205 * Some panels generate long HPDs while keep connected to the port.
206 * This can cause issues with CI tests results. In CI systems we
207 * don't expect to disconnect the panels and could ignore the long
208 * HPDs generated from the faulty panels. This flag can be used as
209 * cue to ignore the long HPDs and can be set / unset using debugfs.
210 */
211 bool ignore_long_hpd;
212};
213
214struct intel_vbt_data {
215 /* bdb version */
216 u16 version;
217
218 /* Feature bits */
219 unsigned int int_tv_support:1;
220 unsigned int int_crt_support:1;
221 unsigned int lvds_use_ssc:1;
222 unsigned int int_lvds_support:1;
223 unsigned int display_clock_mode:1;
224 unsigned int fdi_rx_polarity_inverted:1;
225 int lvds_ssc_freq;
226 enum drm_panel_orientation orientation;
227
228 bool override_afc_startup;
229 u8 override_afc_startup_val;
230
231 int crt_ddc_pin;
232
233 struct list_head display_devices;
234 struct list_head bdb_blocks;
235
236 struct sdvo_device_mapping {
237 u8 initialized;
238 u8 dvo_port;
239 u8 target_addr;
240 u8 dvo_wiring;
241 u8 i2c_pin;
242 u8 ddc_pin;
243 } sdvo_mappings[2];
244};
245
246struct intel_wm {
247 /*
248 * Raw watermark latency values:
249 * in 0.1us units for WM0,
250 * in 0.5us units for WM1+.
251 */
252 /* primary */
253 u16 pri_latency[5];
254 /* sprite */
255 u16 spr_latency[5];
256 /* cursor */
257 u16 cur_latency[5];
258 /*
259 * Raw watermark memory latency values
260 * for SKL for all 8 levels
261 * in 1us units.
262 */
263 u16 skl_latency[8];
264
265 /* current hardware state */
266 union {
267 struct ilk_wm_values hw;
268 struct vlv_wm_values vlv;
269 struct g4x_wm_values g4x;
270 };
271
272 u8 num_levels;
273
274 /*
275 * Should be held around atomic WM register writing; also
276 * protects * intel_crtc->wm.active and
277 * crtc_state->wm.need_postvbl_update.
278 */
279 struct mutex wm_mutex;
280
281 bool ipc_enabled;
282};
283
284struct intel_display {
285 /* drm device backpointer */
286 struct drm_device *drm;
287
288 /* Platform (and subplatform, if any) identification */
289 struct intel_display_platforms platform;
290
291 /* Intel PCH: where the south display engine lives */
292 enum intel_pch pch_type;
293
294 /* Parent, or core, driver functions exposed to display */
295 const struct intel_display_parent_interface *parent;
296
297 /* Display functions */
298 struct {
299 /* Top level crtc-ish functions */
300 const struct intel_display_funcs *display;
301
302 /* Display CDCLK functions */
303 const struct intel_cdclk_funcs *cdclk;
304
305 /* Display pll funcs */
306 const struct intel_dpll_global_funcs *dpll;
307
308 /* irq display functions */
309 const struct intel_hotplug_funcs *hotplug;
310
311 /* pm display functions */
312 const struct intel_wm_funcs *wm;
313
314 /* fdi display functions */
315 const struct intel_fdi_funcs *fdi;
316
317 /* Display internal color functions */
318 const struct intel_color_funcs *color;
319
320 /* Display internal audio functions */
321 const struct intel_audio_funcs *audio;
322 } funcs;
323
324 struct {
325 bool any_task_allowed;
326 struct task_struct *allowed_task;
327 } access;
328
329 struct {
330 /* backlight registers and fields in struct intel_panel */
331 struct mutex lock;
332 } backlight;
333
334 struct {
335 struct intel_global_obj obj;
336
337 struct intel_bw_info {
338 /* for each QGV point */
339 unsigned int deratedbw[I915_NUM_QGV_POINTS];
340 /* for each PSF GV point */
341 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
342 /* Peak BW for each QGV point */
343 unsigned int peakbw[I915_NUM_QGV_POINTS];
344 u8 num_qgv_points;
345 u8 num_psf_gv_points;
346 u8 num_planes;
347 } max[6];
348 } bw;
349
350 struct {
351 /* The current hardware cdclk configuration */
352 struct intel_cdclk_config hw;
353
354 /* cdclk, divider, and ratio table from bspec */
355 const struct intel_cdclk_vals *table;
356
357 struct intel_global_obj obj;
358
359 unsigned int max_cdclk_freq;
360 unsigned int max_dotclk_freq;
361 unsigned int skl_preferred_vco_freq;
362 } cdclk;
363
364 struct {
365 struct drm_property_blob *glk_linear_degamma_lut;
366 } color;
367
368 struct {
369 /* The current hardware dbuf configuration */
370 u8 enabled_slices;
371
372 struct intel_global_obj obj;
373 } dbuf;
374
375 struct {
376 struct intel_global_obj obj;
377 } dbuf_bw;
378
379 struct {
380 /*
381 * dkl.phy_lock protects against concurrent access of the
382 * Dekel TypeC PHYs.
383 */
384 spinlock_t phy_lock;
385 } dkl;
386
387 struct {
388 struct intel_dmc *dmc;
389 intel_wakeref_t wakeref;
390 } dmc;
391
392 struct {
393 /* VLV/CHV/BXT/GLK DSI MMIO register base address */
394 u32 mmio_base;
395 } dsi;
396
397 struct {
398 /* list of fbdev register on this device */
399 struct intel_fbdev *fbdev;
400 } fbdev;
401
402 struct {
403 unsigned int pll_freq;
404 u32 rx_config;
405 } fdi;
406
407 struct {
408 struct list_head obj_list;
409 } global;
410
411 struct {
412 /*
413 * Base address of where the gmbus and gpio blocks are located
414 * (either on PCH or on SoC for platforms without PCH).
415 */
416 u32 mmio_base;
417
418 /*
419 * gmbus.mutex protects against concurrent usage of the single
420 * hw gmbus controller on different i2c buses.
421 */
422 struct mutex mutex;
423
424 struct intel_gmbus *bus[GMBUS_NUM_PINS];
425
426 wait_queue_head_t wait_queue;
427 } gmbus;
428
429 struct {
430 struct i915_hdcp_arbiter *arbiter;
431 bool comp_added;
432
433 /*
434 * HDCP message struct for allocation of memory which can be
435 * reused when sending message to gsc cs.
436 * this is only populated post Meteorlake
437 */
438 struct intel_hdcp_gsc_context *gsc_context;
439 /* Mutex to protect the above hdcp related values. */
440 struct mutex hdcp_mutex;
441 } hdcp;
442
443 struct {
444 /*
445 * HTI (aka HDPORT) state read during initial hw readout. Most
446 * platforms don't have HTI, so this will just stay 0. Those
447 * that do will use this later to figure out which PLLs and PHYs
448 * are unavailable for driver usage.
449 */
450 u32 state;
451 } hti;
452
453 struct {
454 /* Access with DISPLAY_INFO() */
455 const struct intel_display_device_info *__device_info;
456
457 /* Access with DISPLAY_RUNTIME_INFO() */
458 struct intel_display_runtime_info __runtime_info;
459 } info;
460
461 struct {
462 bool false_color;
463 } ips;
464
465 struct {
466 /* protects the irq masks */
467 spinlock_t lock;
468
469 /*
470 * Most platforms treat the display irq block as an always-on
471 * power domain. vlv/chv can disable it at runtime and need
472 * special care to avoid writing any of the display block
473 * registers outside of the power domain. We defer setting up
474 * the display irqs in this case to the runtime pm.
475 */
476 bool vlv_display_irqs_enabled;
477
478 /* For i915gm/i945gm vblank irq workaround */
479 u8 vblank_enabled;
480
481 int vblank_enable_count;
482
483 struct work_struct vblank_notify_work;
484
485 /*
486 * Cached value of VLV/CHV IMR to avoid reads in updating the
487 * bitfield.
488 */
489 u32 vlv_imr_mask;
490 /*
491 * Cached value of gen 5-7 DE IMR to avoid reads in updating the
492 * bitfield.
493 */
494 u32 ilk_de_imr_mask;
495 /*
496 * Cached value of BDW+ DE pipe IMR to avoid reads in updating
497 * the bitfield.
498 */
499 u32 de_pipe_imr_mask[I915_MAX_PIPES];
500 u32 pipestat_irq_mask[I915_MAX_PIPES];
501 } irq;
502
503 struct {
504 /* protected by wm.wm_mutex */
505 u16 linetime[I915_MAX_PIPES];
506 bool disable[I915_MAX_PIPES];
507 } pkgc;
508
509 struct {
510 wait_queue_head_t waitqueue;
511
512 /* mutex to protect pmdemand programming sequence */
513 struct mutex lock;
514
515 struct intel_global_obj obj;
516 } pmdemand;
517
518 struct {
519 struct i915_power_domains domains;
520
521 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
522 u32 chv_phy_control;
523
524 /* perform PHY state sanity checks? */
525 bool chv_phy_assert[2];
526 } power;
527
528 struct {
529 u32 mmio_base;
530
531 /* protects panel power sequencer state */
532 struct mutex mutex;
533 } pps;
534
535 struct {
536 struct drm_property *broadcast_rgb;
537 struct drm_property *force_audio;
538 } properties;
539
540 struct {
541 unsigned long mask;
542 } quirks;
543
544 struct {
545 /* restore state for suspend/resume and display reset */
546 struct drm_atomic_state *modeset_state;
547 struct drm_modeset_acquire_ctx reset_ctx;
548 /* modeset stuck tracking for reset */
549 atomic_t pending_fb_pin;
550 u32 saveDSPARB;
551 u32 saveSWF0[16];
552 u32 saveSWF1[16];
553 u32 saveSWF3[3];
554 u16 saveGCDGMBUS;
555 } restore;
556
557 struct {
558 enum {
559 I915_SAGV_UNKNOWN = 0,
560 I915_SAGV_DISABLED,
561 I915_SAGV_ENABLED,
562 I915_SAGV_NOT_CONTROLLED
563 } status;
564
565 u32 block_time_us;
566 } sagv;
567
568 struct {
569 /* LPT/WPT IOSF sideband protection */
570 struct mutex lock;
571 } sbi;
572
573 struct {
574 /*
575 * DG2: Mask of PHYs that were not calibrated by the firmware
576 * and should not be used.
577 */
578 u8 phy_failed_calibration;
579 } snps;
580
581 struct {
582 /*
583 * Shadows for CHV DPLL_MD regs to keep the state
584 * checker somewhat working in the presence hardware
585 * crappiness (can't read out DPLL_MD for pipes B & C).
586 */
587 u32 chv_dpll_md[I915_MAX_PIPES];
588 u32 bxt_phy_grc;
589 } state;
590
591 struct {
592 unsigned int hpll_freq;
593 unsigned int czclk_freq;
594 } vlv_clock;
595
596 struct {
597 /* ordered wq for modesets */
598 struct workqueue_struct *modeset;
599
600 /* unbound hipri wq for page flips/plane updates */
601 struct workqueue_struct *flip;
602
603 /* hipri wq for commit cleanups */
604 struct workqueue_struct *cleanup;
605
606 /* unordered workqueue for all display unordered work */
607 struct workqueue_struct *unordered;
608 } wq;
609
610 /* Grouping using named structs. Keep sorted. */
611 struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
612 struct intel_audio audio;
613 struct intel_dpll_global dpll;
614 struct intel_fbc *fbc[I915_MAX_FBCS];
615 struct intel_frontbuffer_tracking fb_tracking;
616 struct intel_hotplug hotplug;
617 struct intel_opregion *opregion;
618 struct intel_overlay *overlay;
619 struct intel_display_params params;
620 struct intel_vbt_data vbt;
621 struct intel_dmc_wl wl;
622 struct intel_wm wm;
623
624 struct work_struct psr_dc5_dc6_wa_work;
625};
626
627#endif /* __INTEL_DISPLAY_CORE_H__ */
628

source code of linux/drivers/gpu/drm/i915/display/intel_display_core.h