| 1 | /* SPDX-License-Identifier: MIT */ |
|---|
| 2 | /* Copyright © 2024 Intel Corporation */ |
|---|
| 3 | |
|---|
| 4 | #ifndef __I9XX_WM_REGS_H__ |
|---|
| 5 | #define __I9XX_WM_REGS_H__ |
|---|
| 6 | |
|---|
| 7 | #include "intel_display_reg_defs.h" |
|---|
| 8 | |
|---|
| 9 | #define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) |
|---|
| 10 | #define DSPARB_CSTART_MASK (0x7f << 7) |
|---|
| 11 | #define DSPARB_CSTART_SHIFT 7 |
|---|
| 12 | #define DSPARB_BSTART_MASK (0x7f) |
|---|
| 13 | #define DSPARB_BSTART_SHIFT 0 |
|---|
| 14 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
|---|
| 15 | #define DSPARB_AEND_SHIFT 0 |
|---|
| 16 | #define DSPARB_SPRITEA_SHIFT_VLV 0 |
|---|
| 17 | #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) |
|---|
| 18 | #define DSPARB_SPRITEB_SHIFT_VLV 8 |
|---|
| 19 | #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) |
|---|
| 20 | #define DSPARB_SPRITEC_SHIFT_VLV 16 |
|---|
| 21 | #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) |
|---|
| 22 | #define DSPARB_SPRITED_SHIFT_VLV 24 |
|---|
| 23 | #define DSPARB_SPRITED_MASK_VLV (0xff << 24) |
|---|
| 24 | #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ |
|---|
| 25 | #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 |
|---|
| 26 | #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) |
|---|
| 27 | #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 |
|---|
| 28 | #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) |
|---|
| 29 | #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 |
|---|
| 30 | #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) |
|---|
| 31 | #define DSPARB_SPRITED_HI_SHIFT_VLV 12 |
|---|
| 32 | #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) |
|---|
| 33 | #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 |
|---|
| 34 | #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) |
|---|
| 35 | #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 |
|---|
| 36 | #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) |
|---|
| 37 | #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ |
|---|
| 38 | #define DSPARB_SPRITEE_SHIFT_VLV 0 |
|---|
| 39 | #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) |
|---|
| 40 | #define DSPARB_SPRITEF_SHIFT_VLV 8 |
|---|
| 41 | #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) |
|---|
| 42 | |
|---|
| 43 | /* pnv/gen4/g4x/vlv/chv */ |
|---|
| 44 | #define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) |
|---|
| 45 | #define DSPFW_SR_SHIFT 23 |
|---|
| 46 | #define DSPFW_SR_MASK (0x1ff << 23) |
|---|
| 47 | #define DSPFW_CURSORB_SHIFT 16 |
|---|
| 48 | #define DSPFW_CURSORB_MASK (0x3f << 16) |
|---|
| 49 | #define DSPFW_PLANEB_SHIFT 8 |
|---|
| 50 | #define DSPFW_PLANEB_MASK (0x7f << 8) |
|---|
| 51 | #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ |
|---|
| 52 | #define DSPFW_PLANEA_SHIFT 0 |
|---|
| 53 | #define DSPFW_PLANEA_MASK (0x7f << 0) |
|---|
| 54 | #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ |
|---|
| 55 | #define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) |
|---|
| 56 | #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ |
|---|
| 57 | #define DSPFW_FBC_SR_SHIFT 28 |
|---|
| 58 | #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ |
|---|
| 59 | #define DSPFW_FBC_HPLL_SR_SHIFT 24 |
|---|
| 60 | #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ |
|---|
| 61 | #define DSPFW_SPRITEB_SHIFT (16) |
|---|
| 62 | #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ |
|---|
| 63 | #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ |
|---|
| 64 | #define DSPFW_CURSORA_SHIFT 8 |
|---|
| 65 | #define DSPFW_CURSORA_MASK (0x3f << 8) |
|---|
| 66 | #define DSPFW_PLANEC_OLD_SHIFT 0 |
|---|
| 67 | #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ |
|---|
| 68 | #define DSPFW_SPRITEA_SHIFT 0 |
|---|
| 69 | #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ |
|---|
| 70 | #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ |
|---|
| 71 | #define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) |
|---|
| 72 | #define DSPFW_HPLL_SR_EN (1 << 31) |
|---|
| 73 | #define PINEVIEW_SELF_REFRESH_EN (1 << 30) |
|---|
| 74 | #define DSPFW_CURSOR_SR_SHIFT 24 |
|---|
| 75 | #define DSPFW_CURSOR_SR_MASK (0x3f << 24) |
|---|
| 76 | #define DSPFW_HPLL_CURSOR_SHIFT 16 |
|---|
| 77 | #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) |
|---|
| 78 | #define DSPFW_HPLL_SR_SHIFT 0 |
|---|
| 79 | #define DSPFW_HPLL_SR_MASK (0x1ff << 0) |
|---|
| 80 | |
|---|
| 81 | /* vlv/chv */ |
|---|
| 82 | #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) |
|---|
| 83 | #define DSPFW_SPRITEB_WM1_SHIFT 16 |
|---|
| 84 | #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) |
|---|
| 85 | #define DSPFW_CURSORA_WM1_SHIFT 8 |
|---|
| 86 | #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) |
|---|
| 87 | #define DSPFW_SPRITEA_WM1_SHIFT 0 |
|---|
| 88 | #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) |
|---|
| 89 | #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) |
|---|
| 90 | #define DSPFW_PLANEB_WM1_SHIFT 24 |
|---|
| 91 | #define DSPFW_PLANEB_WM1_MASK (0xff << 24) |
|---|
| 92 | #define DSPFW_PLANEA_WM1_SHIFT 16 |
|---|
| 93 | #define DSPFW_PLANEA_WM1_MASK (0xff << 16) |
|---|
| 94 | #define DSPFW_CURSORB_WM1_SHIFT 8 |
|---|
| 95 | #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) |
|---|
| 96 | #define DSPFW_CURSOR_SR_WM1_SHIFT 0 |
|---|
| 97 | #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) |
|---|
| 98 | #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) |
|---|
| 99 | #define DSPFW_SR_WM1_SHIFT 0 |
|---|
| 100 | #define DSPFW_SR_WM1_MASK (0x1ff << 0) |
|---|
| 101 | #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) |
|---|
| 102 | #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ |
|---|
| 103 | #define DSPFW_SPRITED_WM1_SHIFT 24 |
|---|
| 104 | #define DSPFW_SPRITED_WM1_MASK (0xff << 24) |
|---|
| 105 | #define DSPFW_SPRITED_SHIFT 16 |
|---|
| 106 | #define DSPFW_SPRITED_MASK_VLV (0xff << 16) |
|---|
| 107 | #define DSPFW_SPRITEC_WM1_SHIFT 8 |
|---|
| 108 | #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) |
|---|
| 109 | #define DSPFW_SPRITEC_SHIFT 0 |
|---|
| 110 | #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) |
|---|
| 111 | #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) |
|---|
| 112 | #define DSPFW_SPRITEF_WM1_SHIFT 24 |
|---|
| 113 | #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) |
|---|
| 114 | #define DSPFW_SPRITEF_SHIFT 16 |
|---|
| 115 | #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) |
|---|
| 116 | #define DSPFW_SPRITEE_WM1_SHIFT 8 |
|---|
| 117 | #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) |
|---|
| 118 | #define DSPFW_SPRITEE_SHIFT 0 |
|---|
| 119 | #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) |
|---|
| 120 | #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ |
|---|
| 121 | #define DSPFW_PLANEC_WM1_SHIFT 24 |
|---|
| 122 | #define DSPFW_PLANEC_WM1_MASK (0xff << 24) |
|---|
| 123 | #define DSPFW_PLANEC_SHIFT 16 |
|---|
| 124 | #define DSPFW_PLANEC_MASK_VLV (0xff << 16) |
|---|
| 125 | #define DSPFW_CURSORC_WM1_SHIFT 8 |
|---|
| 126 | #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) |
|---|
| 127 | #define DSPFW_CURSORC_SHIFT 0 |
|---|
| 128 | #define DSPFW_CURSORC_MASK (0x3f << 0) |
|---|
| 129 | |
|---|
| 130 | /* vlv/chv high order bits */ |
|---|
| 131 | #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) |
|---|
| 132 | #define DSPFW_SR_HI_SHIFT 24 |
|---|
| 133 | #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ |
|---|
| 134 | #define DSPFW_SPRITEF_HI_SHIFT 23 |
|---|
| 135 | #define DSPFW_SPRITEF_HI_MASK (1 << 23) |
|---|
| 136 | #define DSPFW_SPRITEE_HI_SHIFT 22 |
|---|
| 137 | #define DSPFW_SPRITEE_HI_MASK (1 << 22) |
|---|
| 138 | #define DSPFW_PLANEC_HI_SHIFT 21 |
|---|
| 139 | #define DSPFW_PLANEC_HI_MASK (1 << 21) |
|---|
| 140 | #define DSPFW_SPRITED_HI_SHIFT 20 |
|---|
| 141 | #define DSPFW_SPRITED_HI_MASK (1 << 20) |
|---|
| 142 | #define DSPFW_SPRITEC_HI_SHIFT 16 |
|---|
| 143 | #define DSPFW_SPRITEC_HI_MASK (1 << 16) |
|---|
| 144 | #define DSPFW_PLANEB_HI_SHIFT 12 |
|---|
| 145 | #define DSPFW_PLANEB_HI_MASK (1 << 12) |
|---|
| 146 | #define DSPFW_SPRITEB_HI_SHIFT 8 |
|---|
| 147 | #define DSPFW_SPRITEB_HI_MASK (1 << 8) |
|---|
| 148 | #define DSPFW_SPRITEA_HI_SHIFT 4 |
|---|
| 149 | #define DSPFW_SPRITEA_HI_MASK (1 << 4) |
|---|
| 150 | #define DSPFW_PLANEA_HI_SHIFT 0 |
|---|
| 151 | #define DSPFW_PLANEA_HI_MASK (1 << 0) |
|---|
| 152 | #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) |
|---|
| 153 | #define DSPFW_SR_WM1_HI_SHIFT 24 |
|---|
| 154 | #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ |
|---|
| 155 | #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 |
|---|
| 156 | #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) |
|---|
| 157 | #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 |
|---|
| 158 | #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) |
|---|
| 159 | #define DSPFW_PLANEC_WM1_HI_SHIFT 21 |
|---|
| 160 | #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) |
|---|
| 161 | #define DSPFW_SPRITED_WM1_HI_SHIFT 20 |
|---|
| 162 | #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) |
|---|
| 163 | #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 |
|---|
| 164 | #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) |
|---|
| 165 | #define DSPFW_PLANEB_WM1_HI_SHIFT 12 |
|---|
| 166 | #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) |
|---|
| 167 | #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 |
|---|
| 168 | #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) |
|---|
| 169 | #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 |
|---|
| 170 | #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) |
|---|
| 171 | #define DSPFW_PLANEA_WM1_HI_SHIFT 0 |
|---|
| 172 | #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) |
|---|
| 173 | |
|---|
| 174 | /* drain latency register values*/ |
|---|
| 175 | #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) |
|---|
| 176 | #define DDL_CURSOR_SHIFT 24 |
|---|
| 177 | #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) |
|---|
| 178 | #define DDL_PLANE_SHIFT 0 |
|---|
| 179 | #define DDL_PRECISION_HIGH (1 << 7) |
|---|
| 180 | #define DDL_PRECISION_LOW (0 << 7) |
|---|
| 181 | #define DRAIN_LATENCY_MASK 0x7f |
|---|
| 182 | |
|---|
| 183 | /* FIFO watermark sizes etc */ |
|---|
| 184 | #define G4X_FIFO_LINE_SIZE 64 |
|---|
| 185 | #define I915_FIFO_LINE_SIZE 64 |
|---|
| 186 | #define I830_FIFO_LINE_SIZE 32 |
|---|
| 187 | |
|---|
| 188 | #define VALLEYVIEW_FIFO_SIZE 255 |
|---|
| 189 | #define G4X_FIFO_SIZE 127 |
|---|
| 190 | #define I965_FIFO_SIZE 512 |
|---|
| 191 | #define I945_FIFO_SIZE 127 |
|---|
| 192 | #define I915_FIFO_SIZE 95 |
|---|
| 193 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
|---|
| 194 | #define I830_FIFO_SIZE 95 |
|---|
| 195 | |
|---|
| 196 | #define VALLEYVIEW_MAX_WM 0xff |
|---|
| 197 | #define G4X_MAX_WM 0x3f |
|---|
| 198 | #define I915_MAX_WM 0x3f |
|---|
| 199 | |
|---|
| 200 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
|---|
| 201 | #define PINEVIEW_FIFO_LINE_SIZE 64 |
|---|
| 202 | #define PINEVIEW_MAX_WM 0x1ff |
|---|
| 203 | #define PINEVIEW_DFT_WM 0x3f |
|---|
| 204 | #define PINEVIEW_DFT_HPLLOFF_WM 0 |
|---|
| 205 | #define PINEVIEW_GUARD_WM 10 |
|---|
| 206 | #define PINEVIEW_CURSOR_FIFO 64 |
|---|
| 207 | #define PINEVIEW_CURSOR_MAX_WM 0x3f |
|---|
| 208 | #define PINEVIEW_CURSOR_DFT_WM 0 |
|---|
| 209 | #define PINEVIEW_CURSOR_GUARD_WM 5 |
|---|
| 210 | |
|---|
| 211 | #define VALLEYVIEW_CURSOR_MAX_WM 64 |
|---|
| 212 | #define I965_CURSOR_FIFO 64 |
|---|
| 213 | #define I965_CURSOR_MAX_WM 32 |
|---|
| 214 | #define I965_CURSOR_DFT_WM 8 |
|---|
| 215 | |
|---|
| 216 | /* define the Watermark register on Ironlake */ |
|---|
| 217 | #define _WM0_PIPEA_ILK 0x45100 |
|---|
| 218 | #define _WM0_PIPEB_ILK 0x45104 |
|---|
| 219 | #define _WM0_PIPEC_IVB 0x45200 |
|---|
| 220 | #define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \ |
|---|
| 221 | _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) |
|---|
| 222 | #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) |
|---|
| 223 | #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) |
|---|
| 224 | #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) |
|---|
| 225 | #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) |
|---|
| 226 | #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) |
|---|
| 227 | #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) |
|---|
| 228 | #define WM1_LP_ILK _MMIO(0x45108) |
|---|
| 229 | #define WM2_LP_ILK _MMIO(0x4510c) |
|---|
| 230 | #define WM3_LP_ILK _MMIO(0x45110) |
|---|
| 231 | #define WM_LP_ENABLE REG_BIT(31) |
|---|
| 232 | #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) |
|---|
| 233 | #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) |
|---|
| 234 | #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) |
|---|
| 235 | #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) |
|---|
| 236 | #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) |
|---|
| 237 | #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) |
|---|
| 238 | #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) |
|---|
| 239 | #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) |
|---|
| 240 | #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) |
|---|
| 241 | #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) |
|---|
| 242 | #define WM1S_LP_ILK _MMIO(0x45120) |
|---|
| 243 | #define WM2S_LP_IVB _MMIO(0x45124) |
|---|
| 244 | #define WM3S_LP_IVB _MMIO(0x45128) |
|---|
| 245 | #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ |
|---|
| 246 | #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) |
|---|
| 247 | #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) |
|---|
| 248 | |
|---|
| 249 | #define WM_MISC _MMIO(0x45260) |
|---|
| 250 | #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) |
|---|
| 251 | |
|---|
| 252 | #define WM_DBG _MMIO(0x45280) |
|---|
| 253 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) |
|---|
| 254 | #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) |
|---|
| 255 | #define WM_DBG_DISALLOW_SPRITE (1 << 2) |
|---|
| 256 | |
|---|
| 257 | #endif /* __I9XX_WM_REGS_H__ */ |
|---|
| 258 | |
|---|
