1/*
2 *
3 * Copyright (c) 2012 Gilles Dartiguelongue, Thomas Richter
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29#include <drm/drm_print.h>
30
31#include "intel_display_types.h"
32#include "intel_dvo_dev.h"
33
34#define NS2501_VID 0x1305
35#define NS2501_DID 0x6726
36
37#define NS2501_VID_LO 0x00
38#define NS2501_VID_HI 0x01
39#define NS2501_DID_LO 0x02
40#define NS2501_DID_HI 0x03
41#define NS2501_REV 0x04
42#define NS2501_RSVD 0x05
43#define NS2501_FREQ_LO 0x06
44#define NS2501_FREQ_HI 0x07
45
46#define NS2501_REG8 0x08
47#define NS2501_8_VEN (1<<5)
48#define NS2501_8_HEN (1<<4)
49#define NS2501_8_DSEL (1<<3)
50#define NS2501_8_BPAS (1<<2)
51#define NS2501_8_RSVD (1<<1)
52#define NS2501_8_PD (1<<0)
53
54#define NS2501_REG9 0x09
55#define NS2501_9_VLOW (1<<7)
56#define NS2501_9_MSEL_MASK (0x7<<4)
57#define NS2501_9_TSEL (1<<3)
58#define NS2501_9_RSEN (1<<2)
59#define NS2501_9_RSVD (1<<1)
60#define NS2501_9_MDI (1<<0)
61
62#define NS2501_REGC 0x0c
63
64/*
65 * The following registers are not part of the official datasheet
66 * and are the result of reverse engineering.
67 */
68
69/*
70 * Register c0 controls how the DVO synchronizes with
71 * its input.
72 */
73#define NS2501_REGC0 0xc0
74#define NS2501_C0_ENABLE (1<<0) /* enable the DVO sync in general */
75#define NS2501_C0_HSYNC (1<<1) /* synchronize horizontal with input */
76#define NS2501_C0_VSYNC (1<<2) /* synchronize vertical with input */
77#define NS2501_C0_RESET (1<<7) /* reset the synchronization flip/flops */
78
79/*
80 * Register 41 is somehow related to the sync register and sync
81 * configuration. It should be 0x32 whenever regC0 is 0x05 (hsync off)
82 * and 0x00 otherwise.
83 */
84#define NS2501_REG41 0x41
85
86/*
87 * this register controls the dithering of the DVO
88 * One bit enables it, the other define the dithering depth.
89 * The higher the value, the lower the dithering depth.
90 */
91#define NS2501_F9_REG 0xf9
92#define NS2501_F9_ENABLE (1<<0) /* if set, dithering is enabled */
93#define NS2501_F9_DITHER_MASK (0x7f<<1) /* controls the dither depth */
94#define NS2501_F9_DITHER_SHIFT 1 /* shifts the dither mask */
95
96/*
97 * PLL configuration register. This is a pair of registers,
98 * one single byte register at 1B, and a pair at 1C,1D.
99 * These registers are counters/dividers.
100 */
101#define NS2501_REG1B 0x1b /* one byte PLL control register */
102#define NS2501_REG1C 0x1c /* low-part of the second register */
103#define NS2501_REG1D 0x1d /* high-part of the second register */
104
105/*
106 * Scaler control registers. Horizontal at b8,b9,
107 * vertical at 10,11. The scale factor is computed as
108 * 2^16/control-value. The low-byte comes first.
109 */
110#define NS2501_REG10 0x10 /* low-byte vertical scaler */
111#define NS2501_REG11 0x11 /* high-byte vertical scaler */
112#define NS2501_REGB8 0xb8 /* low-byte horizontal scaler */
113#define NS2501_REGB9 0xb9 /* high-byte horizontal scaler */
114
115/*
116 * Display window definition. This consists of four registers
117 * per dimension. One register pair defines the start of the
118 * display, one the end.
119 * As far as I understand, this defines the window within which
120 * the scaler samples the input.
121 */
122#define NS2501_REGC1 0xc1 /* low-byte horizontal display start */
123#define NS2501_REGC2 0xc2 /* high-byte horizontal display start */
124#define NS2501_REGC3 0xc3 /* low-byte horizontal display stop */
125#define NS2501_REGC4 0xc4 /* high-byte horizontal display stop */
126#define NS2501_REGC5 0xc5 /* low-byte vertical display start */
127#define NS2501_REGC6 0xc6 /* high-byte vertical display start */
128#define NS2501_REGC7 0xc7 /* low-byte vertical display stop */
129#define NS2501_REGC8 0xc8 /* high-byte vertical display stop */
130
131/*
132 * The following register pair seems to define the start of
133 * the vertical sync. If automatic syncing is enabled, and the
134 * register value defines a sync pulse that is later than the
135 * incoming sync, then the register value is ignored and the
136 * external hsync triggers the synchronization.
137 */
138#define NS2501_REG80 0x80 /* low-byte vsync-start */
139#define NS2501_REG81 0x81 /* high-byte vsync-start */
140
141/*
142 * The following register pair seems to define the total number
143 * of lines created at the output side of the scaler.
144 * This is again a low-high register pair.
145 */
146#define NS2501_REG82 0x82 /* output display height, low byte */
147#define NS2501_REG83 0x83 /* output display height, high byte */
148
149/*
150 * The following registers define the end of the front-porch
151 * in horizontal and vertical position and hence allow to shift
152 * the image left/right or up/down.
153 */
154#define NS2501_REG98 0x98 /* horizontal start of display + 256, low */
155#define NS2501_REG99 0x99 /* horizontal start of display + 256, high */
156#define NS2501_REG8E 0x8e /* vertical start of the display, low byte */
157#define NS2501_REG8F 0x8f /* vertical start of the display, high byte */
158
159/*
160 * The following register pair control the function of the
161 * backlight and the DVO output. To enable the corresponding
162 * function, the corresponding bit must be set in both registers.
163 */
164#define NS2501_REG34 0x34 /* DVO enable functions, first register */
165#define NS2501_REG35 0x35 /* DVO enable functions, second register */
166#define NS2501_34_ENABLE_OUTPUT (1<<0) /* enable DVO output */
167#define NS2501_34_ENABLE_BACKLIGHT (1<<1) /* enable backlight */
168
169/*
170 * Registers 9C and 9D define the vertical output offset
171 * of the visible region.
172 */
173#define NS2501_REG9C 0x9c
174#define NS2501_REG9D 0x9d
175
176/*
177 * The register 9F defines the dithering. This requires the
178 * scaler to be ON. Bit 0 enables dithering, the remaining
179 * bits control the depth of the dither. The higher the value,
180 * the LOWER the dithering amplitude. A good value seems to be
181 * 15 (total register value).
182 */
183#define NS2501_REGF9 0xf9
184#define NS2501_F9_ENABLE_DITHER (1<<0) /* enable dithering */
185#define NS2501_F9_DITHER_MASK (0x7f<<1) /* dither masking */
186#define NS2501_F9_DITHER_SHIFT 1 /* upshift of the dither mask */
187
188enum {
189 MODE_640x480,
190 MODE_800x600,
191 MODE_1024x768,
192};
193
194struct ns2501_reg {
195 u8 offset;
196 u8 value;
197};
198
199/*
200 * The following structure keeps the complete configuration of
201 * the DVO, given a specific output configuration.
202 * This is pretty much guess-work from reverse-engineering, so
203 * read all this with a grain of salt.
204 */
205struct ns2501_configuration {
206 u8 sync; /* configuration of the C0 register */
207 u8 conf; /* configuration register 8 */
208 u8 syncb; /* configuration register 41 */
209 u8 dither; /* configuration of the dithering */
210 u8 pll_a; /* PLL configuration, register A, 1B */
211 u16 pll_b; /* PLL configuration, register B, 1C/1D */
212 u16 hstart; /* horizontal start, registers C1/C2 */
213 u16 hstop; /* horizontal total, registers C3/C4 */
214 u16 vstart; /* vertical start, registers C5/C6 */
215 u16 vstop; /* vertical total, registers C7/C8 */
216 u16 vsync; /* manual vertical sync start, 80/81 */
217 u16 vtotal; /* number of lines generated, 82/83 */
218 u16 hpos; /* horizontal position + 256, 98/99 */
219 u16 vpos; /* vertical position, 8e/8f */
220 u16 voffs; /* vertical output offset, 9c/9d */
221 u16 hscale; /* horizontal scaling factor, b8/b9 */
222 u16 vscale; /* vertical scaling factor, 10/11 */
223};
224
225/*
226 * DVO configuration values, partially based on what the BIOS
227 * of the Fujitsu Lifebook S6010 writes into registers,
228 * partially found by manual tweaking. These configurations assume
229 * a 1024x768 panel.
230 */
231static const struct ns2501_configuration ns2501_modes[] = {
232 [MODE_640x480] = {
233 .sync = NS2501_C0_ENABLE | NS2501_C0_VSYNC,
234 .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD,
235 .syncb = 0x32,
236 .dither = 0x0f,
237 .pll_a = 17,
238 .pll_b = 852,
239 .hstart = 144,
240 .hstop = 783,
241 .vstart = 22,
242 .vstop = 514,
243 .vsync = 2047, /* actually, ignored with this config */
244 .vtotal = 1341,
245 .hpos = 0,
246 .vpos = 16,
247 .voffs = 36,
248 .hscale = 40960,
249 .vscale = 40960
250 },
251 [MODE_800x600] = {
252 .sync = NS2501_C0_ENABLE |
253 NS2501_C0_HSYNC | NS2501_C0_VSYNC,
254 .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD,
255 .syncb = 0x00,
256 .dither = 0x0f,
257 .pll_a = 25,
258 .pll_b = 612,
259 .hstart = 215,
260 .hstop = 1016,
261 .vstart = 26,
262 .vstop = 627,
263 .vsync = 807,
264 .vtotal = 1341,
265 .hpos = 0,
266 .vpos = 4,
267 .voffs = 35,
268 .hscale = 51248,
269 .vscale = 51232
270 },
271 [MODE_1024x768] = {
272 .sync = NS2501_C0_ENABLE | NS2501_C0_VSYNC,
273 .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD,
274 .syncb = 0x32,
275 .dither = 0x0f,
276 .pll_a = 11,
277 .pll_b = 1350,
278 .hstart = 276,
279 .hstop = 1299,
280 .vstart = 15,
281 .vstop = 1056,
282 .vsync = 2047,
283 .vtotal = 1341,
284 .hpos = 0,
285 .vpos = 7,
286 .voffs = 27,
287 .hscale = 65535,
288 .vscale = 65535
289 }
290};
291
292/*
293 * Other configuration values left by the BIOS of the
294 * Fujitsu S6010 in the DVO control registers. Their
295 * value does not depend on the BIOS and their meaning
296 * is unknown.
297 */
298
299static const struct ns2501_reg mode_agnostic_values[] = {
300 /* 08 is mode specific */
301 [0] = { .offset = 0x0a, .value = 0x81, },
302 /* 10,11 are part of the mode specific configuration */
303 [1] = { .offset = 0x12, .value = 0x02, },
304 [2] = { .offset = 0x18, .value = 0x07, },
305 [3] = { .offset = 0x19, .value = 0x00, },
306 [4] = { .offset = 0x1a, .value = 0x00, }, /* PLL?, ignored */
307 /* 1b,1c,1d are part of the mode specific configuration */
308 [5] = { .offset = 0x1e, .value = 0x02, },
309 [6] = { .offset = 0x1f, .value = 0x40, },
310 [7] = { .offset = 0x20, .value = 0x00, },
311 [8] = { .offset = 0x21, .value = 0x00, },
312 [9] = { .offset = 0x22, .value = 0x00, },
313 [10] = { .offset = 0x23, .value = 0x00, },
314 [11] = { .offset = 0x24, .value = 0x00, },
315 [12] = { .offset = 0x25, .value = 0x00, },
316 [13] = { .offset = 0x26, .value = 0x00, },
317 [14] = { .offset = 0x27, .value = 0x00, },
318 [15] = { .offset = 0x7e, .value = 0x18, },
319 /* 80-84 are part of the mode-specific configuration */
320 [16] = { .offset = 0x84, .value = 0x00, },
321 [17] = { .offset = 0x85, .value = 0x00, },
322 [18] = { .offset = 0x86, .value = 0x00, },
323 [19] = { .offset = 0x87, .value = 0x00, },
324 [20] = { .offset = 0x88, .value = 0x00, },
325 [21] = { .offset = 0x89, .value = 0x00, },
326 [22] = { .offset = 0x8a, .value = 0x00, },
327 [23] = { .offset = 0x8b, .value = 0x00, },
328 [24] = { .offset = 0x8c, .value = 0x10, },
329 [25] = { .offset = 0x8d, .value = 0x02, },
330 /* 8e,8f are part of the mode-specific configuration */
331 [26] = { .offset = 0x90, .value = 0xff, },
332 [27] = { .offset = 0x91, .value = 0x07, },
333 [28] = { .offset = 0x92, .value = 0xa0, },
334 [29] = { .offset = 0x93, .value = 0x02, },
335 [30] = { .offset = 0x94, .value = 0x00, },
336 [31] = { .offset = 0x95, .value = 0x00, },
337 [32] = { .offset = 0x96, .value = 0x05, },
338 [33] = { .offset = 0x97, .value = 0x00, },
339 /* 98,99 are part of the mode-specific configuration */
340 [34] = { .offset = 0x9a, .value = 0x88, },
341 [35] = { .offset = 0x9b, .value = 0x00, },
342 /* 9c,9d are part of the mode-specific configuration */
343 [36] = { .offset = 0x9e, .value = 0x25, },
344 [37] = { .offset = 0x9f, .value = 0x03, },
345 [38] = { .offset = 0xa0, .value = 0x28, },
346 [39] = { .offset = 0xa1, .value = 0x01, },
347 [40] = { .offset = 0xa2, .value = 0x28, },
348 [41] = { .offset = 0xa3, .value = 0x05, },
349 /* register 0xa4 is mode specific, but 0x80..0x84 works always */
350 [42] = { .offset = 0xa4, .value = 0x84, },
351 [43] = { .offset = 0xa5, .value = 0x00, },
352 [44] = { .offset = 0xa6, .value = 0x00, },
353 [45] = { .offset = 0xa7, .value = 0x00, },
354 [46] = { .offset = 0xa8, .value = 0x00, },
355 /* 0xa9 to 0xab are mode specific, but have no visible effect */
356 [47] = { .offset = 0xa9, .value = 0x04, },
357 [48] = { .offset = 0xaa, .value = 0x70, },
358 [49] = { .offset = 0xab, .value = 0x4f, },
359 [50] = { .offset = 0xac, .value = 0x00, },
360 [51] = { .offset = 0xad, .value = 0x00, },
361 [52] = { .offset = 0xb6, .value = 0x09, },
362 [53] = { .offset = 0xb7, .value = 0x03, },
363 /* b8,b9 are part of the mode-specific configuration */
364 [54] = { .offset = 0xba, .value = 0x00, },
365 [55] = { .offset = 0xbb, .value = 0x20, },
366 [56] = { .offset = 0xf3, .value = 0x90, },
367 [57] = { .offset = 0xf4, .value = 0x00, },
368 [58] = { .offset = 0xf7, .value = 0x88, },
369 /* f8 is mode specific, but the value does not matter */
370 [59] = { .offset = 0xf8, .value = 0x0a, },
371 [60] = { .offset = 0xf9, .value = 0x00, }
372};
373
374static const struct ns2501_reg regs_init[] = {
375 [0] = { .offset = 0x35, .value = 0xff, },
376 [1] = { .offset = 0x34, .value = 0x00, },
377 [2] = { .offset = 0x08, .value = 0x30, },
378};
379
380struct ns2501_priv {
381 bool quiet;
382 const struct ns2501_configuration *conf;
383};
384
385#define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr))
386
387/*
388** Read a register from the ns2501.
389** Returns true if successful, false otherwise.
390** If it returns false, it might be wise to enable the
391** DVO with the above function.
392*/
393static bool ns2501_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
394{
395 struct ns2501_priv *ns = dvo->dev_priv;
396 struct i2c_adapter *adapter = dvo->i2c_bus;
397 u8 out_buf[2];
398 u8 in_buf[2];
399
400 struct i2c_msg msgs[] = {
401 {
402 .addr = dvo->target_addr,
403 .flags = 0,
404 .len = 1,
405 .buf = out_buf,
406 },
407 {
408 .addr = dvo->target_addr,
409 .flags = I2C_M_RD,
410 .len = 1,
411 .buf = in_buf,
412 }
413 };
414
415 out_buf[0] = addr;
416 out_buf[1] = 0;
417
418 if (i2c_transfer(adap: adapter, msgs, num: 2) == 2) {
419 *ch = in_buf[0];
420 return true;
421 }
422
423 if (!ns->quiet) {
424 DRM_DEBUG_KMS
425 ("Unable to read register 0x%02x from %s:0x%02x.\n", addr,
426 adapter->name, dvo->target_addr);
427 }
428
429 return false;
430}
431
432/*
433** Write a register to the ns2501.
434** Returns true if successful, false otherwise.
435** If it returns false, it might be wise to enable the
436** DVO with the above function.
437*/
438static bool ns2501_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
439{
440 struct ns2501_priv *ns = dvo->dev_priv;
441 struct i2c_adapter *adapter = dvo->i2c_bus;
442 u8 out_buf[2];
443
444 struct i2c_msg msg = {
445 .addr = dvo->target_addr,
446 .flags = 0,
447 .len = 2,
448 .buf = out_buf,
449 };
450
451 out_buf[0] = addr;
452 out_buf[1] = ch;
453
454 if (i2c_transfer(adap: adapter, msgs: &msg, num: 1) == 1) {
455 return true;
456 }
457
458 if (!ns->quiet) {
459 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d\n",
460 addr, adapter->name, dvo->target_addr);
461 }
462
463 return false;
464}
465
466/* National Semiconductor 2501 driver for chip on i2c bus
467 * scan for the chip on the bus.
468 * Hope the VBIOS initialized the PLL correctly so we can
469 * talk to it. If not, it will not be seen and not detected.
470 * Bummer!
471 */
472static bool ns2501_init(struct intel_dvo_device *dvo,
473 struct i2c_adapter *adapter)
474{
475 /* this will detect the NS2501 chip on the specified i2c bus */
476 struct ns2501_priv *ns;
477 unsigned char ch;
478
479 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
480 if (ns == NULL)
481 return false;
482
483 dvo->i2c_bus = adapter;
484 dvo->dev_priv = ns;
485 ns->quiet = true;
486
487 if (!ns2501_readb(dvo, NS2501_VID_LO, ch: &ch))
488 goto out;
489
490 if (ch != (NS2501_VID & 0xff)) {
491 DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Target %d.\n",
492 ch, adapter->name, dvo->target_addr);
493 goto out;
494 }
495
496 if (!ns2501_readb(dvo, NS2501_DID_LO, ch: &ch))
497 goto out;
498
499 if (ch != (NS2501_DID & 0xff)) {
500 DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Target %d.\n",
501 ch, adapter->name, dvo->target_addr);
502 goto out;
503 }
504 ns->quiet = false;
505
506 DRM_DEBUG_KMS("init ns2501 dvo controller successfully!\n");
507
508 return true;
509
510out:
511 kfree(objp: ns);
512 return false;
513}
514
515static enum drm_connector_status ns2501_detect(struct intel_dvo_device *dvo)
516{
517 /*
518 * This is a Laptop display, it doesn't have hotplugging.
519 * Even if not, the detection bit of the 2501 is unreliable as
520 * it only works for some display types.
521 * It is even more unreliable as the PLL must be active for
522 * allowing reading from the chip.
523 */
524 return connector_status_connected;
525}
526
527static enum drm_mode_status ns2501_mode_valid(struct intel_dvo_device *dvo,
528 const struct drm_display_mode *mode)
529{
530 DRM_DEBUG_KMS
531 ("is mode valid (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d)\n",
532 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal);
533
534 /*
535 * Currently, these are all the modes I have data from.
536 * More might exist. Unclear how to find the native resolution
537 * of the panel in here so we could always accept it
538 * by disabling the scaler.
539 */
540 if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) ||
541 (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) ||
542 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) {
543 return MODE_OK;
544 } else {
545 return MODE_ONE_SIZE; /* Is this a reasonable error? */
546 }
547}
548
549static void ns2501_mode_set(struct intel_dvo_device *dvo,
550 const struct drm_display_mode *mode,
551 const struct drm_display_mode *adjusted_mode)
552{
553 const struct ns2501_configuration *conf;
554 struct ns2501_priv *ns = dvo->dev_priv;
555 int mode_idx, i;
556
557 DRM_DEBUG_KMS
558 ("set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d).\n",
559 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal);
560
561 DRM_DEBUG_KMS("Detailed requested mode settings are:\n"
562 "clock : %d kHz\n"
563 "hdisplay : %d\n"
564 "hblank start : %d\n"
565 "hblank end : %d\n"
566 "hsync start : %d\n"
567 "hsync end : %d\n"
568 "htotal : %d\n"
569 "hskew : %d\n"
570 "vdisplay : %d\n"
571 "vblank start : %d\n"
572 "hblank end : %d\n"
573 "vsync start : %d\n"
574 "vsync end : %d\n"
575 "vtotal : %d\n",
576 adjusted_mode->crtc_clock,
577 adjusted_mode->crtc_hdisplay,
578 adjusted_mode->crtc_hblank_start,
579 adjusted_mode->crtc_hblank_end,
580 adjusted_mode->crtc_hsync_start,
581 adjusted_mode->crtc_hsync_end,
582 adjusted_mode->crtc_htotal,
583 adjusted_mode->crtc_hskew,
584 adjusted_mode->crtc_vdisplay,
585 adjusted_mode->crtc_vblank_start,
586 adjusted_mode->crtc_vblank_end,
587 adjusted_mode->crtc_vsync_start,
588 adjusted_mode->crtc_vsync_end,
589 adjusted_mode->crtc_vtotal);
590
591 if (mode->hdisplay == 640 && mode->vdisplay == 480)
592 mode_idx = MODE_640x480;
593 else if (mode->hdisplay == 800 && mode->vdisplay == 600)
594 mode_idx = MODE_800x600;
595 else if (mode->hdisplay == 1024 && mode->vdisplay == 768)
596 mode_idx = MODE_1024x768;
597 else
598 return;
599
600 /* Hopefully doing it every time won't hurt... */
601 for (i = 0; i < ARRAY_SIZE(regs_init); i++)
602 ns2501_writeb(dvo, addr: regs_init[i].offset, ch: regs_init[i].value);
603
604 /* Write the mode-agnostic values */
605 for (i = 0; i < ARRAY_SIZE(mode_agnostic_values); i++)
606 ns2501_writeb(dvo, addr: mode_agnostic_values[i].offset,
607 ch: mode_agnostic_values[i].value);
608
609 /* Write now the mode-specific configuration */
610 conf = ns2501_modes + mode_idx;
611 ns->conf = conf;
612
613 ns2501_writeb(dvo, NS2501_REG8, ch: conf->conf);
614 ns2501_writeb(dvo, NS2501_REG1B, ch: conf->pll_a);
615 ns2501_writeb(dvo, NS2501_REG1C, ch: conf->pll_b & 0xff);
616 ns2501_writeb(dvo, NS2501_REG1D, ch: conf->pll_b >> 8);
617 ns2501_writeb(dvo, NS2501_REGC1, ch: conf->hstart & 0xff);
618 ns2501_writeb(dvo, NS2501_REGC2, ch: conf->hstart >> 8);
619 ns2501_writeb(dvo, NS2501_REGC3, ch: conf->hstop & 0xff);
620 ns2501_writeb(dvo, NS2501_REGC4, ch: conf->hstop >> 8);
621 ns2501_writeb(dvo, NS2501_REGC5, ch: conf->vstart & 0xff);
622 ns2501_writeb(dvo, NS2501_REGC6, ch: conf->vstart >> 8);
623 ns2501_writeb(dvo, NS2501_REGC7, ch: conf->vstop & 0xff);
624 ns2501_writeb(dvo, NS2501_REGC8, ch: conf->vstop >> 8);
625 ns2501_writeb(dvo, NS2501_REG80, ch: conf->vsync & 0xff);
626 ns2501_writeb(dvo, NS2501_REG81, ch: conf->vsync >> 8);
627 ns2501_writeb(dvo, NS2501_REG82, ch: conf->vtotal & 0xff);
628 ns2501_writeb(dvo, NS2501_REG83, ch: conf->vtotal >> 8);
629 ns2501_writeb(dvo, NS2501_REG98, ch: conf->hpos & 0xff);
630 ns2501_writeb(dvo, NS2501_REG99, ch: conf->hpos >> 8);
631 ns2501_writeb(dvo, NS2501_REG8E, ch: conf->vpos & 0xff);
632 ns2501_writeb(dvo, NS2501_REG8F, ch: conf->vpos >> 8);
633 ns2501_writeb(dvo, NS2501_REG9C, ch: conf->voffs & 0xff);
634 ns2501_writeb(dvo, NS2501_REG9D, ch: conf->voffs >> 8);
635 ns2501_writeb(dvo, NS2501_REGB8, ch: conf->hscale & 0xff);
636 ns2501_writeb(dvo, NS2501_REGB9, ch: conf->hscale >> 8);
637 ns2501_writeb(dvo, NS2501_REG10, ch: conf->vscale & 0xff);
638 ns2501_writeb(dvo, NS2501_REG11, ch: conf->vscale >> 8);
639 ns2501_writeb(dvo, NS2501_REGF9, ch: conf->dither);
640 ns2501_writeb(dvo, NS2501_REG41, ch: conf->syncb);
641 ns2501_writeb(dvo, NS2501_REGC0, ch: conf->sync);
642}
643
644/* set the NS2501 power state */
645static bool ns2501_get_hw_state(struct intel_dvo_device *dvo)
646{
647 unsigned char ch;
648
649 if (!ns2501_readb(dvo, NS2501_REG8, ch: &ch))
650 return false;
651
652 return ch & NS2501_8_PD;
653}
654
655/* set the NS2501 power state */
656static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
657{
658 struct ns2501_priv *ns = dvo->dev_priv;
659
660 DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable);
661
662 if (enable) {
663 ns2501_writeb(dvo, NS2501_REGC0, ch: ns->conf->sync | 0x08);
664
665 ns2501_writeb(dvo, NS2501_REG41, ch: ns->conf->syncb);
666
667 ns2501_writeb(dvo, NS2501_REG34, NS2501_34_ENABLE_OUTPUT);
668 msleep(msecs: 15);
669
670 ns2501_writeb(dvo, NS2501_REG8,
671 ch: ns->conf->conf | NS2501_8_BPAS);
672 if (!(ns->conf->conf & NS2501_8_BPAS))
673 ns2501_writeb(dvo, NS2501_REG8, ch: ns->conf->conf);
674 msleep(msecs: 200);
675
676 ns2501_writeb(dvo, NS2501_REG34,
677 NS2501_34_ENABLE_OUTPUT | NS2501_34_ENABLE_BACKLIGHT);
678
679 ns2501_writeb(dvo, NS2501_REGC0, ch: ns->conf->sync);
680 } else {
681 ns2501_writeb(dvo, NS2501_REG34, NS2501_34_ENABLE_OUTPUT);
682 msleep(msecs: 200);
683
684 ns2501_writeb(dvo, NS2501_REG8, NS2501_8_VEN | NS2501_8_HEN |
685 NS2501_8_BPAS);
686 msleep(msecs: 15);
687
688 ns2501_writeb(dvo, NS2501_REG34, ch: 0x00);
689 }
690}
691
692static void ns2501_destroy(struct intel_dvo_device *dvo)
693{
694 struct ns2501_priv *ns = dvo->dev_priv;
695
696 if (ns) {
697 kfree(objp: ns);
698 dvo->dev_priv = NULL;
699 }
700}
701
702const struct intel_dvo_dev_ops ns2501_ops = {
703 .init = ns2501_init,
704 .detect = ns2501_detect,
705 .mode_valid = ns2501_mode_valid,
706 .mode_set = ns2501_mode_set,
707 .dpms = ns2501_dpms,
708 .get_hw_state = ns2501_get_hw_state,
709 .destroy = ns2501_destroy,
710};
711

source code of linux/drivers/gpu/drm/i915/display/dvo_ns2501.c