| 1 | #ifndef STATE_HI_XML |
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| 2 | #define STATE_HI_XML |
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| 3 | |
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| 4 | /* Autogenerated file, DO NOT EDIT manually! |
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| 5 | |
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| 6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
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| 7 | http://0x04.net/cgit/index.cgi/rules-ng-ng |
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| 8 | git clone git://0x04.net/rules-ng-ng |
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| 9 | |
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| 10 | The rules-ng-ng source files this header was generated from are: |
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| 11 | - state.xml ( 30729 bytes, from 2024-06-21 11:31:54) |
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| 12 | - common.xml ( 35664 bytes, from 2023-12-13 09:33:18) |
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| 13 | - common_3d.xml ( 15069 bytes, from 2023-12-13 09:33:18) |
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| 14 | - state_hi.xml ( 35909 bytes, from 2024-06-21 11:31:54) |
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| 15 | - copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03) |
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| 16 | - state_2d.xml ( 52271 bytes, from 2023-05-30 20:50:02) |
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| 17 | - state_3d.xml ( 89626 bytes, from 2024-06-21 11:32:57) |
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| 18 | - state_blt.xml ( 14592 bytes, from 2023-12-13 09:33:18) |
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| 19 | - state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03) |
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| 20 | |
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| 21 | Copyright (C) 2012-2024 by the following authors: |
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| 22 | - Wladimir J. van der Laan <laanwj@gmail.com> |
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| 23 | - Christian Gmeiner <christian.gmeiner@gmail.com> |
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| 24 | - Lucas Stach <l.stach@pengutronix.de> |
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| 25 | - Russell King <rmk@arm.linux.org.uk> |
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| 26 | |
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| 27 | Permission is hereby granted, free of charge, to any person obtaining a |
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| 28 | copy of this software and associated documentation files (the "Software"), |
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| 29 | to deal in the Software without restriction, including without limitation |
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| 30 | the rights to use, copy, modify, merge, publish, distribute, sub license, |
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| 31 | and/or sell copies of the Software, and to permit persons to whom the |
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| 32 | Software is furnished to do so, subject to the following conditions: |
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| 33 | |
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| 34 | The above copyright notice and this permission notice (including the |
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| 35 | next paragraph) shall be included in all copies or substantial portions |
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| 36 | of the Software. |
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| 37 | |
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| 38 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 39 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 40 | FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 41 | THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 42 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 43 | FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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| 44 | DEALINGS IN THE SOFTWARE. |
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| 45 | */ |
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| 46 | |
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| 47 | |
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| 48 | #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001 |
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| 49 | #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002 |
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| 50 | #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003 |
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| 51 | #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004 |
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| 52 | #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005 |
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| 53 | #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006 |
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| 54 | #define VIVS_HI 0x00000000 |
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| 55 | |
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| 56 | #define VIVS_HI_CLOCK_CONTROL 0x00000000 |
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| 57 | #define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS 0x00000001 |
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| 58 | #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS 0x00000002 |
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| 59 | #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK 0x000001fc |
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| 60 | #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT 2 |
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| 61 | #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x) (((x) << VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT) & VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK) |
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| 62 | #define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD 0x00000200 |
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| 63 | #define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING 0x00000400 |
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| 64 | #define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS 0x00000800 |
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| 65 | #define VIVS_HI_CLOCK_CONTROL_SOFT_RESET 0x00001000 |
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| 66 | #define VIVS_HI_CLOCK_CONTROL_IDLE_3D 0x00010000 |
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| 67 | #define VIVS_HI_CLOCK_CONTROL_IDLE_2D 0x00020000 |
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| 68 | #define VIVS_HI_CLOCK_CONTROL_IDLE_VG 0x00040000 |
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| 69 | #define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU 0x00080000 |
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| 70 | #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK 0x00f00000 |
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| 71 | #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT 20 |
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| 72 | #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(x) (((x) << VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT) & VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK) |
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| 73 | |
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| 74 | #define VIVS_HI_IDLE_STATE 0x00000004 |
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| 75 | #define VIVS_HI_IDLE_STATE_FE 0x00000001 |
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| 76 | #define VIVS_HI_IDLE_STATE_DE 0x00000002 |
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| 77 | #define VIVS_HI_IDLE_STATE_PE 0x00000004 |
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| 78 | #define VIVS_HI_IDLE_STATE_SH 0x00000008 |
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| 79 | #define VIVS_HI_IDLE_STATE_PA 0x00000010 |
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| 80 | #define VIVS_HI_IDLE_STATE_SE 0x00000020 |
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| 81 | #define VIVS_HI_IDLE_STATE_RA 0x00000040 |
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| 82 | #define VIVS_HI_IDLE_STATE_TX 0x00000080 |
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| 83 | #define VIVS_HI_IDLE_STATE_VG 0x00000100 |
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| 84 | #define VIVS_HI_IDLE_STATE_IM 0x00000200 |
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| 85 | #define VIVS_HI_IDLE_STATE_FP 0x00000400 |
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| 86 | #define VIVS_HI_IDLE_STATE_TS 0x00000800 |
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| 87 | #define VIVS_HI_IDLE_STATE_BL 0x00001000 |
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| 88 | #define VIVS_HI_IDLE_STATE_ASYNCFE 0x00002000 |
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| 89 | #define VIVS_HI_IDLE_STATE_MC 0x00004000 |
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| 90 | #define VIVS_HI_IDLE_STATE_PPA 0x00008000 |
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| 91 | #define VIVS_HI_IDLE_STATE_WD 0x00010000 |
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| 92 | #define VIVS_HI_IDLE_STATE_NN 0x00020000 |
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| 93 | #define VIVS_HI_IDLE_STATE_TP 0x00040000 |
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| 94 | #define VIVS_HI_IDLE_STATE_AXI_LP 0x80000000 |
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| 95 | |
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| 96 | #define VIVS_HI_AXI_CONFIG 0x00000008 |
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| 97 | #define VIVS_HI_AXI_CONFIG_AWID__MASK 0x0000000f |
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| 98 | #define VIVS_HI_AXI_CONFIG_AWID__SHIFT 0 |
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| 99 | #define VIVS_HI_AXI_CONFIG_AWID(x) (((x) << VIVS_HI_AXI_CONFIG_AWID__SHIFT) & VIVS_HI_AXI_CONFIG_AWID__MASK) |
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| 100 | #define VIVS_HI_AXI_CONFIG_ARID__MASK 0x000000f0 |
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| 101 | #define VIVS_HI_AXI_CONFIG_ARID__SHIFT 4 |
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| 102 | #define VIVS_HI_AXI_CONFIG_ARID(x) (((x) << VIVS_HI_AXI_CONFIG_ARID__SHIFT) & VIVS_HI_AXI_CONFIG_ARID__MASK) |
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| 103 | #define VIVS_HI_AXI_CONFIG_AWCACHE__MASK 0x00000f00 |
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| 104 | #define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT 8 |
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| 105 | #define VIVS_HI_AXI_CONFIG_AWCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_AWCACHE__MASK) |
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| 106 | #define VIVS_HI_AXI_CONFIG_ARCACHE__MASK 0x0000f000 |
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| 107 | #define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT 12 |
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| 108 | #define VIVS_HI_AXI_CONFIG_ARCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_ARCACHE__MASK) |
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| 109 | |
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| 110 | #define VIVS_HI_AXI_STATUS 0x0000000c |
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| 111 | #define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK 0x0000000f |
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| 112 | #define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT 0 |
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| 113 | #define VIVS_HI_AXI_STATUS_WR_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK) |
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| 114 | #define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK 0x000000f0 |
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| 115 | #define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT 4 |
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| 116 | #define VIVS_HI_AXI_STATUS_RD_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK) |
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| 117 | #define VIVS_HI_AXI_STATUS_DET_WR_ERR 0x00000100 |
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| 118 | #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200 |
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| 119 | |
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| 120 | #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010 |
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| 121 | #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff |
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| 122 | #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0 |
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| 123 | #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK) |
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| 124 | #define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000 |
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| 125 | #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000 |
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| 126 | |
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| 127 | #define VIVS_HI_INTR_ENBL 0x00000014 |
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| 128 | #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK 0xffffffff |
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| 129 | #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT 0 |
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| 130 | #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x) (((x) << VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT) & VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK) |
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| 131 | |
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| 132 | #define VIVS_HI_CHIP_IDENTITY 0x00000018 |
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| 133 | #define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK 0xff000000 |
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| 134 | #define VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT 24 |
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| 135 | #define VIVS_HI_CHIP_IDENTITY_FAMILY(x) (((x) << VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK) |
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| 136 | #define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK 0x00ff0000 |
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| 137 | #define VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT 16 |
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| 138 | #define VIVS_HI_CHIP_IDENTITY_PRODUCT(x) (((x) << VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT) & VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK) |
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| 139 | #define VIVS_HI_CHIP_IDENTITY_REVISION__MASK 0x0000f000 |
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| 140 | #define VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT 12 |
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| 141 | #define VIVS_HI_CHIP_IDENTITY_REVISION(x) (((x) << VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT) & VIVS_HI_CHIP_IDENTITY_REVISION__MASK) |
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| 142 | |
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| 143 | #define VIVS_HI_CHIP_FEATURE 0x0000001c |
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| 144 | |
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| 145 | #define VIVS_HI_CHIP_MODEL 0x00000020 |
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| 146 | |
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| 147 | #define VIVS_HI_CHIP_REV 0x00000024 |
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| 148 | |
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| 149 | #define VIVS_HI_CHIP_DATE 0x00000028 |
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| 150 | |
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| 151 | #define VIVS_HI_CHIP_TIME 0x0000002c |
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| 152 | |
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| 153 | #define VIVS_HI_CHIP_CUSTOMER_ID 0x00000030 |
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| 154 | |
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| 155 | #define VIVS_HI_CHIP_MINOR_FEATURE_0 0x00000034 |
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| 156 | |
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| 157 | #define VIVS_HI_CACHE_CONTROL 0x00000038 |
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| 158 | |
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| 159 | #define VIVS_HI_MEMORY_COUNTER_RESET 0x0000003c |
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| 160 | |
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| 161 | #define VIVS_HI_PROFILE_READ_BYTES8 0x00000040 |
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| 162 | |
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| 163 | #define VIVS_HI_PROFILE_WRITE_BYTES8 0x00000044 |
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| 164 | |
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| 165 | #define VIVS_HI_CHIP_SPECS 0x00000048 |
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| 166 | #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK 0x0000000f |
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| 167 | #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT 0 |
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| 168 | #define VIVS_HI_CHIP_SPECS_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK) |
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| 169 | #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK 0x000000f0 |
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| 170 | #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT 4 |
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| 171 | #define VIVS_HI_CHIP_SPECS_REGISTER_MAX(x) (((x) << VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT) & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK) |
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| 172 | #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK 0x00000f00 |
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| 173 | #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT 8 |
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| 174 | #define VIVS_HI_CHIP_SPECS_THREAD_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK) |
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| 175 | #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK 0x0001f000 |
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| 176 | #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT 12 |
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| 177 | #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK) |
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| 178 | #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK 0x01f00000 |
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| 179 | #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT 20 |
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| 180 | #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK) |
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| 181 | #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK 0x0e000000 |
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| 182 | #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT 25 |
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| 183 | #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES(x) (((x) << VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT) & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK) |
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| 184 | #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK 0xf0000000 |
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| 185 | #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT 28 |
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| 186 | #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK) |
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| 187 | |
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| 188 | #define VIVS_HI_PROFILE_WRITE_BURSTS 0x0000004c |
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| 189 | |
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| 190 | #define VIVS_HI_PROFILE_WRITE_REQUESTS 0x00000050 |
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| 191 | |
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| 192 | #define VIVS_HI_PROFILE_READ_BURSTS 0x00000058 |
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| 193 | |
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| 194 | #define VIVS_HI_PROFILE_READ_REQUESTS 0x0000005c |
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| 195 | |
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| 196 | #define VIVS_HI_PROFILE_READ_LASTS 0x00000060 |
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| 197 | |
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| 198 | #define VIVS_HI_GP_OUT0 0x00000064 |
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| 199 | |
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| 200 | #define VIVS_HI_GP_OUT1 0x00000068 |
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| 201 | |
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| 202 | #define VIVS_HI_GP_OUT2 0x0000006c |
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| 203 | |
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| 204 | #define VIVS_HI_AXI_CONTROL 0x00000070 |
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| 205 | #define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE 0x00000001 |
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| 206 | |
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| 207 | #define VIVS_HI_CHIP_MINOR_FEATURE_1 0x00000074 |
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| 208 | |
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| 209 | #define VIVS_HI_PROFILE_TOTAL_CYCLES 0x00000078 |
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| 210 | |
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| 211 | #define VIVS_HI_PROFILE_IDLE_CYCLES 0x0000007c |
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| 212 | |
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| 213 | #define VIVS_HI_CHIP_SPECS_2 0x00000080 |
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| 214 | #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK 0x000000ff |
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| 215 | #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT 0 |
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| 216 | #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK) |
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| 217 | #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK 0x0000ff00 |
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| 218 | #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT 8 |
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| 219 | #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK) |
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| 220 | #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK 0xffff0000 |
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| 221 | #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT 16 |
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| 222 | #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS(x) (((x) << VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT) & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK) |
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| 223 | |
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| 224 | #define VIVS_HI_CHIP_MINOR_FEATURE_2 0x00000084 |
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| 225 | |
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| 226 | #define VIVS_HI_CHIP_MINOR_FEATURE_3 0x00000088 |
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| 227 | |
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| 228 | #define VIVS_HI_CHIP_SPECS_3 0x0000008c |
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| 229 | #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK 0x000001f0 |
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| 230 | #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT 4 |
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| 231 | #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK) |
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| 232 | #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK 0x00000007 |
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| 233 | #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0 |
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| 234 | #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK) |
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| 235 | |
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| 236 | #define VIVS_HI_COMPRESSION_FLAGS 0x00000090 |
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| 237 | #define VIVS_HI_COMPRESSION_FLAGS_DEC300 0x00000040 |
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| 238 | |
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| 239 | #define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094 |
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| 240 | |
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| 241 | #define VIVS_HI_CHIP_SPECS_4 0x0000009c |
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| 242 | #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK 0x0001f000 |
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| 243 | #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT 12 |
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| 244 | #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK) |
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| 245 | |
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| 246 | #define VIVS_HI_CHIP_MINOR_FEATURE_5 0x000000a0 |
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| 247 | |
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| 248 | #define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8 |
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| 249 | |
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| 250 | #define VIVS_HI_BLT_INTR 0x000000d4 |
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| 251 | |
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| 252 | #define VIVS_HI_CHIP_ECO_ID 0x000000e8 |
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| 253 | |
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| 254 | #define VIVS_HI_AUXBIT 0x000000ec |
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| 255 | |
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| 256 | #define VIVS_PM 0x00000000 |
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| 257 | |
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| 258 | #define VIVS_PM_POWER_CONTROLS 0x00000100 |
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| 259 | #define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING 0x00000001 |
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| 260 | #define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING 0x00000002 |
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| 261 | #define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING 0x00000004 |
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| 262 | #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK 0x000000f0 |
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| 263 | #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT 4 |
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| 264 | #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK) |
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| 265 | #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK 0xffff0000 |
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| 266 | #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT 16 |
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| 267 | #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK) |
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| 268 | |
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| 269 | #define VIVS_PM_MODULE_CONTROLS 0x00000104 |
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| 270 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE 0x00000001 |
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| 271 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE 0x00000002 |
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| 272 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE 0x00000004 |
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| 273 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH 0x00000008 |
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| 274 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA 0x00000010 |
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| 275 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020 |
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| 276 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040 |
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| 277 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080 |
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| 278 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU 0x00000400 |
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| 279 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000 |
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| 280 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000 |
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| 281 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_NN 0x00400000 |
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| 282 | |
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| 283 | #define VIVS_PM_MODULE_STATUS 0x00000108 |
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| 284 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001 |
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| 285 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE 0x00000002 |
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| 286 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE 0x00000004 |
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| 287 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH 0x00000008 |
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| 288 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA 0x00000010 |
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| 289 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE 0x00000020 |
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| 290 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA 0x00000040 |
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| 291 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080 |
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| 292 | |
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| 293 | #define VIVS_PM_PULSE_EATER 0x0000010c |
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| 294 | #define VIVS_PM_PULSE_EATER_DISABLE 0x00000001 |
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| 295 | #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK 0x0000ff00 |
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| 296 | #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT 8 |
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| 297 | #define VIVS_PM_PULSE_EATER_DVFS_PERIOD(x) (((x) << VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT) & VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK) |
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| 298 | #define VIVS_PM_PULSE_EATER_UNK16 0x00010000 |
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| 299 | #define VIVS_PM_PULSE_EATER_UNK17 0x00020000 |
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| 300 | #define VIVS_PM_PULSE_EATER_INTERNAL_DFS 0x00040000 |
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| 301 | #define VIVS_PM_PULSE_EATER_UNK19 0x00080000 |
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| 302 | #define VIVS_PM_PULSE_EATER_UNK20 0x00100000 |
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| 303 | #define VIVS_PM_PULSE_EATER_UNK22 0x00400000 |
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| 304 | #define VIVS_PM_PULSE_EATER_UNK23 0x00800000 |
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| 305 | |
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| 306 | #define VIVS_MMUv2 0x00000000 |
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| 307 | |
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| 308 | #define VIVS_MMUv2_SAFE_ADDRESS 0x00000180 |
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| 309 | |
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| 310 | #define VIVS_MMUv2_CONFIGURATION 0x00000184 |
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| 311 | #define VIVS_MMUv2_CONFIGURATION_MODE__MASK 0x00000001 |
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| 312 | #define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT 0 |
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| 313 | #define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K 0x00000000 |
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| 314 | #define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K 0x00000001 |
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| 315 | #define VIVS_MMUv2_CONFIGURATION_MODE_MASK 0x00000008 |
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| 316 | #define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK 0x00000010 |
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| 317 | #define VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT 4 |
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| 318 | #define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH 0x00000010 |
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| 319 | #define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK 0x00000080 |
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| 320 | #define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK 0x00000100 |
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| 321 | #define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK 0xfffffc00 |
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| 322 | #define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT 10 |
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| 323 | #define VIVS_MMUv2_CONFIGURATION_ADDRESS(x) (((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK) |
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| 324 | |
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| 325 | #define VIVS_MMUv2_STATUS 0x00000188 |
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| 326 | #define VIVS_MMUv2_STATUS_EXCEPTION0__MASK 0x0000000f |
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| 327 | #define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT 0 |
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| 328 | #define VIVS_MMUv2_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK) |
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| 329 | #define VIVS_MMUv2_STATUS_EXCEPTION1__MASK 0x000000f0 |
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| 330 | #define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT 4 |
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| 331 | #define VIVS_MMUv2_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK) |
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| 332 | #define VIVS_MMUv2_STATUS_EXCEPTION2__MASK 0x00000f00 |
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| 333 | #define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT 8 |
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| 334 | #define VIVS_MMUv2_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK) |
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| 335 | #define VIVS_MMUv2_STATUS_EXCEPTION3__MASK 0x0000f000 |
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| 336 | #define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT 12 |
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| 337 | #define VIVS_MMUv2_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK) |
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| 338 | |
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| 339 | #define VIVS_MMUv2_CONTROL 0x0000018c |
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| 340 | #define VIVS_MMUv2_CONTROL_ENABLE 0x00000001 |
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| 341 | |
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| 342 | #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0)) |
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| 343 | #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004 |
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| 344 | #define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004 |
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| 345 | |
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| 346 | #define VIVS_MMUv2_PROFILE_BLT_READ 0x000001a4 |
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| 347 | |
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| 348 | #define VIVS_MMUv2_PTA_CONFIG 0x000001ac |
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| 349 | #define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK 0x0000ffff |
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| 350 | #define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT 0 |
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| 351 | #define VIVS_MMUv2_PTA_CONFIG_INDEX(x) (((x) << VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT) & VIVS_MMUv2_PTA_CONFIG_INDEX__MASK) |
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| 352 | #define VIVS_MMUv2_PTA_CONFIG_UNK16 0x00010000 |
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| 353 | |
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| 354 | #define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0)) |
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| 355 | #define VIVS_MMUv2_AXI_POLICY__ESIZE 0x00000004 |
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| 356 | #define VIVS_MMUv2_AXI_POLICY__LEN 0x00000008 |
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| 357 | |
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| 358 | #define VIVS_MMUv2_SEC_EXCEPTION_ADDR 0x00000380 |
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| 359 | |
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| 360 | #define VIVS_MMUv2_SEC_STATUS 0x00000384 |
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| 361 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK 0x00000003 |
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| 362 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT 0 |
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| 363 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK) |
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| 364 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK 0x00000030 |
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| 365 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT 4 |
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| 366 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK) |
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| 367 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK 0x00000300 |
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| 368 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT 8 |
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| 369 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK) |
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| 370 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK 0x00003000 |
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| 371 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT 12 |
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| 372 | #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK) |
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| 373 | |
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| 374 | #define VIVS_MMUv2_SEC_CONTROL 0x00000388 |
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| 375 | #define VIVS_MMUv2_SEC_CONTROL_ENABLE 0x00000001 |
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| 376 | |
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| 377 | #define VIVS_MMUv2_PTA_ADDRESS_LOW 0x0000038c |
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| 378 | |
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| 379 | #define VIVS_MMUv2_PTA_ADDRESS_HIGH 0x00000390 |
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| 380 | |
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| 381 | #define VIVS_MMUv2_PTA_CONTROL 0x00000394 |
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| 382 | #define VIVS_MMUv2_PTA_CONTROL_ENABLE 0x00000001 |
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| 383 | |
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| 384 | #define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW 0x00000398 |
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| 385 | |
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| 386 | #define VIVS_MMUv2_SEC_SAFE_ADDR_LOW 0x0000039c |
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| 387 | |
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| 388 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG 0x000003a0 |
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| 389 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK 0x000000ff |
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| 390 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT 0 |
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| 391 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK) |
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| 392 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15 0x00008000 |
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| 393 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK 0x00ff0000 |
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| 394 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT 16 |
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| 395 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK) |
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| 396 | #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31 0x80000000 |
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| 397 | |
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| 398 | #define VIVS_MMUv2_SEC_COMMAND_CONTROL 0x000003a4 |
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| 399 | #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff |
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| 400 | #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT 0 |
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| 401 | #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK) |
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| 402 | #define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE 0x00010000 |
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| 403 | |
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| 404 | #define VIVS_MMUv2_AHB_CONTROL 0x000003a8 |
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| 405 | #define VIVS_MMUv2_AHB_CONTROL_RESET 0x00000001 |
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| 406 | #define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS 0x00000002 |
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| 407 | |
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| 408 | #define VIVS_MC 0x00000000 |
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| 409 | |
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| 410 | #define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400 |
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| 411 | |
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| 412 | #define VIVS_MC_MMU_TX_PAGE_TABLE 0x00000404 |
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| 413 | |
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| 414 | #define VIVS_MC_MMU_PE_PAGE_TABLE 0x00000408 |
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| 415 | |
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| 416 | #define VIVS_MC_MMU_PEZ_PAGE_TABLE 0x0000040c |
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| 417 | |
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| 418 | #define VIVS_MC_MMU_RA_PAGE_TABLE 0x00000410 |
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| 419 | |
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| 420 | #define VIVS_MC_DEBUG_MEMORY 0x00000414 |
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| 421 | #define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320 0x00000008 |
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| 422 | #define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS 0x00100000 |
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| 423 | #define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS 0x00200000 |
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| 424 | |
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| 425 | #define VIVS_MC_MEMORY_BASE_ADDR_RA 0x00000418 |
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| 426 | |
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| 427 | #define VIVS_MC_MEMORY_BASE_ADDR_FE 0x0000041c |
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| 428 | |
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| 429 | #define VIVS_MC_MEMORY_BASE_ADDR_TX 0x00000420 |
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| 430 | |
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| 431 | #define VIVS_MC_MEMORY_BASE_ADDR_PEZ 0x00000424 |
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| 432 | |
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| 433 | #define VIVS_MC_MEMORY_BASE_ADDR_PE 0x00000428 |
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| 434 | |
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| 435 | #define VIVS_MC_MEMORY_TIMING_CONTROL 0x0000042c |
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| 436 | |
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| 437 | #define VIVS_MC_MEMORY_FLUSH 0x00000430 |
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| 438 | |
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| 439 | #define VIVS_MC_PROFILE_CYCLE_COUNTER 0x00000438 |
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| 440 | |
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| 441 | #define VIVS_MC_DEBUG_READ0 0x0000043c |
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| 442 | |
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| 443 | #define VIVS_MC_DEBUG_READ1 0x00000440 |
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| 444 | |
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| 445 | #define VIVS_MC_DEBUG_WRITE 0x00000444 |
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| 446 | |
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| 447 | #define VIVS_MC_PROFILE_RA_READ 0x00000448 |
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| 448 | |
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| 449 | #define VIVS_MC_PROFILE_TX_READ 0x0000044c |
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| 450 | |
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| 451 | #define VIVS_MC_PROFILE_FE_READ 0x00000450 |
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| 452 | |
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| 453 | #define VIVS_MC_PROFILE_PE_READ 0x00000454 |
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| 454 | |
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| 455 | #define VIVS_MC_PROFILE_DE_READ 0x00000458 |
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| 456 | |
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| 457 | #define VIVS_MC_PROFILE_SH_READ 0x0000045c |
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| 458 | |
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| 459 | #define VIVS_MC_PROFILE_PA_READ 0x00000460 |
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| 460 | |
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| 461 | #define VIVS_MC_PROFILE_SE_READ 0x00000464 |
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| 462 | |
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| 463 | #define VIVS_MC_PROFILE_MC_READ 0x00000468 |
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| 464 | |
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| 465 | #define VIVS_MC_PROFILE_HI_READ 0x0000046c |
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| 466 | |
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| 467 | #define VIVS_MC_PROFILE_CONFIG0 0x00000470 |
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| 468 | #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x000000ff |
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| 469 | #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0 |
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| 470 | #define VIVS_MC_PROFILE_CONFIG0_FE_CURRENT_PRIM 0x00000009 |
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| 471 | #define VIVS_MC_PROFILE_CONFIG0_FE_DRAW_COUNT 0x0000000a |
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| 472 | #define VIVS_MC_PROFILE_CONFIG0_FE_OUT_VERTEX_COUNT 0x0000000b |
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| 473 | #define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_MISS_COUNT 0x0000000c |
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| 474 | #define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f |
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| 475 | #define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_LK_COUNT 0x00000010 |
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| 476 | #define VIVS_MC_PROFILE_CONFIG0_FE_STALL_COUNT 0x00000011 |
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| 477 | #define VIVS_MC_PROFILE_CONFIG0_FE_PROCESS_COUNT 0x00000012 |
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| 478 | #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x0000ff00 |
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| 479 | #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8 |
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| 480 | #define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00 |
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| 481 | #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x00ff0000 |
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| 482 | #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT 16 |
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| 483 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000 |
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| 484 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000 |
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| 485 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE 0x00020000 |
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| 486 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000 |
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| 487 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000 |
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| 488 | #define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000 |
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| 489 | #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0xff000000 |
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| 490 | #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT 24 |
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| 491 | #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000 |
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| 492 | #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000 |
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| 493 | #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER 0x08000000 |
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| 494 | #define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER 0x09000000 |
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| 495 | #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER 0x0a000000 |
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| 496 | #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER 0x0b000000 |
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| 497 | #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER 0x0c000000 |
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| 498 | #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER 0x0d000000 |
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| 499 | #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER 0x0e000000 |
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| 500 | #define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000 |
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| 501 | |
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| 502 | #define VIVS_MC_PROFILE_CONFIG1 0x00000474 |
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| 503 | #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x000000ff |
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| 504 | #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0 |
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| 505 | #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003 |
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| 506 | #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004 |
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| 507 | #define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER 0x00000005 |
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| 508 | #define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER 0x00000006 |
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| 509 | #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007 |
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| 510 | #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008 |
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| 511 | #define VIVS_MC_PROFILE_CONFIG1_PA_DROPED_PRIM_COUNTER 0x00000009 |
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| 512 | #define VIVS_MC_PROFILE_CONFIG1_PA_FRUSTUM_CLIPPED_PRIM_COUNTER 0x0000000a |
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| 513 | #define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f |
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| 514 | #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x0000ff00 |
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| 515 | #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8 |
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| 516 | #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000 |
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| 517 | #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100 |
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| 518 | #define VIVS_MC_PROFILE_CONFIG1_SE_TRIVIAL_REJECTED_LINE_COUNT 0x00000400 |
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| 519 | #define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00 |
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| 520 | #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x00ff0000 |
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| 521 | #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16 |
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| 522 | #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000 |
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| 523 | #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000 |
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| 524 | #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z 0x00020000 |
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| 525 | #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT 0x00030000 |
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| 526 | #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER 0x00090000 |
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| 527 | #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000 |
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| 528 | #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000 |
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| 529 | #define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000 |
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| 530 | #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_HZ_CACHE_MISS_COUNTER 0x00110000 |
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| 531 | #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_HZ_CACHE_MISS_COUNTER 0x00120000 |
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| 532 | #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0xff000000 |
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| 533 | #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24 |
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| 534 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000 |
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| 535 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000 |
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| 536 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS 0x02000000 |
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| 537 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS 0x03000000 |
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| 538 | #define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN 0x04000000 |
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| 539 | #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT 0x05000000 |
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| 540 | #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT 0x06000000 |
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| 541 | #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT 0x07000000 |
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| 542 | #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT 0x08000000 |
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| 543 | #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT 0x09000000 |
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| 544 | #define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000 |
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| 545 | |
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| 546 | #define VIVS_MC_PROFILE_CONFIG2 0x00000478 |
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| 547 | #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x000000ff |
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| 548 | #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0 |
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| 549 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001 |
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| 550 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002 |
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| 551 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003 |
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| 552 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_COLORPIPE 0x00000004 |
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| 553 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_COLORPIPE 0x00000005 |
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| 554 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_DEPTHPIPE 0x00000007 |
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| 555 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_SENTOUT_FROM_DEPTHPIPE 0x00000008 |
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| 556 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_DEPTHPIPE 0x00000009 |
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| 557 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_DEPTHPIPE 0x0000000a |
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| 558 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_DEPTHPIPE 0x0000000b |
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| 559 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_OTHERS 0x0000000c |
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| 560 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_OTHERS 0x0000000d |
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| 561 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_FROM_OTHERS 0x0000000e |
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| 562 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_OTHERS 0x0000000f |
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| 563 | #define VIVS_MC_PROFILE_CONFIG2_MC_FE_READ_BANDWIDTH 0x00000015 |
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| 564 | #define VIVS_MC_PROFILE_CONFIG2_MC_MMU_READ_BANDWIDTH 0x00000016 |
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| 565 | #define VIVS_MC_PROFILE_CONFIG2_MC_BLT_READ_BANDWIDTH 0x00000017 |
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| 566 | #define VIVS_MC_PROFILE_CONFIG2_MC_SH0_READ_BANDWIDTH 0x00000018 |
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| 567 | #define VIVS_MC_PROFILE_CONFIG2_MC_SH1_READ_BANDWIDTH 0x00000019 |
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| 568 | #define VIVS_MC_PROFILE_CONFIG2_MC_PE_WRITE_BANDWIDTH 0x0000001a |
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| 569 | #define VIVS_MC_PROFILE_CONFIG2_MC_BLT_WRITE_BANDWIDTH 0x0000001b |
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| 570 | #define VIVS_MC_PROFILE_CONFIG2_MC_SH0_WRITE_BANDWIDTH 0x0000001c |
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| 571 | #define VIVS_MC_PROFILE_CONFIG2_MC_SH1_WRITE_BANDWIDTH 0x0000001d |
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| 572 | #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x0000ff00 |
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| 573 | #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8 |
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| 574 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000 |
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| 575 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100 |
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| 576 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200 |
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| 577 | #define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00 |
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| 578 | #define VIVS_MC_PROFILE_CONFIG2_L2__MASK 0x00ff0000 |
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| 579 | #define VIVS_MC_PROFILE_CONFIG2_L2__SHIFT 16 |
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| 580 | #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_READ_REQUEST_COUNT 0x00000000 |
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| 581 | #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_WRITE_REQUEST_COUNT 0x00040000 |
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| 582 | #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI1_WRITE_REQUEST_COUNT 0x00050000 |
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| 583 | #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI0 0x00080000 |
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| 584 | #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI1 0x00090000 |
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| 585 | #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI0 0x000c0000 |
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| 586 | #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI1 0x000d0000 |
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| 587 | #define VIVS_MC_PROFILE_CONFIG2_L2_RESET 0x000f0000 |
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| 588 | #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_MINMAX_LATENCY 0x00100000 |
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| 589 | #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_LATENCY 0x00110000 |
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| 590 | #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_REQUEST_COUNT 0x00120000 |
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| 591 | #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_MINMAX_LATENCY 0x00130000 |
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| 592 | #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_LATENCY 0x00140000 |
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| 593 | #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_REQUEST_COUNT 0x00150000 |
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| 594 | #define VIVS_MC_PROFILE_CONFIG2_BLT__MASK 0xff000000 |
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| 595 | #define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT 24 |
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| 596 | #define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 0x00000000 |
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| 597 | |
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| 598 | #define VIVS_MC_PROFILE_CONFIG3 0x0000047c |
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| 599 | |
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| 600 | #define VIVS_MC_BUS_CONFIG 0x00000480 |
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| 601 | #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK 0x0000000f |
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| 602 | #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT 0 |
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| 603 | #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK) |
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| 604 | #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK 0x000000f0 |
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| 605 | #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT 4 |
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| 606 | #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK) |
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| 607 | |
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| 608 | #define VIVS_MC_START_COMPOSITION 0x00000554 |
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| 609 | |
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| 610 | #define VIVS_MC_FLAGS 0x00000558 |
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| 611 | #define VIVS_MC_FLAGS_128B_MERGE 0x00000001 |
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| 612 | #define VIVS_MC_FLAGS_TPCV11_COMPRESSION 0x08000000 |
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| 613 | |
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| 614 | #define VIVS_MC_L2_CACHE_CONFIG 0x0000055c |
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| 615 | |
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| 616 | #define VIVS_MC_PROFILE_L2_READ 0x00000564 |
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| 617 | |
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| 618 | #define VIVS_MC_MC_LATENCY_RESET 0x00000568 |
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| 619 | |
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| 620 | #define VIVS_MC_MC_AXI_MAX_MIN_LATENCY 0x0000056c |
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| 621 | |
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| 622 | #define VIVS_MC_MC_AXI_TOTAL_LATENCY 0x00000570 |
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| 623 | |
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| 624 | #define VIVS_MC_MC_AXI_SAMPLE_COUNT 0x00000574 |
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| 625 | |
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| 626 | #define VIVS_DEC400EX 0x00000000 |
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| 627 | |
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| 628 | #define VIVS_DEC400EX_UNK00800 0x00000800 |
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| 629 | |
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| 630 | #define VIVS_DEC400EX_UNK00808 0x00000808 |
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| 631 | |
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| 632 | |
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| 633 | #endif /* STATE_HI_XML */ |
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| 634 | |
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