1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018 Intel Corp
4 *
5 * Author:
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8
9#include <linux/export.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/errno.h>
14#include <linux/byteorder/generic.h>
15
16#include <drm/display/drm_dp_helper.h>
17#include <drm/display/drm_dsc_helper.h>
18#include <drm/drm_fixed.h>
19#include <drm/drm_print.h>
20
21/**
22 * DOC: dsc helpers
23 *
24 * VESA specification for DP 1.4 adds a new feature called Display Stream
25 * Compression (DSC) used to compress the pixel bits before sending it on
26 * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
27 * display interfaces can support high resolutions at higher frames rates uisng
28 * the maximum available link capacity of these interfaces.
29 *
30 * These functions contain some common logic and helpers to deal with VESA
31 * Display Stream Compression standard required for DSC on Display Port/eDP or
32 * MIPI display interfaces.
33 */
34
35/**
36 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
37 * for DisplayPort as per the DP 1.4 spec.
38 * @pps_header: Secondary data packet header for DSC Picture
39 * Parameter Set as defined in &struct dp_sdp_header
40 *
41 * DP 1.4 spec defines the secondary data packet for sending the
42 * picture parameter infoframes from the source to the sink.
43 * This function populates the SDP header defined in
44 * &struct dp_sdp_header.
45 */
46void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header)
47{
48 memset(pps_header, 0, sizeof(*pps_header));
49
50 pps_header->HB1 = DP_SDP_PPS;
51 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
52}
53EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
54
55/**
56 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
57 * @rc_buffer_block_size: block size code, according to DPCD offset 62h
58 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
59 *
60 * return:
61 * buffer size in bytes, or 0 on invalid input
62 */
63int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size)
64{
65 int size = 1024 * (rc_buffer_size + 1);
66
67 switch (rc_buffer_block_size) {
68 case DP_DSC_RC_BUF_BLK_SIZE_1:
69 return 1 * size;
70 case DP_DSC_RC_BUF_BLK_SIZE_4:
71 return 4 * size;
72 case DP_DSC_RC_BUF_BLK_SIZE_16:
73 return 16 * size;
74 case DP_DSC_RC_BUF_BLK_SIZE_64:
75 return 64 * size;
76 default:
77 return 0;
78 }
79}
80EXPORT_SYMBOL(drm_dsc_dp_rc_buffer_size);
81
82/**
83 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
84 *
85 * @pps_payload:
86 * Bitwise struct for DSC Picture Parameter Set. This is defined
87 * by &struct drm_dsc_picture_parameter_set
88 * @dsc_cfg:
89 * DSC Configuration data filled by driver as defined by
90 * &struct drm_dsc_config
91 *
92 * DSC source device sends a picture parameter set (PPS) containing the
93 * information required by the sink to decode the compressed frame. Driver
94 * populates the DSC PPS struct using the DSC configuration parameters in
95 * the order expected by the DSC Display Sink device. For the DSC, the sink
96 * device expects the PPS payload in big endian format for fields
97 * that span more than 1 byte.
98 */
99void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
100 const struct drm_dsc_config *dsc_cfg)
101{
102 int i;
103
104 /* Protect against someone accidentally changing struct size */
105 BUILD_BUG_ON(sizeof(*pps_payload) !=
106 DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
107
108 memset(pps_payload, 0, sizeof(*pps_payload));
109
110 /* PPS 0 */
111 pps_payload->dsc_version =
112 dsc_cfg->dsc_version_minor |
113 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
114
115 /* PPS 1, 2 is 0 */
116
117 /* PPS 3 */
118 pps_payload->pps_3 =
119 dsc_cfg->line_buf_depth |
120 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
121
122 /* PPS 4 */
123 pps_payload->pps_4 =
124 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
125 DSC_PPS_MSB_SHIFT) |
126 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
127 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
128 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
129 dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
130
131 /* PPS 5 */
132 pps_payload->bits_per_pixel_low =
133 (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
134
135 /*
136 * The DSC panel expects the PPS packet to have big endian format
137 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
138 * to big endian format. If format is little endian, it will swap
139 * bytes to convert to Big endian else keep it unchanged.
140 */
141
142 /* PPS 6, 7 */
143 pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
144
145 /* PPS 8, 9 */
146 pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
147
148 /* PPS 10, 11 */
149 pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
150
151 /* PPS 12, 13 */
152 pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
153
154 /* PPS 14, 15 */
155 pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
156
157 /* PPS 16 */
158 pps_payload->initial_xmit_delay_high =
159 ((dsc_cfg->initial_xmit_delay &
160 DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
161 DSC_PPS_MSB_SHIFT);
162
163 /* PPS 17 */
164 pps_payload->initial_xmit_delay_low =
165 (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
166
167 /* PPS 18, 19 */
168 pps_payload->initial_dec_delay =
169 cpu_to_be16(dsc_cfg->initial_dec_delay);
170
171 /* PPS 20 is 0 */
172
173 /* PPS 21 */
174 pps_payload->initial_scale_value =
175 dsc_cfg->initial_scale_value;
176
177 /* PPS 22, 23 */
178 pps_payload->scale_increment_interval =
179 cpu_to_be16(dsc_cfg->scale_increment_interval);
180
181 /* PPS 24 */
182 pps_payload->scale_decrement_interval_high =
183 ((dsc_cfg->scale_decrement_interval &
184 DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
185 DSC_PPS_MSB_SHIFT);
186
187 /* PPS 25 */
188 pps_payload->scale_decrement_interval_low =
189 (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
190
191 /* PPS 26[7:0], PPS 27[7:5] RESERVED */
192
193 /* PPS 27 */
194 pps_payload->first_line_bpg_offset =
195 dsc_cfg->first_line_bpg_offset;
196
197 /* PPS 28, 29 */
198 pps_payload->nfl_bpg_offset =
199 cpu_to_be16(dsc_cfg->nfl_bpg_offset);
200
201 /* PPS 30, 31 */
202 pps_payload->slice_bpg_offset =
203 cpu_to_be16(dsc_cfg->slice_bpg_offset);
204
205 /* PPS 32, 33 */
206 pps_payload->initial_offset =
207 cpu_to_be16(dsc_cfg->initial_offset);
208
209 /* PPS 34, 35 */
210 pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
211
212 /* PPS 36 */
213 pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
214
215 /* PPS 37 */
216 pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
217
218 /* PPS 38, 39 */
219 pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size);
220
221 /* PPS 40 */
222 pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
223
224 /* PPS 41 */
225 pps_payload->rc_quant_incr_limit0 =
226 dsc_cfg->rc_quant_incr_limit0;
227
228 /* PPS 42 */
229 pps_payload->rc_quant_incr_limit1 =
230 dsc_cfg->rc_quant_incr_limit1;
231
232 /* PPS 43 */
233 pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
234 DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
235
236 /* PPS 44 - 57 */
237 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
238 pps_payload->rc_buf_thresh[i] =
239 dsc_cfg->rc_buf_thresh[i];
240
241 /* PPS 58 - 87 */
242 /*
243 * For DSC sink programming the RC Range parameter fields
244 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
245 */
246 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
247 pps_payload->rc_range_parameters[i] =
248 cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp <<
249 DSC_PPS_RC_RANGE_MINQP_SHIFT) |
250 (dsc_cfg->rc_range_params[i].range_max_qp <<
251 DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
252 (dsc_cfg->rc_range_params[i].range_bpg_offset));
253 }
254
255 /* PPS 88 */
256 pps_payload->native_422_420 = dsc_cfg->native_422 |
257 dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
258
259 /* PPS 89 */
260 pps_payload->second_line_bpg_offset =
261 dsc_cfg->second_line_bpg_offset;
262
263 /* PPS 90, 91 */
264 pps_payload->nsl_bpg_offset =
265 cpu_to_be16(dsc_cfg->nsl_bpg_offset);
266
267 /* PPS 92, 93 */
268 pps_payload->second_line_offset_adj =
269 cpu_to_be16(dsc_cfg->second_line_offset_adj);
270
271 /* PPS 94 - 127 are O */
272}
273EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
274
275/**
276 * drm_dsc_set_const_params() - Set DSC parameters considered typically
277 * constant across operation modes
278 *
279 * @vdsc_cfg:
280 * DSC Configuration data partially filled by driver
281 */
282void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg)
283{
284 if (!vdsc_cfg->rc_model_size)
285 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
286 vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
287 vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST;
288 vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST;
289
290 if (vdsc_cfg->bits_per_component <= 10)
291 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
292 else
293 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
294}
295EXPORT_SYMBOL(drm_dsc_set_const_params);
296
297/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
298static const u16 drm_dsc_rc_buf_thresh[] = {
299 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
300 7744, 7872, 8000, 8064
301};
302
303/**
304 * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
305 * in accordance with the DSC 1.2 specification.
306 *
307 * @vdsc_cfg: DSC Configuration data partially filled by driver
308 */
309void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
310{
311 int i;
312
313 BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
314 DSC_NUM_BUF_RANGES - 1);
315 BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
316 ARRAY_SIZE(vdsc_cfg->rc_buf_thresh));
317
318 for (i = 0; i < ARRAY_SIZE(drm_dsc_rc_buf_thresh); i++)
319 vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
320
321 /*
322 * For 6bpp, RC Buffer threshold 12 and 13 need a different value
323 * as per C Model
324 */
325 if (vdsc_cfg->bits_per_pixel == 6 << 4) {
326 vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
327 vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
328 }
329}
330EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
331
332struct rc_parameters {
333 u16 initial_xmit_delay;
334 u8 first_line_bpg_offset;
335 u16 initial_offset;
336 u8 flatness_min_qp;
337 u8 flatness_max_qp;
338 u8 rc_quant_incr_limit0;
339 u8 rc_quant_incr_limit1;
340 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
341};
342
343struct rc_parameters_data {
344 u8 bpp;
345 u8 bpc;
346 struct rc_parameters params;
347};
348
349#define DSC_BPP(bpp) ((bpp) << 4)
350
351/*
352 * Rate Control Related Parameter Recommended Values from DSC_v1.1 spec prior
353 * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf)
354 *
355 * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
356 */
357static const struct rc_parameters_data rc_parameters_pre_scr[] = {
358 {
359 .bpp = DSC_BPP(6), .bpc = 8,
360 { 683, 15, 6144, 3, 13, 11, 11, {
361 { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
362 { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
363 { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
364 { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
365 }
366 }
367 },
368 {
369 .bpp = DSC_BPP(8), .bpc = 8,
370 { 512, 12, 6144, 3, 12, 11, 11, {
371 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
372 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
373 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
374 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
375 }
376 }
377 },
378 {
379 .bpp = DSC_BPP(8), .bpc = 10,
380 { 512, 12, 6144, 7, 16, 15, 15, {
381 /*
382 * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
383 * VESA DSC 1.1 Table E-5 sets it to 4.
384 */
385 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
386 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
387 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
388 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
389 }
390 }
391 },
392 {
393 .bpp = DSC_BPP(8), .bpc = 12,
394 { 512, 12, 6144, 11, 20, 19, 19, {
395 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
396 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
397 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
398 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
399 { 21, 23, -12 }
400 }
401 }
402 },
403 {
404 .bpp = DSC_BPP(10), .bpc = 8,
405 { 410, 12, 5632, 3, 12, 11, 11, {
406 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
407 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
408 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
409 { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
410 }
411 }
412 },
413 {
414 .bpp = DSC_BPP(10), .bpc = 10,
415 { 410, 12, 5632, 7, 16, 15, 15, {
416 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
417 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
418 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
419 { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
420 }
421 }
422 },
423 {
424 .bpp = DSC_BPP(10), .bpc = 12,
425 { 410, 12, 5632, 11, 20, 19, 19, {
426 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
427 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
428 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
429 { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
430 { 21, 23, -12 }
431 }
432 }
433 },
434 {
435 .bpp = DSC_BPP(12), .bpc = 8,
436 { 341, 15, 2048, 3, 12, 11, 11, {
437 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
438 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
439 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
440 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
441 }
442 }
443 },
444 {
445 .bpp = DSC_BPP(12), .bpc = 10,
446 { 341, 15, 2048, 7, 16, 15, 15, {
447 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
448 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
449 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
450 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
451 }
452 }
453 },
454 {
455 .bpp = DSC_BPP(12), .bpc = 12,
456 { 341, 15, 2048, 11, 20, 19, 19, {
457 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
458 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
459 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
460 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
461 { 21, 23, -12 }
462 }
463 }
464 },
465 {
466 .bpp = DSC_BPP(15), .bpc = 8,
467 { 273, 15, 2048, 3, 12, 11, 11, {
468 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
469 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
470 { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
471 { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
472 }
473 }
474 },
475 {
476 .bpp = DSC_BPP(15), .bpc = 10,
477 { 273, 15, 2048, 7, 16, 15, 15, {
478 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
479 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
480 { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
481 { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
482 }
483 }
484 },
485 {
486 .bpp = DSC_BPP(15), .bpc = 12,
487 { 273, 15, 2048, 11, 20, 19, 19, {
488 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
489 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
490 { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
491 { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
492 { 21, 23, -12 }
493 }
494 }
495 },
496 { /* sentinel */ }
497};
498
499/*
500 * Selected Rate Control Related Parameter Recommended Values from DSC v1.2, v1.2a, v1.2b and
501 * DSC_v1.1_E1 specs.
502 *
503 * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
504 */
505static const struct rc_parameters_data rc_parameters_1_2_444[] = {
506 {
507 .bpp = DSC_BPP(6), .bpc = 8,
508 { 768, 15, 6144, 3, 13, 11, 11, {
509 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
510 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
511 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
512 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
513 }
514 }
515 },
516 {
517 .bpp = DSC_BPP(6), .bpc = 10,
518 { 768, 15, 6144, 7, 17, 15, 15, {
519 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
520 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
521 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
522 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
523 { 17, 18, -12 }
524 }
525 }
526 },
527 {
528 .bpp = DSC_BPP(6), .bpc = 12,
529 { 768, 15, 6144, 11, 21, 19, 19, {
530 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
531 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
532 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
533 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
534 { 21, 22, -12 }
535 }
536 }
537 },
538 {
539 .bpp = DSC_BPP(6), .bpc = 14,
540 { 768, 15, 6144, 15, 25, 23, 23, {
541 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
542 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
543 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
544 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
545 { 25, 26, -12 }
546 }
547 }
548 },
549 {
550 .bpp = DSC_BPP(6), .bpc = 16,
551 { 768, 15, 6144, 19, 29, 27, 27, {
552 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
553 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
554 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
555 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
556 { 29, 30, -12 }
557 }
558 }
559 },
560 {
561 .bpp = DSC_BPP(8), .bpc = 8,
562 { 512, 12, 6144, 3, 12, 11, 11, {
563 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
564 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
565 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
566 { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
567 }
568 }
569 },
570 {
571 .bpp = DSC_BPP(8), .bpc = 10,
572 { 512, 12, 6144, 7, 16, 15, 15, {
573 { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
574 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
575 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
576 { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
577 }
578 }
579 },
580 {
581 .bpp = DSC_BPP(8), .bpc = 12,
582 { 512, 12, 6144, 11, 20, 19, 19, {
583 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
584 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
585 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
586 { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
587 { 20, 21, -12 }
588 }
589 }
590 },
591 {
592 .bpp = DSC_BPP(8), .bpc = 14,
593 { 512, 12, 6144, 15, 24, 23, 23, {
594 { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
595 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
596 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
597 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
598 { 24, 25, -12 }
599 }
600 }
601 },
602 {
603 .bpp = DSC_BPP(8), .bpc = 16,
604 { 512, 12, 6144, 19, 28, 27, 27, {
605 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
606 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
607 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
608 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
609 { 28, 29, -12 }
610 }
611 }
612 },
613 {
614 .bpp = DSC_BPP(10), .bpc = 8,
615 { 410, 15, 5632, 3, 12, 11, 11, {
616 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
617 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
618 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
619 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
620 }
621 }
622 },
623 {
624 .bpp = DSC_BPP(10), .bpc = 10,
625 { 410, 15, 5632, 7, 16, 15, 15, {
626 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
627 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
628 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
629 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
630 }
631 }
632 },
633 {
634 .bpp = DSC_BPP(10), .bpc = 12,
635 { 410, 15, 5632, 11, 20, 19, 19, {
636 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
637 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
638 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
639 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
640 { 19, 20, -12 }
641 }
642 }
643 },
644 {
645 .bpp = DSC_BPP(10), .bpc = 14,
646 { 410, 15, 5632, 15, 24, 23, 23, {
647 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
648 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
649 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
650 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
651 { 23, 24, -12 }
652 }
653 }
654 },
655 {
656 .bpp = DSC_BPP(10), .bpc = 16,
657 { 410, 15, 5632, 19, 28, 27, 27, {
658 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
659 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
660 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
661 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
662 { 27, 28, -12 }
663 }
664 }
665 },
666 {
667 .bpp = DSC_BPP(12), .bpc = 8,
668 { 341, 15, 2048, 3, 12, 11, 11, {
669 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
670 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
671 { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
672 { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
673 }
674 }
675 },
676 {
677 .bpp = DSC_BPP(12), .bpc = 10,
678 { 341, 15, 2048, 7, 16, 15, 15, {
679 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
680 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
681 { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
682 { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
683 }
684 }
685 },
686 {
687 .bpp = DSC_BPP(12), .bpc = 12,
688 { 341, 15, 2048, 11, 20, 19, 19, {
689 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
690 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
691 { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
692 { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
693 { 18, 19, -12 }
694 }
695 }
696 },
697 {
698 .bpp = DSC_BPP(12), .bpc = 14,
699 { 341, 15, 2048, 15, 24, 23, 23, {
700 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
701 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
702 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
703 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
704 { 22, 23, -12 }
705 }
706 }
707 },
708 {
709 .bpp = DSC_BPP(12), .bpc = 16,
710 { 341, 15, 2048, 19, 28, 27, 27, {
711 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
712 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
713 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
714 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
715 { 26, 27, -12 }
716 }
717 }
718 },
719 {
720 .bpp = DSC_BPP(15), .bpc = 8,
721 { 273, 15, 2048, 3, 12, 11, 11, {
722 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
723 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
724 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
725 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
726 }
727 }
728 },
729 {
730 .bpp = DSC_BPP(15), .bpc = 10,
731 { 273, 15, 2048, 7, 16, 15, 15, {
732 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
733 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
734 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
735 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
736 }
737 }
738 },
739 {
740 .bpp = DSC_BPP(15), .bpc = 12,
741 { 273, 15, 2048, 11, 20, 19, 19, {
742 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
743 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
744 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
745 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
746 { 16, 17, -12 }
747 }
748 }
749 },
750 {
751 .bpp = DSC_BPP(15), .bpc = 14,
752 { 273, 15, 2048, 15, 24, 23, 23, {
753 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
754 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
755 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
756 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
757 { 20, 21, -12 }
758 }
759 }
760 },
761 {
762 .bpp = DSC_BPP(15), .bpc = 16,
763 { 273, 15, 2048, 19, 28, 27, 27, {
764 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
765 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
766 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
767 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
768 { 24, 25, -12 }
769 }
770 }
771 },
772 { /* sentinel */ }
773};
774
775/*
776 * Selected Rate Control Related Parameter Recommended Values for 4:2:2 from
777 * DSC v1.2, v1.2a, v1.2b
778 *
779 * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
780 */
781static const struct rc_parameters_data rc_parameters_1_2_422[] = {
782 {
783 .bpp = DSC_BPP(6), .bpc = 8,
784 { 512, 15, 6144, 3, 12, 11, 11, {
785 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
786 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
787 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
788 { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
789 }
790 }
791 },
792 {
793 .bpp = DSC_BPP(6), .bpc = 10,
794 { 512, 15, 6144, 7, 16, 15, 15, {
795 { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
796 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
797 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
798 { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
799 }
800 }
801 },
802 {
803 .bpp = DSC_BPP(6), .bpc = 12,
804 { 512, 15, 6144, 11, 20, 19, 19, {
805 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
806 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
807 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
808 { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
809 { 20, 21, -12 }
810 }
811 }
812 },
813 {
814 .bpp = DSC_BPP(6), .bpc = 14,
815 { 512, 15, 6144, 15, 24, 23, 23, {
816 { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
817 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
818 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
819 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
820 { 24, 25, -12 }
821 }
822 }
823 },
824 {
825 .bpp = DSC_BPP(6), .bpc = 16,
826 { 512, 15, 6144, 19, 28, 27, 27, {
827 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
828 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
829 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
830 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
831 { 28, 29, -12 }
832 }
833 }
834 },
835 {
836 .bpp = DSC_BPP(7), .bpc = 8,
837 { 410, 15, 5632, 3, 12, 11, 11, {
838 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
839 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
840 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
841 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
842 }
843 }
844 },
845 {
846 .bpp = DSC_BPP(7), .bpc = 10,
847 { 410, 15, 5632, 7, 16, 15, 15, {
848 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
849 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
850 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
851 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
852 }
853 }
854 },
855 {
856 .bpp = DSC_BPP(7), .bpc = 12,
857 { 410, 15, 5632, 11, 20, 19, 19, {
858 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
859 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
860 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
861 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
862 { 19, 20, -12 }
863 }
864 }
865 },
866 {
867 .bpp = DSC_BPP(7), .bpc = 14,
868 { 410, 15, 5632, 15, 24, 23, 23, {
869 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
870 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
871 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
872 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
873 { 23, 24, -12 }
874 }
875 }
876 },
877 {
878 .bpp = DSC_BPP(7), .bpc = 16,
879 { 410, 15, 5632, 19, 28, 27, 27, {
880 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
881 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
882 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
883 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
884 { 27, 28, -12 }
885 }
886 }
887 },
888 {
889 .bpp = DSC_BPP(8), .bpc = 8,
890 { 341, 15, 2048, 3, 12, 11, 11, {
891 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
892 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
893 { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
894 { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
895 }
896 }
897 },
898 {
899 .bpp = DSC_BPP(8), .bpc = 10,
900 { 341, 15, 2048, 7, 16, 15, 15, {
901 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
902 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
903 { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
904 { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
905 }
906 }
907 },
908 {
909 .bpp = DSC_BPP(8), .bpc = 12,
910 { 341, 15, 2048, 11, 20, 19, 19, {
911 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
912 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
913 { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
914 { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
915 { 18, 19, -12 }
916 }
917 }
918 },
919 {
920 .bpp = DSC_BPP(8), .bpc = 14,
921 { 341, 15, 2048, 15, 24, 23, 23, {
922 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
923 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
924 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
925 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
926 { 22, 23, -12 }
927 }
928 }
929 },
930 {
931 .bpp = DSC_BPP(8), .bpc = 16,
932 { 341, 15, 2048, 19, 28, 27, 27, {
933 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
934 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
935 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
936 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
937 { 26, 27, -12 }
938 }
939 }
940 },
941 {
942 .bpp = DSC_BPP(10), .bpc = 8,
943 { 273, 15, 2048, 3, 12, 11, 11, {
944 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
945 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
946 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
947 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
948 }
949 }
950 },
951 {
952 .bpp = DSC_BPP(10), .bpc = 10,
953 { 273, 15, 2048, 7, 16, 15, 15, {
954 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
955 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
956 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
957 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
958 }
959 }
960 },
961 {
962 .bpp = DSC_BPP(10), .bpc = 12,
963 { 273, 15, 2048, 11, 20, 19, 19, {
964 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
965 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
966 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
967 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
968 { 16, 17, -12 }
969 }
970 }
971 },
972 {
973 .bpp = DSC_BPP(10), .bpc = 14,
974 { 273, 15, 2048, 15, 24, 23, 23, {
975 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
976 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
977 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
978 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
979 { 20, 21, -12 }
980 }
981 }
982 },
983 {
984 .bpp = DSC_BPP(10), .bpc = 16,
985 { 273, 15, 2048, 19, 28, 27, 27, {
986 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
987 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
988 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
989 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
990 { 24, 25, -12 }
991 }
992 }
993 },
994 { /* sentinel */ }
995};
996
997/*
998 * Selected Rate Control Related Parameter Recommended Values for 4:2:2 from
999 * DSC v1.2, v1.2a, v1.2b
1000 *
1001 * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
1002 */
1003static const struct rc_parameters_data rc_parameters_1_2_420[] = {
1004 {
1005 .bpp = DSC_BPP(4), .bpc = 8,
1006 { 512, 12, 6144, 3, 12, 11, 11, {
1007 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
1008 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
1009 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
1010 { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
1011 }
1012 }
1013 },
1014 {
1015 .bpp = DSC_BPP(4), .bpc = 10,
1016 { 512, 12, 6144, 7, 16, 15, 15, {
1017 { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
1018 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
1019 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
1020 { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
1021 }
1022 }
1023 },
1024 {
1025 .bpp = DSC_BPP(4), .bpc = 12,
1026 { 512, 12, 6144, 11, 20, 19, 19, {
1027 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
1028 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
1029 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
1030 { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
1031 { 20, 21, -12 }
1032 }
1033 }
1034 },
1035 {
1036 .bpp = DSC_BPP(4), .bpc = 14,
1037 { 512, 12, 6144, 15, 24, 23, 23, {
1038 { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
1039 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
1040 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
1041 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
1042 { 24, 25, -12 }
1043 }
1044 }
1045 },
1046 {
1047 .bpp = DSC_BPP(4), .bpc = 16,
1048 { 512, 12, 6144, 19, 28, 27, 27, {
1049 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
1050 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
1051 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
1052 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
1053 { 28, 29, -12 }
1054 }
1055 }
1056 },
1057 {
1058 .bpp = DSC_BPP(5), .bpc = 8,
1059 { 410, 15, 5632, 3, 12, 11, 11, {
1060 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
1061 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
1062 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
1063 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
1064 }
1065 }
1066 },
1067 {
1068 .bpp = DSC_BPP(5), .bpc = 10,
1069 { 410, 15, 5632, 7, 16, 15, 15, {
1070 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
1071 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
1072 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
1073 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
1074 }
1075 }
1076 },
1077 {
1078 .bpp = DSC_BPP(5), .bpc = 12,
1079 { 410, 15, 5632, 11, 20, 19, 19, {
1080 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
1081 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
1082 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
1083 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
1084 { 19, 20, -12 }
1085 }
1086 }
1087 },
1088 {
1089 .bpp = DSC_BPP(5), .bpc = 14,
1090 { 410, 15, 5632, 15, 24, 23, 23, {
1091 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
1092 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
1093 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
1094 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
1095 { 23, 24, -12 }
1096 }
1097 }
1098 },
1099 {
1100 .bpp = DSC_BPP(5), .bpc = 16,
1101 { 410, 15, 5632, 19, 28, 27, 27, {
1102 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
1103 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
1104 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
1105 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
1106 { 27, 28, -12 }
1107 }
1108 }
1109 },
1110 {
1111 .bpp = DSC_BPP(6), .bpc = 8,
1112 { 341, 15, 2048, 3, 12, 11, 11, {
1113 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
1114 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
1115 { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
1116 { 5, 9, -12 }, { 7, 10, -12 }, { 10, 12, -12 }
1117 }
1118 }
1119 },
1120 {
1121 .bpp = DSC_BPP(6), .bpc = 10,
1122 { 341, 15, 2048, 7, 16, 15, 15, {
1123 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
1124 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
1125 { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
1126 { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
1127 }
1128 }
1129 },
1130 {
1131 .bpp = DSC_BPP(6), .bpc = 12,
1132 { 341, 15, 2048, 11, 20, 19, 19, {
1133 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
1134 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
1135 { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
1136 { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
1137 { 18, 19, -12 }
1138 }
1139 }
1140 },
1141 {
1142 .bpp = DSC_BPP(6), .bpc = 14,
1143 { 341, 15, 2048, 15, 24, 23, 23, {
1144 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
1145 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
1146 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
1147 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
1148 { 22, 23, -12 }
1149 }
1150 }
1151 },
1152 {
1153 .bpp = DSC_BPP(6), .bpc = 16,
1154 { 341, 15, 2048, 19, 28, 27, 27, {
1155 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
1156 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
1157 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
1158 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
1159 { 26, 27, -12 }
1160 }
1161 }
1162 },
1163 {
1164 .bpp = DSC_BPP(8), .bpc = 8,
1165 { 256, 15, 2048, 3, 12, 11, 11, {
1166 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
1167 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
1168 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
1169 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
1170 }
1171 }
1172 },
1173 {
1174 .bpp = DSC_BPP(8), .bpc = 10,
1175 { 256, 15, 2048, 7, 16, 15, 15, {
1176 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
1177 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
1178 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
1179 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
1180 }
1181 }
1182 },
1183 {
1184 .bpp = DSC_BPP(8), .bpc = 12,
1185 { 256, 15, 2048, 11, 20, 19, 19, {
1186 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
1187 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
1188 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
1189 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
1190 { 16, 17, -12 }
1191 }
1192 }
1193 },
1194 {
1195 .bpp = DSC_BPP(8), .bpc = 14,
1196 { 256, 15, 2048, 15, 24, 23, 23, {
1197 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
1198 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
1199 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
1200 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
1201 { 20, 21, -12 }
1202 }
1203 }
1204 },
1205 {
1206 .bpp = DSC_BPP(8), .bpc = 16,
1207 { 256, 15, 2048, 19, 28, 27, 27, {
1208 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
1209 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
1210 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
1211 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
1212 { 24, 25, -12 }
1213 }
1214 }
1215 },
1216 { /* sentinel */ }
1217};
1218
1219static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
1220 u16 dsc_bpp,
1221 u8 bits_per_component)
1222{
1223 int i;
1224
1225 for (i = 0; rc_parameters[i].bpp; i++)
1226 if (rc_parameters[i].bpp == dsc_bpp &&
1227 rc_parameters[i].bpc == bits_per_component)
1228 return &rc_parameters[i].params;
1229
1230 return NULL;
1231}
1232
1233/**
1234 * drm_dsc_setup_rc_params() - Set parameters and limits for RC model in
1235 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
1236 * Required bits_per_pixel and bits_per_component to be set before calling this
1237 * function.
1238 *
1239 * @vdsc_cfg: DSC Configuration data partially filled by driver
1240 * @type: operating mode and standard to follow
1241 *
1242 * Return: 0 or -error code in case of an error
1243 */
1244int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type)
1245{
1246 const struct rc_parameters_data *data;
1247 const struct rc_parameters *rc_params;
1248 int i;
1249
1250 if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel ||
1251 !vdsc_cfg->bits_per_component))
1252 return -EINVAL;
1253
1254 switch (type) {
1255 case DRM_DSC_1_2_444:
1256 data = rc_parameters_1_2_444;
1257 break;
1258 case DRM_DSC_1_1_PRE_SCR:
1259 data = rc_parameters_pre_scr;
1260 break;
1261 case DRM_DSC_1_2_422:
1262 data = rc_parameters_1_2_422;
1263 break;
1264 case DRM_DSC_1_2_420:
1265 data = rc_parameters_1_2_420;
1266 break;
1267 default:
1268 return -EINVAL;
1269 }
1270
1271 rc_params = get_rc_params(rc_parameters: data,
1272 dsc_bpp: vdsc_cfg->bits_per_pixel,
1273 bits_per_component: vdsc_cfg->bits_per_component);
1274 if (!rc_params)
1275 return -EINVAL;
1276
1277 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
1278 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
1279 vdsc_cfg->initial_offset = rc_params->initial_offset;
1280 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
1281 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
1282 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
1283 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
1284
1285 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
1286 vdsc_cfg->rc_range_params[i].range_min_qp =
1287 rc_params->rc_range_params[i].range_min_qp;
1288 vdsc_cfg->rc_range_params[i].range_max_qp =
1289 rc_params->rc_range_params[i].range_max_qp;
1290 /*
1291 * Range BPG Offset uses 2's complement and is only a 6 bits. So
1292 * mask it to get only 6 bits.
1293 */
1294 vdsc_cfg->rc_range_params[i].range_bpg_offset =
1295 rc_params->rc_range_params[i].range_bpg_offset &
1296 DSC_RANGE_BPG_OFFSET_MASK;
1297 }
1298
1299 return 0;
1300}
1301EXPORT_SYMBOL(drm_dsc_setup_rc_params);
1302
1303/**
1304 * drm_dsc_compute_rc_parameters() - Write rate control
1305 * parameters to the dsc configuration defined in
1306 * &struct drm_dsc_config in accordance with the DSC 1.2
1307 * specification. Some configuration fields must be present
1308 * beforehand.
1309 *
1310 * @vdsc_cfg:
1311 * DSC Configuration data partially filled by driver
1312 */
1313int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
1314{
1315 unsigned long groups_per_line = 0;
1316 unsigned long groups_total = 0;
1317 unsigned long num_extra_mux_bits = 0;
1318 unsigned long slice_bits = 0;
1319 unsigned long hrd_delay = 0;
1320 unsigned long final_scale = 0;
1321 unsigned long rbs_min = 0;
1322
1323 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
1324 /* Number of groups used to code each line of a slice */
1325 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
1326 DSC_RC_PIXELS_PER_GROUP);
1327
1328 /* chunksize in Bytes */
1329 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
1330 vdsc_cfg->bits_per_pixel,
1331 (8 * 16));
1332 } else {
1333 /* Number of groups used to code each line of a slice */
1334 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
1335 DSC_RC_PIXELS_PER_GROUP);
1336
1337 /* chunksize in Bytes */
1338 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
1339 vdsc_cfg->bits_per_pixel,
1340 (8 * 16));
1341 }
1342
1343 if (vdsc_cfg->convert_rgb)
1344 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
1345 (4 * vdsc_cfg->bits_per_component + 4)
1346 - 2);
1347 else if (vdsc_cfg->native_422)
1348 num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
1349 (4 * vdsc_cfg->bits_per_component + 4) +
1350 3 * (4 * vdsc_cfg->bits_per_component) - 2;
1351 else
1352 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
1353 (4 * vdsc_cfg->bits_per_component + 4) +
1354 2 * (4 * vdsc_cfg->bits_per_component) - 2;
1355 /* Number of bits in one Slice */
1356 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
1357
1358 while ((num_extra_mux_bits > 0) &&
1359 ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
1360 num_extra_mux_bits--;
1361
1362 if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
1363 vdsc_cfg->initial_scale_value = groups_per_line + 8;
1364
1365 /* scale_decrement_interval calculation according to DSC spec 1.11 */
1366 if (vdsc_cfg->initial_scale_value > 8)
1367 vdsc_cfg->scale_decrement_interval = groups_per_line /
1368 (vdsc_cfg->initial_scale_value - 8);
1369 else
1370 vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
1371
1372 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
1373 (vdsc_cfg->initial_xmit_delay *
1374 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
1375
1376 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
1377 DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
1378 return -ERANGE;
1379 }
1380
1381 final_scale = (vdsc_cfg->rc_model_size * 8) /
1382 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
1383 if (vdsc_cfg->slice_height > 1)
1384 /*
1385 * NflBpgOffset is 16 bit value with 11 fractional bits
1386 * hence we multiply by 2^11 for preserving the
1387 * fractional part
1388 */
1389 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
1390 (vdsc_cfg->slice_height - 1));
1391 else
1392 vdsc_cfg->nfl_bpg_offset = 0;
1393
1394 /* Number of groups used to code the entire slice */
1395 groups_total = groups_per_line * vdsc_cfg->slice_height;
1396
1397 /* slice_bpg_offset is 16 bit value with 11 fractional bits */
1398 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
1399 vdsc_cfg->initial_offset +
1400 num_extra_mux_bits) << 11),
1401 groups_total);
1402
1403 if (final_scale > 9) {
1404 /*
1405 * ScaleIncrementInterval =
1406 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
1407 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
1408 * we need divide by 2^11 from pstDscCfg values
1409 */
1410 vdsc_cfg->scale_increment_interval =
1411 (vdsc_cfg->final_offset * (1 << 11)) /
1412 ((vdsc_cfg->nfl_bpg_offset +
1413 vdsc_cfg->slice_bpg_offset) *
1414 (final_scale - 9));
1415 } else {
1416 /*
1417 * If finalScaleValue is less than or equal to 9, a value of 0 should
1418 * be used to disable the scale increment at the end of the slice
1419 */
1420 vdsc_cfg->scale_increment_interval = 0;
1421 }
1422
1423 /*
1424 * DSC spec mentions that bits_per_pixel specifies the target
1425 * bits/pixel (bpp) rate that is used by the encoder,
1426 * in steps of 1/16 of a bit per pixel
1427 */
1428 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
1429 DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
1430 vdsc_cfg->bits_per_pixel, 16) +
1431 groups_per_line * vdsc_cfg->first_line_bpg_offset;
1432
1433 hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
1434 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
1435 vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
1436
1437 return 0;
1438}
1439EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
1440
1441/**
1442 * drm_dsc_get_bpp_int() - Get integer bits per pixel value for the given DRM DSC config
1443 * @vdsc_cfg: Pointer to DRM DSC config struct
1444 *
1445 * Return: Integer BPP value
1446 */
1447u32 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg)
1448{
1449 WARN_ON_ONCE(vdsc_cfg->bits_per_pixel & 0xf);
1450 return vdsc_cfg->bits_per_pixel >> 4;
1451}
1452EXPORT_SYMBOL(drm_dsc_get_bpp_int);
1453
1454/**
1455 * drm_dsc_initial_scale_value() - Calculate the initial scale value for the given DSC config
1456 * @dsc: Pointer to DRM DSC config struct
1457 *
1458 * Return: Calculated initial scale value
1459 */
1460u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc)
1461{
1462 return 8 * dsc->rc_model_size / (dsc->rc_model_size - dsc->initial_offset);
1463}
1464EXPORT_SYMBOL(drm_dsc_initial_scale_value);
1465
1466/**
1467 * drm_dsc_flatness_det_thresh() - Calculate the flatness_det_thresh for the given DSC config
1468 * @dsc: Pointer to DRM DSC config struct
1469 *
1470 * Return: Calculated flatness det thresh value
1471 */
1472u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc)
1473{
1474 return 2 << (dsc->bits_per_component - 8);
1475}
1476EXPORT_SYMBOL(drm_dsc_flatness_det_thresh);
1477
1478static void drm_dsc_dump_config_main_params(struct drm_printer *p, int indent,
1479 const struct drm_dsc_config *cfg)
1480{
1481 drm_printf_indent(p, indent,
1482 "dsc-cfg: version: %d.%d, picture: w=%d, h=%d, slice: count=%d, w=%d, h=%d, size=%d\n",
1483 cfg->dsc_version_major, cfg->dsc_version_minor,
1484 cfg->pic_width, cfg->pic_height,
1485 cfg->slice_count, cfg->slice_width, cfg->slice_height, cfg->slice_chunk_size);
1486 drm_printf_indent(p, indent,
1487 "dsc-cfg: mode: block-pred=%s, vbr=%s, rgb=%s, simple-422=%s, native-422=%s, native-420=%s\n",
1488 str_yes_no(cfg->block_pred_enable), str_yes_no(cfg->vbr_enable),
1489 str_yes_no(cfg->convert_rgb),
1490 str_yes_no(cfg->simple_422), str_yes_no(cfg->native_422), str_yes_no(cfg->native_420));
1491 drm_printf_indent(p, indent,
1492 "dsc-cfg: color-depth: uncompressed-bpc=%d, compressed-bpp=" FXP_Q4_FMT " line-buf-bpp=%d\n",
1493 cfg->bits_per_component, FXP_Q4_ARGS(cfg->bits_per_pixel), cfg->line_buf_depth);
1494 drm_printf_indent(p, indent,
1495 "dsc-cfg: rc-model: size=%d, bits=%d, mux-word-size: %d, initial-delays: xmit=%d, dec=%d\n",
1496 cfg->rc_model_size, cfg->rc_bits, cfg->mux_word_size,
1497 cfg->initial_xmit_delay, cfg->initial_dec_delay);
1498 drm_printf_indent(p, indent,
1499 "dsc-cfg: offsets: initial=%d, final=%d, slice-bpg=%d\n",
1500 cfg->initial_offset, cfg->final_offset, cfg->slice_bpg_offset);
1501 drm_printf_indent(p, indent,
1502 "dsc-cfg: line-bpg-offsets: first=%d, non-first=%d, second=%d, non-second=%d, second-adj=%d\n",
1503 cfg->first_line_bpg_offset, cfg->nfl_bpg_offset,
1504 cfg->second_line_bpg_offset, cfg->nsl_bpg_offset, cfg->second_line_offset_adj);
1505 drm_printf_indent(p, indent,
1506 "dsc-cfg: rc-tgt-offsets: low=%d, high=%d, rc-edge-factor: %d, rc-quant-incr-limits: [0]=%d, [1]=%d\n",
1507 cfg->rc_tgt_offset_low, cfg->rc_tgt_offset_high,
1508 cfg->rc_edge_factor, cfg->rc_quant_incr_limit0, cfg->rc_quant_incr_limit1);
1509 drm_printf_indent(p, indent,
1510 "dsc-cfg: initial-scale: %d, scale-intervals: increment=%d, decrement=%d\n",
1511 cfg->initial_scale_value, cfg->scale_increment_interval, cfg->scale_decrement_interval);
1512 drm_printf_indent(p, indent,
1513 "dsc-cfg: flatness: min-qp=%d, max-qp=%d\n",
1514 cfg->flatness_min_qp, cfg->flatness_max_qp);
1515}
1516
1517static void drm_dsc_dump_config_rc_params(struct drm_printer *p, int indent,
1518 const struct drm_dsc_config *cfg)
1519{
1520 const u16 *bt = cfg->rc_buf_thresh;
1521 const struct drm_dsc_rc_range_parameters *rp = cfg->rc_range_params;
1522
1523 BUILD_BUG_ON(ARRAY_SIZE(cfg->rc_buf_thresh) != 14);
1524 BUILD_BUG_ON(ARRAY_SIZE(cfg->rc_range_params) != 15);
1525
1526 drm_printf_indent(p, indent,
1527 "dsc-cfg: rc-level: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14\n");
1528 drm_printf_indent(p, indent,
1529 "dsc-cfg: rc-buf-thresh: %3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d\n",
1530 bt[0], bt[1], bt[2], bt[3], bt[4], bt[5], bt[6], bt[7],
1531 bt[8], bt[9], bt[10], bt[11], bt[12], bt[13]);
1532 drm_printf_indent(p, indent,
1533 "dsc-cfg: rc-min-qp: %3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d\n",
1534 rp[0].range_min_qp, rp[1].range_min_qp, rp[2].range_min_qp, rp[3].range_min_qp,
1535 rp[4].range_min_qp, rp[5].range_min_qp, rp[6].range_min_qp, rp[7].range_min_qp,
1536 rp[8].range_min_qp, rp[9].range_min_qp, rp[10].range_min_qp, rp[11].range_min_qp,
1537 rp[12].range_min_qp, rp[13].range_min_qp, rp[14].range_min_qp);
1538 drm_printf_indent(p, indent,
1539 "dsc-cfg: rc-max-qp: %3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d\n",
1540 rp[0].range_max_qp, rp[1].range_max_qp, rp[2].range_max_qp, rp[3].range_max_qp,
1541 rp[4].range_max_qp, rp[5].range_max_qp, rp[6].range_max_qp, rp[7].range_max_qp,
1542 rp[8].range_max_qp, rp[9].range_max_qp, rp[10].range_max_qp, rp[11].range_max_qp,
1543 rp[12].range_max_qp, rp[13].range_max_qp, rp[14].range_max_qp);
1544 drm_printf_indent(p, indent,
1545 "dsc-cfg: rc-bpg-offset: %3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d\n",
1546 rp[0].range_bpg_offset, rp[1].range_bpg_offset, rp[2].range_bpg_offset, rp[3].range_bpg_offset,
1547 rp[4].range_bpg_offset, rp[5].range_bpg_offset, rp[6].range_bpg_offset, rp[7].range_bpg_offset,
1548 rp[8].range_bpg_offset, rp[9].range_bpg_offset, rp[10].range_bpg_offset, rp[11].range_bpg_offset,
1549 rp[12].range_bpg_offset, rp[13].range_bpg_offset, rp[14].range_bpg_offset);
1550}
1551
1552/**
1553 * drm_dsc_dump_config - Dump the provided DSC configuration
1554 * @p: The printer used for output
1555 * @indent: Tab indentation level (max 5)
1556 * @cfg: DSC configuration to print
1557 *
1558 * Print the provided DSC configuration in @cfg.
1559 */
1560void drm_dsc_dump_config(struct drm_printer *p, int indent,
1561 const struct drm_dsc_config *cfg)
1562{
1563 drm_dsc_dump_config_main_params(p, indent, cfg);
1564 drm_dsc_dump_config_rc_params(p, indent, cfg);
1565}
1566EXPORT_SYMBOL(drm_dsc_dump_config);
1567

source code of linux/drivers/gpu/drm/display/drm_dsc_helper.c