1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef PP_POWERSTATE_H
24#define PP_POWERSTATE_H
25
26struct pp_hw_power_state {
27 unsigned int magic;
28};
29
30struct pp_power_state;
31
32
33#define PP_INVALID_POWER_STATE_ID (0)
34
35
36/*
37 * An item of a list containing Power States.
38 */
39
40struct PP_StateLinkedList {
41 struct pp_power_state *next;
42 struct pp_power_state *prev;
43};
44
45
46enum PP_StateUILabel {
47 PP_StateUILabel_None,
48 PP_StateUILabel_Battery,
49 PP_StateUILabel_MiddleLow,
50 PP_StateUILabel_Balanced,
51 PP_StateUILabel_MiddleHigh,
52 PP_StateUILabel_Performance,
53 PP_StateUILabel_BACO
54};
55
56enum PP_StateClassificationFlag {
57 PP_StateClassificationFlag_Boot = 0x0001,
58 PP_StateClassificationFlag_Thermal = 0x0002,
59 PP_StateClassificationFlag_LimitedPowerSource = 0x0004,
60 PP_StateClassificationFlag_Rest = 0x0008,
61 PP_StateClassificationFlag_Forced = 0x0010,
62 PP_StateClassificationFlag_User3DPerformance = 0x0020,
63 PP_StateClassificationFlag_User2DPerformance = 0x0040,
64 PP_StateClassificationFlag_3DPerformance = 0x0080,
65 PP_StateClassificationFlag_ACOverdriveTemplate = 0x0100,
66 PP_StateClassificationFlag_Uvd = 0x0200,
67 PP_StateClassificationFlag_3DPerformanceLow = 0x0400,
68 PP_StateClassificationFlag_ACPI = 0x0800,
69 PP_StateClassificationFlag_HD2 = 0x1000,
70 PP_StateClassificationFlag_UvdHD = 0x2000,
71 PP_StateClassificationFlag_UvdSD = 0x4000,
72 PP_StateClassificationFlag_UserDCPerformance = 0x8000,
73 PP_StateClassificationFlag_DCOverdriveTemplate = 0x10000,
74 PP_StateClassificationFlag_BACO = 0x20000,
75 PP_StateClassificationFlag_LimitedPowerSource_2 = 0x40000,
76 PP_StateClassificationFlag_ULV = 0x80000,
77 PP_StateClassificationFlag_UvdMVC = 0x100000,
78};
79
80typedef unsigned int PP_StateClassificationFlags;
81
82struct PP_StateClassificationBlock {
83 enum PP_StateUILabel ui_label;
84 enum PP_StateClassificationFlag flags;
85 int bios_index;
86 bool temporary_state;
87 bool to_be_deleted;
88};
89
90struct PP_StatePcieBlock {
91 unsigned int lanes;
92};
93
94enum PP_RefreshrateSource {
95 PP_RefreshrateSource_EDID,
96 PP_RefreshrateSource_Explicit
97};
98
99struct PP_StateDisplayBlock {
100 bool disableFrameModulation;
101 bool limitRefreshrate;
102 enum PP_RefreshrateSource refreshrateSource;
103 int explicitRefreshrate;
104 int edidRefreshrateIndex;
105 bool enableVariBright;
106};
107
108struct PP_StateMemroyBlock {
109 bool dllOff;
110 uint8_t m3arb;
111 uint8_t unused[3];
112};
113
114struct PP_StateSoftwareAlgorithmBlock {
115 bool disableLoadBalancing;
116 bool enableSleepForTimestamps;
117};
118
119#define PP_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
120
121/**
122 * Type to hold a temperature range.
123 */
124struct PP_TemperatureRange {
125 int min;
126 int max;
127 int edge_emergency_max;
128 int hotspot_min;
129 int hotspot_crit_max;
130 int hotspot_emergency_max;
131 int mem_min;
132 int mem_crit_max;
133 int mem_emergency_max;
134 int sw_ctf_threshold;
135};
136
137struct PP_StateValidationBlock {
138 bool singleDisplayOnly;
139 bool disallowOnDC;
140 uint8_t supportedPowerLevels;
141};
142
143struct PP_UVD_CLOCKS {
144 uint32_t VCLK;
145 uint32_t DCLK;
146};
147
148/**
149* Structure to hold a PowerPlay Power State.
150*/
151struct pp_power_state {
152 uint32_t id;
153 struct PP_StateLinkedList orderedList;
154 struct PP_StateLinkedList allStatesList;
155
156 struct PP_StateClassificationBlock classification;
157 struct PP_StateValidationBlock validation;
158 struct PP_StatePcieBlock pcie;
159 struct PP_StateDisplayBlock display;
160 struct PP_StateMemroyBlock memory;
161 struct PP_TemperatureRange temperatures;
162 struct PP_StateSoftwareAlgorithmBlock software;
163 struct PP_UVD_CLOCKS uvd_clocks;
164 struct pp_hw_power_state hardware;
165};
166
167enum PP_MMProfilingState {
168 PP_MMProfilingState_NA = 0,
169 PP_MMProfilingState_Started,
170 PP_MMProfilingState_Stopped
171};
172
173struct pp_clock_engine_request {
174 unsigned long client_type;
175 unsigned long ctx_id;
176 uint64_t context_handle;
177 unsigned long sclk;
178 unsigned long sclk_hard_min;
179 unsigned long mclk;
180 unsigned long iclk;
181 unsigned long evclk;
182 unsigned long ecclk;
183 unsigned long ecclk_hard_min;
184 unsigned long vclk;
185 unsigned long dclk;
186 unsigned long sclk_over_drive;
187 unsigned long mclk_over_drive;
188 unsigned long sclk_threshold;
189 unsigned long flag;
190 unsigned long vclk_ceiling;
191 unsigned long dclk_ceiling;
192 unsigned long num_cus;
193 unsigned long pm_flag;
194 enum PP_MMProfilingState mm_profiling_state;
195};
196
197#endif
198

source code of linux/drivers/gpu/drm/amd/pm/powerplay/inc/power_state.h