1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _SMU8_HWMGR_H_
25#define _SMU8_HWMGR_H_
26
27#include "cgs_common.h"
28#include "ppatomctrl.h"
29
30#define SMU8_NUM_NBPSTATES 4
31#define SMU8_NUM_NBPMEMORYCLOCK 2
32#define MAX_DISPLAY_CLOCK_LEVEL 8
33#define SMU8_MAX_HARDWARE_POWERLEVELS 8
34#define SMU8_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
35#define SMU8_MIN_DEEP_SLEEP_SCLK 800
36
37/* Carrizo device IDs */
38#define DEVICE_ID_CZ_9870 0x9870
39#define DEVICE_ID_CZ_9874 0x9874
40#define DEVICE_ID_CZ_9875 0x9875
41#define DEVICE_ID_CZ_9876 0x9876
42#define DEVICE_ID_CZ_9877 0x9877
43
44struct smu8_dpm_entry {
45 uint32_t soft_min_clk;
46 uint32_t hard_min_clk;
47 uint32_t soft_max_clk;
48 uint32_t hard_max_clk;
49};
50
51struct smu8_sys_info {
52 uint32_t bootup_uma_clock;
53 uint32_t bootup_engine_clock;
54 uint32_t dentist_vco_freq;
55 uint32_t nb_dpm_enable;
56 uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK];
57 uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES];
58 uint16_t nbp_voltage_index[SMU8_NUM_NBPSTATES];
59 uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL];
60 uint16_t bootup_nb_voltage_index;
61 uint8_t htc_tmp_lmt;
62 uint8_t htc_hyst_lmt;
63 uint32_t system_config;
64 uint32_t uma_channel_number;
65};
66
67#define MAX_DISPLAYPHY_IDS 0x8
68#define DISPLAYPHY_LANEMASK 0xF
69#define UNKNOWN_TRANSMITTER_PHY_ID (-1)
70
71#define DISPLAYPHY_PHYID_SHIFT 24
72#define DISPLAYPHY_LANESELECT_SHIFT 16
73
74#define DISPLAYPHY_RX_SELECT 0x1
75#define DISPLAYPHY_TX_SELECT 0x2
76#define DISPLAYPHY_CORE_SELECT 0x4
77
78#define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \
79 (((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \
80 ((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \
81 ((rx) ? DISPLAYPHY_RX_SELECT : 0) | \
82 ((tx) ? DISPLAYPHY_TX_SELECT : 0) | \
83 ((core) ? DISPLAYPHY_CORE_SELECT : 0))
84
85struct smu8_display_phy_info_entry {
86 uint8_t phy_present;
87 uint8_t active_lane_mapping;
88 uint8_t display_config_type;
89 uint8_t active_number_of_lanes;
90};
91
92#define SMU8_MAX_DISPLAYPHY_IDS 10
93
94struct smu8_display_phy_info {
95 bool display_phy_access_initialized;
96 struct smu8_display_phy_info_entry entries[SMU8_MAX_DISPLAYPHY_IDS];
97};
98
99struct smu8_power_level {
100 uint32_t engineClock;
101 uint8_t vddcIndex;
102 uint8_t dsDividerIndex;
103 uint8_t ssDividerIndex;
104 uint8_t allowGnbSlow;
105 uint8_t forceNBPstate;
106 uint8_t display_wm;
107 uint8_t vce_wm;
108 uint8_t numSIMDToPowerDown;
109 uint8_t hysteresis_up;
110 uint8_t rsv[3];
111};
112
113struct smu8_uvd_clocks {
114 uint32_t vclk;
115 uint32_t dclk;
116 uint32_t vclk_low_divider;
117 uint32_t vclk_high_divider;
118 uint32_t dclk_low_divider;
119 uint32_t dclk_high_divider;
120};
121
122enum smu8_pstate_previous_action {
123 DO_NOTHING = 1,
124 FORCE_HIGH,
125 CANCEL_FORCE_HIGH
126};
127
128struct pp_disable_nb_ps_flags {
129 union {
130 struct {
131 uint32_t entry : 1;
132 uint32_t display : 1;
133 uint32_t driver: 1;
134 uint32_t vce : 1;
135 uint32_t uvd : 1;
136 uint32_t acp : 1;
137 uint32_t reserved: 26;
138 } bits;
139 uint32_t u32All;
140 };
141};
142
143struct smu8_power_state {
144 unsigned int magic;
145 uint32_t level;
146 struct smu8_uvd_clocks uvd_clocks;
147 uint32_t evclk;
148 uint32_t ecclk;
149 uint32_t samclk;
150 uint32_t acpclk;
151 bool need_dfs_bypass;
152 uint32_t nbps_flags;
153 uint32_t bapm_flags;
154 uint8_t dpm_0_pg_nb_ps_low;
155 uint8_t dpm_0_pg_nb_ps_high;
156 uint8_t dpm_x_nb_ps_low;
157 uint8_t dpm_x_nb_ps_high;
158 enum smu8_pstate_previous_action action;
159 struct smu8_power_level levels[SMU8_MAX_HARDWARE_POWERLEVELS];
160 struct pp_disable_nb_ps_flags disable_nb_ps_flag;
161};
162
163#define DPMFlags_SCLK_Enabled 0x00000001
164#define DPMFlags_UVD_Enabled 0x00000002
165#define DPMFlags_VCE_Enabled 0x00000004
166#define DPMFlags_ACP_Enabled 0x00000008
167#define DPMFlags_ForceHighestValid 0x40000000
168#define DPMFlags_Debug 0x80000000
169
170#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 /* bit 0 */
171#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000 /* bit 23 */
172#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000 /* bit 24 */
173
174struct cc6_settings {
175 bool cc6_setting_changed;
176 bool nb_pstate_switch_disable;/* controls NB PState switch */
177 bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
178 bool cpu_pstate_disable;
179 uint32_t cpu_pstate_separation_time;
180};
181
182struct smu8_hwmgr {
183 uint32_t dpm_interval;
184
185 uint32_t voltage_drop_threshold;
186
187 uint32_t voting_rights_clients;
188
189 uint32_t disable_driver_thermal_policy;
190
191 uint32_t static_screen_threshold;
192
193 uint32_t gfx_power_gating_threshold;
194
195 uint32_t activity_hysteresis;
196 uint32_t bootup_sclk_divider;
197 uint32_t gfx_ramp_step;
198 uint32_t gfx_ramp_delay; /* in micro-seconds */
199
200 uint32_t thermal_auto_throttling_treshold;
201
202 struct smu8_sys_info sys_info;
203
204 struct smu8_power_level boot_power_level;
205 struct smu8_power_state *smu8_current_ps;
206 struct smu8_power_state *smu8_requested_ps;
207
208 uint32_t mgcg_cgtt_local0;
209 uint32_t mgcg_cgtt_local1;
210
211 uint32_t tdr_clock; /* in 10khz unit */
212
213 uint32_t ddi_power_gating_disabled;
214 uint32_t disable_gfx_power_gating_in_uvd;
215 uint32_t disable_nb_ps3_in_battery;
216
217 uint32_t lock_nb_ps_in_uvd_play_back;
218
219 struct smu8_display_phy_info display_phy_info;
220 uint32_t vce_slow_sclk_threshold; /* default 200mhz */
221 uint32_t dce_slow_sclk_threshold; /* default 300mhz */
222 uint32_t min_sclk_did; /* minimum sclk divider */
223
224 bool disp_clk_bypass;
225 bool disp_clk_bypass_pending;
226 uint32_t bapm_enabled;
227 uint32_t clock_slow_down_freq;
228 uint32_t skip_clock_slow_down;
229 uint32_t enable_nb_ps_policy;
230 uint32_t voltage_drop_in_dce_power_gating;
231 uint32_t uvd_dpm_interval;
232 uint32_t override_dynamic_mgpg;
233 uint32_t lclk_deep_enabled;
234
235 uint32_t uvd_performance;
236
237 bool video_start;
238 bool battery_state;
239 uint32_t lowest_valid;
240 uint32_t highest_valid;
241 uint32_t high_voltage_threshold;
242 uint32_t is_nb_dpm_enabled;
243 struct cc6_settings cc6_settings;
244 uint32_t is_voltage_island_enabled;
245
246 bool pgacpinit;
247
248 uint8_t disp_config;
249
250 /* PowerTune */
251 uint32_t power_containment_features;
252 bool cac_enabled;
253 bool disable_uvd_power_tune_feature;
254 bool enable_ba_pm_feature;
255 bool enable_tdc_limit_feature;
256
257 uint32_t sram_end;
258 uint32_t dpm_table_start;
259 uint32_t soft_regs_start;
260
261 uint8_t uvd_level_count;
262 uint8_t vce_level_count;
263
264 uint8_t acp_level_count;
265 uint8_t samu_level_count;
266 uint32_t fps_high_threshold;
267 uint32_t fps_low_threshold;
268
269 uint32_t dpm_flags;
270 struct smu8_dpm_entry sclk_dpm;
271 struct smu8_dpm_entry uvd_dpm;
272 struct smu8_dpm_entry vce_dpm;
273 struct smu8_dpm_entry acp_dpm;
274
275 uint8_t uvd_boot_level;
276 uint8_t vce_boot_level;
277 uint8_t acp_boot_level;
278 uint8_t samu_boot_level;
279 uint8_t uvd_interval;
280 uint8_t vce_interval;
281 uint8_t acp_interval;
282 uint8_t samu_interval;
283
284 uint8_t graphics_interval;
285 uint8_t graphics_therm_throttle_enable;
286 uint8_t graphics_voltage_change_enable;
287
288 uint8_t graphics_clk_slow_enable;
289 uint8_t graphics_clk_slow_divider;
290
291 uint32_t display_cac;
292 uint32_t low_sclk_interrupt_threshold;
293
294 uint32_t dram_log_addr_h;
295 uint32_t dram_log_addr_l;
296 uint32_t dram_log_phy_addr_h;
297 uint32_t dram_log_phy_addr_l;
298 uint32_t dram_log_buff_size;
299
300 bool uvd_power_gated;
301 bool vce_power_gated;
302 bool samu_power_gated;
303 bool acp_power_gated;
304 bool acp_power_up_no_dsp;
305 uint32_t active_process_mask;
306
307 uint32_t max_sclk_level;
308 uint32_t num_of_clk_entries;
309};
310
311#endif /* _SMU8_HWMGR_H_ */
312

source code of linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h