1	/*
2	* Copyright (C) 2017 Advanced Micro Devices, Inc.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included
12	* in all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18	* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20	*/
21	#if !defined (_vega10_ENUM_HEADER)
22	#define _vega10_ENUM_HEADER
23
24	#ifndef _DRIVER_BUILD
25	#ifndef GL_ZERO
26	#define GL__ZERO BLEND_ZERO
27	#define GL__ONE BLEND_ONE
28	#define GL__SRC_COLOR BLEND_SRC_COLOR
29	#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
30	#define GL__DST_COLOR BLEND_DST_COLOR
31	#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
32	#define GL__SRC_ALPHA BLEND_SRC_ALPHA
33	#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
34	#define GL__DST_ALPHA BLEND_DST_ALPHA
35	#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
36	#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
37	#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
38	#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
39	#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
40	#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
41	#endif
42	#endif
43
44	/*******************************************************
45	* GDS DATA_TYPE Enums
46	*******************************************************/
47
48	#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
49	#define ENUMS_GDS_PERFCOUNT_SELECT_H
50	typedef enum GDS_PERFCOUNT_SELECT {
51	GDS_PERF_SEL_DS_ADDR_CONFL = 0,
52	GDS_PERF_SEL_DS_BANK_CONFL = 1,
53	GDS_PERF_SEL_WBUF_FLUSH = 2,
54	GDS_PERF_SEL_WR_COMP = 3,
55	GDS_PERF_SEL_WBUF_WR = 4,
56	GDS_PERF_SEL_RBUF_HIT = 5,
57	GDS_PERF_SEL_RBUF_MISS = 6,
58	GDS_PERF_SEL_SE0_SH0_NORET = 7,
59	GDS_PERF_SEL_SE0_SH0_RET = 8,
60	GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
61	GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
62	GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
63	GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
64	GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
65	GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
66	GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
67	GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
68	GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
69	GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
70	GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
71	GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
72	GDS_PERF_SEL_SE0_SH1_NORET = 21,
73	GDS_PERF_SEL_SE0_SH1_RET = 22,
74	GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
75	GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
76	GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
77	GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
78	GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
79	GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
80	GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
81	GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
82	GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
83	GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
84	GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
85	GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
86	GDS_PERF_SEL_SE1_SH0_NORET = 35,
87	GDS_PERF_SEL_SE1_SH0_RET = 36,
88	GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
89	GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
90	GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
91	GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
92	GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
93	GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
94	GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
95	GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
96	GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
97	GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
98	GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
99	GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
100	GDS_PERF_SEL_SE1_SH1_NORET = 49,
101	GDS_PERF_SEL_SE1_SH1_RET = 50,
102	GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
103	GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
104	GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
105	GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
106	GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
107	GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
108	GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
109	GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
110	GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
111	GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
112	GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
113	GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
114	GDS_PERF_SEL_SE2_SH0_NORET = 63,
115	GDS_PERF_SEL_SE2_SH0_RET = 64,
116	GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
117	GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
118	GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
119	GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
120	GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
121	GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
122	GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
123	GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
124	GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
125	GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
126	GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
127	GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
128	GDS_PERF_SEL_SE2_SH1_NORET = 77,
129	GDS_PERF_SEL_SE2_SH1_RET = 78,
130	GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
131	GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
132	GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
133	GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
134	GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
135	GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
136	GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
137	GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
138	GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
139	GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
140	GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
141	GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
142	GDS_PERF_SEL_SE3_SH0_NORET = 91,
143	GDS_PERF_SEL_SE3_SH0_RET = 92,
144	GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
145	GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
146	GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
147	GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
148	GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
149	GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
150	GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
151	GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
152	GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
153	GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
154	GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
155	GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
156	GDS_PERF_SEL_SE3_SH1_NORET = 105,
157	GDS_PERF_SEL_SE3_SH1_RET = 106,
158	GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
159	GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
160	GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
161	GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
162	GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
163	GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
164	GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
165	GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
166	GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
167	GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
168	GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
169	GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
170	GDS_PERF_SEL_GWS_RELEASED = 119,
171	GDS_PERF_SEL_GWS_BYPASS = 120,
172	} GDS_PERFCOUNT_SELECT;
173	#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
174
175	/*******************************************************
176	* Chip Enums
177	*******************************************************/
178
179	/*
180	* MEM_PWR_FORCE_CTRL enum
181	*/
182
183	typedef enum MEM_PWR_FORCE_CTRL {
184	NO_FORCE_REQUEST = 0x00000000,
185	FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186	FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187	FORCE_SHUT_DOWN_REQUEST = 0x00000003,
188	} MEM_PWR_FORCE_CTRL;
189
190	/*
191	* MEM_PWR_FORCE_CTRL2 enum
192	*/
193
194	typedef enum MEM_PWR_FORCE_CTRL2 {
195	NO_FORCE_REQ = 0x00000000,
196	FORCE_LIGHT_SLEEP_REQ = 0x00000001,
197	} MEM_PWR_FORCE_CTRL2;
198
199	/*
200	* MEM_PWR_DIS_CTRL enum
201	*/
202
203	typedef enum MEM_PWR_DIS_CTRL {
204	ENABLE_MEM_PWR_CTRL = 0x00000000,
205	DISABLE_MEM_PWR_CTRL = 0x00000001,
206	} MEM_PWR_DIS_CTRL;
207
208	/*
209	* MEM_PWR_SEL_CTRL enum
210	*/
211
212	typedef enum MEM_PWR_SEL_CTRL {
213	DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
214	DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
215	DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
216	} MEM_PWR_SEL_CTRL;
217
218	/*
219	* MEM_PWR_SEL_CTRL2 enum
220	*/
221
222	typedef enum MEM_PWR_SEL_CTRL2 {
223	DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
224	DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
225	} MEM_PWR_SEL_CTRL2;
226
227	/*
228	* RowSize enum
229	*/
230
231	typedef enum RowSize {
232	ADDR_CONFIG_1KB_ROW = 0x00000000,
233	ADDR_CONFIG_2KB_ROW = 0x00000001,
234	ADDR_CONFIG_4KB_ROW = 0x00000002,
235	} RowSize;
236
237	/*
238	* SurfaceEndian enum
239	*/
240
241	typedef enum SurfaceEndian {
242	ENDIAN_NONE = 0x00000000,
243	ENDIAN_8IN16 = 0x00000001,
244	ENDIAN_8IN32 = 0x00000002,
245	ENDIAN_8IN64 = 0x00000003,
246	} SurfaceEndian;
247
248	/*
249	* ArrayMode enum
250	*/
251
252	typedef enum ArrayMode {
253	ARRAY_LINEAR_GENERAL = 0x00000000,
254	ARRAY_LINEAR_ALIGNED = 0x00000001,
255	ARRAY_1D_TILED_THIN1 = 0x00000002,
256	ARRAY_1D_TILED_THICK = 0x00000003,
257	ARRAY_2D_TILED_THIN1 = 0x00000004,
258	ARRAY_PRT_TILED_THIN1 = 0x00000005,
259	ARRAY_PRT_2D_TILED_THIN1 = 0x00000006,
260	ARRAY_2D_TILED_THICK = 0x00000007,
261	ARRAY_2D_TILED_XTHICK = 0x00000008,
262	ARRAY_PRT_TILED_THICK = 0x00000009,
263	ARRAY_PRT_2D_TILED_THICK = 0x0000000a,
264	ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b,
265	ARRAY_3D_TILED_THIN1 = 0x0000000c,
266	ARRAY_3D_TILED_THICK = 0x0000000d,
267	ARRAY_3D_TILED_XTHICK = 0x0000000e,
268	ARRAY_PRT_3D_TILED_THICK = 0x0000000f,
269	} ArrayMode;
270
271	/*
272	* NumPipes enum
273	*/
274
275	typedef enum NumPipes {
276	ADDR_CONFIG_1_PIPE = 0x00000000,
277	ADDR_CONFIG_2_PIPE = 0x00000001,
278	ADDR_CONFIG_4_PIPE = 0x00000002,
279	ADDR_CONFIG_8_PIPE = 0x00000003,
280	ADDR_CONFIG_16_PIPE = 0x00000004,
281	ADDR_CONFIG_32_PIPE = 0x00000005,
282	} NumPipes;
283
284	/*
285	* NumBanksConfig enum
286	*/
287
288	typedef enum NumBanksConfig {
289	ADDR_CONFIG_1_BANK = 0x00000000,
290	ADDR_CONFIG_2_BANK = 0x00000001,
291	ADDR_CONFIG_4_BANK = 0x00000002,
292	ADDR_CONFIG_8_BANK = 0x00000003,
293	ADDR_CONFIG_16_BANK = 0x00000004,
294	} NumBanksConfig;
295
296	/*
297	* PipeInterleaveSize enum
298	*/
299
300	typedef enum PipeInterleaveSize {
301	ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
302	ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
303	ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002,
304	ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003,
305	} PipeInterleaveSize;
306
307	/*
308	* BankInterleaveSize enum
309	*/
310
311	typedef enum BankInterleaveSize {
312	ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000,
313	ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001,
314	ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002,
315	ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003,
316	} BankInterleaveSize;
317
318	/*
319	* NumShaderEngines enum
320	*/
321
322	typedef enum NumShaderEngines {
323	ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000,
324	ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001,
325	ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002,
326	ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003,
327	} NumShaderEngines;
328
329	/*
330	* NumRbPerShaderEngine enum
331	*/
332
333	typedef enum NumRbPerShaderEngine {
334	ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000,
335	ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001,
336	ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002,
337	} NumRbPerShaderEngine;
338
339	/*
340	* NumGPUs enum
341	*/
342
343	typedef enum NumGPUs {
344	ADDR_CONFIG_1_GPU = 0x00000000,
345	ADDR_CONFIG_2_GPU = 0x00000001,
346	ADDR_CONFIG_4_GPU = 0x00000002,
347	ADDR_CONFIG_8_GPU = 0x00000003,
348	} NumGPUs;
349
350	/*
351	* NumMaxCompressedFragments enum
352	*/
353
354	typedef enum NumMaxCompressedFragments {
355	ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000,
356	ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001,
357	ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002,
358	ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003,
359	} NumMaxCompressedFragments;
360
361	/*
362	* ShaderEngineTileSize enum
363	*/
364
365	typedef enum ShaderEngineTileSize {
366	ADDR_CONFIG_SE_TILE_16 = 0x00000000,
367	ADDR_CONFIG_SE_TILE_32 = 0x00000001,
368	} ShaderEngineTileSize;
369
370	/*
371	* MultiGPUTileSize enum
372	*/
373
374	typedef enum MultiGPUTileSize {
375	ADDR_CONFIG_GPU_TILE_16 = 0x00000000,
376	ADDR_CONFIG_GPU_TILE_32 = 0x00000001,
377	ADDR_CONFIG_GPU_TILE_64 = 0x00000002,
378	ADDR_CONFIG_GPU_TILE_128 = 0x00000003,
379	} MultiGPUTileSize;
380
381	/*
382	* NumLowerPipes enum
383	*/
384
385	typedef enum NumLowerPipes {
386	ADDR_CONFIG_1_LOWER_PIPES = 0x00000000,
387	ADDR_CONFIG_2_LOWER_PIPES = 0x00000001,
388	} NumLowerPipes;
389
390	/*
391	* ColorTransform enum
392	*/
393
394	typedef enum ColorTransform {
395	DCC_CT_AUTO = 0x00000000,
396	DCC_CT_NONE = 0x00000001,
397	ABGR_TO_A_BG_G_RB = 0x00000002,
398	BGRA_TO_BG_G_RB_A = 0x00000003,
399	} ColorTransform;
400
401	/*
402	* CompareRef enum
403	*/
404
405	typedef enum CompareRef {
406	REF_NEVER = 0x00000000,
407	REF_LESS = 0x00000001,
408	REF_EQUAL = 0x00000002,
409	REF_LEQUAL = 0x00000003,
410	REF_GREATER = 0x00000004,
411	REF_NOTEQUAL = 0x00000005,
412	REF_GEQUAL = 0x00000006,
413	REF_ALWAYS = 0x00000007,
414	} CompareRef;
415
416	/*
417	* ReadSize enum
418	*/
419
420	typedef enum ReadSize {
421	READ_256_BITS = 0x00000000,
422	READ_512_BITS = 0x00000001,
423	} ReadSize;
424
425	/*
426	* DepthFormat enum
427	*/
428
429	typedef enum DepthFormat {
430	DEPTH_INVALID = 0x00000000,
431	DEPTH_16 = 0x00000001,
432	DEPTH_X8_24 = 0x00000002,
433	DEPTH_8_24 = 0x00000003,
434	DEPTH_X8_24_FLOAT = 0x00000004,
435	DEPTH_8_24_FLOAT = 0x00000005,
436	DEPTH_32_FLOAT = 0x00000006,
437	DEPTH_X24_8_32_FLOAT = 0x00000007,
438	} DepthFormat;
439
440	/*
441	* ZFormat enum
442	*/
443
444	typedef enum ZFormat {
445	Z_INVALID = 0x00000000,
446	Z_16 = 0x00000001,
447	Z_24 = 0x00000002,
448	Z_32_FLOAT = 0x00000003,
449	} ZFormat;
450
451	/*
452	* StencilFormat enum
453	*/
454
455	typedef enum StencilFormat {
456	STENCIL_INVALID = 0x00000000,
457	STENCIL_8 = 0x00000001,
458	} StencilFormat;
459
460	/*
461	* CmaskMode enum
462	*/
463
464	typedef enum CmaskMode {
465	CMASK_CLEAR_NONE = 0x00000000,
466	CMASK_CLEAR_ONE = 0x00000001,
467	CMASK_CLEAR_ALL = 0x00000002,
468	CMASK_ANY_EXPANDED = 0x00000003,
469	CMASK_ALPHA0_FRAG1 = 0x00000004,
470	CMASK_ALPHA0_FRAG2 = 0x00000005,
471	CMASK_ALPHA0_FRAG4 = 0x00000006,
472	CMASK_ALPHA0_FRAGS = 0x00000007,
473	CMASK_ALPHA1_FRAG1 = 0x00000008,
474	CMASK_ALPHA1_FRAG2 = 0x00000009,
475	CMASK_ALPHA1_FRAG4 = 0x0000000a,
476	CMASK_ALPHA1_FRAGS = 0x0000000b,
477	CMASK_ALPHAX_FRAG1 = 0x0000000c,
478	CMASK_ALPHAX_FRAG2 = 0x0000000d,
479	CMASK_ALPHAX_FRAG4 = 0x0000000e,
480	CMASK_ALPHAX_FRAGS = 0x0000000f,
481	} CmaskMode;
482
483	/*
484	* QuadExportFormat enum
485	*/
486
487	typedef enum QuadExportFormat {
488	EXPORT_UNUSED = 0x00000000,
489	EXPORT_32_R = 0x00000001,
490	EXPORT_32_GR = 0x00000002,
491	EXPORT_32_AR = 0x00000003,
492	EXPORT_FP16_ABGR = 0x00000004,
493	EXPORT_UNSIGNED16_ABGR = 0x00000005,
494	EXPORT_SIGNED16_ABGR = 0x00000006,
495	EXPORT_32_ABGR = 0x00000007,
496	EXPORT_32BPP_8PIX = 0x00000008,
497	EXPORT_16_16_UNSIGNED_8PIX = 0x00000009,
498	EXPORT_16_16_SIGNED_8PIX = 0x0000000a,
499	EXPORT_16_16_FLOAT_8PIX = 0x0000000b,
500	} QuadExportFormat;
501
502	/*
503	* QuadExportFormatOld enum
504	*/
505
506	typedef enum QuadExportFormatOld {
507	EXPORT_4P_32BPC_ABGR = 0x00000000,
508	EXPORT_4P_16BPC_ABGR = 0x00000001,
509	EXPORT_4P_32BPC_GR = 0x00000002,
510	EXPORT_4P_32BPC_AR = 0x00000003,
511	EXPORT_2P_32BPC_ABGR = 0x00000004,
512	EXPORT_8P_32BPC_R = 0x00000005,
513	} QuadExportFormatOld;
514
515	/*
516	* ColorFormat enum
517	*/
518
519	typedef enum ColorFormat {
520	COLOR_INVALID = 0x00000000,
521	COLOR_8 = 0x00000001,
522	COLOR_16 = 0x00000002,
523	COLOR_8_8 = 0x00000003,
524	COLOR_32 = 0x00000004,
525	COLOR_16_16 = 0x00000005,
526	COLOR_10_11_11 = 0x00000006,
527	COLOR_11_11_10 = 0x00000007,
528	COLOR_10_10_10_2 = 0x00000008,
529	COLOR_2_10_10_10 = 0x00000009,
530	COLOR_8_8_8_8 = 0x0000000a,
531	COLOR_32_32 = 0x0000000b,
532	COLOR_16_16_16_16 = 0x0000000c,
533	COLOR_RESERVED_13 = 0x0000000d,
534	COLOR_32_32_32_32 = 0x0000000e,
535	COLOR_RESERVED_15 = 0x0000000f,
536	COLOR_5_6_5 = 0x00000010,
537	COLOR_1_5_5_5 = 0x00000011,
538	COLOR_5_5_5_1 = 0x00000012,
539	COLOR_4_4_4_4 = 0x00000013,
540	COLOR_8_24 = 0x00000014,
541	COLOR_24_8 = 0x00000015,
542	COLOR_X24_8_32_FLOAT = 0x00000016,
543	COLOR_RESERVED_23 = 0x00000017,
544	COLOR_RESERVED_24 = 0x00000018,
545	COLOR_RESERVED_25 = 0x00000019,
546	COLOR_RESERVED_26 = 0x0000001a,
547	COLOR_RESERVED_27 = 0x0000001b,
548	COLOR_RESERVED_28 = 0x0000001c,
549	COLOR_RESERVED_29 = 0x0000001d,
550	COLOR_RESERVED_30 = 0x0000001e,
551	COLOR_2_10_10_10_6E4 = 0x0000001f,
552	} ColorFormat;
553
554	/*
555	* SurfaceFormat enum
556	*/
557
558	typedef enum SurfaceFormat {
559	FMT_INVALID = 0x00000000,
560	FMT_8 = 0x00000001,
561	FMT_16 = 0x00000002,
562	FMT_8_8 = 0x00000003,
563	FMT_32 = 0x00000004,
564	FMT_16_16 = 0x00000005,
565	FMT_10_11_11 = 0x00000006,
566	FMT_11_11_10 = 0x00000007,
567	FMT_10_10_10_2 = 0x00000008,
568	FMT_2_10_10_10 = 0x00000009,
569	FMT_8_8_8_8 = 0x0000000a,
570	FMT_32_32 = 0x0000000b,
571	FMT_16_16_16_16 = 0x0000000c,
572	FMT_32_32_32 = 0x0000000d,
573	FMT_32_32_32_32 = 0x0000000e,
574	FMT_RESERVED_4 = 0x0000000f,
575	FMT_5_6_5 = 0x00000010,
576	FMT_1_5_5_5 = 0x00000011,
577	FMT_5_5_5_1 = 0x00000012,
578	FMT_4_4_4_4 = 0x00000013,
579	FMT_8_24 = 0x00000014,
580	FMT_24_8 = 0x00000015,
581	FMT_X24_8_32_FLOAT = 0x00000016,
582	FMT_RESERVED_33 = 0x00000017,
583	FMT_11_11_10_FLOAT = 0x00000018,
584	FMT_16_FLOAT = 0x00000019,
585	FMT_32_FLOAT = 0x0000001a,
586	FMT_16_16_FLOAT = 0x0000001b,
587	FMT_8_24_FLOAT = 0x0000001c,
588	FMT_24_8_FLOAT = 0x0000001d,
589	FMT_32_32_FLOAT = 0x0000001e,
590	FMT_10_11_11_FLOAT = 0x0000001f,
591	FMT_16_16_16_16_FLOAT = 0x00000020,
592	FMT_3_3_2 = 0x00000021,
593	FMT_6_5_5 = 0x00000022,
594	FMT_32_32_32_32_FLOAT = 0x00000023,
595	FMT_RESERVED_36 = 0x00000024,
596	FMT_1 = 0x00000025,
597	FMT_1_REVERSED = 0x00000026,
598	FMT_GB_GR = 0x00000027,
599	FMT_BG_RG = 0x00000028,
600	FMT_32_AS_8 = 0x00000029,
601	FMT_32_AS_8_8 = 0x0000002a,
602	FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
603	FMT_8_8_8 = 0x0000002c,
604	FMT_16_16_16 = 0x0000002d,
605	FMT_16_16_16_FLOAT = 0x0000002e,
606	FMT_4_4 = 0x0000002f,
607	FMT_32_32_32_FLOAT = 0x00000030,
608	FMT_BC1 = 0x00000031,
609	FMT_BC2 = 0x00000032,
610	FMT_BC3 = 0x00000033,
611	FMT_BC4 = 0x00000034,
612	FMT_BC5 = 0x00000035,
613	FMT_BC6 = 0x00000036,
614	FMT_BC7 = 0x00000037,
615	FMT_32_AS_32_32_32_32 = 0x00000038,
616	FMT_APC3 = 0x00000039,
617	FMT_APC4 = 0x0000003a,
618	FMT_APC5 = 0x0000003b,
619	FMT_APC6 = 0x0000003c,
620	FMT_APC7 = 0x0000003d,
621	FMT_CTX1 = 0x0000003e,
622	FMT_RESERVED_63 = 0x0000003f,
623	} SurfaceFormat;
624
625	/*
626	* BUF_DATA_FORMAT enum
627	*/
628
629	typedef enum BUF_DATA_FORMAT {
630	BUF_DATA_FORMAT_INVALID = 0x00000000,
631	BUF_DATA_FORMAT_8 = 0x00000001,
632	BUF_DATA_FORMAT_16 = 0x00000002,
633	BUF_DATA_FORMAT_8_8 = 0x00000003,
634	BUF_DATA_FORMAT_32 = 0x00000004,
635	BUF_DATA_FORMAT_16_16 = 0x00000005,
636	BUF_DATA_FORMAT_10_11_11 = 0x00000006,
637	BUF_DATA_FORMAT_11_11_10 = 0x00000007,
638	BUF_DATA_FORMAT_10_10_10_2 = 0x00000008,
639	BUF_DATA_FORMAT_2_10_10_10 = 0x00000009,
640	BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a,
641	BUF_DATA_FORMAT_32_32 = 0x0000000b,
642	BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c,
643	BUF_DATA_FORMAT_32_32_32 = 0x0000000d,
644	BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e,
645	BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f,
646	} BUF_DATA_FORMAT;
647
648	/*
649	* IMG_DATA_FORMAT enum
650	*/
651
652	typedef enum IMG_DATA_FORMAT {
653	IMG_DATA_FORMAT_INVALID = 0x00000000,
654	IMG_DATA_FORMAT_8 = 0x00000001,
655	IMG_DATA_FORMAT_16 = 0x00000002,
656	IMG_DATA_FORMAT_8_8 = 0x00000003,
657	IMG_DATA_FORMAT_32 = 0x00000004,
658	IMG_DATA_FORMAT_16_16 = 0x00000005,
659	IMG_DATA_FORMAT_10_11_11 = 0x00000006,
660	IMG_DATA_FORMAT_11_11_10 = 0x00000007,
661	IMG_DATA_FORMAT_10_10_10_2 = 0x00000008,
662	IMG_DATA_FORMAT_2_10_10_10 = 0x00000009,
663	IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a,
664	IMG_DATA_FORMAT_32_32 = 0x0000000b,
665	IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c,
666	IMG_DATA_FORMAT_32_32_32 = 0x0000000d,
667	IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e,
668	IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f,
669	IMG_DATA_FORMAT_5_6_5 = 0x00000010,
670	IMG_DATA_FORMAT_1_5_5_5 = 0x00000011,
671	IMG_DATA_FORMAT_5_5_5_1 = 0x00000012,
672	IMG_DATA_FORMAT_4_4_4_4 = 0x00000013,
673	IMG_DATA_FORMAT_8_24 = 0x00000014,
674	IMG_DATA_FORMAT_24_8 = 0x00000015,
675	IMG_DATA_FORMAT_X24_8_32 = 0x00000016,
676	IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x00000017,
677	IMG_DATA_FORMAT_ETC2_RGB = 0x00000018,
678	IMG_DATA_FORMAT_ETC2_RGBA = 0x00000019,
679	IMG_DATA_FORMAT_ETC2_R = 0x0000001a,
680	IMG_DATA_FORMAT_ETC2_RG = 0x0000001b,
681	IMG_DATA_FORMAT_ETC2_RGBA1 = 0x0000001c,
682	IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d,
683	IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e,
684	IMG_DATA_FORMAT_6E4 = 0x0000001f,
685	IMG_DATA_FORMAT_GB_GR = 0x00000020,
686	IMG_DATA_FORMAT_BG_RG = 0x00000021,
687	IMG_DATA_FORMAT_5_9_9_9 = 0x00000022,
688	IMG_DATA_FORMAT_BC1 = 0x00000023,
689	IMG_DATA_FORMAT_BC2 = 0x00000024,
690	IMG_DATA_FORMAT_BC3 = 0x00000025,
691	IMG_DATA_FORMAT_BC4 = 0x00000026,
692	IMG_DATA_FORMAT_BC5 = 0x00000027,
693	IMG_DATA_FORMAT_BC6 = 0x00000028,
694	IMG_DATA_FORMAT_BC7 = 0x00000029,
695	IMG_DATA_FORMAT_16_AS_32_32 = 0x0000002a,
696	IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x0000002b,
697	IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x0000002c,
698	IMG_DATA_FORMAT_FMASK = 0x0000002d,
699	IMG_DATA_FORMAT_ASTC_2D_LDR = 0x0000002e,
700	IMG_DATA_FORMAT_ASTC_2D_HDR = 0x0000002f,
701	IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 0x00000030,
702	IMG_DATA_FORMAT_ASTC_3D_LDR = 0x00000031,
703	IMG_DATA_FORMAT_ASTC_3D_HDR = 0x00000032,
704	IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 0x00000033,
705	IMG_DATA_FORMAT_N_IN_16 = 0x00000034,
706	IMG_DATA_FORMAT_N_IN_16_16 = 0x00000035,
707	IMG_DATA_FORMAT_N_IN_16_16_16_16 = 0x00000036,
708	IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 0x00000037,
709	IMG_DATA_FORMAT_RESERVED_56 = 0x00000038,
710	IMG_DATA_FORMAT_4_4 = 0x00000039,
711	IMG_DATA_FORMAT_6_5_5 = 0x0000003a,
712	IMG_DATA_FORMAT_RESERVED_59 = 0x0000003b,
713	IMG_DATA_FORMAT_RESERVED_60 = 0x0000003c,
714	IMG_DATA_FORMAT_8_AS_32 = 0x0000003d,
715	IMG_DATA_FORMAT_8_AS_32_32 = 0x0000003e,
716	IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f,
717	} IMG_DATA_FORMAT;
718
719	/*
720	* BUF_NUM_FORMAT enum
721	*/
722
723	typedef enum BUF_NUM_FORMAT {
724	BUF_NUM_FORMAT_UNORM = 0x00000000,
725	BUF_NUM_FORMAT_SNORM = 0x00000001,
726	BUF_NUM_FORMAT_USCALED = 0x00000002,
727	BUF_NUM_FORMAT_SSCALED = 0x00000003,
728	BUF_NUM_FORMAT_UINT = 0x00000004,
729	BUF_NUM_FORMAT_SINT = 0x00000005,
730	BUF_NUM_FORMAT_UNORM_UINT = 0x00000006,
731	BUF_NUM_FORMAT_FLOAT = 0x00000007,
732	} BUF_NUM_FORMAT;
733
734	/*
735	* IMG_NUM_FORMAT enum
736	*/
737
738	typedef enum IMG_NUM_FORMAT {
739	IMG_NUM_FORMAT_UNORM = 0x00000000,
740	IMG_NUM_FORMAT_SNORM = 0x00000001,
741	IMG_NUM_FORMAT_USCALED = 0x00000002,
742	IMG_NUM_FORMAT_SSCALED = 0x00000003,
743	IMG_NUM_FORMAT_UINT = 0x00000004,
744	IMG_NUM_FORMAT_SINT = 0x00000005,
745	IMG_NUM_FORMAT_UNORM_UINT = 0x00000006,
746	IMG_NUM_FORMAT_FLOAT = 0x00000007,
747	IMG_NUM_FORMAT_RESERVED_8 = 0x00000008,
748	IMG_NUM_FORMAT_SRGB = 0x00000009,
749	IMG_NUM_FORMAT_RESERVED_10 = 0x0000000a,
750	IMG_NUM_FORMAT_RESERVED_11 = 0x0000000b,
751	IMG_NUM_FORMAT_RESERVED_12 = 0x0000000c,
752	IMG_NUM_FORMAT_RESERVED_13 = 0x0000000d,
753	IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e,
754	IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f,
755	} IMG_NUM_FORMAT;
756
757	/*
758	* IMG_NUM_FORMAT_FMASK enum
759	*/
760
761	typedef enum IMG_NUM_FORMAT_FMASK {
762	IMG_NUM_FORMAT_FMASK_8_2_1 = 0x00000000,
763	IMG_NUM_FORMAT_FMASK_8_4_1 = 0x00000001,
764	IMG_NUM_FORMAT_FMASK_8_8_1 = 0x00000002,
765	IMG_NUM_FORMAT_FMASK_8_2_2 = 0x00000003,
766	IMG_NUM_FORMAT_FMASK_8_4_2 = 0x00000004,
767	IMG_NUM_FORMAT_FMASK_8_4_4 = 0x00000005,
768	IMG_NUM_FORMAT_FMASK_16_16_1 = 0x00000006,
769	IMG_NUM_FORMAT_FMASK_16_8_2 = 0x00000007,
770	IMG_NUM_FORMAT_FMASK_32_16_2 = 0x00000008,
771	IMG_NUM_FORMAT_FMASK_32_8_4 = 0x00000009,
772	IMG_NUM_FORMAT_FMASK_32_8_8 = 0x0000000a,
773	IMG_NUM_FORMAT_FMASK_64_16_4 = 0x0000000b,
774	IMG_NUM_FORMAT_FMASK_64_16_8 = 0x0000000c,
775	IMG_NUM_FORMAT_FMASK_RESERVED_13 = 0x0000000d,
776	IMG_NUM_FORMAT_FMASK_RESERVED_14 = 0x0000000e,
777	IMG_NUM_FORMAT_FMASK_RESERVED_15 = 0x0000000f,
778	} IMG_NUM_FORMAT_FMASK;
779
780	/*
781	* IMG_NUM_FORMAT_N_IN_16 enum
782	*/
783
784	typedef enum IMG_NUM_FORMAT_N_IN_16 {
785	IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0x00000000,
786	IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 0x00000001,
787	IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 0x00000002,
788	IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 0x00000003,
789	IMG_NUM_FORMAT_N_IN_16_UINT_10 = 0x00000004,
790	IMG_NUM_FORMAT_N_IN_16_UINT_9 = 0x00000005,
791	IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 0x00000006,
792	IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 0x00000007,
793	IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 0x00000008,
794	IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 0x00000009,
795	IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 0x0000000a,
796	IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 0x0000000b,
797	IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 0x0000000c,
798	IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 0x0000000d,
799	IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 0x0000000e,
800	IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 0x0000000f,
801	} IMG_NUM_FORMAT_N_IN_16;
802
803	/*
804	* IMG_NUM_FORMAT_ASTC_2D enum
805	*/
806
807	typedef enum IMG_NUM_FORMAT_ASTC_2D {
808	IMG_NUM_FORMAT_ASTC_2D_4x4 = 0x00000000,
809	IMG_NUM_FORMAT_ASTC_2D_5x4 = 0x00000001,
810	IMG_NUM_FORMAT_ASTC_2D_5x5 = 0x00000002,
811	IMG_NUM_FORMAT_ASTC_2D_6x5 = 0x00000003,
812	IMG_NUM_FORMAT_ASTC_2D_6x6 = 0x00000004,
813	IMG_NUM_FORMAT_ASTC_2D_8x5 = 0x00000005,
814	IMG_NUM_FORMAT_ASTC_2D_8x6 = 0x00000006,
815	IMG_NUM_FORMAT_ASTC_2D_8x8 = 0x00000007,
816	IMG_NUM_FORMAT_ASTC_2D_10x5 = 0x00000008,
817	IMG_NUM_FORMAT_ASTC_2D_10x6 = 0x00000009,
818	IMG_NUM_FORMAT_ASTC_2D_10x8 = 0x0000000a,
819	IMG_NUM_FORMAT_ASTC_2D_10x10 = 0x0000000b,
820	IMG_NUM_FORMAT_ASTC_2D_12x10 = 0x0000000c,
821	IMG_NUM_FORMAT_ASTC_2D_12x12 = 0x0000000d,
822	IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 0x0000000e,
823	IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 0x0000000f,
824	} IMG_NUM_FORMAT_ASTC_2D;
825
826	/*
827	* IMG_NUM_FORMAT_ASTC_3D enum
828	*/
829
830	typedef enum IMG_NUM_FORMAT_ASTC_3D {
831	IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0x00000000,
832	IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 0x00000001,
833	IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 0x00000002,
834	IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 0x00000003,
835	IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 0x00000004,
836	IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 0x00000005,
837	IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 0x00000006,
838	IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 0x00000007,
839	IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 0x00000008,
840	IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 0x00000009,
841	IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 0x0000000a,
842	IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 0x0000000b,
843	IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 0x0000000c,
844	IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 0x0000000d,
845	IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 0x0000000e,
846	IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 0x0000000f,
847	} IMG_NUM_FORMAT_ASTC_3D;
848
849	/*
850	* TileType enum
851	*/
852
853	typedef enum TileType {
854	ARRAY_COLOR_TILE = 0x00000000,
855	ARRAY_DEPTH_TILE = 0x00000001,
856	} TileType;
857
858	/*
859	* NonDispTilingOrder enum
860	*/
861
862	typedef enum NonDispTilingOrder {
863	ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000,
864	ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001,
865	} NonDispTilingOrder;
866
867	/*
868	* MicroTileMode enum
869	*/
870
871	typedef enum MicroTileMode {
872	ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000,
873	ADDR_SURF_THIN_MICRO_TILING = 0x00000001,
874	ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002,
875	ADDR_SURF_ROTATED_MICRO_TILING = 0x00000003,
876	ADDR_SURF_THICK_MICRO_TILING = 0x00000004,
877	} MicroTileMode;
878
879	/*
880	* TileSplit enum
881	*/
882
883	typedef enum TileSplit {
884	ADDR_SURF_TILE_SPLIT_64B = 0x00000000,
885	ADDR_SURF_TILE_SPLIT_128B = 0x00000001,
886	ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
887	ADDR_SURF_TILE_SPLIT_512B = 0x00000003,
888	ADDR_SURF_TILE_SPLIT_1KB = 0x00000004,
889	ADDR_SURF_TILE_SPLIT_2KB = 0x00000005,
890	ADDR_SURF_TILE_SPLIT_4KB = 0x00000006,
891	} TileSplit;
892
893	/*
894	* SampleSplit enum
895	*/
896
897	typedef enum SampleSplit {
898	ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000,
899	ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001,
900	ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002,
901	ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003,
902	} SampleSplit;
903
904	/*
905	* PipeConfig enum
906	*/
907
908	typedef enum PipeConfig {
909	ADDR_SURF_P2 = 0x00000000,
910	ADDR_SURF_P2_RESERVED0 = 0x00000001,
911	ADDR_SURF_P2_RESERVED1 = 0x00000002,
912	ADDR_SURF_P2_RESERVED2 = 0x00000003,
913	ADDR_SURF_P4_8x16 = 0x00000004,
914	ADDR_SURF_P4_16x16 = 0x00000005,
915	ADDR_SURF_P4_16x32 = 0x00000006,
916	ADDR_SURF_P4_32x32 = 0x00000007,
917	ADDR_SURF_P8_16x16_8x16 = 0x00000008,
918	ADDR_SURF_P8_16x32_8x16 = 0x00000009,
919	ADDR_SURF_P8_32x32_8x16 = 0x0000000a,
920	ADDR_SURF_P8_16x32_16x16 = 0x0000000b,
921	ADDR_SURF_P8_32x32_16x16 = 0x0000000c,
922	ADDR_SURF_P8_32x32_16x32 = 0x0000000d,
923	ADDR_SURF_P8_32x64_32x32 = 0x0000000e,
924	ADDR_SURF_P8_RESERVED0 = 0x0000000f,
925	ADDR_SURF_P16_32x32_8x16 = 0x00000010,
926	ADDR_SURF_P16_32x32_16x16 = 0x00000011,
927	} PipeConfig;
928
929	/*
930	* SeEnable enum
931	*/
932
933	typedef enum SeEnable {
934	ADDR_CONFIG_DISABLE_SE = 0x00000000,
935	ADDR_CONFIG_ENABLE_SE = 0x00000001,
936	} SeEnable;
937
938	/*
939	* NumBanks enum
940	*/
941
942	typedef enum NumBanks {
943	ADDR_SURF_2_BANK = 0x00000000,
944	ADDR_SURF_4_BANK = 0x00000001,
945	ADDR_SURF_8_BANK = 0x00000002,
946	ADDR_SURF_16_BANK = 0x00000003,
947	} NumBanks;
948
949	/*
950	* BankWidth enum
951	*/
952
953	typedef enum BankWidth {
954	ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
955	ADDR_SURF_BANK_WIDTH_2 = 0x00000001,
956	ADDR_SURF_BANK_WIDTH_4 = 0x00000002,
957	ADDR_SURF_BANK_WIDTH_8 = 0x00000003,
958	} BankWidth;
959
960	/*
961	* BankHeight enum
962	*/
963
964	typedef enum BankHeight {
965	ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
966	ADDR_SURF_BANK_HEIGHT_2 = 0x00000001,
967	ADDR_SURF_BANK_HEIGHT_4 = 0x00000002,
968	ADDR_SURF_BANK_HEIGHT_8 = 0x00000003,
969	} BankHeight;
970
971	/*
972	* BankWidthHeight enum
973	*/
974
975	typedef enum BankWidthHeight {
976	ADDR_SURF_BANK_WH_1 = 0x00000000,
977	ADDR_SURF_BANK_WH_2 = 0x00000001,
978	ADDR_SURF_BANK_WH_4 = 0x00000002,
979	ADDR_SURF_BANK_WH_8 = 0x00000003,
980	} BankWidthHeight;
981
982	/*
983	* MacroTileAspect enum
984	*/
985
986	typedef enum MacroTileAspect {
987	ADDR_SURF_MACRO_ASPECT_1 = 0x00000000,
988	ADDR_SURF_MACRO_ASPECT_2 = 0x00000001,
989	ADDR_SURF_MACRO_ASPECT_4 = 0x00000002,
990	ADDR_SURF_MACRO_ASPECT_8 = 0x00000003,
991	} MacroTileAspect;
992
993	/*
994	* GATCL1RequestType enum
995	*/
996
997	typedef enum GATCL1RequestType {
998	GATCL1_TYPE_NORMAL = 0x00000000,
999	GATCL1_TYPE_SHOOTDOWN = 0x00000001,
1000	GATCL1_TYPE_BYPASS = 0x00000002,
1001	} GATCL1RequestType;
1002
1003	/*
1004	* UTCL1RequestType enum
1005	*/
1006
1007	typedef enum UTCL1RequestType {
1008	UTCL1_TYPE_NORMAL = 0x00000000,
1009	UTCL1_TYPE_SHOOTDOWN = 0x00000001,
1010	UTCL1_TYPE_BYPASS = 0x00000002,
1011	} UTCL1RequestType;
1012
1013	/*
1014	* UTCL1FaultType enum
1015	*/
1016
1017	typedef enum UTCL1FaultType {
1018	UTCL1_XNACK_SUCCESS = 0x00000000,
1019	UTCL1_XNACK_RETRY = 0x00000001,
1020	UTCL1_XNACK_PRT = 0x00000002,
1021	UTCL1_XNACK_NO_RETRY = 0x00000003,
1022	} UTCL1FaultType;
1023
1024	/*
1025	* TCC_CACHE_POLICIES enum
1026	*/
1027
1028	typedef enum TCC_CACHE_POLICIES {
1029	TCC_CACHE_POLICY_LRU = 0x00000000,
1030	TCC_CACHE_POLICY_STREAM = 0x00000001,
1031	} TCC_CACHE_POLICIES;
1032
1033	/*
1034	* MTYPE enum
1035	*/
1036
1037	typedef enum MTYPE {
1038	MTYPE_NC = 0x00000000,
1039	MTYPE_WC = 0x00000001,
1040	MTYPE_RW = 0x00000001,
1041	MTYPE_CC = 0x00000002,
1042	MTYPE_UC = 0x00000003,
1043	} MTYPE;
1044
1045	/*
1046	* RMI_CID enum
1047	*/
1048
1049	typedef enum RMI_CID {
1050	RMI_CID_CC = 0x00000000,
1051	RMI_CID_FC = 0x00000001,
1052	RMI_CID_CM = 0x00000002,
1053	RMI_CID_DC = 0x00000003,
1054	RMI_CID_Z = 0x00000004,
1055	RMI_CID_S = 0x00000005,
1056	RMI_CID_TILE = 0x00000006,
1057	RMI_CID_ZPCPSD = 0x00000007,
1058	} RMI_CID;
1059
1060	/*
1061	* PERFMON_COUNTER_MODE enum
1062	*/
1063
1064	typedef enum PERFMON_COUNTER_MODE {
1065	PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
1066	PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
1067	PERFMON_COUNTER_MODE_MAX = 0x00000002,
1068	PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
1069	PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
1070	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
1071	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
1072	PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
1073	PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
1074	PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
1075	PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
1076	} PERFMON_COUNTER_MODE;
1077
1078	/*
1079	* PERFMON_SPM_MODE enum
1080	*/
1081
1082	typedef enum PERFMON_SPM_MODE {
1083	PERFMON_SPM_MODE_OFF = 0x00000000,
1084	PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
1085	PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
1086	PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
1087	PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
1088	PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
1089	PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
1090	PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
1091	PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
1092	PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
1093	PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
1094	} PERFMON_SPM_MODE;
1095
1096	/*
1097	* SurfaceTiling enum
1098	*/
1099
1100	typedef enum SurfaceTiling {
1101	ARRAY_LINEAR = 0x00000000,
1102	ARRAY_TILED = 0x00000001,
1103	} SurfaceTiling;
1104
1105	/*
1106	* SurfaceArray enum
1107	*/
1108
1109	typedef enum SurfaceArray {
1110	ARRAY_1D = 0x00000000,
1111	ARRAY_2D = 0x00000001,
1112	ARRAY_3D = 0x00000002,
1113	ARRAY_3D_SLICE = 0x00000003,
1114	} SurfaceArray;
1115
1116	/*
1117	* ColorArray enum
1118	*/
1119
1120	typedef enum ColorArray {
1121	ARRAY_2D_ALT_COLOR = 0x00000000,
1122	ARRAY_2D_COLOR = 0x00000001,
1123	ARRAY_3D_SLICE_COLOR = 0x00000003,
1124	} ColorArray;
1125
1126	/*
1127	* DepthArray enum
1128	*/
1129
1130	typedef enum DepthArray {
1131	ARRAY_2D_ALT_DEPTH = 0x00000000,
1132	ARRAY_2D_DEPTH = 0x00000001,
1133	} DepthArray;
1134
1135	/*
1136	* ENUM_NUM_SIMD_PER_CU enum
1137	*/
1138
1139	typedef enum ENUM_NUM_SIMD_PER_CU {
1140	NUM_SIMD_PER_CU = 0x00000004,
1141	} ENUM_NUM_SIMD_PER_CU;
1142
1143	/*
1144	* DSM_ENABLE_ERROR_INJECT enum
1145	*/
1146
1147	typedef enum DSM_ENABLE_ERROR_INJECT {
1148	DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
1149	DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
1150	DSM_ENABLE_ERROR_INJECT_DOUBLE = 0x00000002,
1151	DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED = 0x00000003,
1152	} DSM_ENABLE_ERROR_INJECT;
1153
1154	/*
1155	* DSM_SELECT_INJECT_DELAY enum
1156	*/
1157
1158	typedef enum DSM_SELECT_INJECT_DELAY {
1159	DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
1160	DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
1161	} DSM_SELECT_INJECT_DELAY;
1162
1163	/*
1164	* SWIZZLE_TYPE_ENUM enum
1165	*/
1166
1167	typedef enum SWIZZLE_TYPE_ENUM {
1168	SW_Z = 0x00000000,
1169	SW_S = 0x00000001,
1170	SW_D = 0x00000002,
1171	SW_R = 0x00000003,
1172	SW_L = 0x00000004,
1173	} SWIZZLE_TYPE_ENUM;
1174
1175	/*
1176	* TC_MICRO_TILE_MODE enum
1177	*/
1178
1179	typedef enum TC_MICRO_TILE_MODE {
1180	MICRO_TILE_MODE_LINEAR = 0x00000000,
1181	MICRO_TILE_MODE_ROTATED = 0x00000001,
1182	MICRO_TILE_MODE_STD_2D = 0x00000002,
1183	MICRO_TILE_MODE_STD_3D = 0x00000003,
1184	MICRO_TILE_MODE_DISPLAY_2D = 0x00000004,
1185	MICRO_TILE_MODE_DISPLAY_3D = 0x00000005,
1186	MICRO_TILE_MODE_Z_2D = 0x00000006,
1187	MICRO_TILE_MODE_Z_3D = 0x00000007,
1188	} TC_MICRO_TILE_MODE;
1189
1190	/*
1191	* SWIZZLE_MODE_ENUM enum
1192	*/
1193
1194	typedef enum SWIZZLE_MODE_ENUM {
1195	SW_LINEAR = 0x00000000,
1196	SW_256B_S = 0x00000001,
1197	SW_256B_D = 0x00000002,
1198	SW_256B_R = 0x00000003,
1199	SW_4KB_Z = 0x00000004,
1200	SW_4KB_S = 0x00000005,
1201	SW_4KB_D = 0x00000006,
1202	SW_4KB_R = 0x00000007,
1203	SW_64KB_Z = 0x00000008,
1204	SW_64KB_S = 0x00000009,
1205	SW_64KB_D = 0x0000000a,
1206	SW_64KB_R = 0x0000000b,
1207	SW_VAR_Z = 0x0000000c,
1208	SW_VAR_S = 0x0000000d,
1209	SW_VAR_D = 0x0000000e,
1210	SW_VAR_R = 0x0000000f,
1211	SW_RESERVED_16 = 0x00000010,
1212	SW_RESERVED_17 = 0x00000011,
1213	SW_RESERVED_18 = 0x00000012,
1214	SW_RESERVED_19 = 0x00000013,
1215	SW_4KB_Z_X = 0x00000014,
1216	SW_4KB_S_X = 0x00000015,
1217	SW_4KB_D_X = 0x00000016,
1218	SW_4KB_R_X = 0x00000017,
1219	SW_64KB_Z_X = 0x00000018,
1220	SW_64KB_S_X = 0x00000019,
1221	SW_64KB_D_X = 0x0000001a,
1222	SW_64KB_R_X = 0x0000001b,
1223	SW_VAR_Z_X = 0x0000001c,
1224	SW_VAR_S_X = 0x0000001d,
1225	SW_VAR_D_X = 0x0000001e,
1226	SW_VAR_R_X = 0x0000001f,
1227	SW_RESERVED_12 = 0x00000020,
1228	SW_RESERVED_13 = 0x00000021,
1229	SW_RESERVED_14 = 0x00000022,
1230	SW_RESERVED_15 = 0x00000023,
1231	} SWIZZLE_MODE_ENUM;
1232
1233	/*
1234	* PipeTiling enum
1235	*/
1236
1237	typedef enum PipeTiling {
1238	CONFIG_1_PIPE = 0x00000000,
1239	CONFIG_2_PIPE = 0x00000001,
1240	CONFIG_4_PIPE = 0x00000002,
1241	CONFIG_8_PIPE = 0x00000003,
1242	} PipeTiling;
1243
1244	/*
1245	* BankTiling enum
1246	*/
1247
1248	typedef enum BankTiling {
1249	CONFIG_4_BANK = 0x00000000,
1250	CONFIG_8_BANK = 0x00000001,
1251	} BankTiling;
1252
1253	/*
1254	* GroupInterleave enum
1255	*/
1256
1257	typedef enum GroupInterleave {
1258	CONFIG_256B_GROUP = 0x00000000,
1259	CONFIG_512B_GROUP = 0x00000001,
1260	} GroupInterleave;
1261
1262	/*
1263	* RowTiling enum
1264	*/
1265
1266	typedef enum RowTiling {
1267	CONFIG_1KB_ROW = 0x00000000,
1268	CONFIG_2KB_ROW = 0x00000001,
1269	CONFIG_4KB_ROW = 0x00000002,
1270	CONFIG_8KB_ROW = 0x00000003,
1271	CONFIG_1KB_ROW_OPT = 0x00000004,
1272	CONFIG_2KB_ROW_OPT = 0x00000005,
1273	CONFIG_4KB_ROW_OPT = 0x00000006,
1274	CONFIG_8KB_ROW_OPT = 0x00000007,
1275	} RowTiling;
1276
1277	/*
1278	* BankSwapBytes enum
1279	*/
1280
1281	typedef enum BankSwapBytes {
1282	CONFIG_128B_SWAPS = 0x00000000,
1283	CONFIG_256B_SWAPS = 0x00000001,
1284	CONFIG_512B_SWAPS = 0x00000002,
1285	CONFIG_1KB_SWAPS = 0x00000003,
1286	} BankSwapBytes;
1287
1288	/*
1289	* SampleSplitBytes enum
1290	*/
1291
1292	typedef enum SampleSplitBytes {
1293	CONFIG_1KB_SPLIT = 0x00000000,
1294	CONFIG_2KB_SPLIT = 0x00000001,
1295	CONFIG_4KB_SPLIT = 0x00000002,
1296	CONFIG_8KB_SPLIT = 0x00000003,
1297	} SampleSplitBytes;
1298
1299	/*******************************************************
1300	* AZSTREAM Enums
1301	*******************************************************/
1302
1303	/*
1304	* OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
1305	*/
1306
1307	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
1308	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000,
1309	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001,
1310	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
1311
1312	/*
1313	* OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
1314	*/
1315
1316	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
1317	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000,
1318	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001,
1319	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
1320
1321	/*
1322	* OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
1323	*/
1324
1325	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
1326	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000,
1327	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001,
1328	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
1329
1330	/*
1331	* OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
1332	*/
1333
1334	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
1335	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000,
1336	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001,
1337	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
1338
1339	/*
1340	* OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
1341	*/
1342
1343	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
1344	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000,
1345	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001,
1346	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
1347
1348	/*
1349	* OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
1350	*/
1351
1352	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
1353	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000,
1354	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001,
1355	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
1356
1357	/*
1358	* OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
1359	*/
1360
1361	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
1362	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000,
1363	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001,
1364	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
1365
1366	/*
1367	* OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
1368	*/
1369
1370	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
1371	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000,
1372	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001,
1373	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
1374
1375	/*
1376	* OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
1377	*/
1378
1379	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
1380	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000,
1381	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001,
1382	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
1383
1384	/*
1385	* OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
1386	*/
1387
1388	typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
1389	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
1390	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
1391	} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
1392
1393	/*
1394	* OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
1395	*/
1396
1397	typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
1398	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
1399	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
1400	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
1401	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
1402	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
1403	} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
1404
1405	/*
1406	* OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
1407	*/
1408
1409	typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
1410	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
1411	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
1412	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
1413	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
1414	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
1415	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
1416	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
1417	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
1418	} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
1419
1420	/*
1421	* OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
1422	*/
1423
1424	typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
1425	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
1426	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
1427	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
1428	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
1429	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
1430	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
1431	} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
1432
1433	/*
1434	* OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
1435	*/
1436
1437	typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
1438	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
1439	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
1440	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
1441	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
1442	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
1443	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
1444	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
1445	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
1446	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008,
1447	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009,
1448	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a,
1449	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b,
1450	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c,
1451	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d,
1452	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e,
1453	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f,
1454	} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
1455
1456	/*******************************************************
1457	* BLNDV Enums
1458	*******************************************************/
1459
1460	/*
1461	* BLNDV_CONTROL_BLND_MODE enum
1462	*/
1463
1464	typedef enum BLNDV_CONTROL_BLND_MODE {
1465	BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
1466	BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001,
1467	BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
1468	BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
1469	} BLNDV_CONTROL_BLND_MODE;
1470
1471	/*
1472	* BLNDV_CONTROL_BLND_STEREO_TYPE enum
1473	*/
1474
1475	typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
1476	BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
1477	BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
1478	BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
1479	BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003,
1480	} BLNDV_CONTROL_BLND_STEREO_TYPE;
1481
1482	/*
1483	* BLNDV_CONTROL_BLND_STEREO_POLARITY enum
1484	*/
1485
1486	typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
1487	BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000,
1488	BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001,
1489	} BLNDV_CONTROL_BLND_STEREO_POLARITY;
1490
1491	/*
1492	* BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum
1493	*/
1494
1495	typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
1496	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000,
1497	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001,
1498	} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
1499
1500	/*
1501	* BLNDV_CONTROL_BLND_ALPHA_MODE enum
1502	*/
1503
1504	typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
1505	BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
1506	BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
1507	BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
1508	BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003,
1509	} BLNDV_CONTROL_BLND_ALPHA_MODE;
1510
1511	/*
1512	* BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
1513	*/
1514
1515	typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
1516	BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
1517	BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
1518	} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
1519
1520	/*
1521	* BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum
1522	*/
1523
1524	typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
1525	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
1526	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001,
1527	} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
1528
1529	/*
1530	* BLNDV_SM_CONTROL2_SM_MODE enum
1531	*/
1532
1533	typedef enum BLNDV_SM_CONTROL2_SM_MODE {
1534	BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000,
1535	BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
1536	BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
1537	BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
1538	} BLNDV_SM_CONTROL2_SM_MODE;
1539
1540	/*
1541	* BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum
1542	*/
1543
1544	typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
1545	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
1546	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
1547	} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
1548
1549	/*
1550	* BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum
1551	*/
1552
1553	typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
1554	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
1555	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
1556	} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
1557
1558	/*
1559	* BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
1560	*/
1561
1562	typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
1563	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
1564	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
1565	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
1566	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
1567	} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
1568
1569	/*
1570	* BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
1571	*/
1572
1573	typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
1574	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
1575	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
1576	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
1577	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
1578	} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
1579
1580	/*
1581	* BLNDV_CONTROL2_PTI_ENABLE enum
1582	*/
1583
1584	typedef enum BLNDV_CONTROL2_PTI_ENABLE {
1585	BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x00000000,
1586	BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x00000001,
1587	} BLNDV_CONTROL2_PTI_ENABLE;
1588
1589	/*
1590	* BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
1591	*/
1592
1593	typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
1594	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
1595	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
1596	} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
1597
1598	/*
1599	* BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
1600	*/
1601
1602	typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
1603	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
1604	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
1605	} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
1606
1607	/*
1608	* BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
1609	*/
1610
1611	typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
1612	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
1613	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
1614	} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
1615
1616	/*
1617	* BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
1618	*/
1619
1620	typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
1621	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
1622	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
1623	} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
1624
1625	/*
1626	* BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
1627	*/
1628
1629	typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
1630	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
1631	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
1632	} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
1633
1634	/*
1635	* BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
1636	*/
1637
1638	typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
1639	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
1640	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
1641	} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
1642
1643	/*
1644	* BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
1645	*/
1646
1647	typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
1648	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
1649	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
1650	} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
1651
1652	/*
1653	* BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
1654	*/
1655
1656	typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
1657	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
1658	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
1659	} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
1660
1661	/*
1662	* BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
1663	*/
1664
1665	typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
1666	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
1667	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
1668	} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
1669
1670	/*
1671	* BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
1672	*/
1673
1674	typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
1675	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
1676	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
1677	} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
1678
1679	/*
1680	* BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
1681	*/
1682
1683	typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
1684	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
1685	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
1686	} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
1687
1688	/*
1689	* BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum
1690	*/
1691
1692	typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
1693	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000,
1694	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001,
1695	} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
1696
1697	/*
1698	* BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
1699	*/
1700
1701	typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
1702	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
1703	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
1704	} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
1705
1706	/*******************************************************
1707	* LBV Enums
1708	*******************************************************/
1709
1710	/*
1711	* LBV_PIXEL_DEPTH enum
1712	*/
1713
1714	typedef enum LBV_PIXEL_DEPTH {
1715	PIXEL_DEPTH_30BPP = 0x00000000,
1716	PIXEL_DEPTH_24BPP = 0x00000001,
1717	PIXEL_DEPTH_18BPP = 0x00000002,
1718	PIXEL_DEPTH_38BPP = 0x00000003,
1719	} LBV_PIXEL_DEPTH;
1720
1721	/*
1722	* LBV_PIXEL_EXPAN_MODE enum
1723	*/
1724
1725	typedef enum LBV_PIXEL_EXPAN_MODE {
1726	PIXEL_EXPAN_MODE_ZERO_EXP = 0x00000000,
1727	PIXEL_EXPAN_MODE_DYN_EXP = 0x00000001,
1728	} LBV_PIXEL_EXPAN_MODE;
1729
1730	/*
1731	* LBV_INTERLEAVE_EN enum
1732	*/
1733
1734	typedef enum LBV_INTERLEAVE_EN {
1735	INTERLEAVE_DIS = 0x00000000,
1736	INTERLEAVE_EN = 0x00000001,
1737	} LBV_INTERLEAVE_EN;
1738
1739	/*
1740	* LBV_PIXEL_REDUCE_MODE enum
1741	*/
1742
1743	typedef enum LBV_PIXEL_REDUCE_MODE {
1744	PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
1745	PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
1746	} LBV_PIXEL_REDUCE_MODE;
1747
1748	/*
1749	* LBV_DYNAMIC_PIXEL_DEPTH enum
1750	*/
1751
1752	typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
1753	DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
1754	DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
1755	} LBV_DYNAMIC_PIXEL_DEPTH;
1756
1757	/*
1758	* LBV_DITHER_EN enum
1759	*/
1760
1761	typedef enum LBV_DITHER_EN {
1762	DITHER_DIS = 0x00000000,
1763	DITHER_EN = 0x00000001,
1764	} LBV_DITHER_EN;
1765
1766	/*
1767	* LBV_DOWNSCALE_PREFETCH_EN enum
1768	*/
1769
1770	typedef enum LBV_DOWNSCALE_PREFETCH_EN {
1771	DOWNSCALE_PREFETCH_DIS = 0x00000000,
1772	DOWNSCALE_PREFETCH_EN = 0x00000001,
1773	} LBV_DOWNSCALE_PREFETCH_EN;
1774
1775	/*
1776	* LBV_MEMORY_CONFIG enum
1777	*/
1778
1779	typedef enum LBV_MEMORY_CONFIG {
1780	MEMORY_CONFIG_0 = 0x00000000,
1781	MEMORY_CONFIG_1 = 0x00000001,
1782	MEMORY_CONFIG_2 = 0x00000002,
1783	MEMORY_CONFIG_3 = 0x00000003,
1784	} LBV_MEMORY_CONFIG;
1785
1786	/*
1787	* LBV_SYNC_RESET_SEL2 enum
1788	*/
1789
1790	typedef enum LBV_SYNC_RESET_SEL2 {
1791	SYNC_RESET_SEL2_VBLANK = 0x00000000,
1792	SYNC_RESET_SEL2_VSYNC = 0x00000001,
1793	} LBV_SYNC_RESET_SEL2;
1794
1795	/*
1796	* LBV_SYNC_DURATION enum
1797	*/
1798
1799	typedef enum LBV_SYNC_DURATION {
1800	SYNC_DURATION_16 = 0x00000000,
1801	SYNC_DURATION_32 = 0x00000001,
1802	SYNC_DURATION_64 = 0x00000002,
1803	SYNC_DURATION_128 = 0x00000003,
1804	} LBV_SYNC_DURATION;
1805
1806	/*******************************************************
1807	* CRTC Enums
1808	*******************************************************/
1809
1810	/*
1811	* CRTC_CONTROL_CRTC_START_POINT_CNTL enum
1812	*/
1813
1814	typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
1815	CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000,
1816	CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x00000001,
1817	} CRTC_CONTROL_CRTC_START_POINT_CNTL;
1818
1819	/*
1820	* CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum
1821	*/
1822
1823	typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
1824	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
1825	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x00000001,
1826	} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
1827
1828	/*
1829	* CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum
1830	*/
1831
1832	typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
1833	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
1834	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
1835	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x00000002,
1836	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
1837	} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
1838
1839	/*
1840	* CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum
1841	*/
1842
1843	typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
1844	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
1845	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
1846	} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
1847
1848	/*
1849	* CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum
1850	*/
1851
1852	typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
1853	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE = 0x00000000,
1854	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x00000001,
1855	} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
1856
1857	/*
1858	* CRTC_CONTROL_CRTC_SOF_PULL_EN enum
1859	*/
1860
1861	typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
1862	CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x00000000,
1863	CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x00000001,
1864	} CRTC_CONTROL_CRTC_SOF_PULL_EN;
1865
1866	/*
1867	* CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum
1868	*/
1869
1870	typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
1871	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x00000000,
1872	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x00000001,
1873	} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
1874
1875	/*
1876	* CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum
1877	*/
1878
1879	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
1880	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
1881	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
1882	} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
1883
1884	/*
1885	* CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum
1886	*/
1887
1888	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
1889	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
1890	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
1891	} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
1892
1893	/*
1894	* CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum
1895	*/
1896
1897	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
1898	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0x00000000,
1899	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE = 0x00000001,
1900	} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
1901
1902	/*
1903	* CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum
1904	*/
1905
1906	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
1907	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
1908	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
1909	} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
1910
1911	/*
1912	* CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum
1913	*/
1914
1915	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
1916	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
1917	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
1918	} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
1919
1920	/*
1921	* CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
1922	*/
1923
1924	typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
1925	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
1926	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 0x00000001,
1927	} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
1928
1929	/*
1930	* CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum
1931	*/
1932
1933	typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
1934	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
1935	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
1936	} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
1937
1938	/*
1939	* CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum
1940	*/
1941
1942	typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
1943	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x00000000,
1944	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x00000001,
1945	} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
1946
1947	/*
1948	* CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum
1949	*/
1950
1951	typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
1952	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x00000000,
1953	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x00000001,
1954	} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
1955
1956	/*
1957	* CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum
1958	*/
1959
1960	typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
1961	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001,
1962	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002,
1963	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF = 0x00000005,
1964	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE = 0x00000006,
1965	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x00000007,
1966	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x00000008,
1967	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x00000009,
1968	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0x0000000a,
1969	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
1970	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
1971	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD = 0x0000000d,
1972	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC = 0x0000000e,
1973	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x00000010,
1974	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x00000011,
1975	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x00000012,
1976	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x00000013,
1977	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA = 0x00000014,
1978	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB = 0x00000015,
1979	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW = 0x00000016,
1980	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW = 0x00000017,
1981	} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
1982
1983	/*
1984	* CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum
1985	*/
1986
1987	typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
1988	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
1989	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
1990	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
1991	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
1992	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB = 0x00000005,
1993	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x00000006,
1994	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC = 0x00000007,
1995	} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
1996
1997	/*
1998	* CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum
1999	*/
2000
2001	typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
2002	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
2003	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
2004	} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
2005
2006	/*
2007	* CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum
2008	*/
2009
2010	typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
2011	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x00000000,
2012	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x00000001,
2013	} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
2014
2015	/*
2016	* CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum
2017	*/
2018
2019	typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
2020	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001,
2021	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002,
2022	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF = 0x00000005,
2023	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE = 0x00000006,
2024	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x00000007,
2025	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x00000008,
2026	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x00000009,
2027	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0x0000000a,
2028	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
2029	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
2030	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD = 0x0000000d,
2031	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC = 0x0000000e,
2032	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x00000010,
2033	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x00000011,
2034	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x00000012,
2035	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x00000013,
2036	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA = 0x00000014,
2037	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB = 0x00000015,
2038	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW = 0x00000016,
2039	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW = 0x00000017,
2040	} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
2041
2042	/*
2043	* CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum
2044	*/
2045
2046	typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
2047	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
2048	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
2049	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
2050	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
2051	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB = 0x00000005,
2052	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x00000006,
2053	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC = 0x00000007,
2054	} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
2055
2056	/*
2057	* CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum
2058	*/
2059
2060	typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
2061	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
2062	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
2063	} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
2064
2065	/*
2066	* CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum
2067	*/
2068
2069	typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
2070	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x00000000,
2071	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x00000001,
2072	} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
2073
2074	/*
2075	* CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum
2076	*/
2077
2078	typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
2079	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
2080	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
2081	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
2082	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
2083	} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
2084
2085	/*
2086	* CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum
2087	*/
2088
2089	typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
2090	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
2091	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
2092	} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
2093
2094	/*
2095	* CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum
2096	*/
2097
2098	typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
2099	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
2100	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
2101	} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
2102
2103	/*
2104	* CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum
2105	*/
2106
2107	typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
2108	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
2109	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
2110	} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
2111
2112	/*
2113	* CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum
2114	*/
2115
2116	typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
2117	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000,
2118	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000001,
2119	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000002,
2120	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000003,
2121	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000004,
2122	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x00000005,
2123	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x00000006,
2124	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x00000007,
2125	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x00000008,
2126	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK = 0x00000009,
2127	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL = 0x0000000a,
2128	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x0000000b,
2129	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x0000000c,
2130	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x0000000d,
2131	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x0000000e,
2132	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x0000000f,
2133	} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
2134
2135	/*
2136	* CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum
2137	*/
2138
2139	typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
2140	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE = 0x00000000,
2141	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE = 0x00000001,
2142	} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
2143
2144	/*
2145	* CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum
2146	*/
2147
2148	typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
2149	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000,
2150	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001,
2151	} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
2152
2153	/*
2154	* CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum
2155	*/
2156
2157	typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
2158	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO = 0x00000000,
2159	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001,
2160	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002,
2161	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003,
2162	} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
2163
2164	/*
2165	* CRTC_CONTROL_CRTC_MASTER_EN enum
2166	*/
2167
2168	typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
2169	CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x00000000,
2170	CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x00000001,
2171	} CRTC_CONTROL_CRTC_MASTER_EN;
2172
2173	/*
2174	* CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum
2175	*/
2176
2177	typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
2178	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x00000000,
2179	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x00000001,
2180	} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
2181
2182	/*
2183	* CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum
2184	*/
2185
2186	typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
2187	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x00000000,
2188	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x00000001,
2189	} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
2190
2191	/*
2192	* CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum
2193	*/
2194
2195	typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
2196	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE = 0x00000000,
2197	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE = 0x00000001,
2198	} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
2199
2200	/*
2201	* CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum
2202	*/
2203
2204	typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
2205	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000,
2206	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD = 0x00000001,
2207	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN = 0x00000002,
2208	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003,
2209	} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
2210
2211	/*
2212	* CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum
2213	*/
2214
2215	typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
2216	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0x00000000,
2217	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 0x00000001,
2218	} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
2219
2220	/*
2221	* CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum
2222	*/
2223
2224	typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
2225	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE = 0x00000000,
2226	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE = 0x00000001,
2227	} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
2228
2229	/*
2230	* CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum
2231	*/
2232
2233	typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
2234	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x00000000,
2235	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x00000001,
2236	} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
2237
2238	/*
2239	* CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum
2240	*/
2241
2242	typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
2243	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
2244	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001,
2245	} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
2246
2247	/*
2248	* CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum
2249	*/
2250
2251	typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
2252	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
2253	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001,
2254	} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
2255
2256	/*
2257	* CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum
2258	*/
2259
2260	typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
2261	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000,
2262	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001,
2263	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002,
2264	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003,
2265	} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
2266
2267	/*
2268	* CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum
2269	*/
2270
2271	typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
2272	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000,
2273	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001,
2274	} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
2275
2276	/*
2277	* CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum
2278	*/
2279
2280	typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
2281	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE = 0x00000000,
2282	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE = 0x00000001,
2283	} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
2284
2285	/*
2286	* CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum
2287	*/
2288
2289	typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
2290	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000,
2291	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001,
2292	} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
2293
2294	/*
2295	* CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum
2296	*/
2297
2298	typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
2299	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x00000000,
2300	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x00000001,
2301	} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
2302
2303	/*
2304	* CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum
2305	*/
2306
2307	typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
2308	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x00000000,
2309	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x00000001,
2310	} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
2311
2312	/*
2313	* CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum
2314	*/
2315
2316	typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
2317	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000,
2318	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001,
2319	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002,
2320	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003,
2321	} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
2322
2323	/*
2324	* CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum
2325	*/
2326
2327	typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
2328	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
2329	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE = 0x00000001,
2330	} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
2331
2332	/*
2333	* CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum
2334	*/
2335
2336	typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
2337	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
2338	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE = 0x00000001,
2339	} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
2340
2341	/*
2342	* CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum
2343	*/
2344
2345	typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
2346	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE = 0x00000000,
2347	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE = 0x00000001,
2348	} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
2349
2350	/*
2351	* CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum
2352	*/
2353
2354	typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
2355	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x00000000,
2356	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x00000001,
2357	} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
2358
2359	/*
2360	* CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum
2361	*/
2362
2363	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
2364	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE = 0x00000000,
2365	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE = 0x00000001,
2366	} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
2367
2368	/*
2369	* CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum
2370	*/
2371
2372	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
2373	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE = 0x00000000,
2374	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE = 0x00000001,
2375	} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
2376
2377	/*
2378	* CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum
2379	*/
2380
2381	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
2382	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE = 0x00000000,
2383	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE = 0x00000001,
2384	} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
2385
2386	/*
2387	* CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum
2388	*/
2389
2390	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
2391	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE = 0x00000000,
2392	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE = 0x00000001,
2393	} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
2394
2395	/*
2396	* CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum
2397	*/
2398
2399	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
2400	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000,
2401	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001,
2402	} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
2403
2404	/*
2405	* CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum
2406	*/
2407
2408	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
2409	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000,
2410	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001,
2411	} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
2412
2413	/*
2414	* CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
2415	*/
2416
2417	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
2418	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000,
2419	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001,
2420	} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
2421
2422	/*
2423	* CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
2424	*/
2425
2426	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
2427	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000,
2428	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001,
2429	} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
2430
2431	/*
2432	* CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum
2433	*/
2434
2435	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
2436	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x00000000,
2437	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x00000001,
2438	} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
2439
2440	/*
2441	* CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum
2442	*/
2443
2444	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
2445	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x00000000,
2446	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x00000001,
2447	} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
2448
2449	/*
2450	* CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum
2451	*/
2452
2453	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
2454	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x00000000,
2455	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x00000001,
2456	} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
2457
2458	/*
2459	* CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum
2460	*/
2461
2462	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
2463	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x00000000,
2464	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x00000001,
2465	} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
2466
2467	/*
2468	* CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum
2469	*/
2470
2471	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
2472	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE = 0x00000000,
2473	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE = 0x00000001,
2474	} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
2475
2476	/*
2477	* CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum
2478	*/
2479
2480	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
2481	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000,
2482	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001,
2483	} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
2484
2485	/*
2486	* CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum
2487	*/
2488
2489	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
2490	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000,
2491	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001,
2492	} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
2493
2494	/*
2495	* CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum
2496	*/
2497
2498	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
2499	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000,
2500	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001,
2501	} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
2502
2503	/*
2504	* CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum
2505	*/
2506
2507	typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
2508	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x00000000,
2509	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x00000001,
2510	} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
2511
2512	/*
2513	* CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum
2514	*/
2515
2516	typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
2517	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE = 0x00000000,
2518	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE = 0x00000001,
2519	} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
2520
2521	/*
2522	* CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum
2523	*/
2524
2525	typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
2526	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0x00000000,
2527	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 0x00000001,
2528	} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
2529
2530	/*
2531	* CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum
2532	*/
2533
2534	typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
2535	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000,
2536	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001,
2537	} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE;
2538
2539	/*
2540	* CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum
2541	*/
2542
2543	typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
2544	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0x00000000,
2545	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE = 0x00000001,
2546	} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
2547
2548	/*
2549	* CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum
2550	*/
2551
2552	typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
2553	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE = 0x00000000,
2554	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE = 0x00000001,
2555	} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
2556
2557	/*
2558	* CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum
2559	*/
2560
2561	typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
2562	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB = 0x00000000,
2563	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601 = 0x00000001,
2564	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709 = 0x00000002,
2565	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS = 0x00000003,
2566	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS = 0x00000004,
2567	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB = 0x00000005,
2568	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB = 0x00000006,
2569	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS = 0x00000007,
2570	} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
2571
2572	/*
2573	* CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum
2574	*/
2575
2576	typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
2577	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE = 0x00000000,
2578	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE = 0x00000001,
2579	} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
2580
2581	/*
2582	* CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum
2583	*/
2584
2585	typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
2586	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC = 0x00000000,
2587	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC = 0x00000001,
2588	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC = 0x00000002,
2589	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED = 0x00000003,
2590	} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
2591
2592	/*
2593	* MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
2594	*/
2595
2596	typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
2597	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
2598	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
2599	} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
2600
2601	/*
2602	* MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum
2603	*/
2604
2605	typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
2606	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
2607	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
2608	} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
2609
2610	/*
2611	* MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
2612	*/
2613
2614	typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
2615	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x00000000,
2616	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x00000001,
2617	} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
2618
2619	/*
2620	* MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum
2621	*/
2622
2623	typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
2624	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x00000000,
2625	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x00000001,
2626	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x00000002,
2627	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x00000003,
2628	} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
2629
2630	/*
2631	* MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
2632	*/
2633
2634	typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
2635	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000,
2636	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN = 0x00000001,
2637	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD = 0x00000002,
2638	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003,
2639	} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
2640
2641	/*
2642	* CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum
2643	*/
2644
2645	typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
2646	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE = 0x00000000,
2647	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG = 0x00000001,
2648	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL = 0x00000002,
2649	} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
2650
2651	/*
2652	* CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum
2653	*/
2654
2655	typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
2656	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x00000000,
2657	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x00000001,
2658	} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
2659
2660	/*
2661	* CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum
2662	*/
2663
2664	typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
2665	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
2666	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 0x00000001,
2667	} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
2668
2669	/*
2670	* CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum
2671	*/
2672
2673	typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
2674	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
2675	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE = 0x00000001,
2676	} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
2677
2678	/*
2679	* CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
2680	*/
2681
2682	typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
2683	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000,
2684	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001,
2685	} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
2686
2687	/*
2688	* CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum
2689	*/
2690
2691	typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
2692	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
2693	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001,
2694	} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
2695
2696	/*
2697	* CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum
2698	*/
2699
2700	typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
2701	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
2702	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001,
2703	} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
2704
2705	/*
2706	* CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum
2707	*/
2708
2709	typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
2710	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000,
2711	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001,
2712	} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
2713
2714	/*
2715	* CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum
2716	*/
2717
2718	typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
2719	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
2720	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001,
2721	} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
2722
2723	/*
2724	* CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum
2725	*/
2726
2727	typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
2728	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
2729	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001,
2730	} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
2731
2732	/*
2733	* CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum
2734	*/
2735
2736	typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
2737	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000,
2738	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001,
2739	} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
2740
2741	/*
2742	* CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum
2743	*/
2744
2745	typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
2746	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
2747	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001,
2748	} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
2749
2750	/*
2751	* CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum
2752	*/
2753
2754	typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
2755	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
2756	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001,
2757	} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
2758
2759	/*
2760	* CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum
2761	*/
2762
2763	typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
2764	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000,
2765	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001,
2766	} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
2767
2768	/*
2769	* CRTC_CRC_CNTL_CRTC_CRC_EN enum
2770	*/
2771
2772	typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
2773	CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x00000000,
2774	CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x00000001,
2775	} CRTC_CRC_CNTL_CRTC_CRC_EN;
2776
2777	/*
2778	* CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum
2779	*/
2780
2781	typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
2782	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x00000000,
2783	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x00000001,
2784	} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
2785
2786	/*
2787	* CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum
2788	*/
2789
2790	typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
2791	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x00000000,
2792	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x00000001,
2793	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x00000002,
2794	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003,
2795	} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
2796
2797	/*
2798	* CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum
2799	*/
2800
2801	typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
2802	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x00000000,
2803	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
2804	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
2805	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003,
2806	} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
2807
2808	/*
2809	* CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum
2810	*/
2811
2812	typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
2813	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
2814	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001,
2815	} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
2816
2817	/*
2818	* CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum
2819	*/
2820
2821	typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
2822	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x00000000,
2823	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x00000001,
2824	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x00000002,
2825	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x00000003,
2826	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x00000004,
2827	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x00000005,
2828	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x00000006,
2829	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x00000007,
2830	} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
2831
2832	/*
2833	* CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum
2834	*/
2835
2836	typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
2837	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x00000000,
2838	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x00000001,
2839	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x00000002,
2840	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x00000003,
2841	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x00000004,
2842	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x00000005,
2843	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x00000006,
2844	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x00000007,
2845	} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
2846
2847	/*
2848	* CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum
2849	*/
2850
2851	typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
2852	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE = 0x00000000,
2853	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT = 0x00000001,
2854	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 0x00000002,
2855	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED = 0x00000003,
2856	} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
2857
2858	/*
2859	* CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
2860	*/
2861
2862	typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
2863	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0x00000000,
2864	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 0x00000001,
2865	} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
2866
2867	/*
2868	* CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
2869	*/
2870
2871	typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
2872	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0x00000000,
2873	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 0x00000001,
2874	} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
2875
2876	/*
2877	* CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
2878	*/
2879
2880	typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
2881	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0x00000000,
2882	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 0x00000001,
2883	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 0x00000002,
2884	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 0x00000003,
2885	} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
2886
2887	/*
2888	* CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum
2889	*/
2890
2891	typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
2892	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0x00000000,
2893	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 0x00000001,
2894	} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
2895
2896	/*
2897	* CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum
2898	*/
2899
2900	typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
2901	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
2902	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 0x00000001,
2903	} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
2904
2905	/*
2906	* CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum
2907	*/
2908
2909	typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
2910	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0x00000000,
2911	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 0x00000001,
2912	} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
2913
2914	/*
2915	* CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum
2916	*/
2917
2918	typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
2919	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0x00000000,
2920	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 0x00000001,
2921	} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
2922
2923	/*
2924	* CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum
2925	*/
2926
2927	typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
2928	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0x00000000,
2929	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 0x00000001,
2930	} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
2931
2932	/*
2933	* CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
2934	*/
2935
2936	typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
2937	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0x00000000,
2938	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 0x00000001,
2939	} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
2940
2941	/*
2942	* CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum
2943	*/
2944
2945	typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
2946	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
2947	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 0x00000001,
2948	} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
2949
2950	/*
2951	* CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
2952	*/
2953
2954	typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
2955	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0x00000000,
2956	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 0x00000001,
2957	} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
2958
2959	/*
2960	* CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
2961	*/
2962
2963	typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
2964	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0x00000000,
2965	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 0x00000001,
2966	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 0x00000002,
2967	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 0x00000003,
2968	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 0x00000004,
2969	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 0x00000005,
2970	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 0x00000006,
2971	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 0x00000007,
2972	} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
2973
2974	/*
2975	* CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum
2976	*/
2977
2978	typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
2979	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0x00000000,
2980	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 0x00000001,
2981	} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
2982
2983	/*
2984	* CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum
2985	*/
2986
2987	typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
2988	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
2989	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE = 0x00000001,
2990	} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
2991
2992	/*
2993	* CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum
2994	*/
2995
2996	typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
2997	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0x00000000,
2998	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE = 0x00000001,
2999	} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
3000
3001	/*
3002	* CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
3003	*/
3004
3005	typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
3006	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0x00000000,
3007	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 0x00000001,
3008	} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
3009
3010	/*
3011	* CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
3012	*/
3013
3014	typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
3015	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
3016	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 0x00000001,
3017	} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
3018
3019	/*
3020	* CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
3021	*/
3022
3023	typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
3024	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0x00000000,
3025	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 0x00000001,
3026	} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
3027
3028	/*
3029	* CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum
3030	*/
3031
3032	typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
3033	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE = 0x00000000,
3034	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE = 0x00000001,
3035	} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
3036
3037	/*
3038	* CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum
3039	*/
3040
3041	typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
3042	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
3043	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE = 0x00000001,
3044	} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
3045
3046	/*
3047	* CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum
3048	*/
3049
3050	typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
3051	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE = 0x00000000,
3052	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE = 0x00000001,
3053	} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
3054
3055	/*
3056	* CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum
3057	*/
3058
3059	typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
3060	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000,
3061	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001,
3062	} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
3063
3064	/*
3065	* CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum
3066	*/
3067
3068	typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
3069	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000,
3070	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001,
3071	} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
3072
3073	/*
3074	* CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum
3075	*/
3076
3077	typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
3078	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE = 0x00000000,
3079	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE = 0x00000001,
3080	} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
3081
3082	/*
3083	* CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum
3084	*/
3085
3086	typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
3087	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE = 0x00000000,
3088	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE = 0x00000001,
3089	} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
3090
3091	/*
3092	* CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum
3093	*/
3094
3095	typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
3096	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000,
3097	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001,
3098	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002,
3099	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003,
3100	} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
3101
3102	/*
3103	* CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum
3104	*/
3105
3106	typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
3107	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000,
3108	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001,
3109	} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
3110
3111	/*
3112	* CRTC_V_SYNC_A_POL enum
3113	*/
3114
3115	typedef enum CRTC_V_SYNC_A_POL {
3116	CRTC_V_SYNC_A_POL_HIGH = 0x00000000,
3117	CRTC_V_SYNC_A_POL_LOW = 0x00000001,
3118	} CRTC_V_SYNC_A_POL;
3119
3120	/*
3121	* CRTC_H_SYNC_A_POL enum
3122	*/
3123
3124	typedef enum CRTC_H_SYNC_A_POL {
3125	CRTC_H_SYNC_A_POL_HIGH = 0x00000000,
3126	CRTC_H_SYNC_A_POL_LOW = 0x00000001,
3127	} CRTC_H_SYNC_A_POL;
3128
3129	/*
3130	* CRTC_HORZ_REPETITION_COUNT enum
3131	*/
3132
3133	typedef enum CRTC_HORZ_REPETITION_COUNT {
3134	CRTC_HORZ_REPETITION_COUNT_0 = 0x00000000,
3135	CRTC_HORZ_REPETITION_COUNT_1 = 0x00000001,
3136	CRTC_HORZ_REPETITION_COUNT_2 = 0x00000002,
3137	CRTC_HORZ_REPETITION_COUNT_3 = 0x00000003,
3138	CRTC_HORZ_REPETITION_COUNT_4 = 0x00000004,
3139	CRTC_HORZ_REPETITION_COUNT_5 = 0x00000005,
3140	CRTC_HORZ_REPETITION_COUNT_6 = 0x00000006,
3141	CRTC_HORZ_REPETITION_COUNT_7 = 0x00000007,
3142	CRTC_HORZ_REPETITION_COUNT_8 = 0x00000008,
3143	CRTC_HORZ_REPETITION_COUNT_9 = 0x00000009,
3144	CRTC_HORZ_REPETITION_COUNT_10 = 0x0000000a,
3145	CRTC_HORZ_REPETITION_COUNT_11 = 0x0000000b,
3146	CRTC_HORZ_REPETITION_COUNT_12 = 0x0000000c,
3147	CRTC_HORZ_REPETITION_COUNT_13 = 0x0000000d,
3148	CRTC_HORZ_REPETITION_COUNT_14 = 0x0000000e,
3149	CRTC_HORZ_REPETITION_COUNT_15 = 0x0000000f,
3150	} CRTC_HORZ_REPETITION_COUNT;
3151
3152	/*
3153	* CRTC_DRR_MODE_DBUF_UPDATE_MODE enum
3154	*/
3155
3156	typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
3157	CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE = 0x00000000,
3158	CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL = 0x00000001,
3159	CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF = 0x00000002,
3160	CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF = 0x00000003,
3161	} CRTC_DRR_MODE_DBUF_UPDATE_MODE;
3162
3163	/*******************************************************
3164	* FMT Enums
3165	*******************************************************/
3166
3167	/*
3168	* FMT_CONTROL_PIXEL_ENCODING enum
3169	*/
3170
3171	typedef enum FMT_CONTROL_PIXEL_ENCODING {
3172	FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
3173	FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001,
3174	FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002,
3175	FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003,
3176	} FMT_CONTROL_PIXEL_ENCODING;
3177
3178	/*
3179	* FMT_CONTROL_SUBSAMPLING_MODE enum
3180	*/
3181
3182	typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3183	FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000,
3184	FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001,
3185	FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002,
3186	FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003,
3187	} FMT_CONTROL_SUBSAMPLING_MODE;
3188
3189	/*
3190	* FMT_CONTROL_SUBSAMPLING_ORDER enum
3191	*/
3192
3193	typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3194	FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
3195	FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
3196	} FMT_CONTROL_SUBSAMPLING_ORDER;
3197
3198	/*
3199	* FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3200	*/
3201
3202	typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3203	FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
3204	FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
3205	} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3206
3207	/*
3208	* FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3209	*/
3210
3211	typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3212	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
3213	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
3214	} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3215
3216	/*
3217	* FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3218	*/
3219
3220	typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3221	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
3222	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
3223	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
3224	} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3225
3226	/*
3227	* FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3228	*/
3229
3230	typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3231	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
3232	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
3233	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
3234	} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3235
3236	/*
3237	* FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3238	*/
3239
3240	typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3241	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
3242	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
3243	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
3244	} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3245
3246	/*
3247	* FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3248	*/
3249
3250	typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3251	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
3252	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
3253	} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3254
3255	/*
3256	* FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3257	*/
3258
3259	typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3260	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000,
3261	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001,
3262	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002,
3263	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
3264	} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3265
3266	/*
3267	* FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3268	*/
3269
3270	typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3271	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000,
3272	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001,
3273	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002,
3274	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003,
3275	} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3276
3277	/*
3278	* FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3279	*/
3280
3281	typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3282	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000,
3283	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001,
3284	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002,
3285	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
3286	} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3287
3288	/*
3289	* FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum
3290	*/
3291
3292	typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3293	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN = 0x00000000,
3294	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN = 0x00000001,
3295	} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
3296
3297	/*
3298	* FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3299	*/
3300
3301	typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3302	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
3303	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
3304	} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3305
3306	/*
3307	* FMT_CLAMP_CNTL_COLOR_FORMAT enum
3308	*/
3309
3310	typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3311	FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000,
3312	FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001,
3313	FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002,
3314	FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003,
3315	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004,
3316	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005,
3317	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006,
3318	FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
3319	} FMT_CLAMP_CNTL_COLOR_FORMAT;
3320
3321	/*
3322	* FMT_CRC_CNTL_CONT_EN enum
3323	*/
3324
3325	typedef enum FMT_CRC_CNTL_CONT_EN {
3326	FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x00000000,
3327	FMT_CRC_CNTL_CONT_EN_CONT = 0x00000001,
3328	} FMT_CRC_CNTL_CONT_EN;
3329
3330	/*
3331	* FMT_CRC_CNTL_INCLUDE_OVERSCAN enum
3332	*/
3333
3334	typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3335	FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x00000000,
3336	FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x00000001,
3337	} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
3338
3339	/*
3340	* FMT_CRC_CNTL_ONLY_BLANKB enum
3341	*/
3342
3343	typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3344	FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x00000000,
3345	FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x00000001,
3346	} FMT_CRC_CNTL_ONLY_BLANKB;
3347
3348	/*
3349	* FMT_CRC_CNTL_PSR_MODE_ENABLE enum
3350	*/
3351
3352	typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3353	FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x00000000,
3354	FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x00000001,
3355	} FMT_CRC_CNTL_PSR_MODE_ENABLE;
3356
3357	/*
3358	* FMT_CRC_CNTL_INTERLACE_MODE enum
3359	*/
3360
3361	typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3362	FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x00000000,
3363	FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x00000001,
3364	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
3365	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x00000003,
3366	} FMT_CRC_CNTL_INTERLACE_MODE;
3367
3368	/*
3369	* FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum
3370	*/
3371
3372	typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3373	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x00000000,
3374	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x00000001,
3375	} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
3376
3377	/*
3378	* FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum
3379	*/
3380
3381	typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3382	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x00000000,
3383	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x00000001,
3384	} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
3385
3386	/*
3387	* FMT_DEBUG_CNTL_COLOR_SELECT enum
3388	*/
3389
3390	typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3391	FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000,
3392	FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001,
3393	FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002,
3394	FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003,
3395	} FMT_DEBUG_CNTL_COLOR_SELECT;
3396
3397	/*
3398	* FMT_SPATIAL_DITHER_MODE enum
3399	*/
3400
3401	typedef enum FMT_SPATIAL_DITHER_MODE {
3402	FMT_SPATIAL_DITHER_MODE_0 = 0x00000000,
3403	FMT_SPATIAL_DITHER_MODE_1 = 0x00000001,
3404	FMT_SPATIAL_DITHER_MODE_2 = 0x00000002,
3405	FMT_SPATIAL_DITHER_MODE_3 = 0x00000003,
3406	} FMT_SPATIAL_DITHER_MODE;
3407
3408	/*
3409	* FMT_STEREOSYNC_OVR_POL enum
3410	*/
3411
3412	typedef enum FMT_STEREOSYNC_OVR_POL {
3413	FMT_STEREOSYNC_OVR_POL_INVERTED = 0x00000000,
3414	FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x00000001,
3415	} FMT_STEREOSYNC_OVR_POL;
3416
3417	/*
3418	* FMT_DYNAMIC_EXP_MODE enum
3419	*/
3420
3421	typedef enum FMT_DYNAMIC_EXP_MODE {
3422	FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000,
3423	FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001,
3424	} FMT_DYNAMIC_EXP_MODE;
3425
3426	/*******************************************************
3427	* HPD Enums
3428	*******************************************************/
3429
3430	/*
3431	* HPD_INT_CONTROL_ACK enum
3432	*/
3433
3434	typedef enum HPD_INT_CONTROL_ACK {
3435	HPD_INT_CONTROL_ACK_0 = 0x00000000,
3436	HPD_INT_CONTROL_ACK_1 = 0x00000001,
3437	} HPD_INT_CONTROL_ACK;
3438
3439	/*
3440	* HPD_INT_CONTROL_POLARITY enum
3441	*/
3442
3443	typedef enum HPD_INT_CONTROL_POLARITY {
3444	HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000,
3445	HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001,
3446	} HPD_INT_CONTROL_POLARITY;
3447
3448	/*
3449	* HPD_INT_CONTROL_RX_INT_ACK enum
3450	*/
3451
3452	typedef enum HPD_INT_CONTROL_RX_INT_ACK {
3453	HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000,
3454	HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001,
3455	} HPD_INT_CONTROL_RX_INT_ACK;
3456
3457	/*******************************************************
3458	* LB Enums
3459	*******************************************************/
3460
3461	/*
3462	* LB_DATA_FORMAT_PIXEL_DEPTH enum
3463	*/
3464
3465	typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3466	LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x00000000,
3467	LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x00000001,
3468	LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x00000002,
3469	LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x00000003,
3470	} LB_DATA_FORMAT_PIXEL_DEPTH;
3471
3472	/*
3473	* LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum
3474	*/
3475
3476	typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3477	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0x00000000,
3478	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 0x00000001,
3479	} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
3480
3481	/*
3482	* LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum
3483	*/
3484
3485	typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3486	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
3487	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
3488	} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
3489
3490	/*
3491	* LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum
3492	*/
3493
3494	typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3495	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
3496	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
3497	} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
3498
3499	/*
3500	* LB_DATA_FORMAT_INTERLEAVE_EN enum
3501	*/
3502
3503	typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3504	LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x00000000,
3505	LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x00000001,
3506	} LB_DATA_FORMAT_INTERLEAVE_EN;
3507
3508	/*
3509	* LB_DATA_FORMAT_REQUEST_MODE enum
3510	*/
3511
3512	typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3513	LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x00000000,
3514	LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x00000001,
3515	} LB_DATA_FORMAT_REQUEST_MODE;
3516
3517	/*
3518	* LB_DATA_FORMAT_ALPHA_EN enum
3519	*/
3520
3521	typedef enum LB_DATA_FORMAT_ALPHA_EN {
3522	LB_DATA_FORMAT_ALPHA_DISABLE = 0x00000000,
3523	LB_DATA_FORMAT_ALPHA_ENABLE = 0x00000001,
3524	} LB_DATA_FORMAT_ALPHA_EN;
3525
3526	/*
3527	* LB_VLINE_START_END_VLINE_INV enum
3528	*/
3529
3530	typedef enum LB_VLINE_START_END_VLINE_INV {
3531	LB_VLINE_START_END_VLINE_NORMAL = 0x00000000,
3532	LB_VLINE_START_END_VLINE_INVERSE = 0x00000001,
3533	} LB_VLINE_START_END_VLINE_INV;
3534
3535	/*
3536	* LB_VLINE2_START_END_VLINE2_INV enum
3537	*/
3538
3539	typedef enum LB_VLINE2_START_END_VLINE2_INV {
3540	LB_VLINE2_START_END_VLINE2_NORMAL = 0x00000000,
3541	LB_VLINE2_START_END_VLINE2_INVERSE = 0x00000001,
3542	} LB_VLINE2_START_END_VLINE2_INV;
3543
3544	/*
3545	* LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum
3546	*/
3547
3548	typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3549	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x00000000,
3550	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x00000001,
3551	} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
3552
3553	/*
3554	* LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum
3555	*/
3556
3557	typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3558	LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x00000000,
3559	LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x00000001,
3560	} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
3561
3562	/*
3563	* LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum
3564	*/
3565
3566	typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3567	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x00000000,
3568	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x00000001,
3569	} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
3570
3571	/*
3572	* LB_VLINE_STATUS_VLINE_ACK enum
3573	*/
3574
3575	typedef enum LB_VLINE_STATUS_VLINE_ACK {
3576	LB_VLINE_STATUS_VLINE_NORMAL = 0x00000000,
3577	LB_VLINE_STATUS_VLINE_CLEAR = 0x00000001,
3578	} LB_VLINE_STATUS_VLINE_ACK;
3579
3580	/*
3581	* LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum
3582	*/
3583
3584	typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3585	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
3586	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
3587	} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
3588
3589	/*
3590	* LB_VLINE2_STATUS_VLINE2_ACK enum
3591	*/
3592
3593	typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3594	LB_VLINE2_STATUS_VLINE2_NORMAL = 0x00000000,
3595	LB_VLINE2_STATUS_VLINE2_CLEAR = 0x00000001,
3596	} LB_VLINE2_STATUS_VLINE2_ACK;
3597
3598	/*
3599	* LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum
3600	*/
3601
3602	typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3603	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
3604	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
3605	} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
3606
3607	/*
3608	* LB_VBLANK_STATUS_VBLANK_ACK enum
3609	*/
3610
3611	typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3612	LB_VBLANK_STATUS_VBLANK_NORMAL = 0x00000000,
3613	LB_VBLANK_STATUS_VBLANK_CLEAR = 0x00000001,
3614	} LB_VBLANK_STATUS_VBLANK_ACK;
3615
3616	/*
3617	* LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum
3618	*/
3619
3620	typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3621	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
3622	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
3623	} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
3624
3625	/*
3626	* LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum
3627	*/
3628
3629	typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3630	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x00000000,
3631	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK = 0x00000001,
3632	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET = 0x00000002,
3633	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET = 0x00000003,
3634	} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
3635
3636	/*
3637	* LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum
3638	*/
3639
3640	typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3641	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x00000000,
3642	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x00000001,
3643	} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
3644
3645	/*
3646	* LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum
3647	*/
3648
3649	typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3650	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x00000000,
3651	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x00000001,
3652	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x00000002,
3653	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x00000003,
3654	} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
3655
3656	/*
3657	* LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum
3658	*/
3659
3660	typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3661	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x00000000,
3662	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x00000001,
3663	} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
3664
3665	/*
3666	* LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum
3667	*/
3668
3669	typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3670	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0x00000000,
3671	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 0x00000001,
3672	} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
3673
3674	/*
3675	* LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum
3676	*/
3677
3678	typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3679	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x00000000,
3680	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x00000001,
3681	} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
3682
3683	/*
3684	* LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum
3685	*/
3686
3687	typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3688	LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x00000000,
3689	LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x00000001,
3690	} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
3691
3692	/*
3693	* LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum
3694	*/
3695
3696	typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3697	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x00000002,
3698	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP = 0x00000003,
3699	} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
3700
3701	/*
3702	* LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum
3703	*/
3704
3705	typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3706	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0x00000000,
3707	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE = 0x00000001,
3708	} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
3709
3710	/*
3711	* LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum
3712	*/
3713
3714	typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3715	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0x00000000,
3716	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 0x00000001,
3717	} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
3718
3719	/*
3720	* LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum
3721	*/
3722
3723	typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3724	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT = 0x00000000,
3725	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG = 0x00000001,
3726	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE = 0x00000002,
3727	} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
3728
3729	/*
3730	* LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum
3731	*/
3732
3733	typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3734	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE = 0x00000000,
3735	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x00000001,
3736	} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
3737
3738	/*
3739	* LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum
3740	*/
3741
3742	typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3743	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER = 0x00000001,
3744	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE = 0x00000002,
3745	} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
3746
3747	/*
3748	* LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum
3749	*/
3750
3751	typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3752	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0x00000000,
3753	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 0x00000001,
3754	} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
3755
3756	/*
3757	* LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum
3758	*/
3759
3760	typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3761	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0x00000000,
3762	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE = 0x00000001,
3763	} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
3764
3765	/*
3766	* LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum
3767	*/
3768
3769	typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3770	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0x00000000,
3771	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO = 0x00000001,
3772	} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
3773
3774	/*
3775	* LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum
3776	*/
3777
3778	typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3779	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0x00000000,
3780	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 0x00000001,
3781	} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
3782
3783	/*******************************************************
3784	* DIG Enums
3785	*******************************************************/
3786
3787	/*
3788	* HDMI_KEEPOUT_MODE enum
3789	*/
3790
3791	typedef enum HDMI_KEEPOUT_MODE {
3792	HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000,
3793	HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001,
3794	} HDMI_KEEPOUT_MODE;
3795
3796	/*
3797	* HDMI_DATA_SCRAMBLE_EN enum
3798	*/
3799
3800	typedef enum HDMI_DATA_SCRAMBLE_EN {
3801	HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000,
3802	HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001,
3803	} HDMI_DATA_SCRAMBLE_EN;
3804
3805	/*
3806	* HDMI_CLOCK_CHANNEL_RATE enum
3807	*/
3808
3809	typedef enum HDMI_CLOCK_CHANNEL_RATE {
3810	HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000,
3811	HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001,
3812	} HDMI_CLOCK_CHANNEL_RATE;
3813
3814	/*
3815	* HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
3816	*/
3817
3818	typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
3819	HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000,
3820	HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001,
3821	} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
3822
3823	/*
3824	* HDMI_PACKET_GEN_VERSION enum
3825	*/
3826
3827	typedef enum HDMI_PACKET_GEN_VERSION {
3828	HDMI_PACKET_GEN_VERSION_OLD = 0x00000000,
3829	HDMI_PACKET_GEN_VERSION_NEW = 0x00000001,
3830	} HDMI_PACKET_GEN_VERSION;
3831
3832	/*
3833	* HDMI_ERROR_ACK enum
3834	*/
3835
3836	typedef enum HDMI_ERROR_ACK {
3837	HDMI_ERROR_ACK_INT = 0x00000000,
3838	HDMI_ERROR_NOT_ACK = 0x00000001,
3839	} HDMI_ERROR_ACK;
3840
3841	/*
3842	* HDMI_ERROR_MASK enum
3843	*/
3844
3845	typedef enum HDMI_ERROR_MASK {
3846	HDMI_ERROR_MASK_INT = 0x00000000,
3847	HDMI_ERROR_NOT_MASK = 0x00000001,
3848	} HDMI_ERROR_MASK;
3849
3850	/*
3851	* HDMI_DEEP_COLOR_DEPTH enum
3852	*/
3853
3854	typedef enum HDMI_DEEP_COLOR_DEPTH {
3855	HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000,
3856	HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001,
3857	HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002,
3858	HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x00000003,
3859	} HDMI_DEEP_COLOR_DEPTH;
3860
3861	/*
3862	* HDMI_AUDIO_DELAY_EN enum
3863	*/
3864
3865	typedef enum HDMI_AUDIO_DELAY_EN {
3866	HDMI_AUDIO_DELAY_DISABLE = 0x00000000,
3867	HDMI_AUDIO_DELAY_58CLK = 0x00000001,
3868	HDMI_AUDIO_DELAY_56CLK = 0x00000002,
3869	HDMI_AUDIO_DELAY_RESERVED = 0x00000003,
3870	} HDMI_AUDIO_DELAY_EN;
3871
3872	/*
3873	* HDMI_AUDIO_SEND_MAX_PACKETS enum
3874	*/
3875
3876	typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
3877	HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000,
3878	HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001,
3879	} HDMI_AUDIO_SEND_MAX_PACKETS;
3880
3881	/*
3882	* HDMI_ACR_SEND enum
3883	*/
3884
3885	typedef enum HDMI_ACR_SEND {
3886	HDMI_ACR_NOT_SEND = 0x00000000,
3887	HDMI_ACR_PKT_SEND = 0x00000001,
3888	} HDMI_ACR_SEND;
3889
3890	/*
3891	* HDMI_ACR_CONT enum
3892	*/
3893
3894	typedef enum HDMI_ACR_CONT {
3895	HDMI_ACR_CONT_DISABLE = 0x00000000,
3896	HDMI_ACR_CONT_ENABLE = 0x00000001,
3897	} HDMI_ACR_CONT;
3898
3899	/*
3900	* HDMI_ACR_SELECT enum
3901	*/
3902
3903	typedef enum HDMI_ACR_SELECT {
3904	HDMI_ACR_SELECT_HW = 0x00000000,
3905	HDMI_ACR_SELECT_32K = 0x00000001,
3906	HDMI_ACR_SELECT_44K = 0x00000002,
3907	HDMI_ACR_SELECT_48K = 0x00000003,
3908	} HDMI_ACR_SELECT;
3909
3910	/*
3911	* HDMI_ACR_SOURCE enum
3912	*/
3913
3914	typedef enum HDMI_ACR_SOURCE {
3915	HDMI_ACR_SOURCE_HW = 0x00000000,
3916	HDMI_ACR_SOURCE_SW = 0x00000001,
3917	} HDMI_ACR_SOURCE;
3918
3919	/*
3920	* HDMI_ACR_N_MULTIPLE enum
3921	*/
3922
3923	typedef enum HDMI_ACR_N_MULTIPLE {
3924	HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000,
3925	HDMI_ACR_1_MULTIPLE = 0x00000001,
3926	HDMI_ACR_2_MULTIPLE = 0x00000002,
3927	HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003,
3928	HDMI_ACR_4_MULTIPLE = 0x00000004,
3929	HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005,
3930	HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006,
3931	HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007,
3932	} HDMI_ACR_N_MULTIPLE;
3933
3934	/*
3935	* HDMI_ACR_AUDIO_PRIORITY enum
3936	*/
3937
3938	typedef enum HDMI_ACR_AUDIO_PRIORITY {
3939	HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
3940	HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
3941	} HDMI_ACR_AUDIO_PRIORITY;
3942
3943	/*
3944	* HDMI_NULL_SEND enum
3945	*/
3946
3947	typedef enum HDMI_NULL_SEND {
3948	HDMI_NULL_NOT_SEND = 0x00000000,
3949	HDMI_NULL_PKT_SEND = 0x00000001,
3950	} HDMI_NULL_SEND;
3951
3952	/*
3953	* HDMI_GC_SEND enum
3954	*/
3955
3956	typedef enum HDMI_GC_SEND {
3957	HDMI_GC_NOT_SEND = 0x00000000,
3958	HDMI_GC_PKT_SEND = 0x00000001,
3959	} HDMI_GC_SEND;
3960
3961	/*
3962	* HDMI_GC_CONT enum
3963	*/
3964
3965	typedef enum HDMI_GC_CONT {
3966	HDMI_GC_CONT_DISABLE = 0x00000000,
3967	HDMI_GC_CONT_ENABLE = 0x00000001,
3968	} HDMI_GC_CONT;
3969
3970	/*
3971	* HDMI_ISRC_SEND enum
3972	*/
3973
3974	typedef enum HDMI_ISRC_SEND {
3975	HDMI_ISRC_NOT_SEND = 0x00000000,
3976	HDMI_ISRC_PKT_SEND = 0x00000001,
3977	} HDMI_ISRC_SEND;
3978
3979	/*
3980	* HDMI_ISRC_CONT enum
3981	*/
3982
3983	typedef enum HDMI_ISRC_CONT {
3984	HDMI_ISRC_CONT_DISABLE = 0x00000000,
3985	HDMI_ISRC_CONT_ENABLE = 0x00000001,
3986	} HDMI_ISRC_CONT;
3987
3988	/*
3989	* HDMI_AVI_INFO_SEND enum
3990	*/
3991
3992	typedef enum HDMI_AVI_INFO_SEND {
3993	HDMI_AVI_INFO_NOT_SEND = 0x00000000,
3994	HDMI_AVI_INFO_PKT_SEND = 0x00000001,
3995	} HDMI_AVI_INFO_SEND;
3996
3997	/*
3998	* HDMI_AVI_INFO_CONT enum
3999	*/
4000
4001	typedef enum HDMI_AVI_INFO_CONT {
4002	HDMI_AVI_INFO_CONT_DISABLE = 0x00000000,
4003	HDMI_AVI_INFO_CONT_ENABLE = 0x00000001,
4004	} HDMI_AVI_INFO_CONT;
4005
4006	/*
4007	* HDMI_AUDIO_INFO_SEND enum
4008	*/
4009
4010	typedef enum HDMI_AUDIO_INFO_SEND {
4011	HDMI_AUDIO_INFO_NOT_SEND = 0x00000000,
4012	HDMI_AUDIO_INFO_PKT_SEND = 0x00000001,
4013	} HDMI_AUDIO_INFO_SEND;
4014
4015	/*
4016	* HDMI_AUDIO_INFO_CONT enum
4017	*/
4018
4019	typedef enum HDMI_AUDIO_INFO_CONT {
4020	HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000,
4021	HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001,
4022	} HDMI_AUDIO_INFO_CONT;
4023
4024	/*
4025	* HDMI_MPEG_INFO_SEND enum
4026	*/
4027
4028	typedef enum HDMI_MPEG_INFO_SEND {
4029	HDMI_MPEG_INFO_NOT_SEND = 0x00000000,
4030	HDMI_MPEG_INFO_PKT_SEND = 0x00000001,
4031	} HDMI_MPEG_INFO_SEND;
4032
4033	/*
4034	* HDMI_MPEG_INFO_CONT enum
4035	*/
4036
4037	typedef enum HDMI_MPEG_INFO_CONT {
4038	HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000,
4039	HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001,
4040	} HDMI_MPEG_INFO_CONT;
4041
4042	/*
4043	* HDMI_GENERIC0_SEND enum
4044	*/
4045
4046	typedef enum HDMI_GENERIC0_SEND {
4047	HDMI_GENERIC0_NOT_SEND = 0x00000000,
4048	HDMI_GENERIC0_PKT_SEND = 0x00000001,
4049	} HDMI_GENERIC0_SEND;
4050
4051	/*
4052	* HDMI_GENERIC0_CONT enum
4053	*/
4054
4055	typedef enum HDMI_GENERIC0_CONT {
4056	HDMI_GENERIC0_CONT_DISABLE = 0x00000000,
4057	HDMI_GENERIC0_CONT_ENABLE = 0x00000001,
4058	} HDMI_GENERIC0_CONT;
4059
4060	/*
4061	* HDMI_GENERIC1_SEND enum
4062	*/
4063
4064	typedef enum HDMI_GENERIC1_SEND {
4065	HDMI_GENERIC1_NOT_SEND = 0x00000000,
4066	HDMI_GENERIC1_PKT_SEND = 0x00000001,
4067	} HDMI_GENERIC1_SEND;
4068
4069	/*
4070	* HDMI_GENERIC1_CONT enum
4071	*/
4072
4073	typedef enum HDMI_GENERIC1_CONT {
4074	HDMI_GENERIC1_CONT_DISABLE = 0x00000000,
4075	HDMI_GENERIC1_CONT_ENABLE = 0x00000001,
4076	} HDMI_GENERIC1_CONT;
4077
4078	/*
4079	* HDMI_GC_AVMUTE_CONT enum
4080	*/
4081
4082	typedef enum HDMI_GC_AVMUTE_CONT {
4083	HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000,
4084	HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001,
4085	} HDMI_GC_AVMUTE_CONT;
4086
4087	/*
4088	* HDMI_PACKING_PHASE_OVERRIDE enum
4089	*/
4090
4091	typedef enum HDMI_PACKING_PHASE_OVERRIDE {
4092	HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000,
4093	HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001,
4094	} HDMI_PACKING_PHASE_OVERRIDE;
4095
4096	/*
4097	* HDMI_GENERIC2_SEND enum
4098	*/
4099
4100	typedef enum HDMI_GENERIC2_SEND {
4101	HDMI_GENERIC2_NOT_SEND = 0x00000000,
4102	HDMI_GENERIC2_PKT_SEND = 0x00000001,
4103	} HDMI_GENERIC2_SEND;
4104
4105	/*
4106	* HDMI_GENERIC2_CONT enum
4107	*/
4108
4109	typedef enum HDMI_GENERIC2_CONT {
4110	HDMI_GENERIC2_CONT_DISABLE = 0x00000000,
4111	HDMI_GENERIC2_CONT_ENABLE = 0x00000001,
4112	} HDMI_GENERIC2_CONT;
4113
4114	/*
4115	* HDMI_GENERIC3_SEND enum
4116	*/
4117
4118	typedef enum HDMI_GENERIC3_SEND {
4119	HDMI_GENERIC3_NOT_SEND = 0x00000000,
4120	HDMI_GENERIC3_PKT_SEND = 0x00000001,
4121	} HDMI_GENERIC3_SEND;
4122
4123	/*
4124	* HDMI_GENERIC3_CONT enum
4125	*/
4126
4127	typedef enum HDMI_GENERIC3_CONT {
4128	HDMI_GENERIC3_CONT_DISABLE = 0x00000000,
4129	HDMI_GENERIC3_CONT_ENABLE = 0x00000001,
4130	} HDMI_GENERIC3_CONT;
4131
4132	/*
4133	* TMDS_PIXEL_ENCODING enum
4134	*/
4135
4136	typedef enum TMDS_PIXEL_ENCODING {
4137	TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000,
4138	TMDS_PIXEL_ENCODING_422 = 0x00000001,
4139	} TMDS_PIXEL_ENCODING;
4140
4141	/*
4142	* TMDS_COLOR_FORMAT enum
4143	*/
4144
4145	typedef enum TMDS_COLOR_FORMAT {
4146	TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000,
4147	TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001,
4148	TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002,
4149	TMDS_COLOR_FORMAT_RESERVED = 0x00000003,
4150	} TMDS_COLOR_FORMAT;
4151
4152	/*
4153	* TMDS_STEREOSYNC_CTL_SEL_REG enum
4154	*/
4155
4156	typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
4157	TMDS_STEREOSYNC_CTL0 = 0x00000000,
4158	TMDS_STEREOSYNC_CTL1 = 0x00000001,
4159	TMDS_STEREOSYNC_CTL2 = 0x00000002,
4160	TMDS_STEREOSYNC_CTL3 = 0x00000003,
4161	} TMDS_STEREOSYNC_CTL_SEL_REG;
4162
4163	/*
4164	* TMDS_CTL0_DATA_SEL enum
4165	*/
4166
4167	typedef enum TMDS_CTL0_DATA_SEL {
4168	TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000,
4169	TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4170	TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002,
4171	TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003,
4172	TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004,
4173	TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4174	TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006,
4175	TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007,
4176	} TMDS_CTL0_DATA_SEL;
4177
4178	/*
4179	* TMDS_CTL0_DATA_INVERT enum
4180	*/
4181
4182	typedef enum TMDS_CTL0_DATA_INVERT {
4183	TMDS_CTL0_DATA_NORMAL = 0x00000000,
4184	TMDS_CTL0_DATA_INVERT_EN = 0x00000001,
4185	} TMDS_CTL0_DATA_INVERT;
4186
4187	/*
4188	* TMDS_CTL0_DATA_MODULATION enum
4189	*/
4190
4191	typedef enum TMDS_CTL0_DATA_MODULATION {
4192	TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000,
4193	TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001,
4194	TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002,
4195	TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003,
4196	} TMDS_CTL0_DATA_MODULATION;
4197
4198	/*
4199	* TMDS_CTL0_PATTERN_OUT_EN enum
4200	*/
4201
4202	typedef enum TMDS_CTL0_PATTERN_OUT_EN {
4203	TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000,
4204	TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001,
4205	} TMDS_CTL0_PATTERN_OUT_EN;
4206
4207	/*
4208	* TMDS_CTL1_DATA_SEL enum
4209	*/
4210
4211	typedef enum TMDS_CTL1_DATA_SEL {
4212	TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000,
4213	TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4214	TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002,
4215	TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003,
4216	TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004,
4217	TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4218	TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006,
4219	TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007,
4220	} TMDS_CTL1_DATA_SEL;
4221
4222	/*
4223	* TMDS_CTL1_DATA_INVERT enum
4224	*/
4225
4226	typedef enum TMDS_CTL1_DATA_INVERT {
4227	TMDS_CTL1_DATA_NORMAL = 0x00000000,
4228	TMDS_CTL1_DATA_INVERT_EN = 0x00000001,
4229	} TMDS_CTL1_DATA_INVERT;
4230
4231	/*
4232	* TMDS_CTL1_DATA_MODULATION enum
4233	*/
4234
4235	typedef enum TMDS_CTL1_DATA_MODULATION {
4236	TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000,
4237	TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001,
4238	TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002,
4239	TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003,
4240	} TMDS_CTL1_DATA_MODULATION;
4241
4242	/*
4243	* TMDS_CTL1_PATTERN_OUT_EN enum
4244	*/
4245
4246	typedef enum TMDS_CTL1_PATTERN_OUT_EN {
4247	TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000,
4248	TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001,
4249	} TMDS_CTL1_PATTERN_OUT_EN;
4250
4251	/*
4252	* TMDS_CTL2_DATA_SEL enum
4253	*/
4254
4255	typedef enum TMDS_CTL2_DATA_SEL {
4256	TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000,
4257	TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4258	TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002,
4259	TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003,
4260	TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004,
4261	TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4262	TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006,
4263	TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007,
4264	} TMDS_CTL2_DATA_SEL;
4265
4266	/*
4267	* TMDS_CTL2_DATA_INVERT enum
4268	*/
4269
4270	typedef enum TMDS_CTL2_DATA_INVERT {
4271	TMDS_CTL2_DATA_NORMAL = 0x00000000,
4272	TMDS_CTL2_DATA_INVERT_EN = 0x00000001,
4273	} TMDS_CTL2_DATA_INVERT;
4274
4275	/*
4276	* TMDS_CTL2_DATA_MODULATION enum
4277	*/
4278
4279	typedef enum TMDS_CTL2_DATA_MODULATION {
4280	TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000,
4281	TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001,
4282	TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002,
4283	TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003,
4284	} TMDS_CTL2_DATA_MODULATION;
4285
4286	/*
4287	* TMDS_CTL2_PATTERN_OUT_EN enum
4288	*/
4289
4290	typedef enum TMDS_CTL2_PATTERN_OUT_EN {
4291	TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000,
4292	TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001,
4293	} TMDS_CTL2_PATTERN_OUT_EN;
4294
4295	/*
4296	* TMDS_CTL3_DATA_INVERT enum
4297	*/
4298
4299	typedef enum TMDS_CTL3_DATA_INVERT {
4300	TMDS_CTL3_DATA_NORMAL = 0x00000000,
4301	TMDS_CTL3_DATA_INVERT_EN = 0x00000001,
4302	} TMDS_CTL3_DATA_INVERT;
4303
4304	/*
4305	* TMDS_CTL3_DATA_MODULATION enum
4306	*/
4307
4308	typedef enum TMDS_CTL3_DATA_MODULATION {
4309	TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000,
4310	TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001,
4311	TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002,
4312	TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003,
4313	} TMDS_CTL3_DATA_MODULATION;
4314
4315	/*
4316	* TMDS_CTL3_PATTERN_OUT_EN enum
4317	*/
4318
4319	typedef enum TMDS_CTL3_PATTERN_OUT_EN {
4320	TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000,
4321	TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001,
4322	} TMDS_CTL3_PATTERN_OUT_EN;
4323
4324	/*
4325	* TMDS_CTL3_DATA_SEL enum
4326	*/
4327
4328	typedef enum TMDS_CTL3_DATA_SEL {
4329	TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000,
4330	TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4331	TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002,
4332	TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003,
4333	TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004,
4334	TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4335	TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006,
4336	TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007,
4337	} TMDS_CTL3_DATA_SEL;
4338
4339	/*
4340	* DIG_FE_CNTL_SOURCE_SELECT enum
4341	*/
4342
4343	typedef enum DIG_FE_CNTL_SOURCE_SELECT {
4344	DIG_FE_SOURCE_FROM_FMT0 = 0x00000000,
4345	DIG_FE_SOURCE_FROM_FMT1 = 0x00000001,
4346	DIG_FE_SOURCE_FROM_FMT2 = 0x00000002,
4347	DIG_FE_SOURCE_FROM_FMT3 = 0x00000003,
4348	DIG_FE_SOURCE_FROM_FMT4 = 0x00000004,
4349	DIG_FE_SOURCE_FROM_FMT5 = 0x00000005,
4350	} DIG_FE_CNTL_SOURCE_SELECT;
4351
4352	/*
4353	* DIG_FE_CNTL_STEREOSYNC_SELECT enum
4354	*/
4355
4356	typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
4357	DIG_FE_STEREOSYNC_FROM_FMT0 = 0x00000000,
4358	DIG_FE_STEREOSYNC_FROM_FMT1 = 0x00000001,
4359	DIG_FE_STEREOSYNC_FROM_FMT2 = 0x00000002,
4360	DIG_FE_STEREOSYNC_FROM_FMT3 = 0x00000003,
4361	DIG_FE_STEREOSYNC_FROM_FMT4 = 0x00000004,
4362	DIG_FE_STEREOSYNC_FROM_FMT5 = 0x00000005,
4363	} DIG_FE_CNTL_STEREOSYNC_SELECT;
4364
4365	/*
4366	* DIG_FIFO_READ_CLOCK_SRC enum
4367	*/
4368
4369	typedef enum DIG_FIFO_READ_CLOCK_SRC {
4370	DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000,
4371	DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001,
4372	} DIG_FIFO_READ_CLOCK_SRC;
4373
4374	/*
4375	* DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
4376	*/
4377
4378	typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
4379	DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000,
4380	DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001,
4381	} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
4382
4383	/*
4384	* DIG_OUTPUT_CRC_DATA_SEL enum
4385	*/
4386
4387	typedef enum DIG_OUTPUT_CRC_DATA_SEL {
4388	DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000,
4389	DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001,
4390	DIG_OUTPUT_CRC_FOR_VBI = 0x00000002,
4391	DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003,
4392	} DIG_OUTPUT_CRC_DATA_SEL;
4393
4394	/*
4395	* DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
4396	*/
4397
4398	typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
4399	DIG_IN_NORMAL_OPERATION = 0x00000000,
4400	DIG_IN_DEBUG_MODE = 0x00000001,
4401	} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
4402
4403	/*
4404	* DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
4405	*/
4406
4407	typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
4408	DIG_10BIT_TEST_PATTERN = 0x00000000,
4409	DIG_ALTERNATING_TEST_PATTERN = 0x00000001,
4410	} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
4411
4412	/*
4413	* DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
4414	*/
4415
4416	typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
4417	DIG_TEST_PATTERN_NORMAL = 0x00000000,
4418	DIG_TEST_PATTERN_RANDOM = 0x00000001,
4419	} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
4420
4421	/*
4422	* DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
4423	*/
4424
4425	typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
4426	DIG_RANDOM_PATTERN_ENABLED = 0x00000000,
4427	DIG_RANDOM_PATTERN_RESETED = 0x00000001,
4428	} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
4429
4430	/*
4431	* DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
4432	*/
4433
4434	typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
4435	DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000,
4436	DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001,
4437	} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
4438
4439	/*
4440	* DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
4441	*/
4442
4443	typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
4444	DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000,
4445	DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001,
4446	} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
4447
4448	/*
4449	* DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
4450	*/
4451
4452	typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
4453	DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000,
4454	DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001,
4455	} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
4456
4457	/*
4458	* DIG_FIFO_ERROR_ACK enum
4459	*/
4460
4461	typedef enum DIG_FIFO_ERROR_ACK {
4462	DIG_FIFO_ERROR_ACK_INT = 0x00000000,
4463	DIG_FIFO_ERROR_NOT_ACK = 0x00000001,
4464	} DIG_FIFO_ERROR_ACK;
4465
4466	/*
4467	* DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
4468	*/
4469
4470	typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
4471	DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000,
4472	DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001,
4473	} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
4474
4475	/*
4476	* DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
4477	*/
4478
4479	typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
4480	DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000,
4481	DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001,
4482	} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
4483
4484	/*
4485	* AFMT_INTERRUPT_STATUS_CHG_MASK enum
4486	*/
4487
4488	typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
4489	AFMT_INTERRUPT_DISABLE = 0x00000000,
4490	AFMT_INTERRUPT_ENABLE = 0x00000001,
4491	} AFMT_INTERRUPT_STATUS_CHG_MASK;
4492
4493	/*
4494	* HDMI_GC_AVMUTE enum
4495	*/
4496
4497	typedef enum HDMI_GC_AVMUTE {
4498	HDMI_GC_AVMUTE_SET = 0x00000000,
4499	HDMI_GC_AVMUTE_UNSET = 0x00000001,
4500	} HDMI_GC_AVMUTE;
4501
4502	/*
4503	* HDMI_DEFAULT_PAHSE enum
4504	*/
4505
4506	typedef enum HDMI_DEFAULT_PAHSE {
4507	HDMI_DEFAULT_PHASE_IS_0 = 0x00000000,
4508	HDMI_DEFAULT_PHASE_IS_1 = 0x00000001,
4509	} HDMI_DEFAULT_PAHSE;
4510
4511	/*
4512	* AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
4513	*/
4514
4515	typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
4516	AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000,
4517	AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001,
4518	} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
4519
4520	/*
4521	* AUDIO_LAYOUT_SELECT enum
4522	*/
4523
4524	typedef enum AUDIO_LAYOUT_SELECT {
4525	AUDIO_LAYOUT_0 = 0x00000000,
4526	AUDIO_LAYOUT_1 = 0x00000001,
4527	} AUDIO_LAYOUT_SELECT;
4528
4529	/*
4530	* AFMT_AUDIO_CRC_CONTROL_CONT enum
4531	*/
4532
4533	typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
4534	AFMT_AUDIO_CRC_ONESHOT = 0x00000000,
4535	AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001,
4536	} AFMT_AUDIO_CRC_CONTROL_CONT;
4537
4538	/*
4539	* AFMT_AUDIO_CRC_CONTROL_SOURCE enum
4540	*/
4541
4542	typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
4543	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000,
4544	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001,
4545	} AFMT_AUDIO_CRC_CONTROL_SOURCE;
4546
4547	/*
4548	* AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
4549	*/
4550
4551	typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
4552	AFMT_AUDIO_CRC_CH0_SIG = 0x00000000,
4553	AFMT_AUDIO_CRC_CH1_SIG = 0x00000001,
4554	AFMT_AUDIO_CRC_CH2_SIG = 0x00000002,
4555	AFMT_AUDIO_CRC_CH3_SIG = 0x00000003,
4556	AFMT_AUDIO_CRC_CH4_SIG = 0x00000004,
4557	AFMT_AUDIO_CRC_CH5_SIG = 0x00000005,
4558	AFMT_AUDIO_CRC_CH6_SIG = 0x00000006,
4559	AFMT_AUDIO_CRC_CH7_SIG = 0x00000007,
4560	AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008,
4561	AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009,
4562	AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a,
4563	AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b,
4564	AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c,
4565	AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d,
4566	AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e,
4567	AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f,
4568	} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
4569
4570	/*
4571	* AFMT_RAMP_CONTROL0_SIGN enum
4572	*/
4573
4574	typedef enum AFMT_RAMP_CONTROL0_SIGN {
4575	AFMT_RAMP_SIGNED = 0x00000000,
4576	AFMT_RAMP_UNSIGNED = 0x00000001,
4577	} AFMT_RAMP_CONTROL0_SIGN;
4578
4579	/*
4580	* AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
4581	*/
4582
4583	typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
4584	AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000,
4585	AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001,
4586	} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
4587
4588	/*
4589	* AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
4590	*/
4591
4592	typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
4593	AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000,
4594	AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001,
4595	} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
4596
4597	/*
4598	* AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
4599	*/
4600
4601	typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
4602	AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000,
4603	AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001,
4604	} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
4605
4606	/*
4607	* AFMT_AUDIO_SRC_CONTROL_SELECT enum
4608	*/
4609
4610	typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
4611	AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000,
4612	AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001,
4613	AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002,
4614	AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003,
4615	AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004,
4616	AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005,
4617	AFMT_AUDIO_SRC_RESERVED = 0x00000006,
4618	} AFMT_AUDIO_SRC_CONTROL_SELECT;
4619
4620	/*
4621	* DIG_BE_CNTL_MODE enum
4622	*/
4623
4624	typedef enum DIG_BE_CNTL_MODE {
4625	DIG_BE_DP_SST_MODE = 0x00000000,
4626	DIG_BE_RESERVED1 = 0x00000001,
4627	DIG_BE_TMDS_DVI_MODE = 0x00000002,
4628	DIG_BE_TMDS_HDMI_MODE = 0x00000003,
4629	DIG_BE_SDVO_RESERVED = 0x00000004,
4630	DIG_BE_DP_MST_MODE = 0x00000005,
4631	DIG_BE_RESERVED2 = 0x00000006,
4632	DIG_BE_RESERVED3 = 0x00000007,
4633	} DIG_BE_CNTL_MODE;
4634
4635	/*
4636	* DIG_BE_CNTL_HPD_SELECT enum
4637	*/
4638
4639	typedef enum DIG_BE_CNTL_HPD_SELECT {
4640	DIG_BE_CNTL_HPD1 = 0x00000000,
4641	DIG_BE_CNTL_HPD2 = 0x00000001,
4642	DIG_BE_CNTL_HPD3 = 0x00000002,
4643	DIG_BE_CNTL_HPD4 = 0x00000003,
4644	DIG_BE_CNTL_HPD5 = 0x00000004,
4645	DIG_BE_CNTL_HPD6 = 0x00000005,
4646	} DIG_BE_CNTL_HPD_SELECT;
4647
4648	/*
4649	* LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
4650	*/
4651
4652	typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
4653	LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000,
4654	LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001,
4655	} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
4656
4657	/*
4658	* TMDS_SYNC_PHASE enum
4659	*/
4660
4661	typedef enum TMDS_SYNC_PHASE {
4662	TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000,
4663	TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001,
4664	} TMDS_SYNC_PHASE;
4665
4666	/*
4667	* TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
4668	*/
4669
4670	typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
4671	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000,
4672	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001,
4673	} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
4674
4675	/*
4676	* TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
4677	*/
4678
4679	typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
4680	TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000,
4681	TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001,
4682	} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
4683
4684	/*
4685	* TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
4686	*/
4687
4688	typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
4689	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
4690	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001,
4691	} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
4692
4693	/*
4694	* TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
4695	*/
4696
4697	typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
4698	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
4699	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001,
4700	} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
4701
4702	/*
4703	* TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
4704	*/
4705
4706	typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
4707	TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000,
4708	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001,
4709	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002,
4710	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003,
4711	} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
4712
4713	/*
4714	* TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
4715	*/
4716
4717	typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
4718	TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000,
4719	TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001,
4720	} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
4721
4722	/*
4723	* TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
4724	*/
4725
4726	typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
4727	TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000,
4728	TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001,
4729	} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
4730
4731	/*
4732	* TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
4733	*/
4734
4735	typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
4736	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000,
4737	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001,
4738	} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
4739
4740	/*
4741	* TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
4742	*/
4743
4744	typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
4745	TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000,
4746	TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001,
4747	} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
4748
4749	/*
4750	* TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
4751	*/
4752
4753	typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
4754	TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000,
4755	TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001,
4756	} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
4757
4758	/*
4759	* TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
4760	*/
4761
4762	typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
4763	TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000,
4764	TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001,
4765	} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
4766
4767	/*
4768	* TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
4769	*/
4770
4771	typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
4772	TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000,
4773	TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001,
4774	} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
4775
4776	/*
4777	* TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
4778	*/
4779
4780	typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
4781	TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000,
4782	TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001,
4783	} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
4784
4785	/*
4786	* TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
4787	*/
4788
4789	typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
4790	TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000,
4791	TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001,
4792	} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
4793
4794	/*
4795	* TMDS_REG_TEST_OUTPUTA_CNTLA enum
4796	*/
4797
4798	typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
4799	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000,
4800	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001,
4801	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002,
4802	TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003,
4803	} TMDS_REG_TEST_OUTPUTA_CNTLA;
4804
4805	/*
4806	* TMDS_REG_TEST_OUTPUTB_CNTLB enum
4807	*/
4808
4809	typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
4810	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000,
4811	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001,
4812	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002,
4813	TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003,
4814	} TMDS_REG_TEST_OUTPUTB_CNTLB;
4815
4816	/*******************************************************
4817	* DCP Enums
4818	*******************************************************/
4819
4820	/*
4821	* DCP_GRPH_ENABLE enum
4822	*/
4823
4824	typedef enum DCP_GRPH_ENABLE {
4825	DCP_GRPH_ENABLE_FALSE = 0x00000000,
4826	DCP_GRPH_ENABLE_TRUE = 0x00000001,
4827	} DCP_GRPH_ENABLE;
4828
4829	/*
4830	* DCP_GRPH_KEYER_ALPHA_SEL enum
4831	*/
4832
4833	typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
4834	DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x00000000,
4835	DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x00000001,
4836	} DCP_GRPH_KEYER_ALPHA_SEL;
4837
4838	/*
4839	* DCP_GRPH_DEPTH enum
4840	*/
4841
4842	typedef enum DCP_GRPH_DEPTH {
4843	DCP_GRPH_DEPTH_8BPP = 0x00000000,
4844	DCP_GRPH_DEPTH_16BPP = 0x00000001,
4845	DCP_GRPH_DEPTH_32BPP = 0x00000002,
4846	DCP_GRPH_DEPTH_64BPP = 0x00000003,
4847	} DCP_GRPH_DEPTH;
4848
4849	/*
4850	* DCP_GRPH_NUM_BANKS enum
4851	*/
4852
4853	typedef enum DCP_GRPH_NUM_BANKS {
4854	DCP_GRPH_NUM_BANKS_1BANK = 0x00000000,
4855	DCP_GRPH_NUM_BANKS_2BANK = 0x00000001,
4856	DCP_GRPH_NUM_BANKS_4BANK = 0x00000002,
4857	DCP_GRPH_NUM_BANKS_8BANK = 0x00000003,
4858	DCP_GRPH_NUM_BANKS_16BANK = 0x00000004,
4859	} DCP_GRPH_NUM_BANKS;
4860
4861	/*
4862	* DCP_GRPH_NUM_PIPES enum
4863	*/
4864
4865	typedef enum DCP_GRPH_NUM_PIPES {
4866	DCP_GRPH_NUM_PIPES_1PIPE = 0x00000000,
4867	DCP_GRPH_NUM_PIPES_2PIPE = 0x00000001,
4868	DCP_GRPH_NUM_PIPES_4PIPE = 0x00000002,
4869	DCP_GRPH_NUM_PIPES_8PIPE = 0x00000003,
4870	} DCP_GRPH_NUM_PIPES;
4871
4872	/*
4873	* DCP_GRPH_FORMAT enum
4874	*/
4875
4876	typedef enum DCP_GRPH_FORMAT {
4877	DCP_GRPH_FORMAT_8BPP = 0x00000000,
4878	DCP_GRPH_FORMAT_16BPP = 0x00000001,
4879	DCP_GRPH_FORMAT_32BPP = 0x00000002,
4880	DCP_GRPH_FORMAT_64BPP = 0x00000003,
4881	} DCP_GRPH_FORMAT;
4882
4883	/*
4884	* DCP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
4885	*/
4886
4887	typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
4888	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x00000000,
4889	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x00000001,
4890	} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
4891
4892	/*
4893	* DCP_GRPH_SW_MODE enum
4894	*/
4895
4896	typedef enum DCP_GRPH_SW_MODE {
4897	DCP_GRPH_SW_MODE_0 = 0x00000000,
4898	DCP_GRPH_SW_MODE_2 = 0x00000002,
4899	DCP_GRPH_SW_MODE_3 = 0x00000003,
4900	DCP_GRPH_SW_MODE_22 = 0x00000016,
4901	DCP_GRPH_SW_MODE_23 = 0x00000017,
4902	DCP_GRPH_SW_MODE_26 = 0x0000001a,
4903	DCP_GRPH_SW_MODE_27 = 0x0000001b,
4904	DCP_GRPH_SW_MODE_30 = 0x0000001e,
4905	DCP_GRPH_SW_MODE_31 = 0x0000001f,
4906	} DCP_GRPH_SW_MODE;
4907
4908	/*
4909	* DCP_GRPH_COLOR_EXPANSION_MODE enum
4910	*/
4911
4912	typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
4913	DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x00000000,
4914	DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x00000001,
4915	} DCP_GRPH_COLOR_EXPANSION_MODE;
4916
4917	/*
4918	* DCP_GRPH_LUT_10BIT_BYPASS_EN enum
4919	*/
4920
4921	typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
4922	DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x00000000,
4923	DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x00000001,
4924	} DCP_GRPH_LUT_10BIT_BYPASS_EN;
4925
4926	/*
4927	* DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN enum
4928	*/
4929
4930	typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
4931	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x00000000,
4932	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x00000001,
4933	} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
4934
4935	/*
4936	* DCP_GRPH_ENDIAN_SWAP enum
4937	*/
4938
4939	typedef enum DCP_GRPH_ENDIAN_SWAP {
4940	DCP_GRPH_ENDIAN_SWAP_NONE = 0x00000000,
4941	DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x00000001,
4942	DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x00000002,
4943	DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x00000003,
4944	} DCP_GRPH_ENDIAN_SWAP;
4945
4946	/*
4947	* DCP_GRPH_RED_CROSSBAR enum
4948	*/
4949
4950	typedef enum DCP_GRPH_RED_CROSSBAR {
4951	DCP_GRPH_RED_CROSSBAR_FROM_R = 0x00000000,
4952	DCP_GRPH_RED_CROSSBAR_FROM_G = 0x00000001,
4953	DCP_GRPH_RED_CROSSBAR_FROM_B = 0x00000002,
4954	DCP_GRPH_RED_CROSSBAR_FROM_A = 0x00000003,
4955	} DCP_GRPH_RED_CROSSBAR;
4956
4957	/*
4958	* DCP_GRPH_GREEN_CROSSBAR enum
4959	*/
4960
4961	typedef enum DCP_GRPH_GREEN_CROSSBAR {
4962	DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x00000000,
4963	DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x00000001,
4964	DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x00000002,
4965	DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x00000003,
4966	} DCP_GRPH_GREEN_CROSSBAR;
4967
4968	/*
4969	* DCP_GRPH_BLUE_CROSSBAR enum
4970	*/
4971
4972	typedef enum DCP_GRPH_BLUE_CROSSBAR {
4973	DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x00000000,
4974	DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x00000001,
4975	DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x00000002,
4976	DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x00000003,
4977	} DCP_GRPH_BLUE_CROSSBAR;
4978
4979	/*
4980	* DCP_GRPH_ALPHA_CROSSBAR enum
4981	*/
4982
4983	typedef enum DCP_GRPH_ALPHA_CROSSBAR {
4984	DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x00000000,
4985	DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x00000001,
4986	DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x00000002,
4987	DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x00000003,
4988	} DCP_GRPH_ALPHA_CROSSBAR;
4989
4990	/*
4991	* DCP_GRPH_PRIMARY_DFQ_ENABLE enum
4992	*/
4993
4994	typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
4995	DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x00000000,
4996	DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x00000001,
4997	} DCP_GRPH_PRIMARY_DFQ_ENABLE;
4998
4999	/*
5000	* DCP_GRPH_SECONDARY_DFQ_ENABLE enum
5001	*/
5002
5003	typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
5004	DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x00000000,
5005	DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x00000001,
5006	} DCP_GRPH_SECONDARY_DFQ_ENABLE;
5007
5008	/*
5009	* DCP_GRPH_INPUT_GAMMA_MODE enum
5010	*/
5011
5012	typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
5013	DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x00000000,
5014	DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x00000001,
5015	} DCP_GRPH_INPUT_GAMMA_MODE;
5016
5017	/*
5018	* DCP_GRPH_MODE_UPDATE_PENDING enum
5019	*/
5020
5021	typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
5022	DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x00000000,
5023	DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x00000001,
5024	} DCP_GRPH_MODE_UPDATE_PENDING;
5025
5026	/*
5027	* DCP_GRPH_MODE_UPDATE_TAKEN enum
5028	*/
5029
5030	typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
5031	DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x00000000,
5032	DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x00000001,
5033	} DCP_GRPH_MODE_UPDATE_TAKEN;
5034
5035	/*
5036	* DCP_GRPH_SURFACE_UPDATE_PENDING enum
5037	*/
5038
5039	typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
5040	DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x00000000,
5041	DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x00000001,
5042	} DCP_GRPH_SURFACE_UPDATE_PENDING;
5043
5044	/*
5045	* DCP_GRPH_SURFACE_UPDATE_TAKEN enum
5046	*/
5047
5048	typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
5049	DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x00000000,
5050	DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x00000001,
5051	} DCP_GRPH_SURFACE_UPDATE_TAKEN;
5052
5053	/*
5054	* DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE enum
5055	*/
5056
5057	typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
5058	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x00000000,
5059	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x00000001,
5060	} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
5061
5062	/*
5063	* DCP_GRPH_UPDATE_LOCK enum
5064	*/
5065
5066	typedef enum DCP_GRPH_UPDATE_LOCK {
5067	DCP_GRPH_UPDATE_LOCK_FALSE = 0x00000000,
5068	DCP_GRPH_UPDATE_LOCK_TRUE = 0x00000001,
5069	} DCP_GRPH_UPDATE_LOCK;
5070
5071	/*
5072	* DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
5073	*/
5074
5075	typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
5076	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x00000000,
5077	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x00000001,
5078	} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
5079
5080	/*
5081	* DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
5082	*/
5083
5084	typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
5085	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
5086	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
5087	} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
5088
5089	/*
5090	* DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
5091	*/
5092
5093	typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
5094	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
5095	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
5096	} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
5097
5098	/*
5099	* DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN enum
5100	*/
5101
5102	typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
5103	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x00000000,
5104	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x00000001,
5105	} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
5106
5107	/*
5108	* DCP_GRPH_XDMA_SUPER_AA_EN enum
5109	*/
5110
5111	typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
5112	DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x00000000,
5113	DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x00000001,
5114	} DCP_GRPH_XDMA_SUPER_AA_EN;
5115
5116	/*
5117	* DCP_GRPH_DFQ_RESET enum
5118	*/
5119
5120	typedef enum DCP_GRPH_DFQ_RESET {
5121	DCP_GRPH_DFQ_RESET_FALSE = 0x00000000,
5122	DCP_GRPH_DFQ_RESET_TRUE = 0x00000001,
5123	} DCP_GRPH_DFQ_RESET;
5124
5125	/*
5126	* DCP_GRPH_DFQ_SIZE enum
5127	*/
5128
5129	typedef enum DCP_GRPH_DFQ_SIZE {
5130	DCP_GRPH_DFQ_SIZE_DEEP1 = 0x00000000,
5131	DCP_GRPH_DFQ_SIZE_DEEP2 = 0x00000001,
5132	DCP_GRPH_DFQ_SIZE_DEEP3 = 0x00000002,
5133	DCP_GRPH_DFQ_SIZE_DEEP4 = 0x00000003,
5134	DCP_GRPH_DFQ_SIZE_DEEP5 = 0x00000004,
5135	DCP_GRPH_DFQ_SIZE_DEEP6 = 0x00000005,
5136	DCP_GRPH_DFQ_SIZE_DEEP7 = 0x00000006,
5137	DCP_GRPH_DFQ_SIZE_DEEP8 = 0x00000007,
5138	} DCP_GRPH_DFQ_SIZE;
5139
5140	/*
5141	* DCP_GRPH_DFQ_MIN_FREE_ENTRIES enum
5142	*/
5143
5144	typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
5145	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x00000000,
5146	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x00000001,
5147	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x00000002,
5148	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x00000003,
5149	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x00000004,
5150	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x00000005,
5151	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x00000006,
5152	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x00000007,
5153	} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
5154
5155	/*
5156	* DCP_GRPH_DFQ_RESET_ACK enum
5157	*/
5158
5159	typedef enum DCP_GRPH_DFQ_RESET_ACK {
5160	DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x00000000,
5161	DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x00000001,
5162	} DCP_GRPH_DFQ_RESET_ACK;
5163
5164	/*
5165	* DCP_GRPH_PFLIP_INT_CLEAR enum
5166	*/
5167
5168	typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
5169	DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x00000000,
5170	DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x00000001,
5171	} DCP_GRPH_PFLIP_INT_CLEAR;
5172
5173	/*
5174	* DCP_GRPH_PFLIP_INT_MASK enum
5175	*/
5176
5177	typedef enum DCP_GRPH_PFLIP_INT_MASK {
5178	DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x00000000,
5179	DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x00000001,
5180	} DCP_GRPH_PFLIP_INT_MASK;
5181
5182	/*
5183	* DCP_GRPH_PFLIP_INT_TYPE enum
5184	*/
5185
5186	typedef enum DCP_GRPH_PFLIP_INT_TYPE {
5187	DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x00000000,
5188	DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x00000001,
5189	} DCP_GRPH_PFLIP_INT_TYPE;
5190
5191	/*
5192	* DCP_GRPH_PRESCALE_SELECT enum
5193	*/
5194
5195	typedef enum DCP_GRPH_PRESCALE_SELECT {
5196	DCP_GRPH_PRESCALE_SELECT_FIXED = 0x00000000,
5197	DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x00000001,
5198	} DCP_GRPH_PRESCALE_SELECT;
5199
5200	/*
5201	* DCP_GRPH_PRESCALE_R_SIGN enum
5202	*/
5203
5204	typedef enum DCP_GRPH_PRESCALE_R_SIGN {
5205	DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x00000000,
5206	DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x00000001,
5207	} DCP_GRPH_PRESCALE_R_SIGN;
5208
5209	/*
5210	* DCP_GRPH_PRESCALE_G_SIGN enum
5211	*/
5212
5213	typedef enum DCP_GRPH_PRESCALE_G_SIGN {
5214	DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x00000000,
5215	DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x00000001,
5216	} DCP_GRPH_PRESCALE_G_SIGN;
5217
5218	/*
5219	* DCP_GRPH_PRESCALE_B_SIGN enum
5220	*/
5221
5222	typedef enum DCP_GRPH_PRESCALE_B_SIGN {
5223	DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x00000000,
5224	DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x00000001,
5225	} DCP_GRPH_PRESCALE_B_SIGN;
5226
5227	/*
5228	* DCP_GRPH_PRESCALE_BYPASS enum
5229	*/
5230
5231	typedef enum DCP_GRPH_PRESCALE_BYPASS {
5232	DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x00000000,
5233	DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x00000001,
5234	} DCP_GRPH_PRESCALE_BYPASS;
5235
5236	/*
5237	* DCP_INPUT_CSC_GRPH_MODE enum
5238	*/
5239
5240	typedef enum DCP_INPUT_CSC_GRPH_MODE {
5241	DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x00000000,
5242	DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x00000001,
5243	DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x00000002,
5244	DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x00000003,
5245	} DCP_INPUT_CSC_GRPH_MODE;
5246
5247	/*
5248	* DCP_OUTPUT_CSC_GRPH_MODE enum
5249	*/
5250
5251	typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
5252	DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x00000000,
5253	DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x00000001,
5254	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x00000002,
5255	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x00000003,
5256	DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x00000004,
5257	DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x00000005,
5258	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x00000006,
5259	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x00000007,
5260	} DCP_OUTPUT_CSC_GRPH_MODE;
5261
5262	/*
5263	* DCP_DENORM_MODE enum
5264	*/
5265
5266	typedef enum DCP_DENORM_MODE {
5267	DCP_DENORM_MODE_UNITY = 0x00000000,
5268	DCP_DENORM_MODE_6BIT = 0x00000001,
5269	DCP_DENORM_MODE_8BIT = 0x00000002,
5270	DCP_DENORM_MODE_10BIT = 0x00000003,
5271	DCP_DENORM_MODE_11BIT = 0x00000004,
5272	DCP_DENORM_MODE_12BIT = 0x00000005,
5273	DCP_DENORM_MODE_RESERVED0 = 0x00000006,
5274	DCP_DENORM_MODE_RESERVED1 = 0x00000007,
5275	} DCP_DENORM_MODE;
5276
5277	/*
5278	* DCP_DENORM_14BIT_OUT enum
5279	*/
5280
5281	typedef enum DCP_DENORM_14BIT_OUT {
5282	DCP_DENORM_14BIT_OUT_FALSE = 0x00000000,
5283	DCP_DENORM_14BIT_OUT_TRUE = 0x00000001,
5284	} DCP_DENORM_14BIT_OUT;
5285
5286	/*
5287	* DCP_OUT_ROUND_TRUNC_MODE enum
5288	*/
5289
5290	typedef enum DCP_OUT_ROUND_TRUNC_MODE {
5291	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x00000000,
5292	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x00000001,
5293	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x00000002,
5294	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x00000003,
5295	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x00000004,
5296	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x00000005,
5297	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x00000006,
5298	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x00000007,
5299	DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x00000008,
5300	DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x00000009,
5301	DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0x0000000a,
5302	DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0x0000000b,
5303	DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0x0000000c,
5304	DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0x0000000d,
5305	DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0x0000000e,
5306	DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0x0000000f,
5307	} DCP_OUT_ROUND_TRUNC_MODE;
5308
5309	/*
5310	* DCP_KEY_MODE enum
5311	*/
5312
5313	typedef enum DCP_KEY_MODE {
5314	DCP_KEY_MODE_ALPHA0 = 0x00000000,
5315	DCP_KEY_MODE_ALPHA1 = 0x00000001,
5316	DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x00000002,
5317	DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x00000003,
5318	} DCP_KEY_MODE;
5319
5320	/*
5321	* DCP_GRPH_DEGAMMA_MODE enum
5322	*/
5323
5324	typedef enum DCP_GRPH_DEGAMMA_MODE {
5325	DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x00000000,
5326	DCP_GRPH_DEGAMMA_MODE_ROMA = 0x00000001,
5327	DCP_GRPH_DEGAMMA_MODE_ROMB = 0x00000002,
5328	DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x00000003,
5329	} DCP_GRPH_DEGAMMA_MODE;
5330
5331	/*
5332	* DCP_CURSOR_DEGAMMA_MODE enum
5333	*/
5334
5335	typedef enum DCP_CURSOR_DEGAMMA_MODE {
5336	DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x00000000,
5337	DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x00000001,
5338	DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x00000002,
5339	DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x00000003,
5340	} DCP_CURSOR_DEGAMMA_MODE;
5341
5342	/*
5343	* DCP_GRPH_GAMUT_REMAP_MODE enum
5344	*/
5345
5346	typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
5347	DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x00000000,
5348	DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x00000001,
5349	DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x00000002,
5350	DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x00000003,
5351	} DCP_GRPH_GAMUT_REMAP_MODE;
5352
5353	/*
5354	* DCP_SPATIAL_DITHER_EN enum
5355	*/
5356
5357	typedef enum DCP_SPATIAL_DITHER_EN {
5358	DCP_SPATIAL_DITHER_EN_FALSE = 0x00000000,
5359	DCP_SPATIAL_DITHER_EN_TRUE = 0x00000001,
5360	} DCP_SPATIAL_DITHER_EN;
5361
5362	/*
5363	* DCP_SPATIAL_DITHER_MODE enum
5364	*/
5365
5366	typedef enum DCP_SPATIAL_DITHER_MODE {
5367	DCP_SPATIAL_DITHER_MODE_BYPASS = 0x00000000,
5368	DCP_SPATIAL_DITHER_MODE_ROMA = 0x00000001,
5369	DCP_SPATIAL_DITHER_MODE_ROMB = 0x00000002,
5370	DCP_SPATIAL_DITHER_MODE_RESERVED = 0x00000003,
5371	} DCP_SPATIAL_DITHER_MODE;
5372
5373	/*
5374	* DCP_SPATIAL_DITHER_DEPTH enum
5375	*/
5376
5377	typedef enum DCP_SPATIAL_DITHER_DEPTH {
5378	DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x00000000,
5379	DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
5380	DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x00000002,
5381	DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x00000003,
5382	} DCP_SPATIAL_DITHER_DEPTH;
5383
5384	/*
5385	* DCP_FRAME_RANDOM_ENABLE enum
5386	*/
5387
5388	typedef enum DCP_FRAME_RANDOM_ENABLE {
5389	DCP_FRAME_RANDOM_ENABLE_FALSE = 0x00000000,
5390	DCP_FRAME_RANDOM_ENABLE_TRUE = 0x00000001,
5391	} DCP_FRAME_RANDOM_ENABLE;
5392
5393	/*
5394	* DCP_RGB_RANDOM_ENABLE enum
5395	*/
5396
5397	typedef enum DCP_RGB_RANDOM_ENABLE {
5398	DCP_RGB_RANDOM_ENABLE_FALSE = 0x00000000,
5399	DCP_RGB_RANDOM_ENABLE_TRUE = 0x00000001,
5400	} DCP_RGB_RANDOM_ENABLE;
5401
5402	/*
5403	* DCP_HIGHPASS_RANDOM_ENABLE enum
5404	*/
5405
5406	typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
5407	DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x00000000,
5408	DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x00000001,
5409	} DCP_HIGHPASS_RANDOM_ENABLE;
5410
5411	/*
5412	* DCP_CURSOR_EN enum
5413	*/
5414
5415	typedef enum DCP_CURSOR_EN {
5416	DCP_CURSOR_EN_FALSE = 0x00000000,
5417	DCP_CURSOR_EN_TRUE = 0x00000001,
5418	} DCP_CURSOR_EN;
5419
5420	/*
5421	* DCP_CUR_INV_TRANS_CLAMP enum
5422	*/
5423
5424	typedef enum DCP_CUR_INV_TRANS_CLAMP {
5425	DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x00000000,
5426	DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x00000001,
5427	} DCP_CUR_INV_TRANS_CLAMP;
5428
5429	/*
5430	* DCP_CURSOR_MODE enum
5431	*/
5432
5433	typedef enum DCP_CURSOR_MODE {
5434	DCP_CURSOR_MODE_MONO_2BPP = 0x00000000,
5435	DCP_CURSOR_MODE_24BPP_1BIT = 0x00000001,
5436	DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x00000002,
5437	DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x00000003,
5438	} DCP_CURSOR_MODE;
5439
5440	/*
5441	* DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM enum
5442	*/
5443
5444	typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM {
5445	DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE = 0x00000000,
5446	DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO = 0x00000001,
5447	} DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM;
5448
5449	/*
5450	* DCP_CURSOR_2X_MAGNIFY enum
5451	*/
5452
5453	typedef enum DCP_CURSOR_2X_MAGNIFY {
5454	DCP_CURSOR_2X_MAGNIFY_FALSE = 0x00000000,
5455	DCP_CURSOR_2X_MAGNIFY_TRUE = 0x00000001,
5456	} DCP_CURSOR_2X_MAGNIFY;
5457
5458	/*
5459	* DCP_CURSOR_FORCE_MC_ON enum
5460	*/
5461
5462	typedef enum DCP_CURSOR_FORCE_MC_ON {
5463	DCP_CURSOR_FORCE_MC_ON_FALSE = 0x00000000,
5464	DCP_CURSOR_FORCE_MC_ON_TRUE = 0x00000001,
5465	} DCP_CURSOR_FORCE_MC_ON;
5466
5467	/*
5468	* DCP_CURSOR_URGENT_CONTROL enum
5469	*/
5470
5471	typedef enum DCP_CURSOR_URGENT_CONTROL {
5472	DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x00000000,
5473	DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x00000001,
5474	DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x00000002,
5475	DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x00000003,
5476	DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x00000004,
5477	} DCP_CURSOR_URGENT_CONTROL;
5478
5479	/*
5480	* DCP_CURSOR_UPDATE_PENDING enum
5481	*/
5482
5483	typedef enum DCP_CURSOR_UPDATE_PENDING {
5484	DCP_CURSOR_UPDATE_PENDING_FALSE = 0x00000000,
5485	DCP_CURSOR_UPDATE_PENDING_TRUE = 0x00000001,
5486	} DCP_CURSOR_UPDATE_PENDING;
5487
5488	/*
5489	* DCP_CURSOR_UPDATE_TAKEN enum
5490	*/
5491
5492	typedef enum DCP_CURSOR_UPDATE_TAKEN {
5493	DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x00000000,
5494	DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x00000001,
5495	} DCP_CURSOR_UPDATE_TAKEN;
5496
5497	/*
5498	* DCP_CURSOR_UPDATE_LOCK enum
5499	*/
5500
5501	typedef enum DCP_CURSOR_UPDATE_LOCK {
5502	DCP_CURSOR_UPDATE_LOCK_FALSE = 0x00000000,
5503	DCP_CURSOR_UPDATE_LOCK_TRUE = 0x00000001,
5504	} DCP_CURSOR_UPDATE_LOCK;
5505
5506	/*
5507	* DCP_CURSOR_DISABLE_MULTIPLE_UPDATE enum
5508	*/
5509
5510	typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
5511	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
5512	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
5513	} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
5514
5515	/*
5516	* DCP_CURSOR_UPDATE_STEREO_MODE enum
5517	*/
5518
5519	typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
5520	DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x00000000,
5521	DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x00000001,
5522	DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x00000002,
5523	DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x00000003,
5524	} DCP_CURSOR_UPDATE_STEREO_MODE;
5525
5526	/*
5527	* DCP_CUR2_INV_TRANS_CLAMP enum
5528	*/
5529
5530	typedef enum DCP_CUR2_INV_TRANS_CLAMP {
5531	DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x00000000,
5532	DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x00000001,
5533	} DCP_CUR2_INV_TRANS_CLAMP;
5534
5535	/*
5536	* DCP_CUR_REQUEST_FILTER_DIS enum
5537	*/
5538
5539	typedef enum DCP_CUR_REQUEST_FILTER_DIS {
5540	DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x00000000,
5541	DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x00000001,
5542	} DCP_CUR_REQUEST_FILTER_DIS;
5543
5544	/*
5545	* DCP_CURSOR_STEREO_EN enum
5546	*/
5547
5548	typedef enum DCP_CURSOR_STEREO_EN {
5549	DCP_CURSOR_STEREO_EN_FALSE = 0x00000000,
5550	DCP_CURSOR_STEREO_EN_TRUE = 0x00000001,
5551	} DCP_CURSOR_STEREO_EN;
5552
5553	/*
5554	* DCP_CURSOR_STEREO_OFFSET_YNX enum
5555	*/
5556
5557	typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
5558	DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x00000000,
5559	DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x00000001,
5560	} DCP_CURSOR_STEREO_OFFSET_YNX;
5561
5562	/*
5563	* DCP_DC_LUT_RW_MODE enum
5564	*/
5565
5566	typedef enum DCP_DC_LUT_RW_MODE {
5567	DCP_DC_LUT_RW_MODE_256_ENTRY = 0x00000000,
5568	DCP_DC_LUT_RW_MODE_PWL = 0x00000001,
5569	} DCP_DC_LUT_RW_MODE;
5570
5571	/*
5572	* DCP_DC_LUT_VGA_ACCESS_ENABLE enum
5573	*/
5574
5575	typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
5576	DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x00000000,
5577	DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x00000001,
5578	} DCP_DC_LUT_VGA_ACCESS_ENABLE;
5579
5580	/*
5581	* DCP_DC_LUT_AUTOFILL enum
5582	*/
5583
5584	typedef enum DCP_DC_LUT_AUTOFILL {
5585	DCP_DC_LUT_AUTOFILL_FALSE = 0x00000000,
5586	DCP_DC_LUT_AUTOFILL_TRUE = 0x00000001,
5587	} DCP_DC_LUT_AUTOFILL;
5588
5589	/*
5590	* DCP_DC_LUT_AUTOFILL_DONE enum
5591	*/
5592
5593	typedef enum DCP_DC_LUT_AUTOFILL_DONE {
5594	DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x00000000,
5595	DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x00000001,
5596	} DCP_DC_LUT_AUTOFILL_DONE;
5597
5598	/*
5599	* DCP_DC_LUT_INC_B enum
5600	*/
5601
5602	typedef enum DCP_DC_LUT_INC_B {
5603	DCP_DC_LUT_INC_B_NA = 0x00000000,
5604	DCP_DC_LUT_INC_B_2 = 0x00000001,
5605	DCP_DC_LUT_INC_B_4 = 0x00000002,
5606	DCP_DC_LUT_INC_B_8 = 0x00000003,
5607	DCP_DC_LUT_INC_B_16 = 0x00000004,
5608	DCP_DC_LUT_INC_B_32 = 0x00000005,
5609	DCP_DC_LUT_INC_B_64 = 0x00000006,
5610	DCP_DC_LUT_INC_B_128 = 0x00000007,
5611	DCP_DC_LUT_INC_B_256 = 0x00000008,
5612	DCP_DC_LUT_INC_B_512 = 0x00000009,
5613	} DCP_DC_LUT_INC_B;
5614
5615	/*
5616	* DCP_DC_LUT_DATA_B_SIGNED_EN enum
5617	*/
5618
5619	typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
5620	DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x00000000,
5621	DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x00000001,
5622	} DCP_DC_LUT_DATA_B_SIGNED_EN;
5623
5624	/*
5625	* DCP_DC_LUT_DATA_B_FLOAT_POINT_EN enum
5626	*/
5627
5628	typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
5629	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x00000000,
5630	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x00000001,
5631	} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
5632
5633	/*
5634	* DCP_DC_LUT_DATA_B_FORMAT enum
5635	*/
5636
5637	typedef enum DCP_DC_LUT_DATA_B_FORMAT {
5638	DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x00000000,
5639	DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x00000001,
5640	DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x00000002,
5641	DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x00000003,
5642	} DCP_DC_LUT_DATA_B_FORMAT;
5643
5644	/*
5645	* DCP_DC_LUT_INC_G enum
5646	*/
5647
5648	typedef enum DCP_DC_LUT_INC_G {
5649	DCP_DC_LUT_INC_G_NA = 0x00000000,
5650	DCP_DC_LUT_INC_G_2 = 0x00000001,
5651	DCP_DC_LUT_INC_G_4 = 0x00000002,
5652	DCP_DC_LUT_INC_G_8 = 0x00000003,
5653	DCP_DC_LUT_INC_G_16 = 0x00000004,
5654	DCP_DC_LUT_INC_G_32 = 0x00000005,
5655	DCP_DC_LUT_INC_G_64 = 0x00000006,
5656	DCP_DC_LUT_INC_G_128 = 0x00000007,
5657	DCP_DC_LUT_INC_G_256 = 0x00000008,
5658	DCP_DC_LUT_INC_G_512 = 0x00000009,
5659	} DCP_DC_LUT_INC_G;
5660
5661	/*
5662	* DCP_DC_LUT_DATA_G_SIGNED_EN enum
5663	*/
5664
5665	typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
5666	DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x00000000,
5667	DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x00000001,
5668	} DCP_DC_LUT_DATA_G_SIGNED_EN;
5669
5670	/*
5671	* DCP_DC_LUT_DATA_G_FLOAT_POINT_EN enum
5672	*/
5673
5674	typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
5675	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x00000000,
5676	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x00000001,
5677	} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
5678
5679	/*
5680	* DCP_DC_LUT_DATA_G_FORMAT enum
5681	*/
5682
5683	typedef enum DCP_DC_LUT_DATA_G_FORMAT {
5684	DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x00000000,
5685	DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x00000001,
5686	DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x00000002,
5687	DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x00000003,
5688	} DCP_DC_LUT_DATA_G_FORMAT;
5689
5690	/*
5691	* DCP_DC_LUT_INC_R enum
5692	*/
5693
5694	typedef enum DCP_DC_LUT_INC_R {
5695	DCP_DC_LUT_INC_R_NA = 0x00000000,
5696	DCP_DC_LUT_INC_R_2 = 0x00000001,
5697	DCP_DC_LUT_INC_R_4 = 0x00000002,
5698	DCP_DC_LUT_INC_R_8 = 0x00000003,
5699	DCP_DC_LUT_INC_R_16 = 0x00000004,
5700	DCP_DC_LUT_INC_R_32 = 0x00000005,
5701	DCP_DC_LUT_INC_R_64 = 0x00000006,
5702	DCP_DC_LUT_INC_R_128 = 0x00000007,
5703	DCP_DC_LUT_INC_R_256 = 0x00000008,
5704	DCP_DC_LUT_INC_R_512 = 0x00000009,
5705	} DCP_DC_LUT_INC_R;
5706
5707	/*
5708	* DCP_DC_LUT_DATA_R_SIGNED_EN enum
5709	*/
5710
5711	typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
5712	DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x00000000,
5713	DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x00000001,
5714	} DCP_DC_LUT_DATA_R_SIGNED_EN;
5715
5716	/*
5717	* DCP_DC_LUT_DATA_R_FLOAT_POINT_EN enum
5718	*/
5719
5720	typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
5721	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x00000000,
5722	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x00000001,
5723	} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
5724
5725	/*
5726	* DCP_DC_LUT_DATA_R_FORMAT enum
5727	*/
5728
5729	typedef enum DCP_DC_LUT_DATA_R_FORMAT {
5730	DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x00000000,
5731	DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x00000001,
5732	DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x00000002,
5733	DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x00000003,
5734	} DCP_DC_LUT_DATA_R_FORMAT;
5735
5736	/*
5737	* DCP_CRC_ENABLE enum
5738	*/
5739
5740	typedef enum DCP_CRC_ENABLE {
5741	DCP_CRC_ENABLE_FALSE = 0x00000000,
5742	DCP_CRC_ENABLE_TRUE = 0x00000001,
5743	} DCP_CRC_ENABLE;
5744
5745	/*
5746	* DCP_CRC_SOURCE_SEL enum
5747	*/
5748
5749	typedef enum DCP_CRC_SOURCE_SEL {
5750	DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x00000000,
5751	DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x00000001,
5752	DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x00000002,
5753	DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x00000004,
5754	} DCP_CRC_SOURCE_SEL;
5755
5756	/*
5757	* DCP_CRC_LINE_SEL enum
5758	*/
5759
5760	typedef enum DCP_CRC_LINE_SEL {
5761	DCP_CRC_LINE_SEL_RESERVED = 0x00000000,
5762	DCP_CRC_LINE_SEL_EVEN = 0x00000001,
5763	DCP_CRC_LINE_SEL_ODD = 0x00000002,
5764	DCP_CRC_LINE_SEL_BOTH = 0x00000003,
5765	} DCP_CRC_LINE_SEL;
5766
5767	/*
5768	* DCP_GRPH_FLIP_RATE enum
5769	*/
5770
5771	typedef enum DCP_GRPH_FLIP_RATE {
5772	DCP_GRPH_FLIP_RATE_1FRAME = 0x00000000,
5773	DCP_GRPH_FLIP_RATE_2FRAME = 0x00000001,
5774	DCP_GRPH_FLIP_RATE_3FRAME = 0x00000002,
5775	DCP_GRPH_FLIP_RATE_4FRAME = 0x00000003,
5776	DCP_GRPH_FLIP_RATE_5FRAME = 0x00000004,
5777	DCP_GRPH_FLIP_RATE_6FRAME = 0x00000005,
5778	DCP_GRPH_FLIP_RATE_7FRAME = 0x00000006,
5779	DCP_GRPH_FLIP_RATE_8FRAME = 0x00000007,
5780	} DCP_GRPH_FLIP_RATE;
5781
5782	/*
5783	* DCP_GRPH_FLIP_RATE_ENABLE enum
5784	*/
5785
5786	typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
5787	DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x00000000,
5788	DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x00000001,
5789	} DCP_GRPH_FLIP_RATE_ENABLE;
5790
5791	/*
5792	* DCP_GSL0_EN enum
5793	*/
5794
5795	typedef enum DCP_GSL0_EN {
5796	DCP_GSL0_EN_FALSE = 0x00000000,
5797	DCP_GSL0_EN_TRUE = 0x00000001,
5798	} DCP_GSL0_EN;
5799
5800	/*
5801	* DCP_GSL1_EN enum
5802	*/
5803
5804	typedef enum DCP_GSL1_EN {
5805	DCP_GSL1_EN_FALSE = 0x00000000,
5806	DCP_GSL1_EN_TRUE = 0x00000001,
5807	} DCP_GSL1_EN;
5808
5809	/*
5810	* DCP_GSL2_EN enum
5811	*/
5812
5813	typedef enum DCP_GSL2_EN {
5814	DCP_GSL2_EN_FALSE = 0x00000000,
5815	DCP_GSL2_EN_TRUE = 0x00000001,
5816	} DCP_GSL2_EN;
5817
5818	/*
5819	* DCP_GSL_MASTER_EN enum
5820	*/
5821
5822	typedef enum DCP_GSL_MASTER_EN {
5823	DCP_GSL_MASTER_EN_FALSE = 0x00000000,
5824	DCP_GSL_MASTER_EN_TRUE = 0x00000001,
5825	} DCP_GSL_MASTER_EN;
5826
5827	/*
5828	* DCP_GSL_XDMA_GROUP enum
5829	*/
5830
5831	typedef enum DCP_GSL_XDMA_GROUP {
5832	DCP_GSL_XDMA_GROUP_VSYNC = 0x00000000,
5833	DCP_GSL_XDMA_GROUP_HSYNC0 = 0x00000001,
5834	DCP_GSL_XDMA_GROUP_HSYNC1 = 0x00000002,
5835	DCP_GSL_XDMA_GROUP_HSYNC2 = 0x00000003,
5836	} DCP_GSL_XDMA_GROUP;
5837
5838	/*
5839	* DCP_GSL_XDMA_GROUP_UNDERFLOW_EN enum
5840	*/
5841
5842	typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
5843	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x00000000,
5844	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x00000001,
5845	} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
5846
5847	/*
5848	* DCP_GSL_SYNC_SOURCE enum
5849	*/
5850
5851	typedef enum DCP_GSL_SYNC_SOURCE {
5852	DCP_GSL_SYNC_SOURCE_FLIP = 0x00000000,
5853	DCP_GSL_SYNC_SOURCE_PHASE0 = 0x00000001,
5854	DCP_GSL_SYNC_SOURCE_RESET = 0x00000002,
5855	DCP_GSL_SYNC_SOURCE_PHASE1 = 0x00000003,
5856	} DCP_GSL_SYNC_SOURCE;
5857
5858	/*
5859	* DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC enum
5860	*/
5861
5862	typedef enum DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC {
5863	DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS = 0x00000000,
5864	DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN = 0x00000001,
5865	} DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC;
5866
5867	/*
5868	* DCP_GSL_DELAY_SURFACE_UPDATE_PENDING enum
5869	*/
5870
5871	typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
5872	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x00000000,
5873	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x00000001,
5874	} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
5875
5876	/*
5877	* DCP_TEST_DEBUG_WRITE_EN enum
5878	*/
5879
5880	typedef enum DCP_TEST_DEBUG_WRITE_EN {
5881	DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
5882	DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
5883	} DCP_TEST_DEBUG_WRITE_EN;
5884
5885	/*
5886	* DCP_GRPH_STEREOSYNC_FLIP_EN enum
5887	*/
5888
5889	typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
5890	DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x00000000,
5891	DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x00000001,
5892	} DCP_GRPH_STEREOSYNC_FLIP_EN;
5893
5894	/*
5895	* DCP_GRPH_STEREOSYNC_FLIP_MODE enum
5896	*/
5897
5898	typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
5899	DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x00000000,
5900	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x00000001,
5901	DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x00000002,
5902	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x00000003,
5903	} DCP_GRPH_STEREOSYNC_FLIP_MODE;
5904
5905	/*
5906	* DCP_GRPH_STEREOSYNC_SELECT_DISABLE enum
5907	*/
5908
5909	typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
5910	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x00000000,
5911	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x00000001,
5912	} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
5913
5914	/*
5915	* DCP_GRPH_ROTATION_ANGLE enum
5916	*/
5917
5918	typedef enum DCP_GRPH_ROTATION_ANGLE {
5919	DCP_GRPH_ROTATION_ANGLE_0 = 0x00000000,
5920	DCP_GRPH_ROTATION_ANGLE_90 = 0x00000001,
5921	DCP_GRPH_ROTATION_ANGLE_180 = 0x00000002,
5922	DCP_GRPH_ROTATION_ANGLE_270 = 0x00000003,
5923	} DCP_GRPH_ROTATION_ANGLE;
5924
5925	/*
5926	* DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN enum
5927	*/
5928
5929	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
5930	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x00000000,
5931	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x00000001,
5932	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
5933
5934	/*
5935	* DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE enum
5936	*/
5937
5938	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
5939	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x00000000,
5940	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE = 0x00000001,
5941	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
5942
5943	/*
5944	* DCP_GRPH_REGAMMA_MODE enum
5945	*/
5946
5947	typedef enum DCP_GRPH_REGAMMA_MODE {
5948	DCP_GRPH_REGAMMA_MODE_BYPASS = 0x00000000,
5949	DCP_GRPH_REGAMMA_MODE_SRGB = 0x00000001,
5950	DCP_GRPH_REGAMMA_MODE_XVYCC = 0x00000002,
5951	DCP_GRPH_REGAMMA_MODE_PROGA = 0x00000003,
5952	DCP_GRPH_REGAMMA_MODE_PROGB = 0x00000004,
5953	} DCP_GRPH_REGAMMA_MODE;
5954
5955	/*
5956	* DCP_ALPHA_ROUND_TRUNC_MODE enum
5957	*/
5958
5959	typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
5960	DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x00000000,
5961	DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x00000001,
5962	} DCP_ALPHA_ROUND_TRUNC_MODE;
5963
5964	/*
5965	* DCP_CURSOR_ALPHA_BLND_ENA enum
5966	*/
5967
5968	typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
5969	DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x00000000,
5970	DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x00000001,
5971	} DCP_CURSOR_ALPHA_BLND_ENA;
5972
5973	/*
5974	* DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK enum
5975	*/
5976
5977	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
5978	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x00000000,
5979	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x00000001,
5980	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
5981
5982	/*
5983	* DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK enum
5984	*/
5985
5986	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
5987	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x00000000,
5988	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x00000001,
5989	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
5990
5991	/*
5992	* DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK enum
5993	*/
5994
5995	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
5996	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
5997	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
5998	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
5999
6000	/*
6001	* DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK enum
6002	*/
6003
6004	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
6005	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
6006	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
6007	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
6008
6009	/*
6010	* DCP_GRPH_SURFACE_COUNTER_EN enum
6011	*/
6012
6013	typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
6014	DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x00000000,
6015	DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x00000001,
6016	} DCP_GRPH_SURFACE_COUNTER_EN;
6017
6018	/*
6019	* DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT enum
6020	*/
6021
6022	typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
6023	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x00000000,
6024	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x00000001,
6025	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x00000002,
6026	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x00000003,
6027	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x00000004,
6028	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x00000005,
6029	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x00000006,
6030	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x00000007,
6031	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x00000008,
6032	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x00000009,
6033	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0x0000000a,
6034	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0x0000000b,
6035	} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
6036
6037	/*
6038	* DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED enum
6039	*/
6040
6041	typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
6042	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x00000000,
6043	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x00000001,
6044	} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
6045
6046	/*
6047	* DCP_GRPH_XDMA_FLIP_TYPE_CLEAR enum
6048	*/
6049
6050	typedef enum DCP_GRPH_XDMA_FLIP_TYPE_CLEAR {
6051	DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE = 0x00000000,
6052	DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE = 0x00000001,
6053	} DCP_GRPH_XDMA_FLIP_TYPE_CLEAR;
6054
6055	/*
6056	* DCP_GRPH_XDMA_DRR_MODE_ENABLE enum
6057	*/
6058
6059	typedef enum DCP_GRPH_XDMA_DRR_MODE_ENABLE {
6060	DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE = 0x00000000,
6061	DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE = 0x00000001,
6062	} DCP_GRPH_XDMA_DRR_MODE_ENABLE;
6063
6064	/*
6065	* DCP_GRPH_XDMA_MULTIFLIP_ENABLE enum
6066	*/
6067
6068	typedef enum DCP_GRPH_XDMA_MULTIFLIP_ENABLE {
6069	DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE = 0x00000000,
6070	DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE = 0x00000001,
6071	} DCP_GRPH_XDMA_MULTIFLIP_ENABLE;
6072
6073	/*
6074	* DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK enum
6075	*/
6076
6077	typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK {
6078	DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE = 0x00000000,
6079	DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE = 0x00000001,
6080	} DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK;
6081
6082	/*
6083	* DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK enum
6084	*/
6085
6086	typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK {
6087	DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE = 0x00000000,
6088	DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE = 0x00000001,
6089	} DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK;
6090
6091	/*******************************************************
6092	* DC_PERFMON Enums
6093	*******************************************************/
6094
6095	/*
6096	* PERFCOUNTER_CVALUE_SEL enum
6097	*/
6098
6099	typedef enum PERFCOUNTER_CVALUE_SEL {
6100	PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000,
6101	PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001,
6102	PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002,
6103	PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003,
6104	PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004,
6105	PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005,
6106	PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006,
6107	PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007,
6108	} PERFCOUNTER_CVALUE_SEL;
6109
6110	/*
6111	* PERFCOUNTER_INC_MODE enum
6112	*/
6113
6114	typedef enum PERFCOUNTER_INC_MODE {
6115	PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000,
6116	PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001,
6117	PERFCOUNTER_INC_MODE_LSB = 0x00000002,
6118	PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003,
6119	PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004,
6120	} PERFCOUNTER_INC_MODE;
6121
6122	/*
6123	* PERFCOUNTER_HW_CNTL_SEL enum
6124	*/
6125
6126	typedef enum PERFCOUNTER_HW_CNTL_SEL {
6127	PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000,
6128	PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001,
6129	} PERFCOUNTER_HW_CNTL_SEL;
6130
6131	/*
6132	* PERFCOUNTER_RUNEN_MODE enum
6133	*/
6134
6135	typedef enum PERFCOUNTER_RUNEN_MODE {
6136	PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000,
6137	PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001,
6138	} PERFCOUNTER_RUNEN_MODE;
6139
6140	/*
6141	* PERFCOUNTER_CNTOFF_START_DIS enum
6142	*/
6143
6144	typedef enum PERFCOUNTER_CNTOFF_START_DIS {
6145	PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000,
6146	PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001,
6147	} PERFCOUNTER_CNTOFF_START_DIS;
6148
6149	/*
6150	* PERFCOUNTER_RESTART_EN enum
6151	*/
6152
6153	typedef enum PERFCOUNTER_RESTART_EN {
6154	PERFCOUNTER_RESTART_DISABLE = 0x00000000,
6155	PERFCOUNTER_RESTART_ENABLE = 0x00000001,
6156	} PERFCOUNTER_RESTART_EN;
6157
6158	/*
6159	* PERFCOUNTER_INT_EN enum
6160	*/
6161
6162	typedef enum PERFCOUNTER_INT_EN {
6163	PERFCOUNTER_INT_DISABLE = 0x00000000,
6164	PERFCOUNTER_INT_ENABLE = 0x00000001,
6165	} PERFCOUNTER_INT_EN;
6166
6167	/*
6168	* PERFCOUNTER_OFF_MASK enum
6169	*/
6170
6171	typedef enum PERFCOUNTER_OFF_MASK {
6172	PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000,
6173	PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001,
6174	} PERFCOUNTER_OFF_MASK;
6175
6176	/*
6177	* PERFCOUNTER_ACTIVE enum
6178	*/
6179
6180	typedef enum PERFCOUNTER_ACTIVE {
6181	PERFCOUNTER_IS_IDLE = 0x00000000,
6182	PERFCOUNTER_IS_ACTIVE = 0x00000001,
6183	} PERFCOUNTER_ACTIVE;
6184
6185	/*
6186	* PERFCOUNTER_INT_TYPE enum
6187	*/
6188
6189	typedef enum PERFCOUNTER_INT_TYPE {
6190	PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000,
6191	PERFCOUNTER_INT_TYPE_PULSE = 0x00000001,
6192	} PERFCOUNTER_INT_TYPE;
6193
6194	/*
6195	* PERFCOUNTER_COUNTED_VALUE_TYPE enum
6196	*/
6197
6198	typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
6199	PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000,
6200	PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001,
6201	PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002,
6202	} PERFCOUNTER_COUNTED_VALUE_TYPE;
6203
6204	/*
6205	* PERFCOUNTER_CNTL_SEL enum
6206	*/
6207
6208	typedef enum PERFCOUNTER_CNTL_SEL {
6209	PERFCOUNTER_CNTL_SEL_0 = 0x00000000,
6210	PERFCOUNTER_CNTL_SEL_1 = 0x00000001,
6211	PERFCOUNTER_CNTL_SEL_2 = 0x00000002,
6212	PERFCOUNTER_CNTL_SEL_3 = 0x00000003,
6213	PERFCOUNTER_CNTL_SEL_4 = 0x00000004,
6214	PERFCOUNTER_CNTL_SEL_5 = 0x00000005,
6215	PERFCOUNTER_CNTL_SEL_6 = 0x00000006,
6216	PERFCOUNTER_CNTL_SEL_7 = 0x00000007,
6217	} PERFCOUNTER_CNTL_SEL;
6218
6219	/*
6220	* PERFCOUNTER_CNT0_STATE enum
6221	*/
6222
6223	typedef enum PERFCOUNTER_CNT0_STATE {
6224	PERFCOUNTER_CNT0_STATE_RESET = 0x00000000,
6225	PERFCOUNTER_CNT0_STATE_START = 0x00000001,
6226	PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002,
6227	PERFCOUNTER_CNT0_STATE_HW = 0x00000003,
6228	} PERFCOUNTER_CNT0_STATE;
6229
6230	/*
6231	* PERFCOUNTER_STATE_SEL0 enum
6232	*/
6233
6234	typedef enum PERFCOUNTER_STATE_SEL0 {
6235	PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000,
6236	PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001,
6237	} PERFCOUNTER_STATE_SEL0;
6238
6239	/*
6240	* PERFCOUNTER_CNT1_STATE enum
6241	*/
6242
6243	typedef enum PERFCOUNTER_CNT1_STATE {
6244	PERFCOUNTER_CNT1_STATE_RESET = 0x00000000,
6245	PERFCOUNTER_CNT1_STATE_START = 0x00000001,
6246	PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002,
6247	PERFCOUNTER_CNT1_STATE_HW = 0x00000003,
6248	} PERFCOUNTER_CNT1_STATE;
6249
6250	/*
6251	* PERFCOUNTER_STATE_SEL1 enum
6252	*/
6253
6254	typedef enum PERFCOUNTER_STATE_SEL1 {
6255	PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000,
6256	PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001,
6257	} PERFCOUNTER_STATE_SEL1;
6258
6259	/*
6260	* PERFCOUNTER_CNT2_STATE enum
6261	*/
6262
6263	typedef enum PERFCOUNTER_CNT2_STATE {
6264	PERFCOUNTER_CNT2_STATE_RESET = 0x00000000,
6265	PERFCOUNTER_CNT2_STATE_START = 0x00000001,
6266	PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002,
6267	PERFCOUNTER_CNT2_STATE_HW = 0x00000003,
6268	} PERFCOUNTER_CNT2_STATE;
6269
6270	/*
6271	* PERFCOUNTER_STATE_SEL2 enum
6272	*/
6273
6274	typedef enum PERFCOUNTER_STATE_SEL2 {
6275	PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000,
6276	PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001,
6277	} PERFCOUNTER_STATE_SEL2;
6278
6279	/*
6280	* PERFCOUNTER_CNT3_STATE enum
6281	*/
6282
6283	typedef enum PERFCOUNTER_CNT3_STATE {
6284	PERFCOUNTER_CNT3_STATE_RESET = 0x00000000,
6285	PERFCOUNTER_CNT3_STATE_START = 0x00000001,
6286	PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002,
6287	PERFCOUNTER_CNT3_STATE_HW = 0x00000003,
6288	} PERFCOUNTER_CNT3_STATE;
6289
6290	/*
6291	* PERFCOUNTER_STATE_SEL3 enum
6292	*/
6293
6294	typedef enum PERFCOUNTER_STATE_SEL3 {
6295	PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000,
6296	PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001,
6297	} PERFCOUNTER_STATE_SEL3;
6298
6299	/*
6300	* PERFCOUNTER_CNT4_STATE enum
6301	*/
6302
6303	typedef enum PERFCOUNTER_CNT4_STATE {
6304	PERFCOUNTER_CNT4_STATE_RESET = 0x00000000,
6305	PERFCOUNTER_CNT4_STATE_START = 0x00000001,
6306	PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002,
6307	PERFCOUNTER_CNT4_STATE_HW = 0x00000003,
6308	} PERFCOUNTER_CNT4_STATE;
6309
6310	/*
6311	* PERFCOUNTER_STATE_SEL4 enum
6312	*/
6313
6314	typedef enum PERFCOUNTER_STATE_SEL4 {
6315	PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000,
6316	PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001,
6317	} PERFCOUNTER_STATE_SEL4;
6318
6319	/*
6320	* PERFCOUNTER_CNT5_STATE enum
6321	*/
6322
6323	typedef enum PERFCOUNTER_CNT5_STATE {
6324	PERFCOUNTER_CNT5_STATE_RESET = 0x00000000,
6325	PERFCOUNTER_CNT5_STATE_START = 0x00000001,
6326	PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002,
6327	PERFCOUNTER_CNT5_STATE_HW = 0x00000003,
6328	} PERFCOUNTER_CNT5_STATE;
6329
6330	/*
6331	* PERFCOUNTER_STATE_SEL5 enum
6332	*/
6333
6334	typedef enum PERFCOUNTER_STATE_SEL5 {
6335	PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000,
6336	PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001,
6337	} PERFCOUNTER_STATE_SEL5;
6338
6339	/*
6340	* PERFCOUNTER_CNT6_STATE enum
6341	*/
6342
6343	typedef enum PERFCOUNTER_CNT6_STATE {
6344	PERFCOUNTER_CNT6_STATE_RESET = 0x00000000,
6345	PERFCOUNTER_CNT6_STATE_START = 0x00000001,
6346	PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002,
6347	PERFCOUNTER_CNT6_STATE_HW = 0x00000003,
6348	} PERFCOUNTER_CNT6_STATE;
6349
6350	/*
6351	* PERFCOUNTER_STATE_SEL6 enum
6352	*/
6353
6354	typedef enum PERFCOUNTER_STATE_SEL6 {
6355	PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000,
6356	PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001,
6357	} PERFCOUNTER_STATE_SEL6;
6358
6359	/*
6360	* PERFCOUNTER_CNT7_STATE enum
6361	*/
6362
6363	typedef enum PERFCOUNTER_CNT7_STATE {
6364	PERFCOUNTER_CNT7_STATE_RESET = 0x00000000,
6365	PERFCOUNTER_CNT7_STATE_START = 0x00000001,
6366	PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002,
6367	PERFCOUNTER_CNT7_STATE_HW = 0x00000003,
6368	} PERFCOUNTER_CNT7_STATE;
6369
6370	/*
6371	* PERFCOUNTER_STATE_SEL7 enum
6372	*/
6373
6374	typedef enum PERFCOUNTER_STATE_SEL7 {
6375	PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000,
6376	PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001,
6377	} PERFCOUNTER_STATE_SEL7;
6378
6379	/*
6380	* PERFMON_STATE enum
6381	*/
6382
6383	typedef enum PERFMON_STATE {
6384	PERFMON_STATE_RESET = 0x00000000,
6385	PERFMON_STATE_START = 0x00000001,
6386	PERFMON_STATE_FREEZE = 0x00000002,
6387	PERFMON_STATE_HW = 0x00000003,
6388	} PERFMON_STATE;
6389
6390	/*
6391	* PERFMON_CNTOFF_AND_OR enum
6392	*/
6393
6394	typedef enum PERFMON_CNTOFF_AND_OR {
6395	PERFMON_CNTOFF_OR = 0x00000000,
6396	PERFMON_CNTOFF_AND = 0x00000001,
6397	} PERFMON_CNTOFF_AND_OR;
6398
6399	/*
6400	* PERFMON_CNTOFF_INT_EN enum
6401	*/
6402
6403	typedef enum PERFMON_CNTOFF_INT_EN {
6404	PERFMON_CNTOFF_INT_DISABLE = 0x00000000,
6405	PERFMON_CNTOFF_INT_ENABLE = 0x00000001,
6406	} PERFMON_CNTOFF_INT_EN;
6407
6408	/*
6409	* PERFMON_CNTOFF_INT_TYPE enum
6410	*/
6411
6412	typedef enum PERFMON_CNTOFF_INT_TYPE {
6413	PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000,
6414	PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001,
6415	} PERFMON_CNTOFF_INT_TYPE;
6416
6417	/*******************************************************
6418	* SCL Enums
6419	*******************************************************/
6420
6421	/*
6422	* SCL_C_RAM_TAP_PAIR_IDX enum
6423	*/
6424
6425	typedef enum SCL_C_RAM_TAP_PAIR_IDX {
6426	SCL_C_RAM_TAP_PAIR_ID0 = 0x00000000,
6427	SCL_C_RAM_TAP_PAIR_ID1 = 0x00000001,
6428	SCL_C_RAM_TAP_PAIR_ID2 = 0x00000002,
6429	SCL_C_RAM_TAP_PAIR_ID3 = 0x00000003,
6430	SCL_C_RAM_TAP_PAIR_ID4 = 0x00000004,
6431	} SCL_C_RAM_TAP_PAIR_IDX;
6432
6433	/*
6434	* SCL_C_RAM_PHASE enum
6435	*/
6436
6437	typedef enum SCL_C_RAM_PHASE {
6438	SCL_C_RAM_PHASE_0 = 0x00000000,
6439	SCL_C_RAM_PHASE_1 = 0x00000001,
6440	SCL_C_RAM_PHASE_2 = 0x00000002,
6441	SCL_C_RAM_PHASE_3 = 0x00000003,
6442	SCL_C_RAM_PHASE_4 = 0x00000004,
6443	SCL_C_RAM_PHASE_5 = 0x00000005,
6444	SCL_C_RAM_PHASE_6 = 0x00000006,
6445	SCL_C_RAM_PHASE_7 = 0x00000007,
6446	SCL_C_RAM_PHASE_8 = 0x00000008,
6447	} SCL_C_RAM_PHASE;
6448
6449	/*
6450	* SCL_C_RAM_FILTER_TYPE enum
6451	*/
6452
6453	typedef enum SCL_C_RAM_FILTER_TYPE {
6454	SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x00000000,
6455	SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x00000001,
6456	SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x00000002,
6457	SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x00000003,
6458	} SCL_C_RAM_FILTER_TYPE;
6459
6460	/*
6461	* SCL_MODE_SEL enum
6462	*/
6463
6464	typedef enum SCL_MODE_SEL {
6465	SCL_MODE_RGB_BYPASS = 0x00000000,
6466	SCL_MODE_RGB_SCALING = 0x00000001,
6467	SCL_MODE_YCBCR_SCALING = 0x00000002,
6468	SCL_MODE_YCBCR_BYPASS = 0x00000003,
6469	} SCL_MODE_SEL;
6470
6471	/*
6472	* SCL_PSCL_EN enum
6473	*/
6474
6475	typedef enum SCL_PSCL_EN {
6476	SCL_PSCL_DISABLE = 0x00000000,
6477	SCL_PSCL_ENANBLE = 0x00000001,
6478	} SCL_PSCL_EN;
6479
6480	/*
6481	* SCL_V_NUM_OF_TAPS enum
6482	*/
6483
6484	typedef enum SCL_V_NUM_OF_TAPS {
6485	SCL_V_NUM_OF_TAPS_1 = 0x00000000,
6486	SCL_V_NUM_OF_TAPS_2 = 0x00000001,
6487	SCL_V_NUM_OF_TAPS_3 = 0x00000002,
6488	SCL_V_NUM_OF_TAPS_4 = 0x00000003,
6489	SCL_V_NUM_OF_TAPS_5 = 0x00000004,
6490	SCL_V_NUM_OF_TAPS_6 = 0x00000005,
6491	} SCL_V_NUM_OF_TAPS;
6492
6493	/*
6494	* SCL_H_NUM_OF_TAPS enum
6495	*/
6496
6497	typedef enum SCL_H_NUM_OF_TAPS {
6498	SCL_H_NUM_OF_TAPS_1 = 0x00000000,
6499	SCL_H_NUM_OF_TAPS_2 = 0x00000001,
6500	SCL_H_NUM_OF_TAPS_4 = 0x00000003,
6501	SCL_H_NUM_OF_TAPS_6 = 0x00000005,
6502	SCL_H_NUM_OF_TAPS_8 = 0x00000007,
6503	SCL_H_NUM_OF_TAPS_10 = 0x00000009,
6504	} SCL_H_NUM_OF_TAPS;
6505
6506	/*
6507	* SCL_BOUNDARY_MODE enum
6508	*/
6509
6510	typedef enum SCL_BOUNDARY_MODE {
6511	SCL_BOUNDARY_MODE_BLACK = 0x00000000,
6512	SCL_BOUNDARY_MODE_EDGE = 0x00000001,
6513	} SCL_BOUNDARY_MODE;
6514
6515	/*
6516	* SCL_EARLY_EOL_MOD enum
6517	*/
6518
6519	typedef enum SCL_EARLY_EOL_MOD {
6520	SCL_EARLY_EOL_MODE_CRTC = 0x00000000,
6521	SCL_EARLY_EOL_MODE_INTERNAL = 0x00000001,
6522	} SCL_EARLY_EOL_MOD;
6523
6524	/*
6525	* SCL_BYPASS_MODE enum
6526	*/
6527
6528	typedef enum SCL_BYPASS_MODE {
6529	SCL_BYPASS_MODE_MC_MR = 0x00000000,
6530	SCL_BYPASS_MODE_AC_NR = 0x00000001,
6531	SCL_BYPASS_MODE_AC_AR = 0x00000002,
6532	SCL_BYPASS_MODE_RESERVED = 0x00000003,
6533	} SCL_BYPASS_MODE;
6534
6535	/*
6536	* SCL_V_MANUAL_REPLICATE_FACTOR enum
6537	*/
6538
6539	typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
6540	SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x00000000,
6541	SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x00000001,
6542	SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x00000002,
6543	SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x00000003,
6544	SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x00000004,
6545	SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x00000005,
6546	SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x00000006,
6547	SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x00000007,
6548	SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x00000008,
6549	SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x00000009,
6550	SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0x0000000a,
6551	SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0x0000000b,
6552	SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0x0000000c,
6553	SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0x0000000d,
6554	SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0x0000000e,
6555	SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0x0000000f,
6556	} SCL_V_MANUAL_REPLICATE_FACTOR;
6557
6558	/*
6559	* SCL_H_MANUAL_REPLICATE_FACTOR enum
6560	*/
6561
6562	typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
6563	SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x00000000,
6564	SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x00000001,
6565	SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x00000002,
6566	SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x00000003,
6567	SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x00000004,
6568	SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x00000005,
6569	SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x00000006,
6570	SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x00000007,
6571	SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x00000008,
6572	SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x00000009,
6573	SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0x0000000a,
6574	SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0x0000000b,
6575	SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0x0000000c,
6576	SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0x0000000d,
6577	SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0x0000000e,
6578	SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0x0000000f,
6579	} SCL_H_MANUAL_REPLICATE_FACTOR;
6580
6581	/*
6582	* SCL_V_CALC_AUTO_RATIO_EN enum
6583	*/
6584
6585	typedef enum SCL_V_CALC_AUTO_RATIO_EN {
6586	SCL_V_CALC_AUTO_RATIO_DISABLE = 0x00000000,
6587	SCL_V_CALC_AUTO_RATIO_ENABLE = 0x00000001,
6588	} SCL_V_CALC_AUTO_RATIO_EN;
6589
6590	/*
6591	* SCL_H_CALC_AUTO_RATIO_EN enum
6592	*/
6593
6594	typedef enum SCL_H_CALC_AUTO_RATIO_EN {
6595	SCL_H_CALC_AUTO_RATIO_DISABLE = 0x00000000,
6596	SCL_H_CALC_AUTO_RATIO_ENABLE = 0x00000001,
6597	} SCL_H_CALC_AUTO_RATIO_EN;
6598
6599	/*
6600	* SCL_H_FILTER_PICK_NEAREST enum
6601	*/
6602
6603	typedef enum SCL_H_FILTER_PICK_NEAREST {
6604	SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x00000000,
6605	SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x00000001,
6606	} SCL_H_FILTER_PICK_NEAREST;
6607
6608	/*
6609	* SCL_H_2TAP_HARDCODE_COEF_EN enum
6610	*/
6611
6612	typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
6613	SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x00000000,
6614	SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x00000001,
6615	} SCL_H_2TAP_HARDCODE_COEF_EN;
6616
6617	/*
6618	* SCL_V_FILTER_PICK_NEAREST enum
6619	*/
6620
6621	typedef enum SCL_V_FILTER_PICK_NEAREST {
6622	SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x00000000,
6623	SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x00000001,
6624	} SCL_V_FILTER_PICK_NEAREST;
6625
6626	/*
6627	* SCL_V_2TAP_HARDCODE_COEF_EN enum
6628	*/
6629
6630	typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
6631	SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x00000000,
6632	SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x00000001,
6633	} SCL_V_2TAP_HARDCODE_COEF_EN;
6634
6635	/*
6636	* SCL_UPDATE_TAKEN enum
6637	*/
6638
6639	typedef enum SCL_UPDATE_TAKEN {
6640	SCL_UPDATE_TAKEN_NO = 0x00000000,
6641	SCL_UPDATE_TAKEN_YES = 0x00000001,
6642	} SCL_UPDATE_TAKEN;
6643
6644	/*
6645	* SCL_UPDATE_LOCK enum
6646	*/
6647
6648	typedef enum SCL_UPDATE_LOCK {
6649	SCL_UPDATE_UNLOCKED = 0x00000000,
6650	SCL_UPDATE_LOCKED = 0x00000001,
6651	} SCL_UPDATE_LOCK;
6652
6653	/*
6654	* SCL_COEF_UPDATE_COMPLETE enum
6655	*/
6656
6657	typedef enum SCL_COEF_UPDATE_COMPLETE {
6658	SCL_COEF_UPDATE_NOT_COMPLETED = 0x00000000,
6659	SCL_COEF_UPDATE_COMPLETED = 0x00000001,
6660	} SCL_COEF_UPDATE_COMPLETE;
6661
6662	/*
6663	* SCL_HF_SHARP_SCALE_FACTOR enum
6664	*/
6665
6666	typedef enum SCL_HF_SHARP_SCALE_FACTOR {
6667	SCL_HF_SHARP_SCALE_FACTOR_0 = 0x00000000,
6668	SCL_HF_SHARP_SCALE_FACTOR_1 = 0x00000001,
6669	SCL_HF_SHARP_SCALE_FACTOR_2 = 0x00000002,
6670	SCL_HF_SHARP_SCALE_FACTOR_3 = 0x00000003,
6671	SCL_HF_SHARP_SCALE_FACTOR_4 = 0x00000004,
6672	SCL_HF_SHARP_SCALE_FACTOR_5 = 0x00000005,
6673	SCL_HF_SHARP_SCALE_FACTOR_6 = 0x00000006,
6674	SCL_HF_SHARP_SCALE_FACTOR_7 = 0x00000007,
6675	} SCL_HF_SHARP_SCALE_FACTOR;
6676
6677	/*
6678	* SCL_HF_SHARP_EN enum
6679	*/
6680
6681	typedef enum SCL_HF_SHARP_EN {
6682	SCL_HF_SHARP_DISABLE = 0x00000000,
6683	SCL_HF_SHARP_ENABLE = 0x00000001,
6684	} SCL_HF_SHARP_EN;
6685
6686	/*
6687	* SCL_VF_SHARP_SCALE_FACTOR enum
6688	*/
6689
6690	typedef enum SCL_VF_SHARP_SCALE_FACTOR {
6691	SCL_VF_SHARP_SCALE_FACTOR_0 = 0x00000000,
6692	SCL_VF_SHARP_SCALE_FACTOR_1 = 0x00000001,
6693	SCL_VF_SHARP_SCALE_FACTOR_2 = 0x00000002,
6694	SCL_VF_SHARP_SCALE_FACTOR_3 = 0x00000003,
6695	SCL_VF_SHARP_SCALE_FACTOR_4 = 0x00000004,
6696	SCL_VF_SHARP_SCALE_FACTOR_5 = 0x00000005,
6697	SCL_VF_SHARP_SCALE_FACTOR_6 = 0x00000006,
6698	SCL_VF_SHARP_SCALE_FACTOR_7 = 0x00000007,
6699	} SCL_VF_SHARP_SCALE_FACTOR;
6700
6701	/*
6702	* SCL_VF_SHARP_EN enum
6703	*/
6704
6705	typedef enum SCL_VF_SHARP_EN {
6706	SCL_VF_SHARP_DISABLE = 0x00000000,
6707	SCL_VF_SHARP_ENABLE = 0x00000001,
6708	} SCL_VF_SHARP_EN;
6709
6710	/*
6711	* SCL_ALU_DISABLE enum
6712	*/
6713
6714	typedef enum SCL_ALU_DISABLE {
6715	SCL_ALU_ENABLED = 0x00000000,
6716	SCL_ALU_DISABLED = 0x00000001,
6717	} SCL_ALU_DISABLE;
6718
6719	/*
6720	* SCL_HOST_CONFLICT_MASK enum
6721	*/
6722
6723	typedef enum SCL_HOST_CONFLICT_MASK {
6724	SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x00000000,
6725	SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x00000001,
6726	} SCL_HOST_CONFLICT_MASK;
6727
6728	/*
6729	* SCL_SCL_MODE_CHANGE_MASK enum
6730	*/
6731
6732	typedef enum SCL_SCL_MODE_CHANGE_MASK {
6733	SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x00000000,
6734	SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x00000001,
6735	} SCL_SCL_MODE_CHANGE_MASK;
6736
6737	/*******************************************************
6738	* SCLV Enums
6739	*******************************************************/
6740
6741	/*
6742	* SCLV_MODE_SEL enum
6743	*/
6744
6745	typedef enum SCLV_MODE_SEL {
6746	SCLV_MODE_RGB_BYPASS = 0x00000000,
6747	SCLV_MODE_RGB_SCALING = 0x00000001,
6748	SCLV_MODE_YCBCR_SCALING = 0x00000002,
6749	SCLV_MODE_YCBCR_BYPASS = 0x00000003,
6750	} SCLV_MODE_SEL;
6751
6752	/*
6753	* SCLV_INTERLACE_SOURCE enum
6754	*/
6755
6756	typedef enum SCLV_INTERLACE_SOURCE {
6757	INTERLACE_SOURCE_PROGRESSIVE = 0x00000000,
6758	INTERLACE_SOURCE_INTERLEAVE = 0x00000001,
6759	INTERLACE_SOURCE_STACK = 0x00000002,
6760	} SCLV_INTERLACE_SOURCE;
6761
6762	/*
6763	* SCLV_UPDATE_LOCK enum
6764	*/
6765
6766	typedef enum SCLV_UPDATE_LOCK {
6767	UPDATE_UNLOCKED = 0x00000000,
6768	UPDATE_LOCKED = 0x00000001,
6769	} SCLV_UPDATE_LOCK;
6770
6771	/*
6772	* SCLV_COEF_UPDATE_COMPLETE enum
6773	*/
6774
6775	typedef enum SCLV_COEF_UPDATE_COMPLETE {
6776	COEF_UPDATE_NOT_COMPLETE = 0x00000000,
6777	COEF_UPDATE_COMPLETE = 0x00000001,
6778	} SCLV_COEF_UPDATE_COMPLETE;
6779
6780	/*******************************************************
6781	* DPRX_SD Enums
6782	*******************************************************/
6783
6784	/*
6785	* DPRX_SD_PIXEL_ENCODING enum
6786	*/
6787
6788	typedef enum DPRX_SD_PIXEL_ENCODING {
6789	PIXEL_FORMAT_RGB_444 = 0x00000000,
6790	PIXEL_FORMAT_YCBCR_444 = 0x00000001,
6791	PIXEL_FORMAT_YCBCR_422 = 0x00000002,
6792	PIXEL_FORMAT_Y_ONLY = 0x00000003,
6793	} DPRX_SD_PIXEL_ENCODING;
6794
6795	/*
6796	* DPRX_SD_COMPONENT_DEPTH enum
6797	*/
6798
6799	typedef enum DPRX_SD_COMPONENT_DEPTH {
6800	COMPONENT_DEPTH_6BPC = 0x00000000,
6801	COMPONENT_DEPTH_8BPC = 0x00000001,
6802	COMPONENT_DEPTH_10BPC = 0x00000002,
6803	COMPONENT_DEPTH_12BPC = 0x00000003,
6804	COMPONENT_DEPTH_16BPC = 0x00000004,
6805	} DPRX_SD_COMPONENT_DEPTH;
6806
6807	/*******************************************************
6808	* AZF0STREAM Enums
6809	*******************************************************/
6810
6811	/*
6812	* AZ_LATENCY_COUNTER_CONTROL enum
6813	*/
6814
6815	typedef enum AZ_LATENCY_COUNTER_CONTROL {
6816	AZ_LATENCY_COUNTER_NO_RESET = 0x00000000,
6817	AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001,
6818	} AZ_LATENCY_COUNTER_CONTROL;
6819
6820	/*******************************************************
6821	* BLND Enums
6822	*******************************************************/
6823
6824	/*
6825	* BLND_CONTROL_BLND_MODE enum
6826	*/
6827
6828	typedef enum BLND_CONTROL_BLND_MODE {
6829	BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
6830	BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001,
6831	BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
6832	BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
6833	} BLND_CONTROL_BLND_MODE;
6834
6835	/*
6836	* BLND_CONTROL_BLND_STEREO_TYPE enum
6837	*/
6838
6839	typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
6840	BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
6841	BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
6842	BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
6843	BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003,
6844	} BLND_CONTROL_BLND_STEREO_TYPE;
6845
6846	/*
6847	* BLND_CONTROL_BLND_STEREO_POLARITY enum
6848	*/
6849
6850	typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
6851	BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000,
6852	BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001,
6853	} BLND_CONTROL_BLND_STEREO_POLARITY;
6854
6855	/*
6856	* BLND_CONTROL_BLND_FEEDTHROUGH_EN enum
6857	*/
6858
6859	typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
6860	BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000,
6861	BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001,
6862	} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
6863
6864	/*
6865	* BLND_CONTROL_BLND_ALPHA_MODE enum
6866	*/
6867
6868	typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
6869	BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
6870	BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
6871	BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
6872	BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003,
6873	} BLND_CONTROL_BLND_ALPHA_MODE;
6874
6875	/*
6876	* BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
6877	*/
6878
6879	typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
6880	BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0x00000000,
6881	BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 0x00000001,
6882	} BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
6883
6884	/*
6885	* BLND_CONTROL_BLND_MULTIPLIED_MODE enum
6886	*/
6887
6888	typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
6889	BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
6890	BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001,
6891	} BLND_CONTROL_BLND_MULTIPLIED_MODE;
6892
6893	/*
6894	* BLND_SM_CONTROL2_SM_MODE enum
6895	*/
6896
6897	typedef enum BLND_SM_CONTROL2_SM_MODE {
6898	BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000,
6899	BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
6900	BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
6901	BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
6902	} BLND_SM_CONTROL2_SM_MODE;
6903
6904	/*
6905	* BLND_SM_CONTROL2_SM_FRAME_ALTERNATE enum
6906	*/
6907
6908	typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
6909	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
6910	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
6911	} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
6912
6913	/*
6914	* BLND_SM_CONTROL2_SM_FIELD_ALTERNATE enum
6915	*/
6916
6917	typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
6918	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
6919	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
6920	} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
6921
6922	/*
6923	* BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
6924	*/
6925
6926	typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
6927	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
6928	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
6929	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
6930	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
6931	} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
6932
6933	/*
6934	* BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
6935	*/
6936
6937	typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
6938	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
6939	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
6940	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
6941	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
6942	} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
6943
6944	/*
6945	* BLND_CONTROL2_PTI_ENABLE enum
6946	*/
6947
6948	typedef enum BLND_CONTROL2_PTI_ENABLE {
6949	BLND_CONTROL2_PTI_ENABLE_FALSE = 0x00000000,
6950	BLND_CONTROL2_PTI_ENABLE_TRUE = 0x00000001,
6951	} BLND_CONTROL2_PTI_ENABLE;
6952
6953	/*
6954	* BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
6955	*/
6956
6957	typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
6958	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
6959	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
6960	} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
6961
6962	/*
6963	* BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
6964	*/
6965
6966	typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
6967	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
6968	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
6969	} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
6970
6971	/*
6972	* BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
6973	*/
6974
6975	typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
6976	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
6977	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
6978	} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
6979
6980	/*
6981	* BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
6982	*/
6983
6984	typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
6985	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
6986	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
6987	} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
6988
6989	/*
6990	* BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
6991	*/
6992
6993	typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
6994	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
6995	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
6996	} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
6997
6998	/*
6999	* BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
7000	*/
7001
7002	typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
7003	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
7004	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
7005	} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
7006
7007	/*
7008	* BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
7009	*/
7010
7011	typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
7012	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
7013	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
7014	} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
7015
7016	/*
7017	* BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
7018	*/
7019
7020	typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
7021	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
7022	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
7023	} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
7024
7025	/*
7026	* BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
7027	*/
7028
7029	typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
7030	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
7031	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
7032	} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
7033
7034	/*
7035	* BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
7036	*/
7037
7038	typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
7039	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
7040	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
7041	} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
7042
7043	/*
7044	* BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
7045	*/
7046
7047	typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
7048	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
7049	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
7050	} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
7051
7052	/*
7053	* BLND_DEBUG_BLND_CNV_MUX_SELECT enum
7054	*/
7055
7056	typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
7057	BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000,
7058	BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001,
7059	} BLND_DEBUG_BLND_CNV_MUX_SELECT;
7060
7061	/*
7062	* BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
7063	*/
7064
7065	typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
7066	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
7067	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
7068	} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
7069
7070	/*******************************************************
7071	* AZF0ENDPOINT Enums
7072	*******************************************************/
7073
7074	/*
7075	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7076	*/
7077
7078	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7079	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
7080	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
7081	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
7082	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
7083	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
7084	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
7085	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
7086	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
7087	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
7088	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
7089	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7090
7091	/*
7092	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7093	*/
7094
7095	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7096	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
7097	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
7098	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7099
7100	/*
7101	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7102	*/
7103
7104	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7105	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
7106	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
7107	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7108
7109	/*
7110	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7111	*/
7112
7113	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7114	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
7115	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
7116	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7117
7118	/*
7119	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7120	*/
7121
7122	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7123	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
7124	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
7125	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7126
7127	/*
7128	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7129	*/
7130
7131	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7132	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
7133	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
7134	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7135
7136	/*
7137	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7138	*/
7139
7140	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7141	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
7142	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
7143	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7144
7145	/*
7146	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7147	*/
7148
7149	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7150	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
7151	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
7152	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7153
7154	/*
7155	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7156	*/
7157
7158	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7159	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
7160	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001,
7161	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
7162
7163	/*
7164	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7165	*/
7166
7167	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7168	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
7169	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
7170	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7171
7172	/*
7173	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7174	*/
7175
7176	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7177	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
7178	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
7179	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7180
7181	/*
7182	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7183	*/
7184
7185	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7186	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
7187	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
7188	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7189
7190	/*
7191	* AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7192	*/
7193
7194	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
7195	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
7196	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
7197	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
7198
7199	/*
7200	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7201	*/
7202
7203	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7204	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
7205	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
7206	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
7207	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
7208	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
7209	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
7210	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
7211	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
7212	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
7213	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
7214	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7215
7216	/*
7217	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7218	*/
7219
7220	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7221	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
7222	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
7223	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7224
7225	/*
7226	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7227	*/
7228
7229	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7230	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
7231	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
7232	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7233
7234	/*
7235	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7236	*/
7237
7238	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7239	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
7240	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
7241	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7242
7243	/*
7244	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7245	*/
7246
7247	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7248	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
7249	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
7250	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7251
7252	/*
7253	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7254	*/
7255
7256	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7257	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
7258	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
7259	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7260
7261	/*
7262	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7263	*/
7264
7265	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7266	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
7267	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
7268	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7269
7270	/*
7271	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7272	*/
7273
7274	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7275	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
7276	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
7277	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7278
7279	/*
7280	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7281	*/
7282
7283	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7284	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
7285	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
7286	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7287
7288	/*
7289	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7290	*/
7291
7292	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7293	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
7294	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
7295	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7296
7297	/*
7298	* AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7299	*/
7300
7301	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7302	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000,
7303	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
7304	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7305
7306	/*
7307	* AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7308	*/
7309
7310	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7311	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000,
7312	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001,
7313	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
7314
7315	/*
7316	* AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7317	*/
7318
7319	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7320	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000,
7321	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
7322	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
7323
7324	/*
7325	* AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7326	*/
7327
7328	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7329	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
7330	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
7331	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
7332
7333	/*
7334	* AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7335	*/
7336
7337	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7338	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
7339	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
7340	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
7341
7342	/*
7343	* AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7344	*/
7345
7346	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7347	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
7348	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
7349	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
7350
7351	/*
7352	* AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7353	*/
7354
7355	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7356	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000,
7357	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001,
7358	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
7359
7360	/*
7361	* AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7362	*/
7363
7364	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7365	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
7366	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
7367	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
7368
7369	/*
7370	* AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7371	*/
7372
7373	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7374	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
7375	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
7376	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
7377
7378	/*
7379	* AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
7380	*/
7381
7382	typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
7383	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
7384	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
7385	} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
7386
7387	/*
7388	* AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7389	*/
7390
7391	typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7392	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000,
7393	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001,
7394	} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
7395
7396	/*******************************************************
7397	* AZF0INPUTENDPOINT Enums
7398	*******************************************************/
7399
7400	/*
7401	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7402	*/
7403
7404	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7405	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
7406	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
7407	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
7408	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
7409	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
7410	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
7411	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
7412	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
7413	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
7414	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
7415	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7416
7417	/*
7418	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7419	*/
7420
7421	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7422	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
7423	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
7424	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7425
7426	/*
7427	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7428	*/
7429
7430	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7431	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
7432	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
7433	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7434
7435	/*
7436	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7437	*/
7438
7439	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7440	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000,
7441	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001,
7442	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7443
7444	/*
7445	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7446	*/
7447
7448	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7449	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
7450	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
7451	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7452
7453	/*
7454	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7455	*/
7456
7457	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7458	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
7459	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
7460	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7461
7462	/*
7463	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7464	*/
7465
7466	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7467	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000,
7468	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
7469	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7470
7471	/*
7472	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7473	*/
7474
7475	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7476	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000,
7477	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
7478	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7479
7480	/*
7481	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7482	*/
7483
7484	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7485	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
7486	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001,
7487	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
7488
7489	/*
7490	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7491	*/
7492
7493	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7494	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
7495	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001,
7496	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7497
7498	/*
7499	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7500	*/
7501
7502	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7503	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
7504	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
7505	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7506
7507	/*
7508	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7509	*/
7510
7511	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7512	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
7513	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
7514	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7515
7516	/*
7517	* AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7518	*/
7519
7520	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
7521	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
7522	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
7523	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
7524
7525	/*
7526	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7527	*/
7528
7529	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7530	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
7531	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
7532	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
7533	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
7534	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
7535	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
7536	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
7537	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
7538	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
7539	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
7540	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7541
7542	/*
7543	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7544	*/
7545
7546	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7547	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000,
7548	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001,
7549	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7550
7551	/*
7552	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7553	*/
7554
7555	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7556	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
7557	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
7558	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7559
7560	/*
7561	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7562	*/
7563
7564	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7565	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
7566	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
7567	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7568
7569	/*
7570	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7571	*/
7572
7573	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7574	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
7575	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
7576	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7577
7578	/*
7579	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7580	*/
7581
7582	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7583	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
7584	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
7585	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7586
7587	/*
7588	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7589	*/
7590
7591	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7592	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000,
7593	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001,
7594	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7595
7596	/*
7597	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7598	*/
7599
7600	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7601	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
7602	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
7603	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7604
7605	/*
7606	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7607	*/
7608
7609	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7610	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
7611	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
7612	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7613
7614	/*
7615	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7616	*/
7617
7618	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7619	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
7620	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
7621	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7622
7623	/*
7624	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7625	*/
7626
7627	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7628	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
7629	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
7630	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7631
7632	/*
7633	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
7634	*/
7635
7636	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
7637	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000,
7638	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001,
7639	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
7640
7641	/*
7642	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7643	*/
7644
7645	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7646	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000,
7647	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001,
7648	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
7649
7650	/*
7651	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
7652	*/
7653
7654	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
7655	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000,
7656	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001,
7657	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
7658
7659	/*
7660	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7661	*/
7662
7663	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7664	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000,
7665	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
7666	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
7667
7668	/*
7669	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7670	*/
7671
7672	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7673	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
7674	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
7675	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
7676
7677	/*
7678	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7679	*/
7680
7681	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7682	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
7683	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
7684	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
7685
7686	/*
7687	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7688	*/
7689
7690	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7691	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
7692	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
7693	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
7694
7695	/*
7696	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7697	*/
7698
7699	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7700	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000,
7701	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001,
7702	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
7703
7704	/*
7705	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7706	*/
7707
7708	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7709	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
7710	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
7711	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
7712
7713	/*
7714	* AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7715	*/
7716
7717	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7718	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
7719	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
7720	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
7721
7722	/*
7723	* AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7724	*/
7725
7726	typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7727	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000,
7728	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001,
7729	} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
7730
7731	/*******************************************************
7732	* UNP Enums
7733	*******************************************************/
7734
7735	/*
7736	* UNP_GRPH_EN enum
7737	*/
7738
7739	typedef enum UNP_GRPH_EN {
7740	UNP_GRPH_DISABLED = 0x00000000,
7741	UNP_GRPH_ENABLED = 0x00000001,
7742	} UNP_GRPH_EN;
7743
7744	/*
7745	* UNP_GRPH_DEPTH enum
7746	*/
7747
7748	typedef enum UNP_GRPH_DEPTH {
7749	UNP_GRPH_8BPP = 0x00000000,
7750	UNP_GRPH_16BPP = 0x00000001,
7751	UNP_GRPH_32BPP = 0x00000002,
7752	} UNP_GRPH_DEPTH;
7753
7754	/*
7755	* UNP_GRPH_NUM_BANKS enum
7756	*/
7757
7758	typedef enum UNP_GRPH_NUM_BANKS {
7759	UNP_GRPH_ADDR_SURF_2_BANK = 0x00000000,
7760	UNP_GRPH_ADDR_SURF_4_BANK = 0x00000001,
7761	UNP_GRPH_ADDR_SURF_8_BANK = 0x00000002,
7762	UNP_GRPH_ADDR_SURF_16_BANK = 0x00000003,
7763	} UNP_GRPH_NUM_BANKS;
7764
7765	/*
7766	* UNP_GRPH_BANK_WIDTH enum
7767	*/
7768
7769	typedef enum UNP_GRPH_BANK_WIDTH {
7770	UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
7771	UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x00000001,
7772	UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x00000002,
7773	UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x00000003,
7774	} UNP_GRPH_BANK_WIDTH;
7775
7776	/*
7777	* UNP_GRPH_BANK_HEIGHT enum
7778	*/
7779
7780	typedef enum UNP_GRPH_BANK_HEIGHT {
7781	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
7782	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x00000001,
7783	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x00000002,
7784	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x00000003,
7785	} UNP_GRPH_BANK_HEIGHT;
7786
7787	/*
7788	* UNP_GRPH_TILE_SPLIT enum
7789	*/
7790
7791	typedef enum UNP_GRPH_TILE_SPLIT {
7792	UNP_ADDR_SURF_TILE_SPLIT_64B = 0x00000000,
7793	UNP_ADDR_SURF_TILE_SPLIT_128B = 0x00000001,
7794	UNP_ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
7795	UNP_ADDR_SURF_TILE_SPLIT_512B = 0x00000003,
7796	UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x00000004,
7797	UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x00000005,
7798	UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x00000006,
7799	} UNP_GRPH_TILE_SPLIT;
7800
7801	/*
7802	* UNP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
7803	*/
7804
7805	typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
7806	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x00000000,
7807	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x00000001,
7808	} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
7809
7810	/*
7811	* UNP_GRPH_MACRO_TILE_ASPECT enum
7812	*/
7813
7814	typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
7815	UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x00000000,
7816	UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x00000001,
7817	UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x00000002,
7818	UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x00000003,
7819	} UNP_GRPH_MACRO_TILE_ASPECT;
7820
7821	/*
7822	* UNP_GRPH_COLOR_EXPANSION_MODE enum
7823	*/
7824
7825	typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
7826	UNP_GRPH_DYNAMIC_EXPANSION = 0x00000000,
7827	UNP_GRPH_ZERO_EXPANSION = 0x00000001,
7828	} UNP_GRPH_COLOR_EXPANSION_MODE;
7829
7830	/*
7831	* UNP_VIDEO_FORMAT enum
7832	*/
7833
7834	typedef enum UNP_VIDEO_FORMAT {
7835	UNP_VIDEO_FORMAT0 = 0x00000000,
7836	UNP_VIDEO_FORMAT1 = 0x00000001,
7837	UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x00000002,
7838	UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x00000003,
7839	UNP_VIDEO_FORMAT_YUV422_YCb = 0x00000004,
7840	UNP_VIDEO_FORMAT_YUV422_YCr = 0x00000005,
7841	UNP_VIDEO_FORMAT_YUV422_CbY = 0x00000006,
7842	UNP_VIDEO_FORMAT_YUV422_CrY = 0x00000007,
7843	} UNP_VIDEO_FORMAT;
7844
7845	/*
7846	* UNP_GRPH_ENDIAN_SWAP enum
7847	*/
7848
7849	typedef enum UNP_GRPH_ENDIAN_SWAP {
7850	UNP_GRPH_ENDIAN_SWAP_NONE = 0x00000000,
7851	UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x00000001,
7852	UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x00000002,
7853	UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x00000003,
7854	} UNP_GRPH_ENDIAN_SWAP;
7855
7856	/*
7857	* UNP_GRPH_RED_CROSSBAR enum
7858	*/
7859
7860	typedef enum UNP_GRPH_RED_CROSSBAR {
7861	UNP_GRPH_RED_CROSSBAR_R_Cr = 0x00000000,
7862	UNP_GRPH_RED_CROSSBAR_G_Y = 0x00000001,
7863	UNP_GRPH_RED_CROSSBAR_B_Cb = 0x00000002,
7864	UNP_GRPH_RED_CROSSBAR_A = 0x00000003,
7865	} UNP_GRPH_RED_CROSSBAR;
7866
7867	/*
7868	* UNP_GRPH_GREEN_CROSSBAR enum
7869	*/
7870
7871	typedef enum UNP_GRPH_GREEN_CROSSBAR {
7872	UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x00000000,
7873	UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x00000001,
7874	UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x00000002,
7875	UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x00000003,
7876	} UNP_GRPH_GREEN_CROSSBAR;
7877
7878	/*
7879	* UNP_GRPH_BLUE_CROSSBAR enum
7880	*/
7881
7882	typedef enum UNP_GRPH_BLUE_CROSSBAR {
7883	UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x00000000,
7884	UNP_GRPH_BLUE_CROSSBAR_A = 0x00000001,
7885	UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x00000002,
7886	UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x00000003,
7887	} UNP_GRPH_BLUE_CROSSBAR;
7888
7889	/*
7890	* UNP_GRPH_MODE_UPDATE_LOCKG enum
7891	*/
7892
7893	typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
7894	UNP_GRPH_UPDATE_LOCK_0 = 0x00000000,
7895	UNP_GRPH_UPDATE_LOCK_1 = 0x00000001,
7896	} UNP_GRPH_MODE_UPDATE_LOCKG;
7897
7898	/*
7899	* UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
7900	*/
7901
7902	typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
7903	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x00000000,
7904	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x00000001,
7905	} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
7906
7907	/*
7908	* UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
7909	*/
7910
7911	typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
7912	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x00000000,
7913	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x00000001,
7914	} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
7915
7916	/*
7917	* UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
7918	*/
7919
7920	typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
7921	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x00000000,
7922	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x00000001,
7923	} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
7924
7925	/*
7926	* UNP_GRPH_STEREOSYNC_FLIP_EN enum
7927	*/
7928
7929	typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
7930	UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x00000000,
7931	UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x00000001,
7932	} UNP_GRPH_STEREOSYNC_FLIP_EN;
7933
7934	/*
7935	* UNP_GRPH_STEREOSYNC_FLIP_MODE enum
7936	*/
7937
7938	typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
7939	UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x00000000,
7940	UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x00000001,
7941	UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x00000002,
7942	UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x00000003,
7943	} UNP_GRPH_STEREOSYNC_FLIP_MODE;
7944
7945	/*
7946	* UNP_GRPH_STACK_INTERLACE_FLIP_EN enum
7947	*/
7948
7949	typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
7950	UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x00000000,
7951	UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x00000001,
7952	} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
7953
7954	/*
7955	* UNP_GRPH_STACK_INTERLACE_FLIP_MODE enum
7956	*/
7957
7958	typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
7959	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x00000000,
7960	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x00000001,
7961	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x00000002,
7962	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x00000003,
7963	} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
7964
7965	/*
7966	* UNP_GRPH_STEREOSYNC_SELECT_DISABLE enum
7967	*/
7968
7969	typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
7970	UNP_GRPH_STEREOSYNC_SELECT_EN = 0x00000000,
7971	UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x00000001,
7972	} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
7973
7974	/*
7975	* UNP_CRC_SOURCE_SEL enum
7976	*/
7977
7978	typedef enum UNP_CRC_SOURCE_SEL {
7979	UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x00000000,
7980	UNP_CRC_SOURCE_SEL_LOWER32 = 0x00000001,
7981	UNP_CRC_SOURCE_SEL_RESERVED = 0x00000002,
7982	UNP_CRC_SOURCE_SEL_LOWER16 = 0x00000003,
7983	UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x00000004,
7984	} UNP_CRC_SOURCE_SEL;
7985
7986	/*
7987	* UNP_CRC_LINE_SEL enum
7988	*/
7989
7990	typedef enum UNP_CRC_LINE_SEL {
7991	UNP_CRC_LINE_SEL_RESERVED = 0x00000000,
7992	UNP_CRC_LINE_SEL_EVEN_ONLY = 0x00000001,
7993	UNP_CRC_LINE_SEL_ODD_ONLY = 0x00000002,
7994	UNP_CRC_LINE_SEL_ODD_EVEN = 0x00000003,
7995	} UNP_CRC_LINE_SEL;
7996
7997	/*
7998	* UNP_ROTATION_ANGLE enum
7999	*/
8000
8001	typedef enum UNP_ROTATION_ANGLE {
8002	UNP_ROTATION_ANGLE_0 = 0x00000000,
8003	UNP_ROTATION_ANGLE_90 = 0x00000001,
8004	UNP_ROTATION_ANGLE_180 = 0x00000002,
8005	UNP_ROTATION_ANGLE_270 = 0x00000003,
8006	UNP_ROTATION_ANGLE_0m = 0x00000004,
8007	UNP_ROTATION_ANGLE_90m = 0x00000005,
8008	UNP_ROTATION_ANGLE_180m = 0x00000006,
8009	UNP_ROTATION_ANGLE_270m = 0x00000007,
8010	} UNP_ROTATION_ANGLE;
8011
8012	/*
8013	* UNP_PIXEL_DROP enum
8014	*/
8015
8016	typedef enum UNP_PIXEL_DROP {
8017	UNP_PIXEL_NO_DROP = 0x00000000,
8018	UNP_PIXEL_DROPPING = 0x00000001,
8019	} UNP_PIXEL_DROP;
8020
8021	/*
8022	* UNP_BUFFER_MODE enum
8023	*/
8024
8025	typedef enum UNP_BUFFER_MODE {
8026	UNP_BUFFER_MODE_LUMA = 0x00000000,
8027	UNP_BUFFER_MODE_LUMA_CHROMA = 0x00000001,
8028	} UNP_BUFFER_MODE;
8029
8030	/*******************************************************
8031	* DP Enums
8032	*******************************************************/
8033
8034	/*
8035	* DP_LINK_TRAINING_COMPLETE enum
8036	*/
8037
8038	typedef enum DP_LINK_TRAINING_COMPLETE {
8039	DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000,
8040	DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001,
8041	} DP_LINK_TRAINING_COMPLETE;
8042
8043	/*
8044	* DP_EMBEDDED_PANEL_MODE enum
8045	*/
8046
8047	typedef enum DP_EMBEDDED_PANEL_MODE {
8048	DP_EXTERNAL_PANEL = 0x00000000,
8049	DP_EMBEDDED_PANEL = 0x00000001,
8050	} DP_EMBEDDED_PANEL_MODE;
8051
8052	/*
8053	* DP_PIXEL_ENCODING enum
8054	*/
8055
8056	typedef enum DP_PIXEL_ENCODING {
8057	DP_PIXEL_ENCODING_RGB444 = 0x00000000,
8058	DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
8059	DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
8060	DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
8061	DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
8062	DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
8063	DP_PIXEL_ENCODING_RESERVED = 0x00000006,
8064	} DP_PIXEL_ENCODING;
8065
8066	/*
8067	* DP_DYN_RANGE enum
8068	*/
8069
8070	typedef enum DP_DYN_RANGE {
8071	DP_DYN_VESA_RANGE = 0x00000000,
8072	DP_DYN_CEA_RANGE = 0x00000001,
8073	} DP_DYN_RANGE;
8074
8075	/*
8076	* DP_YCBCR_RANGE enum
8077	*/
8078
8079	typedef enum DP_YCBCR_RANGE {
8080	DP_YCBCR_RANGE_BT601_5 = 0x00000000,
8081	DP_YCBCR_RANGE_BT709_5 = 0x00000001,
8082	} DP_YCBCR_RANGE;
8083
8084	/*
8085	* DP_COMPONENT_DEPTH enum
8086	*/
8087
8088	typedef enum DP_COMPONENT_DEPTH {
8089	DP_COMPONENT_DEPTH_6BPC = 0x00000000,
8090	DP_COMPONENT_DEPTH_8BPC = 0x00000001,
8091	DP_COMPONENT_DEPTH_10BPC = 0x00000002,
8092	DP_COMPONENT_DEPTH_12BPC = 0x00000003,
8093	DP_COMPONENT_DEPTH_16BPC_RESERVED = 0x00000004,
8094	DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
8095	} DP_COMPONENT_DEPTH;
8096
8097	/*
8098	* DP_MSA_MISC0_OVERRIDE_ENABLE enum
8099	*/
8100
8101	typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
8102	MSA_MISC0_OVERRIDE_DISABLE = 0x00000000,
8103	MSA_MISC0_OVERRIDE_ENABLE = 0x00000001,
8104	} DP_MSA_MISC0_OVERRIDE_ENABLE;
8105
8106	/*
8107	* DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE enum
8108	*/
8109
8110	typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
8111	MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0x00000000,
8112	MSA_MISC1_BIT7_OVERRIDE_ENABLE = 0x00000001,
8113	} DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE;
8114
8115	/*
8116	* DP_UDI_LANES enum
8117	*/
8118
8119	typedef enum DP_UDI_LANES {
8120	DP_UDI_1_LANE = 0x00000000,
8121	DP_UDI_2_LANES = 0x00000001,
8122	DP_UDI_LANES_RESERVED = 0x00000002,
8123	DP_UDI_4_LANES = 0x00000003,
8124	} DP_UDI_LANES;
8125
8126	/*
8127	* DP_VID_STREAM_DIS_DEFER enum
8128	*/
8129
8130	typedef enum DP_VID_STREAM_DIS_DEFER {
8131	DP_VID_STREAM_DIS_NO_DEFER = 0x00000000,
8132	DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001,
8133	DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002,
8134	} DP_VID_STREAM_DIS_DEFER;
8135
8136	/*
8137	* DP_STEER_OVERFLOW_ACK enum
8138	*/
8139
8140	typedef enum DP_STEER_OVERFLOW_ACK {
8141	DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
8142	DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
8143	} DP_STEER_OVERFLOW_ACK;
8144
8145	/*
8146	* DP_STEER_OVERFLOW_MASK enum
8147	*/
8148
8149	typedef enum DP_STEER_OVERFLOW_MASK {
8150	DP_STEER_OVERFLOW_MASKED = 0x00000000,
8151	DP_STEER_OVERFLOW_UNMASK = 0x00000001,
8152	} DP_STEER_OVERFLOW_MASK;
8153
8154	/*
8155	* DP_TU_OVERFLOW_ACK enum
8156	*/
8157
8158	typedef enum DP_TU_OVERFLOW_ACK {
8159	DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
8160	DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
8161	} DP_TU_OVERFLOW_ACK;
8162
8163	/*
8164	* DPHY_ALT_SCRAMBLER_RESET_EN enum
8165	*/
8166
8167	typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
8168	DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0x00000000,
8169	DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 0x00000001,
8170	} DPHY_ALT_SCRAMBLER_RESET_EN;
8171
8172	/*
8173	* DPHY_ALT_SCRAMBLER_RESET_SEL enum
8174	*/
8175
8176	typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
8177	DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0x00000000,
8178	DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 0x00000001,
8179	} DPHY_ALT_SCRAMBLER_RESET_SEL;
8180
8181	/*
8182	* DP_VID_TIMING_MODE enum
8183	*/
8184
8185	typedef enum DP_VID_TIMING_MODE {
8186	DP_VID_TIMING_MODE_ASYNC = 0x00000000,
8187	DP_VID_TIMING_MODE_SYNC = 0x00000001,
8188	} DP_VID_TIMING_MODE;
8189
8190	/*
8191	* DP_VID_M_N_DOUBLE_BUFFER_MODE enum
8192	*/
8193
8194	typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
8195	DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000,
8196	DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001,
8197	} DP_VID_M_N_DOUBLE_BUFFER_MODE;
8198
8199	/*
8200	* DP_VID_M_N_GEN_EN enum
8201	*/
8202
8203	typedef enum DP_VID_M_N_GEN_EN {
8204	DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000,
8205	DP_VID_M_N_CALC_AUTO = 0x00000001,
8206	} DP_VID_M_N_GEN_EN;
8207
8208	/*
8209	* DP_VID_M_DOUBLE_VALUE_EN enum
8210	*/
8211
8212	typedef enum DP_VID_M_DOUBLE_VALUE_EN {
8213	DP_VID_M_INPUT_PIXEL_RATE = 0x00000000,
8214	DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 0x00000001,
8215	} DP_VID_M_DOUBLE_VALUE_EN;
8216
8217	/*
8218	* DP_VID_ENHANCED_FRAME_MODE enum
8219	*/
8220
8221	typedef enum DP_VID_ENHANCED_FRAME_MODE {
8222	VID_NORMAL_FRAME_MODE = 0x00000000,
8223	VID_ENHANCED_MODE = 0x00000001,
8224	} DP_VID_ENHANCED_FRAME_MODE;
8225
8226	/*
8227	* DP_VID_MSA_TOP_FIELD_MODE enum
8228	*/
8229
8230	typedef enum DP_VID_MSA_TOP_FIELD_MODE {
8231	DP_TOP_FIELD_ONLY = 0x00000000,
8232	DP_TOP_PLUS_BOTTOM_FIELD = 0x00000001,
8233	} DP_VID_MSA_TOP_FIELD_MODE;
8234
8235	/*
8236	* DP_VID_VBID_FIELD_POL enum
8237	*/
8238
8239	typedef enum DP_VID_VBID_FIELD_POL {
8240	DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000,
8241	DP_VID_VBID_FIELD_POL_INV = 0x00000001,
8242	} DP_VID_VBID_FIELD_POL;
8243
8244	/*
8245	* DP_VID_STREAM_DISABLE_ACK enum
8246	*/
8247
8248	typedef enum DP_VID_STREAM_DISABLE_ACK {
8249	ID_STREAM_DISABLE_NO_ACK = 0x00000000,
8250	ID_STREAM_DISABLE_ACKED = 0x00000001,
8251	} DP_VID_STREAM_DISABLE_ACK;
8252
8253	/*
8254	* DP_VID_STREAM_DISABLE_MASK enum
8255	*/
8256
8257	typedef enum DP_VID_STREAM_DISABLE_MASK {
8258	VID_STREAM_DISABLE_MASKED = 0x00000000,
8259	VID_STREAM_DISABLE_UNMASK = 0x00000001,
8260	} DP_VID_STREAM_DISABLE_MASK;
8261
8262	/*
8263	* DPHY_ATEST_SEL_LANE0 enum
8264	*/
8265
8266	typedef enum DPHY_ATEST_SEL_LANE0 {
8267	DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000,
8268	DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001,
8269	} DPHY_ATEST_SEL_LANE0;
8270
8271	/*
8272	* DPHY_ATEST_SEL_LANE1 enum
8273	*/
8274
8275	typedef enum DPHY_ATEST_SEL_LANE1 {
8276	DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000,
8277	DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001,
8278	} DPHY_ATEST_SEL_LANE1;
8279
8280	/*
8281	* DPHY_ATEST_SEL_LANE2 enum
8282	*/
8283
8284	typedef enum DPHY_ATEST_SEL_LANE2 {
8285	DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000,
8286	DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001,
8287	} DPHY_ATEST_SEL_LANE2;
8288
8289	/*
8290	* DPHY_ATEST_SEL_LANE3 enum
8291	*/
8292
8293	typedef enum DPHY_ATEST_SEL_LANE3 {
8294	DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000,
8295	DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001,
8296	} DPHY_ATEST_SEL_LANE3;
8297
8298	/*
8299	* DPHY_SCRAMBLER_SEL enum
8300	*/
8301
8302	typedef enum DPHY_SCRAMBLER_SEL {
8303	DPHY_SCRAMBLER_SEL_LANE_DATA = 0x00000000,
8304	DPHY_SCRAMBLER_SEL_DBG_DATA = 0x00000001,
8305	} DPHY_SCRAMBLER_SEL;
8306
8307	/*
8308	* DPHY_BYPASS enum
8309	*/
8310
8311	typedef enum DPHY_BYPASS {
8312	DPHY_8B10B_OUTPUT = 0x00000000,
8313	DPHY_DBG_OUTPUT = 0x00000001,
8314	} DPHY_BYPASS;
8315
8316	/*
8317	* DPHY_SKEW_BYPASS enum
8318	*/
8319
8320	typedef enum DPHY_SKEW_BYPASS {
8321	DPHY_WITH_SKEW = 0x00000000,
8322	DPHY_NO_SKEW = 0x00000001,
8323	} DPHY_SKEW_BYPASS;
8324
8325	/*
8326	* DPHY_TRAINING_PATTERN_SEL enum
8327	*/
8328
8329	typedef enum DPHY_TRAINING_PATTERN_SEL {
8330	DPHY_TRAINING_PATTERN_1 = 0x00000000,
8331	DPHY_TRAINING_PATTERN_2 = 0x00000001,
8332	DPHY_TRAINING_PATTERN_3 = 0x00000002,
8333	DPHY_TRAINING_PATTERN_4 = 0x00000003,
8334	} DPHY_TRAINING_PATTERN_SEL;
8335
8336	/*
8337	* DPHY_8B10B_RESET enum
8338	*/
8339
8340	typedef enum DPHY_8B10B_RESET {
8341	DPHY_8B10B_NOT_RESET = 0x00000000,
8342	DPHY_8B10B_RESETET = 0x00000001,
8343	} DPHY_8B10B_RESET;
8344
8345	/*
8346	* DP_DPHY_8B10B_EXT_DISP enum
8347	*/
8348
8349	typedef enum DP_DPHY_8B10B_EXT_DISP {
8350	DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000,
8351	DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001,
8352	} DP_DPHY_8B10B_EXT_DISP;
8353
8354	/*
8355	* DPHY_8B10B_CUR_DISP enum
8356	*/
8357
8358	typedef enum DPHY_8B10B_CUR_DISP {
8359	DPHY_8B10B_CUR_DISP_ZERO = 0x00000000,
8360	DPHY_8B10B_CUR_DISP_ONE = 0x00000001,
8361	} DPHY_8B10B_CUR_DISP;
8362
8363	/*
8364	* DPHY_PRBS_EN enum
8365	*/
8366
8367	typedef enum DPHY_PRBS_EN {
8368	DPHY_PRBS_DISABLE = 0x00000000,
8369	DPHY_PRBS_ENABLE = 0x00000001,
8370	} DPHY_PRBS_EN;
8371
8372	/*
8373	* DPHY_PRBS_SEL enum
8374	*/
8375
8376	typedef enum DPHY_PRBS_SEL {
8377	DPHY_PRBS7_SELECTED = 0x00000000,
8378	DPHY_PRBS23_SELECTED = 0x00000001,
8379	DPHY_PRBS11_SELECTED = 0x00000002,
8380	} DPHY_PRBS_SEL;
8381
8382	/*
8383	* DPHY_SCRAMBLER_DIS enum
8384	*/
8385
8386	typedef enum DPHY_SCRAMBLER_DIS {
8387	DPHY_SCR_ENABLED = 0x00000000,
8388	DPHY_SCR_DISABLED = 0x00000001,
8389	} DPHY_SCRAMBLER_DIS;
8390
8391	/*
8392	* DPHY_SCRAMBLER_ADVANCE enum
8393	*/
8394
8395	typedef enum DPHY_SCRAMBLER_ADVANCE {
8396	DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0x00000000,
8397	DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 0x00000001,
8398	} DPHY_SCRAMBLER_ADVANCE;
8399
8400	/*
8401	* DPHY_SCRAMBLER_KCODE enum
8402	*/
8403
8404	typedef enum DPHY_SCRAMBLER_KCODE {
8405	DPHY_SCRAMBLER_KCODE_DISABLED = 0x00000000,
8406	DPHY_SCRAMBLER_KCODE_ENABLED = 0x00000001,
8407	} DPHY_SCRAMBLER_KCODE;
8408
8409	/*
8410	* DPHY_LOAD_BS_COUNT_START enum
8411	*/
8412
8413	typedef enum DPHY_LOAD_BS_COUNT_START {
8414	DPHY_LOAD_BS_COUNT_STARTED = 0x00000000,
8415	DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001,
8416	} DPHY_LOAD_BS_COUNT_START;
8417
8418	/*
8419	* DPHY_CRC_EN enum
8420	*/
8421
8422	typedef enum DPHY_CRC_EN {
8423	DPHY_CRC_DISABLED = 0x00000000,
8424	DPHY_CRC_ENABLED = 0x00000001,
8425	} DPHY_CRC_EN;
8426
8427	/*
8428	* DPHY_CRC_CONT_EN enum
8429	*/
8430
8431	typedef enum DPHY_CRC_CONT_EN {
8432	DPHY_CRC_ONE_SHOT = 0x00000000,
8433	DPHY_CRC_CONTINUOUS = 0x00000001,
8434	} DPHY_CRC_CONT_EN;
8435
8436	/*
8437	* DPHY_CRC_FIELD enum
8438	*/
8439
8440	typedef enum DPHY_CRC_FIELD {
8441	DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000,
8442	DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001,
8443	} DPHY_CRC_FIELD;
8444
8445	/*
8446	* DPHY_CRC_SEL enum
8447	*/
8448
8449	typedef enum DPHY_CRC_SEL {
8450	DPHY_CRC_LANE0_SELECTED = 0x00000000,
8451	DPHY_CRC_LANE1_SELECTED = 0x00000001,
8452	DPHY_CRC_LANE2_SELECTED = 0x00000002,
8453	DPHY_CRC_LANE3_SELECTED = 0x00000003,
8454	} DPHY_CRC_SEL;
8455
8456	/*
8457	* DPHY_RX_FAST_TRAINING_CAPABLE enum
8458	*/
8459
8460	typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
8461	DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000,
8462	DPHY_FAST_TRAINING_CAPABLE = 0x00000001,
8463	} DPHY_RX_FAST_TRAINING_CAPABLE;
8464
8465	/*
8466	* DP_SEC_COLLISION_ACK enum
8467	*/
8468
8469	typedef enum DP_SEC_COLLISION_ACK {
8470	DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000,
8471	DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001,
8472	} DP_SEC_COLLISION_ACK;
8473
8474	/*
8475	* DP_SEC_AUDIO_MUTE enum
8476	*/
8477
8478	typedef enum DP_SEC_AUDIO_MUTE {
8479	DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000,
8480	DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001,
8481	} DP_SEC_AUDIO_MUTE;
8482
8483	/*
8484	* DP_SEC_TIMESTAMP_MODE enum
8485	*/
8486
8487	typedef enum DP_SEC_TIMESTAMP_MODE {
8488	DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000,
8489	DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001,
8490	} DP_SEC_TIMESTAMP_MODE;
8491
8492	/*
8493	* DP_SEC_ASP_PRIORITY enum
8494	*/
8495
8496	typedef enum DP_SEC_ASP_PRIORITY {
8497	DP_SEC_ASP_LOW_PRIORITY = 0x00000000,
8498	DP_SEC_ASP_HIGH_PRIORITY = 0x00000001,
8499	} DP_SEC_ASP_PRIORITY;
8500
8501	/*
8502	* DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
8503	*/
8504
8505	typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
8506	DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000,
8507	DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
8508	} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
8509
8510	/*
8511	* DP_MSE_SAT_UPDATE_ACT enum
8512	*/
8513
8514	typedef enum DP_MSE_SAT_UPDATE_ACT {
8515	DP_MSE_SAT_UPDATE_NO_ACTION = 0x00000000,
8516	DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x00000001,
8517	DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x00000002,
8518	} DP_MSE_SAT_UPDATE_ACT;
8519
8520	/*
8521	* DP_MSE_LINK_LINE enum
8522	*/
8523
8524	typedef enum DP_MSE_LINK_LINE {
8525	DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000,
8526	DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001,
8527	DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002,
8528	DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003,
8529	} DP_MSE_LINK_LINE;
8530
8531	/*
8532	* DP_MSE_BLANK_CODE enum
8533	*/
8534
8535	typedef enum DP_MSE_BLANK_CODE {
8536	DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000,
8537	DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001,
8538	} DP_MSE_BLANK_CODE;
8539
8540	/*
8541	* DP_MSE_TIMESTAMP_MODE enum
8542	*/
8543
8544	typedef enum DP_MSE_TIMESTAMP_MODE {
8545	DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000,
8546	DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001,
8547	} DP_MSE_TIMESTAMP_MODE;
8548
8549	/*
8550	* DP_MSE_ZERO_ENCODER enum
8551	*/
8552
8553	typedef enum DP_MSE_ZERO_ENCODER {
8554	DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000,
8555	DP_MSE_ZERO_FE_ENCODER = 0x00000001,
8556	} DP_MSE_ZERO_ENCODER;
8557
8558	/*
8559	* DP_MSE_OUTPUT_DPDBG_DATA enum
8560	*/
8561
8562	typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
8563	DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x00000000,
8564	DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x00000001,
8565	} DP_MSE_OUTPUT_DPDBG_DATA;
8566
8567	/*
8568	* DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
8569	*/
8570
8571	typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
8572	DP_DPHY_HBR2_PASS_THROUGH = 0x00000000,
8573	DP_DPHY_HBR2_PATTERN_1 = 0x00000001,
8574	DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002,
8575	DP_DPHY_HBR2_PATTERN_3 = 0x00000003,
8576	DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006,
8577	} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
8578
8579	/*
8580	* DPHY_CRC_MST_PHASE_ERROR_ACK enum
8581	*/
8582
8583	typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
8584	DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000,
8585	DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001,
8586	} DPHY_CRC_MST_PHASE_ERROR_ACK;
8587
8588	/*
8589	* DPHY_SW_FAST_TRAINING_START enum
8590	*/
8591
8592	typedef enum DPHY_SW_FAST_TRAINING_START {
8593	DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000,
8594	DPHY_SW_FAST_TRAINING_STARTED = 0x00000001,
8595	} DPHY_SW_FAST_TRAINING_START;
8596
8597	/*
8598	* DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
8599	*/
8600
8601	typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
8602	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000,
8603	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001,
8604	} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
8605
8606	/*
8607	* DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
8608	*/
8609
8610	typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
8611	DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000,
8612	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001,
8613	} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
8614
8615	/*
8616	* DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
8617	*/
8618
8619	typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
8620	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000,
8621	DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001,
8622	} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
8623
8624	/*
8625	* DP_MSA_V_TIMING_OVERRIDE_EN enum
8626	*/
8627
8628	typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
8629	MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000,
8630	MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001,
8631	} DP_MSA_V_TIMING_OVERRIDE_EN;
8632
8633	/*
8634	* DP_SEC_GSP0_PRIORITY enum
8635	*/
8636
8637	typedef enum DP_SEC_GSP0_PRIORITY {
8638	SEC_GSP0_PRIORITY_LOW = 0x00000000,
8639	SEC_GSP0_PRIORITY_HIGH = 0x00000001,
8640	} DP_SEC_GSP0_PRIORITY;
8641
8642	/*
8643	* DP_SEC_GSP0_SEND enum
8644	*/
8645
8646	typedef enum DP_SEC_GSP0_SEND {
8647	NOT_SENT = 0x00000000,
8648	FORCE_SENT = 0x00000001,
8649	} DP_SEC_GSP0_SEND;
8650
8651	/*******************************************************
8652	* COL_MAN Enums
8653	*******************************************************/
8654
8655	/*
8656	* COL_MAN_UPDATE_LOCK enum
8657	*/
8658
8659	typedef enum COL_MAN_UPDATE_LOCK {
8660	COL_MAN_UPDATE_UNLOCKED = 0x00000000,
8661	COL_MAN_UPDATE_LOCKED = 0x00000001,
8662	} COL_MAN_UPDATE_LOCK;
8663
8664	/*
8665	* COL_MAN_DISABLE_MULTIPLE_UPDATE enum
8666	*/
8667
8668	typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
8669	COL_MAN_MULTIPLE_UPDATE = 0x00000000,
8670	COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x00000001,
8671	} COL_MAN_DISABLE_MULTIPLE_UPDATE;
8672
8673	/*
8674	* COL_MAN_INPUTCSC_MODE enum
8675	*/
8676
8677	typedef enum COL_MAN_INPUTCSC_MODE {
8678	INPUTCSC_MODE_BYPASS = 0x00000000,
8679	INPUTCSC_MODE_A = 0x00000001,
8680	INPUTCSC_MODE_B = 0x00000002,
8681	INPUTCSC_MODE_UNITY = 0x00000003,
8682	} COL_MAN_INPUTCSC_MODE;
8683
8684	/*
8685	* COL_MAN_INPUTCSC_TYPE enum
8686	*/
8687
8688	typedef enum COL_MAN_INPUTCSC_TYPE {
8689	INPUTCSC_TYPE_12_0 = 0x00000000,
8690	INPUTCSC_TYPE_10_2 = 0x00000001,
8691	INPUTCSC_TYPE_8_4 = 0x00000002,
8692	} COL_MAN_INPUTCSC_TYPE;
8693
8694	/*
8695	* COL_MAN_INPUTCSC_CONVERT enum
8696	*/
8697
8698	typedef enum COL_MAN_INPUTCSC_CONVERT {
8699	INPUTCSC_ROUND = 0x00000000,
8700	INPUTCSC_TRUNCATE = 0x00000001,
8701	} COL_MAN_INPUTCSC_CONVERT;
8702
8703	/*
8704	* COL_MAN_PRESCALE_MODE enum
8705	*/
8706
8707	typedef enum COL_MAN_PRESCALE_MODE {
8708	PRESCALE_MODE_BYPASS = 0x00000000,
8709	PRESCALE_MODE_PROGRAM = 0x00000001,
8710	PRESCALE_MODE_UNITY = 0x00000002,
8711	} COL_MAN_PRESCALE_MODE;
8712
8713	/*
8714	* COL_MAN_INPUT_GAMMA_MODE enum
8715	*/
8716
8717	typedef enum COL_MAN_INPUT_GAMMA_MODE {
8718	INGAMMA_MODE_BYPASS = 0x00000000,
8719	INGAMMA_MODE_FIX = 0x00000001,
8720	INGAMMA_MODE_FLOAT = 0x00000002,
8721	} COL_MAN_INPUT_GAMMA_MODE;
8722
8723	/*
8724	* COL_MAN_OUTPUT_CSC_MODE enum
8725	*/
8726
8727	typedef enum COL_MAN_OUTPUT_CSC_MODE {
8728	COL_MAN_OUTPUT_CSC_BYPASS = 0x00000000,
8729	COL_MAN_OUTPUT_CSC_RGB = 0x00000001,
8730	COL_MAN_OUTPUT_CSC_YCrCb601 = 0x00000002,
8731	COL_MAN_OUTPUT_CSC_YCrCb709 = 0x00000003,
8732	COL_MAN_OUTPUT_CSC_A = 0x00000004,
8733	COL_MAN_OUTPUT_CSC_B = 0x00000005,
8734	COL_MAN_OUTPUT_CSC_UNITY = 0x00000006,
8735	} COL_MAN_OUTPUT_CSC_MODE;
8736
8737	/*
8738	* COL_MAN_DENORM_CLAMP_CONTROL enum
8739	*/
8740
8741	typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
8742	DENORM_CLAMP_MODE_UNITY = 0x00000000,
8743	DENORM_CLAMP_MODE_8 = 0x00000001,
8744	DENORM_CLAMP_MODE_10 = 0x00000002,
8745	DENORM_CLAMP_MODE_12 = 0x00000003,
8746	} COL_MAN_DENORM_CLAMP_CONTROL;
8747
8748	/*
8749	* COL_MAN_REGAMMA_MODE_CONTROL enum
8750	*/
8751
8752	typedef enum COL_MAN_REGAMMA_MODE_CONTROL {
8753	COL_MAN_REGAMMA_MODE_BYPASS = 0x00000000,
8754	COL_MAN_REGAMMA_MODE_ROM_A = 0x00000001,
8755	COL_MAN_REGAMMA_MODE_ROM_B = 0x00000002,
8756	COL_MAN_REGAMMA_MODE_A = 0x00000003,
8757	COL_MAN_REGAMMA_MODE_B = 0x00000004,
8758	} COL_MAN_REGAMMA_MODE_CONTROL;
8759
8760	/*
8761	* COL_MAN_GLOBAL_PASSTHROUGH_ENABLE enum
8762	*/
8763
8764	typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
8765	CM_GLOBAL_PASSTHROUGH_DISBALE = 0x00000000,
8766	CM_GLOBAL_PASSTHROUGH_ENABLE = 0x00000001,
8767	} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
8768
8769	/*
8770	* COL_MAN_DEGAMMA_MODE enum
8771	*/
8772
8773	typedef enum COL_MAN_DEGAMMA_MODE {
8774	DEGAMMA_MODE_BYPASS = 0x00000000,
8775	DEGAMMA_MODE_A = 0x00000001,
8776	DEGAMMA_MODE_B = 0x00000002,
8777	} COL_MAN_DEGAMMA_MODE;
8778
8779	/*
8780	* COL_MAN_GAMUT_REMAP_MODE enum
8781	*/
8782
8783	typedef enum COL_MAN_GAMUT_REMAP_MODE {
8784	GAMUT_REMAP_MODE_BYPASS = 0x00000000,
8785	GAMUT_REMAP_MODE_1 = 0x00000001,
8786	GAMUT_REMAP_MODE_2 = 0x00000002,
8787	GAMUT_REMAP_MODE_3 = 0x00000003,
8788	} COL_MAN_GAMUT_REMAP_MODE;
8789
8790	/*******************************************************
8791	* MCIF_WB Enums
8792	*******************************************************/
8793
8794	/*******************************************************
8795	* DP_AUX Enums
8796	*******************************************************/
8797
8798	/*
8799	* DP_AUX_CONTROL_HPD_SEL enum
8800	*/
8801
8802	typedef enum DP_AUX_CONTROL_HPD_SEL {
8803	DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000,
8804	DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001,
8805	DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002,
8806	DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003,
8807	DP_AUX_CONTROL_HPD5_SELECTED = 0x00000004,
8808	DP_AUX_CONTROL_HPD6_SELECTED = 0x00000005,
8809	} DP_AUX_CONTROL_HPD_SEL;
8810
8811	/*
8812	* DP_AUX_CONTROL_TEST_MODE enum
8813	*/
8814
8815	typedef enum DP_AUX_CONTROL_TEST_MODE {
8816	DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000,
8817	DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001,
8818	} DP_AUX_CONTROL_TEST_MODE;
8819
8820	/*
8821	* DP_AUX_SW_CONTROL_SW_GO enum
8822	*/
8823
8824	typedef enum DP_AUX_SW_CONTROL_SW_GO {
8825	DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000,
8826	DP_AUX_SW_CONTROL_SW__GO = 0x00000001,
8827	} DP_AUX_SW_CONTROL_SW_GO;
8828
8829	/*
8830	* DP_AUX_SW_CONTROL_LS_READ_TRIG enum
8831	*/
8832
8833	typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
8834	DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000,
8835	DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001,
8836	} DP_AUX_SW_CONTROL_LS_READ_TRIG;
8837
8838	/*
8839	* DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
8840	*/
8841
8842	typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
8843	DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000,
8844	DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001,
8845	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002,
8846	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003,
8847	} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
8848
8849	/*
8850	* DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
8851	*/
8852
8853	typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
8854	DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000,
8855	DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001,
8856	} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
8857
8858	/*
8859	* DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
8860	*/
8861
8862	typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
8863	DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
8864	DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001,
8865	} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
8866
8867	/*
8868	* DP_AUX_INT_ACK enum
8869	*/
8870
8871	typedef enum DP_AUX_INT_ACK {
8872	DP_AUX_INT__NOT_ACK = 0x00000000,
8873	DP_AUX_INT__ACK = 0x00000001,
8874	} DP_AUX_INT_ACK;
8875
8876	/*
8877	* DP_AUX_LS_UPDATE_ACK enum
8878	*/
8879
8880	typedef enum DP_AUX_LS_UPDATE_ACK {
8881	DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000,
8882	DP_AUX_INT_LS_UPDATE_ACK = 0x00000001,
8883	} DP_AUX_LS_UPDATE_ACK;
8884
8885	/*
8886	* DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
8887	*/
8888
8889	typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
8890	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000,
8891	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001,
8892	} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
8893
8894	/*
8895	* DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
8896	*/
8897
8898	typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
8899	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
8900	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
8901	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
8902	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
8903	} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
8904
8905	/*
8906	* DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN enum
8907	*/
8908
8909	typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
8910	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x00000000,
8911	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x00000001,
8912	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x00000002,
8913	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x00000003,
8914	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x00000004,
8915	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x00000005,
8916	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x00000006,
8917	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x00000007,
8918	} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
8919
8920	/*
8921	* DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
8922	*/
8923
8924	typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
8925	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
8926	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
8927	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
8928	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
8929	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
8930	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
8931	} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
8932
8933	/*
8934	* DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
8935	*/
8936
8937	typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
8938	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000,
8939	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001,
8940	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002,
8941	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003,
8942	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004,
8943	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005,
8944	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006,
8945	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007,
8946	} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
8947
8948	/*
8949	* DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
8950	*/
8951
8952	typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
8953	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000,
8954	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001,
8955	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002,
8956	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003,
8957	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004,
8958	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005,
8959	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006,
8960	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007,
8961	} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
8962
8963	/*
8964	* DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
8965	*/
8966
8967	typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
8968	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
8969	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
8970	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
8971	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
8972	} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
8973
8974	/*
8975	* DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
8976	*/
8977
8978	typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
8979	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
8980	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
8981	} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
8982
8983	/*
8984	* DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
8985	*/
8986
8987	typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
8988	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
8989	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
8990	} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
8991
8992	/*
8993	* DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
8994	*/
8995
8996	typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
8997	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
8998	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
8999	} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
9000
9001	/*
9002	* DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
9003	*/
9004
9005	typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
9006	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
9007	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
9008	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
9009	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
9010	} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
9011
9012	/*
9013	* DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN enum
9014	*/
9015
9016	typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
9017	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x00000000,
9018	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x00000001,
9019	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x00000002,
9020	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x00000003,
9021	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x00000004,
9022	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x00000005,
9023	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x00000006,
9024	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x00000007,
9025	} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
9026
9027	/*
9028	* DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
9029	*/
9030
9031	typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
9032	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000,
9033	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001,
9034	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002,
9035	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003,
9036	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004,
9037	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005,
9038	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006,
9039	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007,
9040	} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
9041
9042	/*
9043	* DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
9044	*/
9045
9046	typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
9047	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000,
9048	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001,
9049	} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
9050
9051	/*
9052	* DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
9053	*/
9054
9055	typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
9056	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
9057	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
9058	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
9059	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
9060	} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
9061
9062	/*
9063	* DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
9064	*/
9065
9066	typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
9067	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
9068	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
9069	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
9070	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
9071	} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
9072
9073	/*
9074	* DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
9075	*/
9076
9077	typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
9078	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000,
9079	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001,
9080	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002,
9081	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003,
9082	} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
9083
9084	/*
9085	* DP_AUX_ERR_OCCURRED_ACK enum
9086	*/
9087
9088	typedef enum DP_AUX_ERR_OCCURRED_ACK {
9089	DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000,
9090	DP_AUX_ERR_OCCURRED__ACK = 0x00000001,
9091	} DP_AUX_ERR_OCCURRED_ACK;
9092
9093	/*
9094	* DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
9095	*/
9096
9097	typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
9098	DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000,
9099	DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001,
9100	} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
9101
9102	/*
9103	* DP_AUX_DEFINITE_ERR_REACHED_ACK enum
9104	*/
9105
9106	typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
9107	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
9108	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001,
9109	} DP_AUX_DEFINITE_ERR_REACHED_ACK;
9110
9111	/*
9112	* DP_AUX_RESET enum
9113	*/
9114
9115	typedef enum DP_AUX_RESET {
9116	DP_AUX_RESET_DEASSERTED = 0x00000000,
9117	DP_AUX_RESET_ASSERTED = 0x00000001,
9118	} DP_AUX_RESET;
9119
9120	/*
9121	* DP_AUX_RESET_DONE enum
9122	*/
9123
9124	typedef enum DP_AUX_RESET_DONE {
9125	DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000,
9126	DP_AUX_RESET_SEQUENCE_DONE = 0x00000001,
9127	} DP_AUX_RESET_DONE;
9128
9129	/*******************************************************
9130	* DSI Enums
9131	*******************************************************/
9132
9133	/*
9134	* DSI_COMMAND_MODE_SRC_FORMAT enum
9135	*/
9136
9137	typedef enum DSI_COMMAND_MODE_SRC_FORMAT {
9138	DSI_COMMAND_SRC_FORMAT_RGB8BIT = 0x00000002,
9139	DSI_COMMAND_SRC_FORMAT_RGB332 = 0x00000003,
9140	DSI_COMMAND_SRC_FORMAT_RGB444 = 0x00000004,
9141	DSI_COMMAND_SRC_FORMAT_RGB555 = 0x00000005,
9142	DSI_COMMAND_SRC_FORMAT_RGB565 = 0x00000006,
9143	DSI_COMMAND_SRC_FORMAT_RGB888 = 0x00000008,
9144	} DSI_COMMAND_MODE_SRC_FORMAT;
9145
9146	/*
9147	* DSI_COMMAND_MODE_DST_FORMAT enum
9148	*/
9149
9150	typedef enum DSI_COMMAND_MODE_DST_FORMAT {
9151	DSI_COMMAND_DST_FORMAT_RGB111 = 0x00000000,
9152	DSI_COMMAND_DST_FORMAT_RGB332 = 0x00000003,
9153	DSI_COMMAND_DST_FORMAT_RGB444 = 0x00000004,
9154	DSI_COMMAND_DST_FORMAT_RGB565 = 0x00000006,
9155	DSI_COMMAND_DST_FORMAT_RGB666 = 0x00000007,
9156	DSI_COMMAND_DST_FORMAT_RGB888 = 0x00000008,
9157	} DSI_COMMAND_MODE_DST_FORMAT;
9158
9159	/*
9160	* DSI_FLAG_CLR enum
9161	*/
9162
9163	typedef enum DSI_FLAG_CLR {
9164	DSI_FLAG_NO_CLEAR = 0x00000000,
9165	DSI_FLAG_CLEAR = 0x00000001,
9166	} DSI_FLAG_CLR;
9167
9168	/*
9169	* DSI_BIT_SWAP enum
9170	*/
9171
9172	typedef enum DSI_BIT_SWAP {
9173	DSI_BIT_SWAP_DISABLE = 0x00000000,
9174	DSI_BIT_SWAP_ENABLE = 0x00000001,
9175	} DSI_BIT_SWAP;
9176
9177	/*
9178	* DSI_CLK_GATING enum
9179	*/
9180
9181	typedef enum DSI_CLK_GATING {
9182	DSI_CLK_GATING_ENABLE = 0x00000000,
9183	DSI_CLK_GATING_DISABLE = 0x00000001,
9184	} DSI_CLK_GATING;
9185
9186	/*
9187	* DSI_LANE_ULPS_REQUEST enum
9188	*/
9189
9190	typedef enum DSI_LANE_ULPS_REQUEST {
9191	DSI_LANE_ULPS_REQUEST_DEASSERT = 0x00000000,
9192	DSI_LANE_ULPS_REQUEST_ASSERT = 0x00000001,
9193	} DSI_LANE_ULPS_REQUEST;
9194
9195	/*
9196	* DSI_LANE_ULPS_EXIT enum
9197	*/
9198
9199	typedef enum DSI_LANE_ULPS_EXIT {
9200	DSI_LANE_ULPS_EXIT_DEASSERT = 0x00000000,
9201	DSI_LANE_ULPS_EXIT_ASSERT = 0x00000001,
9202	} DSI_LANE_ULPS_EXIT;
9203
9204	/*
9205	* DSI_LANE_FORCE_TX_STOP enum
9206	*/
9207
9208	typedef enum DSI_LANE_FORCE_TX_STOP {
9209	DSI_LANE_FORCE_TX_STOP_DEASSERT = 0x00000000,
9210	DSI_LANE_FORCE_TX_STOP_ASSERT = 0x00000001,
9211	} DSI_LANE_FORCE_TX_STOP;
9212
9213	/*
9214	* DSI_CLOCK_LANE_HS_FORCE_REQUEST enum
9215	*/
9216
9217	typedef enum DSI_CLOCK_LANE_HS_FORCE_REQUEST {
9218	DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT = 0x00000000,
9219	DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT = 0x00000001,
9220	} DSI_CLOCK_LANE_HS_FORCE_REQUEST;
9221
9222	/*
9223	* DSI_CONTROLLER_EN enum
9224	*/
9225
9226	typedef enum DSI_CONTROLLER_EN {
9227	DSI_CONTROLLER_DISABLE = 0x00000000,
9228	DSI_CONTROLLER_ENABLE = 0x00000001,
9229	} DSI_CONTROLLER_EN;
9230
9231	/*
9232	* DSI_VIDEO_MODE_EN enum
9233	*/
9234
9235	typedef enum DSI_VIDEO_MODE_EN {
9236	DSI_VIDEO_MODE_DISABLE = 0x00000000,
9237	DSI_VIDEO_MODE_ENABLE = 0x00000001,
9238	} DSI_VIDEO_MODE_EN;
9239
9240	/*
9241	* DSI_CMD_MODE_EN enum
9242	*/
9243
9244	typedef enum DSI_CMD_MODE_EN {
9245	DSI_CMD_MODE_DISABLE = 0x00000000,
9246	DSI_CMD_MODE_ENABLE = 0x00000001,
9247	} DSI_CMD_MODE_EN;
9248
9249	/*
9250	* DSI_DATA_LANE0_EN enum
9251	*/
9252
9253	typedef enum DSI_DATA_LANE0_EN {
9254	DSI_DATA_LANE0_DISABLE = 0x00000000,
9255	DSI_DATA_LANE0_ENABLE = 0x00000001,
9256	} DSI_DATA_LANE0_EN;
9257
9258	/*
9259	* DSI_DATA_LANE1_EN enum
9260	*/
9261
9262	typedef enum DSI_DATA_LANE1_EN {
9263	DSI_DATA_LANE1_DISABLE = 0x00000000,
9264	DSI_DATA_LANE1_ENABLE = 0x00000001,
9265	} DSI_DATA_LANE1_EN;
9266
9267	/*
9268	* DSI_DATA_LANE2_EN enum
9269	*/
9270
9271	typedef enum DSI_DATA_LANE2_EN {
9272	DSI_DATA_LANE2_DISABLE = 0x00000000,
9273	DSI_DATA_LANE2_ENABLE = 0x00000001,
9274	} DSI_DATA_LANE2_EN;
9275
9276	/*
9277	* DSI_DATA_LANE3_EN enum
9278	*/
9279
9280	typedef enum DSI_DATA_LANE3_EN {
9281	DSI_DATA_LANE3_DISABLE = 0x00000000,
9282	DSI_DATA_LANE3_ENABLE = 0x00000001,
9283	} DSI_DATA_LANE3_EN;
9284
9285	/*
9286	* DSI_CLOCK_LANE_EN enum
9287	*/
9288
9289	typedef enum DSI_CLOCK_LANE_EN {
9290	DSI_CLOCK_LANE_DISABLE = 0x00000000,
9291	DSI_CLOCK_LANE_ENABLE = 0x00000001,
9292	} DSI_CLOCK_LANE_EN;
9293
9294	/*
9295	* DSI_PHY_DATA_LANE0_EN enum
9296	*/
9297
9298	typedef enum DSI_PHY_DATA_LANE0_EN {
9299	DSI_PHY_DATA_LANE0_DISABLE = 0x00000000,
9300	DSI_PHY_DATA_LANE0_ENABLE = 0x00000001,
9301	} DSI_PHY_DATA_LANE0_EN;
9302
9303	/*
9304	* DSI_PHY_DATA_LANE1_EN enum
9305	*/
9306
9307	typedef enum DSI_PHY_DATA_LANE1_EN {
9308	DSI_PHY_DATA_LANE1_DISABLE = 0x00000000,
9309	DSI_PHY_DATA_LANE1_ENABLE = 0x00000001,
9310	} DSI_PHY_DATA_LANE1_EN;
9311
9312	/*
9313	* DSI_PHY_DATA_LANE2_EN enum
9314	*/
9315
9316	typedef enum DSI_PHY_DATA_LANE2_EN {
9317	DSI_PHY_DATA_LANE2_DISABLE = 0x00000000,
9318	DSI_PHY_DATA_LANE2_ENABLE = 0x00000001,
9319	} DSI_PHY_DATA_LANE2_EN;
9320
9321	/*
9322	* DSI_PHY_DATA_LANE3_EN enum
9323	*/
9324
9325	typedef enum DSI_PHY_DATA_LANE3_EN {
9326	DSI_PHY_DATA_LANE3_DISABLE = 0x00000000,
9327	DSI_PHY_DATA_LANE3_ENABLE = 0x00000001,
9328	} DSI_PHY_DATA_LANE3_EN;
9329
9330	/*
9331	* DSI_RESET_DISPCLK enum
9332	*/
9333
9334	typedef enum DSI_RESET_DISPCLK {
9335	DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0x00000000,
9336	DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0x00000001,
9337	} DSI_RESET_DISPCLK;
9338
9339	/*
9340	* DSI_RESET_DSICLK enum
9341	*/
9342
9343	typedef enum DSI_RESET_DSICLK {
9344	DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC = 0x00000000,
9345	DSI_RESET_ON_DSICLK_DOMAIN_LOGIC = 0x00000001,
9346	} DSI_RESET_DSICLK;
9347
9348	/*
9349	* DSI_RESET_BYTECLK enum
9350	*/
9351
9352	typedef enum DSI_RESET_BYTECLK {
9353	DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0x00000000,
9354	DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0x00000001,
9355	} DSI_RESET_BYTECLK;
9356
9357	/*
9358	* DSI_RESET_ESCCLK enum
9359	*/
9360
9361	typedef enum DSI_RESET_ESCCLK {
9362	DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0x00000000,
9363	DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0x00000001,
9364	} DSI_RESET_ESCCLK;
9365
9366	/*
9367	* DSI_CRTC_SEL enum
9368	*/
9369
9370	typedef enum DSI_CRTC_SEL {
9371	DSI_GET_PIXEL_STREAM_FROM_FMT0 = 0x00000000,
9372	DSI_GET_PIXEL_STREAM_FROM_FMT1 = 0x00000001,
9373	DSI_GET_PIXEL_STREAM_FROM_FMT2 = 0x00000002,
9374	DSI_GET_PIXEL_STREAM_FROM_FMT3 = 0x00000003,
9375	DSI_GET_PIXEL_STREAM_FROM_FMT4 = 0x00000004,
9376	DSI_GET_PIXEL_STREAM_FROM_FMT5 = 0x00000005,
9377	} DSI_CRTC_SEL;
9378
9379	/*
9380	* DSI_PACKET_BYTE_MSB_LSB_FLIP enum
9381	*/
9382
9383	typedef enum DSI_PACKET_BYTE_MSB_LSB_FLIP {
9384	DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP = 0x00000000,
9385	DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP = 0x00000001,
9386	} DSI_PACKET_BYTE_MSB_LSB_FLIP;
9387
9388	/*
9389	* DSI_VIDEO_MODE_DST_FORMAT enum
9390	*/
9391
9392	typedef enum DSI_VIDEO_MODE_DST_FORMAT {
9393	DSI_VIDEO_DST_FORMAT_RGB565 = 0x00000000,
9394	DSI_VIDEO_DST_FORMAT_RGB666_PACKED = 0x00000001,
9395	DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 0x00000002,
9396	DSI_VIDEO_DST_FORMAT_RGB888 = 0x00000003,
9397	} DSI_VIDEO_MODE_DST_FORMAT;
9398
9399	/*
9400	* DSI_VIDEO_TRAFFIC_MODE enum
9401	*/
9402
9403	typedef enum DSI_VIDEO_TRAFFIC_MODE {
9404	DSI_TRAFFIC_MODE_SYNC_PULSES = 0x00000000,
9405	DSI_TRAFFIC_MODE_SYNC_EVENTS = 0x00000001,
9406	DSI_TRAFFIC_MODE_BURST = 0x00000002,
9407	DSI_TRAFFIC_MODE_RESERVED = 0x00000003,
9408	} DSI_VIDEO_TRAFFIC_MODE;
9409
9410	/*
9411	* DSI_VIDEO_BLLP_PWR_MODE enum
9412	*/
9413
9414	typedef enum DSI_VIDEO_BLLP_PWR_MODE {
9415	DSI_VIDEO_BLLP_PWR_MODE_HS = 0x00000000,
9416	DSI_VIDEO_BLLP_PWR_MODE_LP = 0x00000001,
9417	} DSI_VIDEO_BLLP_PWR_MODE;
9418
9419	/*
9420	* DSI_VIDEO_EOF_BLLP_PWR_MODE enum
9421	*/
9422
9423	typedef enum DSI_VIDEO_EOF_BLLP_PWR_MODE {
9424	DSI_VIDEO_EOF_BLLP_PWR_MODE_HS = 0x00000000,
9425	DSI_VIDEO_EOF_BLLP_PWR_MODE_LP = 0x00000001,
9426	} DSI_VIDEO_EOF_BLLP_PWR_MODE;
9427
9428	/*
9429	* DSI_VIDEO_PWR_MODE enum
9430	*/
9431
9432	typedef enum DSI_VIDEO_PWR_MODE {
9433	DSI_VIDEO_PWR_MODE_HS = 0x00000000,
9434	DSI_VIDEO_PWR_MODE_LP = 0x00000001,
9435	} DSI_VIDEO_PWR_MODE;
9436
9437	/*
9438	* DSI_VIDEO_PULSE_MODE_OPT enum
9439	*/
9440
9441	typedef enum DSI_VIDEO_PULSE_MODE_OPT {
9442	PULSE_MODE_OPT_NO_HSA = 0x00000000,
9443	PULSE_MODE_OPT_SEND = 0x00000001,
9444	} DSI_VIDEO_PULSE_MODE_OPT;
9445
9446	/*
9447	* DSI_RGB_SWAP enum
9448	*/
9449
9450	typedef enum DSI_RGB_SWAP {
9451	DSI_SWAP_RGB = 0x00000000,
9452	DSI_SWAP_RBG = 0x00000001,
9453	DSI_SWAP_BGR = 0x00000002,
9454	DSI_SWAP_BRG = 0x00000003,
9455	DSI_SWAP_GRB = 0x00000004,
9456	DSI_SWAP_GBR = 0x00000005,
9457	} DSI_RGB_SWAP;
9458
9459	/*
9460	* DSI_CMD_PACKET_TYPE enum
9461	*/
9462
9463	typedef enum DSI_CMD_PACKET_TYPE {
9464	DSI_CMD_PACKET_TYPE_SHORT = 0x00000000,
9465	DSI_CMD_PACKET_TYPE_LONG = 0x00000001,
9466	} DSI_CMD_PACKET_TYPE;
9467
9468	/*
9469	* DSI_CMD_PWR_MODE enum
9470	*/
9471
9472	typedef enum DSI_CMD_PWR_MODE {
9473	DSI_CMD_PWR_MODE_HS = 0x00000000,
9474	DSI_CMD_PWR_MODE_LP = 0x00000001,
9475	} DSI_CMD_PWR_MODE;
9476
9477	/*
9478	* DSI_CMD_EMBEDDED_MODE enum
9479	*/
9480
9481	typedef enum DSI_CMD_EMBEDDED_MODE {
9482	CMD_EMBEDDED_MODE_DISABLE = 0x00000000,
9483	CMD_EMBEDDED_MODE_ENABLE = 0x00000001,
9484	} DSI_CMD_EMBEDDED_MODE;
9485
9486	/*
9487	* DSI_CMD_ORDER enum
9488	*/
9489
9490	typedef enum DSI_CMD_ORDER {
9491	DSI_CMD_ORDER_COMMAND_FIRST = 0x00000000,
9492	DSI_CMD_ORDER_DATA_FIRST = 0x00000001,
9493	} DSI_CMD_ORDER;
9494
9495	/*
9496	* DSI_DATA_BUFFER_ID enum
9497	*/
9498
9499	typedef enum DSI_DATA_BUFFER_ID {
9500	DSI_DATA_BUFFER_OFFSET0 = 0x00000000,
9501	DSI_DATA_BUFFER_OFFSET1 = 0x00000001,
9502	} DSI_DATA_BUFFER_ID;
9503
9504	/*
9505	* DSI_DWORD_BYTE_SWAP enum
9506	*/
9507
9508	typedef enum DSI_DWORD_BYTE_SWAP {
9509	DWORD_BYTE_SWAP_NO_SWAP = 0x00000000,
9510	DWORD_BYTE_SWAP_BYTE_SWAP = 0x00000001,
9511	DWORD_BYTE_SWAP_WORD_SWAP = 0x00000002,
9512	DWORD_BYTE_SWAP_BOTH_SWAP = 0x00000003,
9513	} DSI_DWORD_BYTE_SWAP;
9514
9515	/*
9516	* DSI_INSERT_DCS_COMMAND enum
9517	*/
9518
9519	typedef enum DSI_INSERT_DCS_COMMAND {
9520	DSI_INSERT_DCS_COMMAND_DISABLE = 0x00000000,
9521	DSI_INSERT_DCS_COMMAND_ENABLE = 0x00000001,
9522	} DSI_INSERT_DCS_COMMAND;
9523
9524	/*
9525	* DSI_DMAFIFO_WRITE_WATERMARK enum
9526	*/
9527
9528	typedef enum DSI_DMAFIFO_WRITE_WATERMARK {
9529	DSI_DMAFIFO_WRITE_WATERMARK_HALF = 0x00000000,
9530	DSI_DMAFIFO_WRITE_WATERMARK_FOURTH = 0x00000001,
9531	DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH = 0x00000002,
9532	DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH = 0x00000003,
9533	} DSI_DMAFIFO_WRITE_WATERMARK;
9534
9535	/*
9536	* DSI_DMAFIFO_READ_WATERMARK enum
9537	*/
9538
9539	typedef enum DSI_DMAFIFO_READ_WATERMARK {
9540	DSI_DMAFIFO_READ_WATERMARK_HALF = 0x00000000,
9541	DSI_DMAFIFO_READ_WATERMARK_FOURTH = 0x00000001,
9542	DSI_DMAFIFO_READ_WATERMARK_EIGHTH = 0x00000002,
9543	DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH = 0x00000003,
9544	} DSI_DMAFIFO_READ_WATERMARK;
9545
9546	/*
9547	* DSI_USE_DENG_LENGTH enum
9548	*/
9549
9550	typedef enum DSI_USE_DENG_LENGTH {
9551	DSI_USE_DENG_LENGTH_DISABLE = 0x00000000,
9552	DSI_USE_DENG_LENGTH_ENABLE = 0x00000001,
9553	} DSI_USE_DENG_LENGTH;
9554
9555	/*
9556	* DSI_COMMAND_TRIGGER_MODE enum
9557	*/
9558
9559	typedef enum DSI_COMMAND_TRIGGER_MODE {
9560	DSI_COMMAND_TRIGGER_MODE_AUTO = 0x00000000,
9561	DSI_COMMAND_TRIGGER_MODE_MANUAL = 0x00000001,
9562	} DSI_COMMAND_TRIGGER_MODE;
9563
9564	/*
9565	* DSI_COMMAND_TRIGGER_SEL enum
9566	*/
9567
9568	typedef enum DSI_COMMAND_TRIGGER_SEL {
9569	DSI_COMMAND_TRIGGER_SEL_NONE = 0x00000000,
9570	DSI_COMMAND_TRIGGER_SEL_CRTC = 0x00000001,
9571	DSI_COMMAND_TRIGGER_SEL_TE = 0x00000002,
9572	DSI_COMMAND_TRIGGER_SEL_HW = 0x00000003,
9573	} DSI_COMMAND_TRIGGER_SEL;
9574
9575	/*
9576	* DSI_HW_SOURCE_SEL enum
9577	*/
9578
9579	typedef enum DSI_HW_SOURCE_SEL {
9580	HW_SOURCE_SEL_NONE = 0x00000000,
9581	HW_SOURCE_SEL_DSC_VUP = 0x00000001,
9582	HW_SOURCE_SEL_DSC_VLP = 0x00000002,
9583	HW_SOURCE_SEL_DSC_JPEG = 0x00000003,
9584	} DSI_HW_SOURCE_SEL;
9585
9586	/*
9587	* DSI_COMMAND_TRIGGER_ORDER enum
9588	*/
9589
9590	typedef enum DSI_COMMAND_TRIGGER_ORDER {
9591	DSI_COMMAND_TRIGGER_ORDER_DMA = 0x00000000,
9592	DSI_COMMAND_TRIGGER_ORDER_DENG = 0x00000001,
9593	} DSI_COMMAND_TRIGGER_ORDER;
9594
9595	/*
9596	* DSI_TE_SRC_SEL enum
9597	*/
9598
9599	typedef enum DSI_TE_SRC_SEL {
9600	DSI_TE_SEL_LINK = 0x00000000,
9601	DSI_TE_SEL_PIN = 0x00000001,
9602	} DSI_TE_SRC_SEL;
9603
9604	/*
9605	* DSI_EXT_TE_MUX enum
9606	*/
9607
9608	typedef enum DSI_EXT_TE_MUX {
9609	DSI_XT_TE_MUX_LCDD17 = 0x00000000,
9610	DSI_XT_TE_MUX_DCLK = 0x00000001,
9611	DSI_XT_TE_MUX_SS = 0x00000002,
9612	DSI_XT_TE_MUX_GCLK = 0x00000003,
9613	DSI_XT_TE_MUX_GOE = 0x00000004,
9614	DSI_XT_TE_MUX_DINV = 0x00000005,
9615	DSI_XT_TE_MUX_FRAME = 0x00000006,
9616	DSI_XT_TE_MUX_GPIO4 = 0x00000007,
9617	DSI_XT_TE_MUX_GPIO5 = 0x00000008,
9618	} DSI_EXT_TE_MUX;
9619
9620	/*
9621	* DSI_EXT_TE_MODE enum
9622	*/
9623
9624	typedef enum DSI_EXT_TE_MODE {
9625	DSI_EXT_TE_MODE_VSYNC_EDGE = 0x00000000,
9626	DSI_EXT_TE_MODE_VSYNC_WIDTH = 0x00000001,
9627	DSI_EXT_TE_MODE_HVSYNC_EDGE = 0x00000002,
9628	DSI_EXT_TE_MODE_HVSYNC_WIDTH = 0x00000003,
9629	} DSI_EXT_TE_MODE;
9630
9631	/*
9632	* DSI_EXT_RESET_POL enum
9633	*/
9634
9635	typedef enum DSI_EXT_RESET_POL {
9636	DSI_EXT_RESET_POL_HIGH = 0x00000000,
9637	DSI_EXT_RESET_POL_LOW = 0x00000001,
9638	} DSI_EXT_RESET_POL;
9639
9640	/*
9641	* DSI_EXT_TE_POL enum
9642	*/
9643
9644	typedef enum DSI_EXT_TE_POL {
9645	DSI_EXT_TE_POL_RISING = 0x00000000,
9646	DSI_EXT_TE_POL_FALLING = 0x00000001,
9647	} DSI_EXT_TE_POL;
9648
9649	/*
9650	* DSI_RESET_PANEL enum
9651	*/
9652
9653	typedef enum DSI_RESET_PANEL {
9654	DSI_RESET_PANEL_DEASSERT = 0x00000000,
9655	DSI_RESET_PANEL_ASSERT = 0x00000001,
9656	} DSI_RESET_PANEL;
9657
9658	/*
9659	* DSI_CRC_ENABLE enum
9660	*/
9661
9662	typedef enum DSI_CRC_ENABLE {
9663	DSI_CRC_CAL_DISABLE = 0x00000000,
9664	DSI_CRC_CAL_ENABLE = 0x00000001,
9665	} DSI_CRC_ENABLE;
9666
9667	/*
9668	* DSI_TX_EOT_APPEND enum
9669	*/
9670
9671	typedef enum DSI_TX_EOT_APPEND {
9672	DSI_TX_EOT_APPEND_DISABLE = 0x00000000,
9673	DSI_TX_EOT_APPEND_ENABLE = 0x00000001,
9674	} DSI_TX_EOT_APPEND;
9675
9676	/*
9677	* DSI_RX_EOT_IGNORE enum
9678	*/
9679
9680	typedef enum DSI_RX_EOT_IGNORE {
9681	DSI_RX_EOT_IGNORE_DISABLE = 0x00000000,
9682	DSI_RX_EOT_IGNORE_ENABLE = 0x00000001,
9683	} DSI_RX_EOT_IGNORE;
9684
9685	/*
9686	* DSI_MIPI_BIST_RESET enum
9687	*/
9688
9689	typedef enum DSI_MIPI_BIST_RESET {
9690	DSI_MIPI_BIST_RESET_DEASSERT = 0x00000000,
9691	DSI_MIPI_BIST_RESET_ASSERT = 0x00000001,
9692	} DSI_MIPI_BIST_RESET;
9693
9694	/*
9695	* DSI_MIPI_BIST_VIDEO_FRMT enum
9696	*/
9697
9698	typedef enum DSI_MIPI_BIST_VIDEO_FRMT {
9699	DSI_MIPI_BIST_VIDEO_FRMT_YUV422 = 0x00000000,
9700	DSI_MIPI_BIST_VIDEO_FRMT_RAW8 = 0x00000001,
9701	} DSI_MIPI_BIST_VIDEO_FRMT;
9702
9703	/*
9704	* DSI_MIPI_BIST_START enum
9705	*/
9706
9707	typedef enum DSI_MIPI_BIST_START {
9708	DSI_MIPI_BIST_START_DEASSERT = 0x00000000,
9709	DSI_MIPI_BIST_START_ASSERT = 0x00000001,
9710	} DSI_MIPI_BIST_START;
9711
9712	/*
9713	* DSI_DBG_CLK_SEL enum
9714	*/
9715
9716	typedef enum DSI_DBG_CLK_SEL {
9717	DSI_TEST_CLK_SEL_DISPCLK_P = 0x00000000,
9718	DSI_TEST_CLK_SEL_DISPCLK_G = 0x00000001,
9719	DSI_TEST_CLK_SEL_DISPCLK_R = 0x00000002,
9720	DSI_TEST_CLK_SEL_ESCCLK_G = 0x00000003,
9721	DSI_TEST_CLK_SEL_BYTECLK_G = 0x00000004,
9722	DSI_TEST_CLK_SEL_DSICLK_P = 0x00000005,
9723	DSI_TEST_CLK_SEL_DSICLK_R = 0x00000006,
9724	DSI_TEST_CLK_SEL_DSICLK_G = 0x00000007,
9725	DSI_TEST_CLK_SEL_DSICLK_TRN = 0x00000008,
9726	} DSI_DBG_CLK_SEL;
9727
9728	/*
9729	* DSI_DENG_FIFO_USE_OVERWRITE_LEVEL enum
9730	*/
9731
9732	typedef enum DSI_DENG_FIFO_USE_OVERWRITE_LEVEL {
9733	DSI_DENG_FIFO_LEVEL_OVERWRITE = 0x00000000,
9734	DSI_DENG_FIFO_LEVEL_CAL_AVERAGE = 0x00000001,
9735	} DSI_DENG_FIFO_USE_OVERWRITE_LEVEL;
9736
9737	/*
9738	* DSI_DENG_FIFO_FORCE_RECAL_AVERAGE enum
9739	*/
9740
9741	typedef enum DSI_DENG_FIFO_FORCE_RECAL_AVERAGE {
9742	DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT = 0x00000000,
9743	DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT = 0x00000001,
9744	} DSI_DENG_FIFO_FORCE_RECAL_AVERAGE;
9745
9746	/*
9747	* DSI_DENG_FIFO_FORCE_RECOMP_MINMAX enum
9748	*/
9749
9750	typedef enum DSI_DENG_FIFO_FORCE_RECOMP_MINMAX {
9751	DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT = 0x00000000,
9752	DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT = 0x00000001,
9753	} DSI_DENG_FIFO_FORCE_RECOMP_MINMAX;
9754
9755	/*
9756	* DSI_DENG_FIFO_START enum
9757	*/
9758
9759	typedef enum DSI_DENG_FIFO_START {
9760	DSI_DENG_FIFO_START_DEASSERT = 0x00000000,
9761	DSI_DENG_FIFO_START_ASSERT = 0x00000001,
9762	} DSI_DENG_FIFO_START;
9763
9764	/*
9765	* DSI_USE_CMDFIFO enum
9766	*/
9767
9768	typedef enum DSI_USE_CMDFIFO {
9769	DSI_CMD_USE_DMAFIFO = 0x00000000,
9770	DSI_CMD_USE_CMDFIFO = 0x00000001,
9771	} DSI_USE_CMDFIFO;
9772
9773	/*
9774	* DSI_CRTC_FREEZE_TRIG enum
9775	*/
9776
9777	typedef enum DSI_CRTC_FREEZE_TRIG {
9778	DSI_CRTC_FREEZE_TRIG_DEASSERT = 0x00000000,
9779	DSI_CRTC_FREEZE_TRIG_ASSERT = 0x00000001,
9780	} DSI_CRTC_FREEZE_TRIG;
9781
9782	/*
9783	* DSI_PERF_LATENCY_SEL enum
9784	*/
9785
9786	typedef enum DSI_PERF_LATENCY_SEL {
9787	DSI_PERF_LATENCY_SEL_DATA_LANE0 = 0x00000000,
9788	DSI_PERF_LATENCY_SEL_DATA_LANE1 = 0x00000001,
9789	DSI_PERF_LATENCY_SEL_DATA_LANE2 = 0x00000002,
9790	DSI_PERF_LATENCY_SEL_DATA_LANE3 = 0x00000003,
9791	} DSI_PERF_LATENCY_SEL;
9792
9793	/*
9794	* DSI_DEBUG_DSICLK_SEL enum
9795	*/
9796
9797	typedef enum DSI_DEBUG_DSICLK_SEL {
9798	DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE = 0x00000000,
9799	DSI_DEBUG_DSICLK_SEL_CMD_ENGINE = 0x00000001,
9800	DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO = 0x00000002,
9801	DSI_DEBUG_DSICLK_SEL_CMDFIFO = 0x00000003,
9802	DSI_DEBUG_DSICLK_SEL_CMDBUFFER = 0x00000004,
9803	DSI_DEBUG_DSICLK_SEL_AFIFO = 0x00000005,
9804	DSI_DEBUG_DSICLK_SEL_LANECTRL = 0x00000006,
9805	} DSI_DEBUG_DSICLK_SEL;
9806
9807	/*
9808	* DSI_DEBUG_BYTECLK_SEL enum
9809	*/
9810
9811	typedef enum DSI_DEBUG_BYTECLK_SEL {
9812	DSI_DEBUG_BYTECLK_SEL_AFIFO = 0x00000000,
9813	DSI_DEBUG_BYTECLK_SEL_LANEFIFO0 = 0x00000001,
9814	DSI_DEBUG_BYTECLK_SEL_LANEFIFO1 = 0x00000002,
9815	DSI_DEBUG_BYTECLK_SEL_LANEFIFO2 = 0x00000003,
9816	DSI_DEBUG_BYTECLK_SEL_LANEFIFO3 = 0x00000004,
9817	DSI_DEBUG_BYTECLK_SEL_LANEBUF0 = 0x00000005,
9818	DSI_DEBUG_BYTECLK_SEL_LANEBUF1 = 0x00000006,
9819	DSI_DEBUG_BYTECLK_SEL_LANEBUF2 = 0x00000007,
9820	DSI_DEBUG_BYTECLK_SEL_LANEBUF3 = 0x00000008,
9821	DSI_DEBUG_BYTECLK_SEL_PINGPONG0 = 0x00000009,
9822	DSI_DEBUG_BYTECLK_SEL_PINGPONG1 = 0x0000000a,
9823	DSI_DEBUG_BYTECLK_SEL_PINGPING2 = 0x0000000b,
9824	DSI_DEBUG_BYTECLK_SEL_PINGPING3 = 0x0000000c,
9825	DSI_DEBUG_BYTECLK_SEL_EOT = 0x0000000d,
9826	DSI_DEBUG_BYTECLK_SEL_LANECTRL = 0x0000000e,
9827	} DSI_DEBUG_BYTECLK_SEL;
9828
9829	/*******************************************************
9830	* DCIO_CHIP Enums
9831	*******************************************************/
9832
9833	/*
9834	* DCIOCHIP_HPD_SEL enum
9835	*/
9836
9837	typedef enum DCIOCHIP_HPD_SEL {
9838	DCIOCHIP_HPD_SEL_ASYNC = 0x00000000,
9839	DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001,
9840	} DCIOCHIP_HPD_SEL;
9841
9842	/*
9843	* DCIOCHIP_PAD_MODE enum
9844	*/
9845
9846	typedef enum DCIOCHIP_PAD_MODE {
9847	DCIOCHIP_PAD_MODE_DDC = 0x00000000,
9848	DCIOCHIP_PAD_MODE_DP = 0x00000001,
9849	} DCIOCHIP_PAD_MODE;
9850
9851	/*
9852	* DCIOCHIP_AUXSLAVE_PAD_MODE enum
9853	*/
9854
9855	typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
9856	DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x00000000,
9857	DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x00000001,
9858	} DCIOCHIP_AUXSLAVE_PAD_MODE;
9859
9860	/*
9861	* DCIOCHIP_INVERT enum
9862	*/
9863
9864	typedef enum DCIOCHIP_INVERT {
9865	DCIOCHIP_POL_NON_INVERT = 0x00000000,
9866	DCIOCHIP_POL_INVERT = 0x00000001,
9867	} DCIOCHIP_INVERT;
9868
9869	/*
9870	* DCIOCHIP_PD_EN enum
9871	*/
9872
9873	typedef enum DCIOCHIP_PD_EN {
9874	DCIOCHIP_PD_EN_NOTALLOW = 0x00000000,
9875	DCIOCHIP_PD_EN_ALLOW = 0x00000001,
9876	} DCIOCHIP_PD_EN;
9877
9878	/*
9879	* DCIOCHIP_GPIO_MASK_EN enum
9880	*/
9881
9882	typedef enum DCIOCHIP_GPIO_MASK_EN {
9883	DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000,
9884	DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001,
9885	} DCIOCHIP_GPIO_MASK_EN;
9886
9887	/*
9888	* DCIOCHIP_MASK enum
9889	*/
9890
9891	typedef enum DCIOCHIP_MASK {
9892	DCIOCHIP_MASK_DISABLE = 0x00000000,
9893	DCIOCHIP_MASK_ENABLE = 0x00000001,
9894	} DCIOCHIP_MASK;
9895
9896	/*
9897	* DCIOCHIP_GPIO_I2C_MASK enum
9898	*/
9899
9900	typedef enum DCIOCHIP_GPIO_I2C_MASK {
9901	DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x00000000,
9902	DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x00000001,
9903	} DCIOCHIP_GPIO_I2C_MASK;
9904
9905	/*
9906	* DCIOCHIP_GPIO_I2C_DRIVE enum
9907	*/
9908
9909	typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
9910	DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x00000000,
9911	DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x00000001,
9912	} DCIOCHIP_GPIO_I2C_DRIVE;
9913
9914	/*
9915	* DCIOCHIP_GPIO_I2C_EN enum
9916	*/
9917
9918	typedef enum DCIOCHIP_GPIO_I2C_EN {
9919	DCIOCHIP_GPIO_I2C_DISABLE = 0x00000000,
9920	DCIOCHIP_GPIO_I2C_ENABLE = 0x00000001,
9921	} DCIOCHIP_GPIO_I2C_EN;
9922
9923	/*
9924	* DCIOCHIP_MASK_4BIT enum
9925	*/
9926
9927	typedef enum DCIOCHIP_MASK_4BIT {
9928	DCIOCHIP_MASK_4BIT_DISABLE = 0x00000000,
9929	DCIOCHIP_MASK_4BIT_ENABLE = 0x0000000f,
9930	} DCIOCHIP_MASK_4BIT;
9931
9932	/*
9933	* DCIOCHIP_ENABLE_4BIT enum
9934	*/
9935
9936	typedef enum DCIOCHIP_ENABLE_4BIT {
9937	DCIOCHIP_4BIT_DISABLE = 0x00000000,
9938	DCIOCHIP_4BIT_ENABLE = 0x0000000f,
9939	} DCIOCHIP_ENABLE_4BIT;
9940
9941	/*
9942	* DCIOCHIP_MASK_5BIT enum
9943	*/
9944
9945	typedef enum DCIOCHIP_MASK_5BIT {
9946	DCIOCHIP_MASIK_5BIT_DISABLE = 0x00000000,
9947	DCIOCHIP_MASIK_5BIT_ENABLE = 0x0000001f,
9948	} DCIOCHIP_MASK_5BIT;
9949
9950	/*
9951	* DCIOCHIP_ENABLE_5BIT enum
9952	*/
9953
9954	typedef enum DCIOCHIP_ENABLE_5BIT {
9955	DCIOCHIP_5BIT_DISABLE = 0x00000000,
9956	DCIOCHIP_5BIT_ENABLE = 0x0000001f,
9957	} DCIOCHIP_ENABLE_5BIT;
9958
9959	/*
9960	* DCIOCHIP_MASK_2BIT enum
9961	*/
9962
9963	typedef enum DCIOCHIP_MASK_2BIT {
9964	DCIOCHIP_MASK_2BIT_DISABLE = 0x00000000,
9965	DCIOCHIP_MASK_2BIT_ENABLE = 0x00000003,
9966	} DCIOCHIP_MASK_2BIT;
9967
9968	/*
9969	* DCIOCHIP_ENABLE_2BIT enum
9970	*/
9971
9972	typedef enum DCIOCHIP_ENABLE_2BIT {
9973	DCIOCHIP_2BIT_DISABLE = 0x00000000,
9974	DCIOCHIP_2BIT_ENABLE = 0x00000003,
9975	} DCIOCHIP_ENABLE_2BIT;
9976
9977	/*
9978	* DCIOCHIP_REF_27_SRC_SEL enum
9979	*/
9980
9981	typedef enum DCIOCHIP_REF_27_SRC_SEL {
9982	DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000,
9983	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001,
9984	DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002,
9985	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003,
9986	} DCIOCHIP_REF_27_SRC_SEL;
9987
9988	/*
9989	* DCIOCHIP_DVO_VREFPON enum
9990	*/
9991
9992	typedef enum DCIOCHIP_DVO_VREFPON {
9993	DCIOCHIP_DVO_VREFPON_DISABLE = 0x00000000,
9994	DCIOCHIP_DVO_VREFPON_ENABLE = 0x00000001,
9995	} DCIOCHIP_DVO_VREFPON;
9996
9997	/*
9998	* DCIOCHIP_DVO_VREFSEL enum
9999	*/
10000
10001	typedef enum DCIOCHIP_DVO_VREFSEL {
10002	DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x00000000,
10003	DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x00000001,
10004	} DCIOCHIP_DVO_VREFSEL;
10005
10006	/*
10007	* DCIOCHIP_SPDIF1_IMODE enum
10008	*/
10009
10010	typedef enum DCIOCHIP_SPDIF1_IMODE {
10011	DCIOCHIP_SPDIF1_IMODE_OE_A = 0x00000000,
10012	DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 0x00000001,
10013	} DCIOCHIP_SPDIF1_IMODE;
10014
10015	/*
10016	* DCIOCHIP_AUX_FALLSLEWSEL enum
10017	*/
10018
10019	typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
10020	DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000,
10021	DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001,
10022	DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002,
10023	DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003,
10024	} DCIOCHIP_AUX_FALLSLEWSEL;
10025
10026	/*
10027	* DCIOCHIP_AUX_SPIKESEL enum
10028	*/
10029
10030	typedef enum DCIOCHIP_AUX_SPIKESEL {
10031	DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000,
10032	DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001,
10033	} DCIOCHIP_AUX_SPIKESEL;
10034
10035	/*
10036	* DCIOCHIP_AUX_CSEL0P9 enum
10037	*/
10038
10039	typedef enum DCIOCHIP_AUX_CSEL0P9 {
10040	DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000,
10041	DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001,
10042	} DCIOCHIP_AUX_CSEL0P9;
10043
10044	/*
10045	* DCIOCHIP_AUX_CSEL1P1 enum
10046	*/
10047
10048	typedef enum DCIOCHIP_AUX_CSEL1P1 {
10049	DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000,
10050	DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001,
10051	} DCIOCHIP_AUX_CSEL1P1;
10052
10053	/*
10054	* DCIOCHIP_AUX_RSEL0P9 enum
10055	*/
10056
10057	typedef enum DCIOCHIP_AUX_RSEL0P9 {
10058	DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000,
10059	DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001,
10060	} DCIOCHIP_AUX_RSEL0P9;
10061
10062	/*
10063	* DCIOCHIP_AUX_RSEL1P1 enum
10064	*/
10065
10066	typedef enum DCIOCHIP_AUX_RSEL1P1 {
10067	DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000,
10068	DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001,
10069	} DCIOCHIP_AUX_RSEL1P1;
10070
10071	/*******************************************************
10072	* AZCONTROLLER Enums
10073	*******************************************************/
10074
10075	/*
10076	* GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
10077	*/
10078
10079	typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
10080	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000,
10081	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001,
10082	} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
10083
10084	/*
10085	* GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
10086	*/
10087
10088	typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
10089	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000,
10090	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001,
10091	} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
10092
10093	/*
10094	* GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
10095	*/
10096
10097	typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
10098	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000,
10099	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001,
10100	} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
10101
10102	/*
10103	* GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
10104	*/
10105
10106	typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
10107	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000,
10108	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001,
10109	} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
10110
10111	/*
10112	* AZ_GLOBAL_CAPABILITIES enum
10113	*/
10114
10115	typedef enum AZ_GLOBAL_CAPABILITIES {
10116	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000,
10117	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001,
10118	} AZ_GLOBAL_CAPABILITIES;
10119
10120	/*
10121	* GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
10122	*/
10123
10124	typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
10125	ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000,
10126	ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001,
10127	} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
10128
10129	/*
10130	* GLOBAL_CONTROL_FLUSH_CONTROL enum
10131	*/
10132
10133	typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
10134	FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000,
10135	FLUSH_CONTROL_FLUSH_STARTED = 0x00000001,
10136	} GLOBAL_CONTROL_FLUSH_CONTROL;
10137
10138	/*
10139	* GLOBAL_CONTROL_CONTROLLER_RESET enum
10140	*/
10141
10142	typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
10143	CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000,
10144	CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001,
10145	} GLOBAL_CONTROL_CONTROLLER_RESET;
10146
10147	/*
10148	* AZ_STATE_CHANGE_STATUS enum
10149	*/
10150
10151	typedef enum AZ_STATE_CHANGE_STATUS {
10152	AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000,
10153	AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001,
10154	} AZ_STATE_CHANGE_STATUS;
10155
10156	/*
10157	* GLOBAL_STATUS_FLUSH_STATUS enum
10158	*/
10159
10160	typedef enum GLOBAL_STATUS_FLUSH_STATUS {
10161	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000,
10162	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001,
10163	} GLOBAL_STATUS_FLUSH_STATUS;
10164
10165	/*
10166	* STREAM_0_SYNCHRONIZATION enum
10167	*/
10168
10169	typedef enum STREAM_0_SYNCHRONIZATION {
10170	STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10171	STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10172	} STREAM_0_SYNCHRONIZATION;
10173
10174	/*
10175	* STREAM_1_SYNCHRONIZATION enum
10176	*/
10177
10178	typedef enum STREAM_1_SYNCHRONIZATION {
10179	STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10180	STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10181	} STREAM_1_SYNCHRONIZATION;
10182
10183	/*
10184	* STREAM_2_SYNCHRONIZATION enum
10185	*/
10186
10187	typedef enum STREAM_2_SYNCHRONIZATION {
10188	STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10189	STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10190	} STREAM_2_SYNCHRONIZATION;
10191
10192	/*
10193	* STREAM_3_SYNCHRONIZATION enum
10194	*/
10195
10196	typedef enum STREAM_3_SYNCHRONIZATION {
10197	STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10198	STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10199	} STREAM_3_SYNCHRONIZATION;
10200
10201	/*
10202	* STREAM_4_SYNCHRONIZATION enum
10203	*/
10204
10205	typedef enum STREAM_4_SYNCHRONIZATION {
10206	STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10207	STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10208	} STREAM_4_SYNCHRONIZATION;
10209
10210	/*
10211	* STREAM_5_SYNCHRONIZATION enum
10212	*/
10213
10214	typedef enum STREAM_5_SYNCHRONIZATION {
10215	STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10216	STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10217	} STREAM_5_SYNCHRONIZATION;
10218
10219	/*
10220	* STREAM_6_SYNCHRONIZATION enum
10221	*/
10222
10223	typedef enum STREAM_6_SYNCHRONIZATION {
10224	STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10225	STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10226	} STREAM_6_SYNCHRONIZATION;
10227
10228	/*
10229	* STREAM_7_SYNCHRONIZATION enum
10230	*/
10231
10232	typedef enum STREAM_7_SYNCHRONIZATION {
10233	STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10234	STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10235	} STREAM_7_SYNCHRONIZATION;
10236
10237	/*
10238	* STREAM_8_SYNCHRONIZATION enum
10239	*/
10240
10241	typedef enum STREAM_8_SYNCHRONIZATION {
10242	STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10243	STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10244	} STREAM_8_SYNCHRONIZATION;
10245
10246	/*
10247	* STREAM_9_SYNCHRONIZATION enum
10248	*/
10249
10250	typedef enum STREAM_9_SYNCHRONIZATION {
10251	STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10252	STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10253	} STREAM_9_SYNCHRONIZATION;
10254
10255	/*
10256	* STREAM_10_SYNCHRONIZATION enum
10257	*/
10258
10259	typedef enum STREAM_10_SYNCHRONIZATION {
10260	STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10261	STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10262	} STREAM_10_SYNCHRONIZATION;
10263
10264	/*
10265	* STREAM_11_SYNCHRONIZATION enum
10266	*/
10267
10268	typedef enum STREAM_11_SYNCHRONIZATION {
10269	STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10270	STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10271	} STREAM_11_SYNCHRONIZATION;
10272
10273	/*
10274	* STREAM_12_SYNCHRONIZATION enum
10275	*/
10276
10277	typedef enum STREAM_12_SYNCHRONIZATION {
10278	STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10279	STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10280	} STREAM_12_SYNCHRONIZATION;
10281
10282	/*
10283	* STREAM_13_SYNCHRONIZATION enum
10284	*/
10285
10286	typedef enum STREAM_13_SYNCHRONIZATION {
10287	STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10288	STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10289	} STREAM_13_SYNCHRONIZATION;
10290
10291	/*
10292	* STREAM_14_SYNCHRONIZATION enum
10293	*/
10294
10295	typedef enum STREAM_14_SYNCHRONIZATION {
10296	STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10297	STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10298	} STREAM_14_SYNCHRONIZATION;
10299
10300	/*
10301	* STREAM_15_SYNCHRONIZATION enum
10302	*/
10303
10304	typedef enum STREAM_15_SYNCHRONIZATION {
10305	STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10306	STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10307	} STREAM_15_SYNCHRONIZATION;
10308
10309	/*
10310	* CORB_READ_POINTER_RESET enum
10311	*/
10312
10313	typedef enum CORB_READ_POINTER_RESET {
10314	CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000,
10315	CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001,
10316	} CORB_READ_POINTER_RESET;
10317
10318	/*
10319	* AZ_CORB_SIZE enum
10320	*/
10321
10322	typedef enum AZ_CORB_SIZE {
10323	AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000,
10324	AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001,
10325	AZ_CORB_SIZE_256ENTRIES = 0x00000002,
10326	AZ_CORB_SIZE_RESERVED = 0x00000003,
10327	} AZ_CORB_SIZE;
10328
10329	/*
10330	* AZ_RIRB_WRITE_POINTER_RESET enum
10331	*/
10332
10333	typedef enum AZ_RIRB_WRITE_POINTER_RESET {
10334	AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000,
10335	AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001,
10336	} AZ_RIRB_WRITE_POINTER_RESET;
10337
10338	/*
10339	* RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
10340	*/
10341
10342	typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
10343	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
10344	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
10345	} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
10346
10347	/*
10348	* RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
10349	*/
10350
10351	typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
10352	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
10353	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
10354	} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
10355
10356	/*
10357	* AZ_RIRB_SIZE enum
10358	*/
10359
10360	typedef enum AZ_RIRB_SIZE {
10361	AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000,
10362	AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001,
10363	AZ_RIRB_SIZE_256ENTRIES = 0x00000002,
10364	AZ_RIRB_SIZE_UNDEFINED = 0x00000003,
10365	} AZ_RIRB_SIZE;
10366
10367	/*
10368	* IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
10369	*/
10370
10371	typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
10372	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000,
10373	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001,
10374	} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
10375
10376	/*
10377	* IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
10378	*/
10379
10380	typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
10381	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000,
10382	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001,
10383	} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
10384
10385	/*
10386	* DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
10387	*/
10388
10389	typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
10390	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000,
10391	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001,
10392	} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
10393
10394	/*******************************************************
10395	* AZENDPOINT Enums
10396	*******************************************************/
10397
10398	/*
10399	* AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10400	*/
10401
10402	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10403	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
10404	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
10405	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10406
10407	/*
10408	* AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10409	*/
10410
10411	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10412	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
10413	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
10414	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10415
10416	/*
10417	* AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10418	*/
10419
10420	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10421	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
10422	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
10423	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
10424	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
10425	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
10426	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10427
10428	/*
10429	* AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10430	*/
10431
10432	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10433	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
10434	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
10435	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
10436	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
10437	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
10438	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
10439	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
10440	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
10441	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10442
10443	/*
10444	* AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10445	*/
10446
10447	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10448	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
10449	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
10450	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
10451	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
10452	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
10453	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
10454	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10455
10456	/*
10457	* AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10458	*/
10459
10460	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10461	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
10462	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
10463	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
10464	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
10465	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
10466	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
10467	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
10468	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
10469	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
10470	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10471
10472	/*
10473	* AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10474	*/
10475
10476	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10477	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000,
10478	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001,
10479	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
10480
10481	/*
10482	* AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10483	*/
10484
10485	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10486	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000,
10487	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001,
10488	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
10489
10490	/*
10491	* AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10492	*/
10493
10494	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10495	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000,
10496	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001,
10497	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
10498
10499	/*
10500	* AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10501	*/
10502
10503	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10504	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000,
10505	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001,
10506	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
10507
10508	/*
10509	* AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10510	*/
10511
10512	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10513	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000,
10514	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001,
10515	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
10516
10517	/*
10518	* AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10519	*/
10520
10521	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10522	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000,
10523	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001,
10524	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
10525
10526	/*
10527	* AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10528	*/
10529
10530	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10531	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000,
10532	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001,
10533	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
10534
10535	/*
10536	* AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10537	*/
10538
10539	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10540	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
10541	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
10542	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10543
10544	/*
10545	* AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10546	*/
10547
10548	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10549	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000,
10550	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001,
10551	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
10552
10553	/*
10554	* AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10555	*/
10556
10557	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10558	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000,
10559	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001,
10560	} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
10561
10562	/*
10563	* AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10564	*/
10565
10566	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10567	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
10568	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
10569	} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10570
10571	/*
10572	* AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10573	*/
10574
10575	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10576	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000,
10577	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001,
10578	} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
10579
10580	/*
10581	* AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10582	*/
10583
10584	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10585	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000,
10586	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001,
10587	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
10588
10589	/*
10590	* AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10591	*/
10592
10593	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10594	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000,
10595	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001,
10596	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
10597
10598	/*
10599	* AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10600	*/
10601
10602	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10603	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000,
10604	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001,
10605	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
10606
10607	/*
10608	* AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10609	*/
10610
10611	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10612	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000,
10613	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001,
10614	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
10615
10616	/*
10617	* AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10618	*/
10619
10620	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10621	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
10622	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
10623	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10624
10625	/*
10626	* AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10627	*/
10628
10629	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10630	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
10631	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
10632	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10633
10634	/*
10635	* AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10636	*/
10637
10638	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10639	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
10640	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
10641	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10642
10643	/*
10644	* AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10645	*/
10646
10647	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10648	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
10649	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
10650	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10651
10652	/*
10653	* AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10654	*/
10655
10656	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10657	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
10658	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
10659	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10660
10661	/*******************************************************
10662	* AZF0CONTROLLER Enums
10663	*******************************************************/
10664
10665	/*
10666	* AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10667	*/
10668
10669	typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10670	AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000,
10671	AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001,
10672	} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
10673
10674	/*******************************************************
10675	* AZF0ROOT Enums
10676	*******************************************************/
10677
10678	/*
10679	* CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
10680	*/
10681
10682	typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
10683	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000,
10684	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001,
10685	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002,
10686	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003,
10687	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004,
10688	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005,
10689	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006,
10690	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007,
10691	} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
10692
10693	/*
10694	* CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
10695	*/
10696
10697	typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
10698	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000,
10699	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001,
10700	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002,
10701	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003,
10702	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004,
10703	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005,
10704	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006,
10705	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007,
10706	} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
10707
10708	/*******************************************************
10709	* AZINPUTENDPOINT Enums
10710	*******************************************************/
10711
10712	/*
10713	* AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10714	*/
10715
10716	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10717	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
10718	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
10719	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10720
10721	/*
10722	* AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10723	*/
10724
10725	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10726	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
10727	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
10728	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10729
10730	/*
10731	* AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10732	*/
10733
10734	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10735	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
10736	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
10737	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
10738	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
10739	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
10740	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10741
10742	/*
10743	* AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10744	*/
10745
10746	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10747	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
10748	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
10749	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
10750	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
10751	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
10752	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
10753	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
10754	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
10755	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10756
10757	/*
10758	* AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10759	*/
10760
10761	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10762	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
10763	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
10764	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
10765	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
10766	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
10767	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
10768	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10769
10770	/*
10771	* AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10772	*/
10773
10774	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10775	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
10776	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
10777	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
10778	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
10779	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
10780	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
10781	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
10782	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
10783	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
10784	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10785
10786	/*
10787	* AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10788	*/
10789
10790	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10791	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
10792	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
10793	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10794
10795	/*
10796	* AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
10797	*/
10798
10799	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
10800	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000,
10801	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001,
10802	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
10803
10804	/*
10805	* AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10806	*/
10807
10808	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10809	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
10810	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
10811	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10812
10813	/*
10814	* AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
10815	*/
10816
10817	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
10818	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000,
10819	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001,
10820	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
10821
10822	/*
10823	* AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10824	*/
10825
10826	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10827	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
10828	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
10829	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10830
10831	/*
10832	* AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
10833	*/
10834
10835	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
10836	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000,
10837	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001,
10838	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
10839
10840	/*
10841	* AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10842	*/
10843
10844	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10845	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
10846	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
10847	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10848
10849	/*
10850	* AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
10851	*/
10852
10853	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
10854	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000,
10855	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001,
10856	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
10857
10858	/*
10859	* AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10860	*/
10861
10862	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10863	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
10864	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
10865	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10866
10867	/*
10868	* AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
10869	*/
10870
10871	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
10872	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000,
10873	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001,
10874	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
10875
10876	/*
10877	* AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10878	*/
10879
10880	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10881	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
10882	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
10883	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10884
10885	/*******************************************************
10886	* AZROOT Enums
10887	*******************************************************/
10888
10889	/*
10890	* AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
10891	*/
10892
10893	typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
10894	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000,
10895	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001,
10896	} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
10897
10898	/*******************************************************
10899	* DCCG Enums
10900	*******************************************************/
10901
10902	/*
10903	* ENABLE enum
10904	*/
10905
10906	typedef enum ENABLE {
10907	DISABLE_THE_FEATURE = 0x00000000,
10908	ENABLE_THE_FEATURE = 0x00000001,
10909	} ENABLE;
10910
10911	/*
10912	* ENABLE_CLOCK enum
10913	*/
10914
10915	typedef enum ENABLE_CLOCK {
10916	DISABLE_THE_CLOCK = 0x00000000,
10917	ENABLE_THE_CLOCK = 0x00000001,
10918	} ENABLE_CLOCK;
10919
10920	/*
10921	* FORCE_VBI enum
10922	*/
10923
10924	typedef enum FORCE_VBI {
10925	FORCE_VBI_LOW = 0x00000000,
10926	FORCE_VBI_HIGH = 0x00000001,
10927	} FORCE_VBI;
10928
10929	/*
10930	* OVERRIDE_CGTT_SCLK enum
10931	*/
10932
10933	typedef enum OVERRIDE_CGTT_SCLK {
10934	OVERRIDE_CGTT_SCLK_NOOP = 0x00000000,
10935	SET_OVERRIDE_CGTT_SCLK = 0x00000001,
10936	} OVERRIDE_CGTT_SCLK;
10937
10938	/*
10939	* CLEAR_SMU_INTR enum
10940	*/
10941
10942	typedef enum CLEAR_SMU_INTR {
10943	SMU_INTR_STATUS_NOOP = 0x00000000,
10944	SMU_INTR_STATUS_CLEAR = 0x00000001,
10945	} CLEAR_SMU_INTR;
10946
10947	/*
10948	* STATIC_SCREEN_SMU_INTR enum
10949	*/
10950
10951	typedef enum STATIC_SCREEN_SMU_INTR {
10952	STATIC_SCREEN_SMU_INTR_NOOP = 0x00000000,
10953	SET_STATIC_SCREEN_SMU_INTR = 0x00000001,
10954	} STATIC_SCREEN_SMU_INTR;
10955
10956	/*
10957	* JITTER_REMOVE_DISABLE enum
10958	*/
10959
10960	typedef enum JITTER_REMOVE_DISABLE {
10961	ENABLE_JITTER_REMOVAL = 0x00000000,
10962	DISABLE_JITTER_REMOVAL = 0x00000001,
10963	} JITTER_REMOVE_DISABLE;
10964
10965	/*
10966	* DS_REF_SRC enum
10967	*/
10968
10969	typedef enum DS_REF_SRC {
10970	DS_REF_IS_XTALIN = 0x00000000,
10971	DS_REF_IS_EXT_GENLOCK = 0x00000001,
10972	DS_REF_IS_PCIE = 0x00000002,
10973	} DS_REF_SRC;
10974
10975	/*
10976	* DISABLE_CLOCK_GATING enum
10977	*/
10978
10979	typedef enum DISABLE_CLOCK_GATING {
10980	CLOCK_GATING_ENABLED = 0x00000000,
10981	CLOCK_GATING_DISABLED = 0x00000001,
10982	} DISABLE_CLOCK_GATING;
10983
10984	/*
10985	* DISABLE_CLOCK_GATING_IN_DCO enum
10986	*/
10987
10988	typedef enum DISABLE_CLOCK_GATING_IN_DCO {
10989	CLOCK_GATING_ENABLED_IN_DCO = 0x00000000,
10990	CLOCK_GATING_DISABLED_IN_DCO = 0x00000001,
10991	} DISABLE_CLOCK_GATING_IN_DCO;
10992
10993	/*
10994	* DCCG_DEEP_COLOR_CNTL enum
10995	*/
10996
10997	typedef enum DCCG_DEEP_COLOR_CNTL {
10998	DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000,
10999	DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001,
11000	DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002,
11001	DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003,
11002	} DCCG_DEEP_COLOR_CNTL;
11003
11004	/*
11005	* REFCLK_CLOCK_EN enum
11006	*/
11007
11008	typedef enum REFCLK_CLOCK_EN {
11009	REFCLK_CLOCK_EN_XTALIN_CLK = 0x00000000,
11010	REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 0x00000001,
11011	} REFCLK_CLOCK_EN;
11012
11013	/*
11014	* REFCLK_SRC_SEL enum
11015	*/
11016
11017	typedef enum REFCLK_SRC_SEL {
11018	REFCLK_SRC_SEL_PCIE_REFCLK = 0x00000000,
11019	REFCLK_SRC_SEL_CPL_REFCLK = 0x00000001,
11020	} REFCLK_SRC_SEL;
11021
11022	/*
11023	* DPREFCLK_SRC_SEL enum
11024	*/
11025
11026	typedef enum DPREFCLK_SRC_SEL {
11027	DPREFCLK_SRC_SEL_CK = 0x00000000,
11028	DPREFCLK_SRC_SEL_P0PLL = 0x00000001,
11029	DPREFCLK_SRC_SEL_P1PLL = 0x00000002,
11030	DPREFCLK_SRC_SEL_P2PLL = 0x00000003,
11031	DPREFCLK_SRC_SEL_P3PLL = 0x00000004,
11032	} DPREFCLK_SRC_SEL;
11033
11034	/*
11035	* XTAL_REF_SEL enum
11036	*/
11037
11038	typedef enum XTAL_REF_SEL {
11039	XTAL_REF_SEL_1X = 0x00000000,
11040	XTAL_REF_SEL_2X = 0x00000001,
11041	} XTAL_REF_SEL;
11042
11043	/*
11044	* XTAL_REF_CLOCK_SOURCE_SEL enum
11045	*/
11046
11047	typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
11048	XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000,
11049	XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 0x00000001,
11050	} XTAL_REF_CLOCK_SOURCE_SEL;
11051
11052	/*
11053	* MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11054	*/
11055
11056	typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11057	MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
11058	MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x00000001,
11059	} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
11060
11061	/*
11062	* ALLOW_SR_ON_TRANS_REQ enum
11063	*/
11064
11065	typedef enum ALLOW_SR_ON_TRANS_REQ {
11066	ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000,
11067	ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001,
11068	} ALLOW_SR_ON_TRANS_REQ;
11069
11070	/*
11071	* MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11072	*/
11073
11074	typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11075	MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
11076	MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x00000001,
11077	} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
11078
11079	/*
11080	* PIPE_PIXEL_RATE_SOURCE enum
11081	*/
11082
11083	typedef enum PIPE_PIXEL_RATE_SOURCE {
11084	PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000,
11085	PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001,
11086	PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002,
11087	} PIPE_PIXEL_RATE_SOURCE;
11088
11089	/*
11090	* PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
11091	*/
11092
11093	typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
11094	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000,
11095	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001,
11096	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002,
11097	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003,
11098	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x00000004,
11099	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x00000005,
11100	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 0x00000006,
11101	} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
11102
11103	/*
11104	* PIPE_PIXEL_RATE_PLL_SOURCE enum
11105	*/
11106
11107	typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
11108	PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000,
11109	PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001,
11110	} PIPE_PIXEL_RATE_PLL_SOURCE;
11111
11112	/*
11113	* DP_DTO_DS_DISABLE enum
11114	*/
11115
11116	typedef enum DP_DTO_DS_DISABLE {
11117	DP_DTO_DESPREAD_DISABLE = 0x00000000,
11118	DP_DTO_DESPREAD_ENABLE = 0x00000001,
11119	} DP_DTO_DS_DISABLE;
11120
11121	/*
11122	* CRTC_ADD_PIXEL enum
11123	*/
11124
11125	typedef enum CRTC_ADD_PIXEL {
11126	CRTC_ADD_PIXEL_NOOP = 0x00000000,
11127	CRTC_ADD_PIXEL_FORCE = 0x00000001,
11128	} CRTC_ADD_PIXEL;
11129
11130	/*
11131	* CRTC_DROP_PIXEL enum
11132	*/
11133
11134	typedef enum CRTC_DROP_PIXEL {
11135	CRTC_DROP_PIXEL_NOOP = 0x00000000,
11136	CRTC_DROP_PIXEL_FORCE = 0x00000001,
11137	} CRTC_DROP_PIXEL;
11138
11139	/*
11140	* SYMCLK_FE_FORCE_EN enum
11141	*/
11142
11143	typedef enum SYMCLK_FE_FORCE_EN {
11144	SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000,
11145	SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001,
11146	} SYMCLK_FE_FORCE_EN;
11147
11148	/*
11149	* SYMCLK_FE_FORCE_SRC enum
11150	*/
11151
11152	typedef enum SYMCLK_FE_FORCE_SRC {
11153	SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000,
11154	SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001,
11155	SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002,
11156	SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003,
11157	SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x00000004,
11158	SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x00000005,
11159	SYMCLK_FE_FORCE_SRC_UNIPHYG = 0x00000006,
11160	} SYMCLK_FE_FORCE_SRC;
11161
11162	/*
11163	* DPDBG_CLK_FORCE_EN enum
11164	*/
11165
11166	typedef enum DPDBG_CLK_FORCE_EN {
11167	DPDBG_CLK_FORCE_EN_DISABLE = 0x00000000,
11168	DPDBG_CLK_FORCE_EN_ENABLE = 0x00000001,
11169	} DPDBG_CLK_FORCE_EN;
11170
11171	/*
11172	* DVOACLK_COARSE_SKEW_CNTL enum
11173	*/
11174
11175	typedef enum DVOACLK_COARSE_SKEW_CNTL {
11176	DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
11177	DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
11178	DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
11179	DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
11180	DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004,
11181	DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005,
11182	DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006,
11183	DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007,
11184	DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008,
11185	DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009,
11186	DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a,
11187	DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b,
11188	DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c,
11189	DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d,
11190	DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e,
11191	DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f,
11192	DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010,
11193	DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011,
11194	DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012,
11195	DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013,
11196	DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014,
11197	DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015,
11198	DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016,
11199	DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017,
11200	DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018,
11201	DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019,
11202	DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a,
11203	DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b,
11204	DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c,
11205	DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d,
11206	DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e,
11207	} DVOACLK_COARSE_SKEW_CNTL;
11208
11209	/*
11210	* DVOACLK_FINE_SKEW_CNTL enum
11211	*/
11212
11213	typedef enum DVOACLK_FINE_SKEW_CNTL {
11214	DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
11215	DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
11216	DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
11217	DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
11218	DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004,
11219	DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005,
11220	DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006,
11221	DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007,
11222	} DVOACLK_FINE_SKEW_CNTL;
11223
11224	/*
11225	* DVOACLKD_IN_PHASE enum
11226	*/
11227
11228	typedef enum DVOACLKD_IN_PHASE {
11229	DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
11230	DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
11231	} DVOACLKD_IN_PHASE;
11232
11233	/*
11234	* DVOACLKC_IN_PHASE enum
11235	*/
11236
11237	typedef enum DVOACLKC_IN_PHASE {
11238	DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
11239	DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
11240	} DVOACLKC_IN_PHASE;
11241
11242	/*
11243	* DVOACLKC_MVP_IN_PHASE enum
11244	*/
11245
11246	typedef enum DVOACLKC_MVP_IN_PHASE {
11247	DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
11248	DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
11249	} DVOACLKC_MVP_IN_PHASE;
11250
11251	/*
11252	* DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
11253	*/
11254
11255	typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
11256	DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000,
11257	DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001,
11258	} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
11259
11260	/*
11261	* MVP_CLK_SRC_SEL enum
11262	*/
11263
11264	typedef enum MVP_CLK_SRC_SEL {
11265	MVP_CLK_SRC_SEL_RSRV = 0x00000000,
11266	MVP_CLK_SRC_SEL_IO_1 = 0x00000001,
11267	MVP_CLK_SRC_SEL_IO_2 = 0x00000002,
11268	MVP_CLK_SRC_SEL_REFCLK = 0x00000003,
11269	} MVP_CLK_SRC_SEL;
11270
11271	/*
11272	* DCCG_AUDIO_DTO0_SOURCE_SEL enum
11273	*/
11274
11275	typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
11276	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0x00000000,
11277	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 0x00000001,
11278	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 0x00000002,
11279	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 0x00000003,
11280	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 0x00000004,
11281	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 0x00000005,
11282	DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000006,
11283	} DCCG_AUDIO_DTO0_SOURCE_SEL;
11284
11285	/*
11286	* DCCG_AUDIO_DTO_SEL enum
11287	*/
11288
11289	typedef enum DCCG_AUDIO_DTO_SEL {
11290	DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000,
11291	DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001,
11292	DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002,
11293	} DCCG_AUDIO_DTO_SEL;
11294
11295	/*
11296	* DCCG_AUDIO_DTO2_SOURCE_SEL enum
11297	*/
11298
11299	typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
11300	DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000,
11301	DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x00000001,
11302	} DCCG_AUDIO_DTO2_SOURCE_SEL;
11303
11304	/*
11305	* DCCG_AUDIO_DTO_USE_512FBR_DTO enum
11306	*/
11307
11308	typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
11309	DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000,
11310	DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001,
11311	} DCCG_AUDIO_DTO_USE_512FBR_DTO;
11312
11313	/*
11314	* DCCG_DBG_EN enum
11315	*/
11316
11317	typedef enum DCCG_DBG_EN {
11318	DCCG_DBG_EN_DISABLE = 0x00000000,
11319	DCCG_DBG_EN_ENABLE = 0x00000001,
11320	} DCCG_DBG_EN;
11321
11322	/*
11323	* DCCG_DBG_BLOCK_SEL enum
11324	*/
11325
11326	typedef enum DCCG_DBG_BLOCK_SEL {
11327	DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000,
11328	DCCG_DBG_BLOCK_SEL_PMON = 0x00000001,
11329	DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002,
11330	} DCCG_DBG_BLOCK_SEL;
11331
11332	/*
11333	* DISPCLK_FREQ_RAMP_DONE enum
11334	*/
11335
11336	typedef enum DISPCLK_FREQ_RAMP_DONE {
11337	DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000,
11338	DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001,
11339	} DISPCLK_FREQ_RAMP_DONE;
11340
11341	/*
11342	* DCCG_FIFO_ERRDET_RESET enum
11343	*/
11344
11345	typedef enum DCCG_FIFO_ERRDET_RESET {
11346	DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000,
11347	DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001,
11348	} DCCG_FIFO_ERRDET_RESET;
11349
11350	/*
11351	* DCCG_FIFO_ERRDET_STATE enum
11352	*/
11353
11354	typedef enum DCCG_FIFO_ERRDET_STATE {
11355	DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000000,
11356	DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000001,
11357	} DCCG_FIFO_ERRDET_STATE;
11358
11359	/*
11360	* DCCG_FIFO_ERRDET_OVR_EN enum
11361	*/
11362
11363	typedef enum DCCG_FIFO_ERRDET_OVR_EN {
11364	DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000,
11365	DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001,
11366	} DCCG_FIFO_ERRDET_OVR_EN;
11367
11368	/*
11369	* DISPCLK_CHG_FWD_CORR_DISABLE enum
11370	*/
11371
11372	typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
11373	DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000,
11374	DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001,
11375	} DISPCLK_CHG_FWD_CORR_DISABLE;
11376
11377	/*
11378	* DC_MEM_GLOBAL_PWR_REQ_DIS enum
11379	*/
11380
11381	typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
11382	DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000,
11383	DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001,
11384	} DC_MEM_GLOBAL_PWR_REQ_DIS;
11385
11386	/*
11387	* DCCG_PERF_RUN enum
11388	*/
11389
11390	typedef enum DCCG_PERF_RUN {
11391	DCCG_PERF_RUN_NOOP = 0x00000000,
11392	DCCG_PERF_RUN_START = 0x00000001,
11393	} DCCG_PERF_RUN;
11394
11395	/*
11396	* DCCG_PERF_MODE_VSYNC enum
11397	*/
11398
11399	typedef enum DCCG_PERF_MODE_VSYNC {
11400	DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000,
11401	DCCG_PERF_MODE_VSYNC_START = 0x00000001,
11402	} DCCG_PERF_MODE_VSYNC;
11403
11404	/*
11405	* DCCG_PERF_MODE_HSYNC enum
11406	*/
11407
11408	typedef enum DCCG_PERF_MODE_HSYNC {
11409	DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000,
11410	DCCG_PERF_MODE_HSYNC_START = 0x00000001,
11411	} DCCG_PERF_MODE_HSYNC;
11412
11413	/*
11414	* DCCG_PERF_CRTC_SELECT enum
11415	*/
11416
11417	typedef enum DCCG_PERF_CRTC_SELECT {
11418	DCCG_PERF_SEL_CRTC0 = 0x00000000,
11419	DCCG_PERF_SEL_CRTC1 = 0x00000001,
11420	DCCG_PERF_SEL_CRTC2 = 0x00000002,
11421	DCCG_PERF_SEL_CRTC3 = 0x00000003,
11422	DCCG_PERF_SEL_CRTC4 = 0x00000004,
11423	DCCG_PERF_SEL_CRTC5 = 0x00000005,
11424	} DCCG_PERF_CRTC_SELECT;
11425
11426	/*
11427	* CLOCK_BRANCH_SOFT_RESET enum
11428	*/
11429
11430	typedef enum CLOCK_BRANCH_SOFT_RESET {
11431	CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000,
11432	CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001,
11433	} CLOCK_BRANCH_SOFT_RESET;
11434
11435	/*
11436	* PLL_CFG_IF_SOFT_RESET enum
11437	*/
11438
11439	typedef enum PLL_CFG_IF_SOFT_RESET {
11440	PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000,
11441	PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001,
11442	} PLL_CFG_IF_SOFT_RESET;
11443
11444	/*
11445	* DVO_ENABLE_RST enum
11446	*/
11447
11448	typedef enum DVO_ENABLE_RST {
11449	DVO_ENABLE_RST_DISABLE = 0x00000000,
11450	DVO_ENABLE_RST_ENABLE = 0x00000001,
11451	} DVO_ENABLE_RST;
11452
11453	/*******************************************************
11454	* DCI Enums
11455	*******************************************************/
11456
11457	/*
11458	* LptNumPipes enum
11459	*/
11460
11461	typedef enum LptNumPipes {
11462	LPT_NUM_PIPES_1CH = 0x00000000,
11463	LPT_NUM_PIPES_2CH = 0x00000001,
11464	LPT_NUM_PIPES_4CH = 0x00000002,
11465	LPT_NUM_PIPES_8CH = 0x00000003,
11466	} LptNumPipes;
11467
11468	/*
11469	* LptNumBanks enum
11470	*/
11471
11472	typedef enum LptNumBanks {
11473	LPT_NUM_BANKS_2BANK = 0x00000000,
11474	LPT_NUM_BANKS_4BANK = 0x00000001,
11475	LPT_NUM_BANKS_8BANK = 0x00000002,
11476	LPT_NUM_BANKS_16BANK = 0x00000003,
11477	LPT_NUM_BANKS_32BANK = 0x00000004,
11478	} LptNumBanks;
11479
11480	/*
11481	* OVERRIDE_CGTT_DCEFCLK enum
11482	*/
11483
11484	typedef enum OVERRIDE_CGTT_DCEFCLK {
11485	OVERRIDE_CGTT_DCEFCLK_NOOP = 0x00000000,
11486	SET_OVERRIDE_CGTT_DCEFCLK = 0x00000001,
11487	} OVERRIDE_CGTT_DCEFCLK;
11488
11489	/*******************************************************
11490	* DCIO Enums
11491	*******************************************************/
11492
11493	/*
11494	* DCIO_DC_GENERICA_SEL enum
11495	*/
11496
11497	typedef enum DCIO_DC_GENERICA_SEL {
11498	DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x00000000,
11499	DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001,
11500	DCIO_GENERICA_SEL_DACA_PIXCLK = 0x00000002,
11501	DCIO_GENERICA_SEL_DACB_PIXCLK = 0x00000003,
11502	DCIO_GENERICA_SEL_DVOA_CTL3 = 0x00000004,
11503	DCIO_GENERICA_SEL_P1_PLLCLK = 0x00000005,
11504	DCIO_GENERICA_SEL_P2_PLLCLK = 0x00000006,
11505	DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x00000007,
11506	DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x00000008,
11507	DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x00000009,
11508	DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a,
11509	DCIO_GENERICA_SEL_SYNCEN = 0x0000000b,
11510	DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 0x0000000c,
11511	DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 0x0000000d,
11512	DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e,
11513	DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f,
11514	DCIO_GENERICA_SEL_GENERICA_DPRX = 0x00000010,
11515	DCIO_GENERICA_SEL_GENERICB_DPRX = 0x00000011,
11516	} DCIO_DC_GENERICA_SEL;
11517
11518	/*
11519	* DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
11520	*/
11521
11522	typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
11523	DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000,
11524	DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001,
11525	DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002,
11526	DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003,
11527	DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004,
11528	DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005,
11529	DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006,
11530	DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x00000007,
11531	DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x00000008,
11532	} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
11533
11534	/*
11535	* DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
11536	*/
11537
11538	typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
11539	DCIO_UNIPHYA_FBDIV_CLK = 0x00000000,
11540	DCIO_UNIPHYB_FBDIV_CLK = 0x00000001,
11541	DCIO_UNIPHYC_FBDIV_CLK = 0x00000002,
11542	DCIO_UNIPHYD_FBDIV_CLK = 0x00000003,
11543	DCIO_UNIPHYE_FBDIV_CLK = 0x00000004,
11544	DCIO_UNIPHYF_FBDIV_CLK = 0x00000005,
11545	DCIO_UNIPHYG_FBDIV_CLK = 0x00000006,
11546	DCIO_UNIPHYLPA_FBDIV_CLK = 0x00000007,
11547	DCIO_UNIPHYLPB_FBDIV_CLK = 0x00000008,
11548	} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
11549
11550	/*
11551	* DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
11552	*/
11553
11554	typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
11555	DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000,
11556	DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001,
11557	DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002,
11558	DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003,
11559	DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004,
11560	DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005,
11561	DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006,
11562	DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x00000007,
11563	DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x00000008,
11564	} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
11565
11566	/*
11567	* DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
11568	*/
11569
11570	typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
11571	DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000,
11572	DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001,
11573	DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002,
11574	DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003,
11575	DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004,
11576	DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005,
11577	DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006,
11578	DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x00000007,
11579	DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x00000008,
11580	} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
11581
11582	/*
11583	* DCIO_DC_GENERICB_SEL enum
11584	*/
11585
11586	typedef enum DCIO_DC_GENERICB_SEL {
11587	DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x00000000,
11588	DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001,
11589	DCIO_GENERICB_SEL_DACA_PIXCLK = 0x00000002,
11590	DCIO_GENERICB_SEL_DACB_PIXCLK = 0x00000003,
11591	DCIO_GENERICB_SEL_DVOA_CTL3 = 0x00000004,
11592	DCIO_GENERICB_SEL_P1_PLLCLK = 0x00000005,
11593	DCIO_GENERICB_SEL_P2_PLLCLK = 0x00000006,
11594	DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x00000007,
11595	DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x00000008,
11596	DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x00000009,
11597	DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a,
11598	DCIO_GENERICB_SEL_SYNCEN = 0x0000000b,
11599	DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 0x0000000c,
11600	DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 0x0000000d,
11601	DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e,
11602	DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f,
11603	} DCIO_DC_GENERICB_SEL;
11604
11605	/*
11606	* DCIO_DC_PAD_EXTERN_SIG_SEL enum
11607	*/
11608
11609	typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
11610	DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x00000000,
11611	DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x00000001,
11612	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x00000002,
11613	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x00000003,
11614	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x00000004,
11615	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x00000005,
11616	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x00000006,
11617	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x00000007,
11618	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x00000008,
11619	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x00000009,
11620	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0x0000000a,
11621	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0x0000000b,
11622	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0x0000000c,
11623	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0x0000000d,
11624	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0x0000000e,
11625	DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0x0000000f,
11626	} DCIO_DC_PAD_EXTERN_SIG_SEL;
11627
11628	/*
11629	* DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS enum
11630	*/
11631
11632	typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
11633	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x00000000,
11634	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x00000001,
11635	DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x00000002,
11636	DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x00000003,
11637	} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
11638
11639	/*
11640	* DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
11641	*/
11642
11643	typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
11644	DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x00000000,
11645	DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x00000001,
11646	DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x00000002,
11647	DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x00000003,
11648	} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
11649
11650	/*
11651	* DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
11652	*/
11653
11654	typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
11655	DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000,
11656	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001,
11657	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002,
11658	DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003,
11659	} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
11660
11661	/*
11662	* DCIO_DC_GPIO_VIP_DEBUG enum
11663	*/
11664
11665	typedef enum DCIO_DC_GPIO_VIP_DEBUG {
11666	DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x00000000,
11667	DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x00000001,
11668	} DCIO_DC_GPIO_VIP_DEBUG;
11669
11670	/*
11671	* DCIO_DC_GPIO_MACRO_DEBUG enum
11672	*/
11673
11674	typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
11675	DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x00000000,
11676	DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x00000001,
11677	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x00000002,
11678	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x00000003,
11679	} DCIO_DC_GPIO_MACRO_DEBUG;
11680
11681	/*
11682	* DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL enum
11683	*/
11684
11685	typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
11686	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x00000000,
11687	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x00000001,
11688	} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
11689
11690	/*
11691	* DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN enum
11692	*/
11693
11694	typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
11695	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x00000000,
11696	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x00000001,
11697	} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
11698
11699	/*
11700	* DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
11701	*/
11702
11703	typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
11704	DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x00000000,
11705	DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x00000001,
11706	} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
11707
11708	/*
11709	* DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
11710	*/
11711
11712	typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
11713	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000,
11714	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001,
11715	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002,
11716	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003,
11717	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004,
11718	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005,
11719	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006,
11720	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007,
11721	} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
11722
11723	/*
11724	* DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
11725	*/
11726
11727	typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
11728	DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000,
11729	DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001,
11730	} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
11731
11732	/*
11733	* DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
11734	*/
11735
11736	typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
11737	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000,
11738	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001,
11739	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002,
11740	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003,
11741	} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
11742
11743	/*
11744	* DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
11745	*/
11746
11747	typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
11748	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000,
11749	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001,
11750	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002,
11751	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003,
11752	} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
11753
11754	/*
11755	* DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
11756	*/
11757
11758	typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
11759	DCIO_VIP_MUX_EN_DVO = 0x00000000,
11760	DCIO_VIP_MUX_EN_VIP = 0x00000001,
11761	} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
11762
11763	/*
11764	* DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
11765	*/
11766
11767	typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
11768	DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x00000000,
11769	DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001,
11770	} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
11771
11772	/*
11773	* DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
11774	*/
11775
11776	typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
11777	DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x00000000,
11778	DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001,
11779	} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
11780
11781	/*
11782	* DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
11783	*/
11784
11785	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
11786	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0x00000000,
11787	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 0x00000001,
11788	} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
11789
11790	/*
11791	* DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
11792	*/
11793
11794	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
11795	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000,
11796	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001,
11797	} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
11798
11799	/*
11800	* DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
11801	*/
11802
11803	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
11804	DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x00000000,
11805	DCIO_LVTMA_SYNCEN_POL_INVERT = 0x00000001,
11806	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
11807
11808	/*
11809	* DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
11810	*/
11811
11812	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
11813	DCIO_LVTMA_DIGON_OFF = 0x00000000,
11814	DCIO_LVTMA_DIGON_ON = 0x00000001,
11815	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
11816
11817	/*
11818	* DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
11819	*/
11820
11821	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
11822	DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x00000000,
11823	DCIO_LVTMA_DIGON_POL_INVERT = 0x00000001,
11824	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
11825
11826	/*
11827	* DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
11828	*/
11829
11830	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
11831	DCIO_LVTMA_BLON_OFF = 0x00000000,
11832	DCIO_LVTMA_BLON_ON = 0x00000001,
11833	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
11834
11835	/*
11836	* DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
11837	*/
11838
11839	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
11840	DCIO_LVTMA_BLON_POL_NON_INVERT = 0x00000000,
11841	DCIO_LVTMA_BLON_POL_INVERT = 0x00000001,
11842	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
11843
11844	/*
11845	* DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
11846	*/
11847
11848	typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
11849	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x00000000,
11850	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001,
11851	} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
11852
11853	/*
11854	* DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
11855	*/
11856
11857	typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
11858	DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x00000000,
11859	DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x00000001,
11860	} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
11861
11862	/*
11863	* DCIO_BL_PWM_CNTL_BL_PWM_EN enum
11864	*/
11865
11866	typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
11867	DCIO_BL_PWM_DISABLE = 0x00000000,
11868	DCIO_BL_PWM_ENABLE = 0x00000001,
11869	} DCIO_BL_PWM_CNTL_BL_PWM_EN;
11870
11871	/*
11872	* DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
11873	*/
11874
11875	typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
11876	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000,
11877	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001,
11878	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002,
11879	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003,
11880	} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
11881
11882	/*
11883	* DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
11884	*/
11885
11886	typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
11887	DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000,
11888	DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001,
11889	} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
11890
11891	/*
11892	* DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
11893	*/
11894
11895	typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
11896	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x00000000,
11897	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x00000001,
11898	} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
11899
11900	/*
11901	* DCIO_BL_PWM_GRP1_REG_LOCK enum
11902	*/
11903
11904	typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
11905	DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000,
11906	DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001,
11907	} DCIO_BL_PWM_GRP1_REG_LOCK;
11908
11909	/*
11910	* DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
11911	*/
11912
11913	typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
11914	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000,
11915	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001,
11916	} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
11917
11918	/*
11919	* DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
11920	*/
11921
11922	typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
11923	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000,
11924	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001,
11925	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002,
11926	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003,
11927	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004,
11928	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005,
11929	} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
11930
11931	/*
11932	* DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
11933	*/
11934
11935	typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
11936	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000,
11937	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001,
11938	} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
11939
11940	/*
11941	* DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
11942	*/
11943
11944	typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
11945	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000,
11946	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001,
11947	} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
11948
11949	/*
11950	* DCIO_GSL_SEL enum
11951	*/
11952
11953	typedef enum DCIO_GSL_SEL {
11954	DCIO_GSL_SEL_GROUP_0 = 0x00000000,
11955	DCIO_GSL_SEL_GROUP_1 = 0x00000001,
11956	DCIO_GSL_SEL_GROUP_2 = 0x00000002,
11957	} DCIO_GSL_SEL;
11958
11959	/*
11960	* DCIO_GENLK_CLK_GSL_MASK enum
11961	*/
11962
11963	typedef enum DCIO_GENLK_CLK_GSL_MASK {
11964	DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000,
11965	DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001,
11966	DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002,
11967	} DCIO_GENLK_CLK_GSL_MASK;
11968
11969	/*
11970	* DCIO_GENLK_VSYNC_GSL_MASK enum
11971	*/
11972
11973	typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
11974	DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000,
11975	DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001,
11976	DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002,
11977	} DCIO_GENLK_VSYNC_GSL_MASK;
11978
11979	/*
11980	* DCIO_SWAPLOCK_A_GSL_MASK enum
11981	*/
11982
11983	typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
11984	DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000,
11985	DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001,
11986	DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002,
11987	} DCIO_SWAPLOCK_A_GSL_MASK;
11988
11989	/*
11990	* DCIO_SWAPLOCK_B_GSL_MASK enum
11991	*/
11992
11993	typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
11994	DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000,
11995	DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001,
11996	DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002,
11997	} DCIO_SWAPLOCK_B_GSL_MASK;
11998
11999	/*
12000	* DCIO_GSL_VSYNC_SEL enum
12001	*/
12002
12003	typedef enum DCIO_GSL_VSYNC_SEL {
12004	DCIO_GSL_VSYNC_SEL_PIPE0 = 0x00000000,
12005	DCIO_GSL_VSYNC_SEL_PIPE1 = 0x00000001,
12006	DCIO_GSL_VSYNC_SEL_PIPE2 = 0x00000002,
12007	DCIO_GSL_VSYNC_SEL_PIPE3 = 0x00000003,
12008	DCIO_GSL_VSYNC_SEL_PIPE4 = 0x00000004,
12009	DCIO_GSL_VSYNC_SEL_PIPE5 = 0x00000005,
12010	} DCIO_GSL_VSYNC_SEL;
12011
12012	/*
12013	* DCIO_GSL0_TIMING_SYNC_SEL enum
12014	*/
12015
12016	typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
12017	DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x00000000,
12018	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001,
12019	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002,
12020	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003,
12021	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004,
12022	} DCIO_GSL0_TIMING_SYNC_SEL;
12023
12024	/*
12025	* DCIO_GSL0_GLOBAL_UNLOCK_SEL enum
12026	*/
12027
12028	typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
12029	DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000,
12030	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
12031	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002,
12032	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003,
12033	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004,
12034	} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
12035
12036	/*
12037	* DCIO_GSL1_TIMING_SYNC_SEL enum
12038	*/
12039
12040	typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
12041	DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x00000000,
12042	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001,
12043	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002,
12044	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003,
12045	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004,
12046	} DCIO_GSL1_TIMING_SYNC_SEL;
12047
12048	/*
12049	* DCIO_GSL1_GLOBAL_UNLOCK_SEL enum
12050	*/
12051
12052	typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
12053	DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000,
12054	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
12055	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002,
12056	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003,
12057	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004,
12058	} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
12059
12060	/*
12061	* DCIO_GSL2_TIMING_SYNC_SEL enum
12062	*/
12063
12064	typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
12065	DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x00000000,
12066	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001,
12067	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002,
12068	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003,
12069	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004,
12070	} DCIO_GSL2_TIMING_SYNC_SEL;
12071
12072	/*
12073	* DCIO_GSL2_GLOBAL_UNLOCK_SEL enum
12074	*/
12075
12076	typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
12077	DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000,
12078	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
12079	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002,
12080	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003,
12081	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004,
12082	} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
12083
12084	/*
12085	* DCIO_DC_GPU_TIMER_START_POSITION enum
12086	*/
12087
12088	typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
12089	DCIO_GPU_TIMER_START_0_END_27 = 0x00000000,
12090	DCIO_GPU_TIMER_START_1_END_28 = 0x00000001,
12091	DCIO_GPU_TIMER_START_2_END_29 = 0x00000002,
12092	DCIO_GPU_TIMER_START_3_END_30 = 0x00000003,
12093	DCIO_GPU_TIMER_START_4_END_31 = 0x00000004,
12094	DCIO_GPU_TIMER_START_6_END_33 = 0x00000005,
12095	DCIO_GPU_TIMER_START_8_END_35 = 0x00000006,
12096	DCIO_GPU_TIMER_START_10_END_37 = 0x00000007,
12097	} DCIO_DC_GPU_TIMER_START_POSITION;
12098
12099	/*
12100	* DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
12101	*/
12102
12103	typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
12104	DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000,
12105	DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001,
12106	DCIO_TEST_CLK_SEL_SCLK = 0x00000002,
12107	} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
12108
12109	/*
12110	* DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
12111	*/
12112
12113	typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
12114	DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000,
12115	DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001,
12116	} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
12117
12118	/*
12119	* DCIO_DCO_DCFE_EXT_VSYNC_MUX enum
12120	*/
12121
12122	typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
12123	DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000,
12124	DCIO_EXT_VSYNC_MUX_CRTC0 = 0x00000001,
12125	DCIO_EXT_VSYNC_MUX_CRTC1 = 0x00000002,
12126	DCIO_EXT_VSYNC_MUX_CRTC2 = 0x00000003,
12127	DCIO_EXT_VSYNC_MUX_CRTC3 = 0x00000004,
12128	DCIO_EXT_VSYNC_MUX_CRTC4 = 0x00000005,
12129	DCIO_EXT_VSYNC_MUX_CRTC5 = 0x00000006,
12130	DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007,
12131	} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
12132
12133	/*
12134	* DCIO_DCO_EXT_VSYNC_MASK enum
12135	*/
12136
12137	typedef enum DCIO_DCO_EXT_VSYNC_MASK {
12138	DCIO_EXT_VSYNC_MASK_NONE = 0x00000000,
12139	DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001,
12140	DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002,
12141	DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003,
12142	DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004,
12143	DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005,
12144	DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006,
12145	DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007,
12146	} DCIO_DCO_EXT_VSYNC_MASK;
12147
12148	/*
12149	* DCIO_DSYNC_SOFT_RESET enum
12150	*/
12151
12152	typedef enum DCIO_DSYNC_SOFT_RESET {
12153	DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x00000000,
12154	DCIO_DSYNC_SOFT_RESET_ASSERT = 0x00000001,
12155	} DCIO_DSYNC_SOFT_RESET;
12156
12157	/*
12158	* DCIO_DACA_SOFT_RESET enum
12159	*/
12160
12161	typedef enum DCIO_DACA_SOFT_RESET {
12162	DCIO_DACA_SOFT_RESET_DEASSERT = 0x00000000,
12163	DCIO_DACA_SOFT_RESET_ASSERT = 0x00000001,
12164	} DCIO_DACA_SOFT_RESET;
12165
12166	/*
12167	* DCIO_DCRXPHY_SOFT_RESET enum
12168	*/
12169
12170	typedef enum DCIO_DCRXPHY_SOFT_RESET {
12171	DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000,
12172	DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001,
12173	} DCIO_DCRXPHY_SOFT_RESET;
12174
12175	/*
12176	* DCIO_DPHY_LANE_SEL enum
12177	*/
12178
12179	typedef enum DCIO_DPHY_LANE_SEL {
12180	DCIO_DPHY_LANE_SEL_LANE0 = 0x00000000,
12181	DCIO_DPHY_LANE_SEL_LANE1 = 0x00000001,
12182	DCIO_DPHY_LANE_SEL_LANE2 = 0x00000002,
12183	DCIO_DPHY_LANE_SEL_LANE3 = 0x00000003,
12184	} DCIO_DPHY_LANE_SEL;
12185
12186	/*
12187	* DCIO_DPCS_INTERRUPT_TYPE enum
12188	*/
12189
12190	typedef enum DCIO_DPCS_INTERRUPT_TYPE {
12191	DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
12192	DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
12193	} DCIO_DPCS_INTERRUPT_TYPE;
12194
12195	/*
12196	* DCIO_DPCS_INTERRUPT_MASK enum
12197	*/
12198
12199	typedef enum DCIO_DPCS_INTERRUPT_MASK {
12200	DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000,
12201	DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001,
12202	} DCIO_DPCS_INTERRUPT_MASK;
12203
12204	/*
12205	* DCIO_DC_GPU_TIMER_READ_SELECT enum
12206	*/
12207
12208	typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
12209	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000,
12210	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001,
12211	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x00000002,
12212	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x00000003,
12213	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x00000004,
12214	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x00000005,
12215	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x00000006,
12216	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x00000007,
12217	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x00000008,
12218	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x00000009,
12219	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0x0000000a,
12220	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0x0000000b,
12221	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x0000000c,
12222	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x0000000d,
12223	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0x0000000e,
12224	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0x0000000f,
12225	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x00000010,
12226	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x00000011,
12227	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x00000012,
12228	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x00000013,
12229	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x00000014,
12230	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x00000015,
12231	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x00000016,
12232	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x00000017,
12233	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000018,
12234	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000019,
12235	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x0000001a,
12236	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x0000001b,
12237	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x0000001c,
12238	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x0000001d,
12239	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x0000001e,
12240	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x0000001f,
12241	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x00000020,
12242	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x00000021,
12243	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x00000022,
12244	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x00000023,
12245	} DCIO_DC_GPU_TIMER_READ_SELECT;
12246
12247	/*
12248	* DCIO_IMPCAL_STEP_DELAY enum
12249	*/
12250
12251	typedef enum DCIO_IMPCAL_STEP_DELAY {
12252	DCIO_IMPCAL_STEP_DELAY_1us = 0x00000000,
12253	DCIO_IMPCAL_STEP_DELAY_2us = 0x00000001,
12254	DCIO_IMPCAL_STEP_DELAY_3us = 0x00000002,
12255	DCIO_IMPCAL_STEP_DELAY_4us = 0x00000003,
12256	DCIO_IMPCAL_STEP_DELAY_5us = 0x00000004,
12257	DCIO_IMPCAL_STEP_DELAY_6us = 0x00000005,
12258	DCIO_IMPCAL_STEP_DELAY_7us = 0x00000006,
12259	DCIO_IMPCAL_STEP_DELAY_8us = 0x00000007,
12260	DCIO_IMPCAL_STEP_DELAY_9us = 0x00000008,
12261	DCIO_IMPCAL_STEP_DELAY_10us = 0x00000009,
12262	DCIO_IMPCAL_STEP_DELAY_11us = 0x0000000a,
12263	DCIO_IMPCAL_STEP_DELAY_12us = 0x0000000b,
12264	DCIO_IMPCAL_STEP_DELAY_13us = 0x0000000c,
12265	DCIO_IMPCAL_STEP_DELAY_14us = 0x0000000d,
12266	DCIO_IMPCAL_STEP_DELAY_15us = 0x0000000e,
12267	DCIO_IMPCAL_STEP_DELAY_16us = 0x0000000f,
12268	} DCIO_IMPCAL_STEP_DELAY;
12269
12270	/*
12271	* DCIO_UNIPHY_IMPCAL_SEL enum
12272	*/
12273
12274	typedef enum DCIO_UNIPHY_IMPCAL_SEL {
12275	DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000,
12276	DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001,
12277	} DCIO_UNIPHY_IMPCAL_SEL;
12278
12279	/*
12280	* DCIO_DBG_ASYNC_BLOCK_SEL enum
12281	*/
12282
12283	typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
12284	DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0x00000000,
12285	DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 0x00000001,
12286	DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 0x00000002,
12287	DCIO_DBG_ASYNC_BLOCK_SEL_DCO = 0x00000003,
12288	} DCIO_DBG_ASYNC_BLOCK_SEL;
12289
12290	/*
12291	* DCIO_DBG_ASYNC_4BIT_SEL enum
12292	*/
12293
12294	typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
12295	DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0x00000000,
12296	DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 0x00000001,
12297	DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 0x00000002,
12298	DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 0x00000003,
12299	DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 0x00000004,
12300	DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 0x00000005,
12301	DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 0x00000006,
12302	DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 0x00000007,
12303	} DCIO_DBG_ASYNC_4BIT_SEL;
12304
12305	/*******************************************************
12306	* AOUT Enums
12307	*******************************************************/
12308
12309	/*
12310	* AOUT_EN enum
12311	*/
12312
12313	typedef enum AOUT_EN {
12314	AOUT_DISABLE = 0x00000000,
12315	AOUT_ENABLE = 0x00000001,
12316	} AOUT_EN;
12317
12318	/*
12319	* AOUT_FIFO_START_ADDR enum
12320	*/
12321
12322	typedef enum AOUT_FIFO_START_ADDR {
12323	AOUT_FIFO_START_ADDR_2 = 0x00000000,
12324	AOUT_FIFO_START_ADDR_3 = 0x00000001,
12325	} AOUT_FIFO_START_ADDR;
12326
12327	/*
12328	* AOUT_CRC_TEST_EN enum
12329	*/
12330
12331	typedef enum AOUT_CRC_TEST_EN {
12332	AOUT_CRC_DISABLE = 0x00000000,
12333	AOUT_CRC_ENABLE = 0x00000001,
12334	} AOUT_CRC_TEST_EN;
12335
12336	/*
12337	* AOUT_CRC_SOFT_RESET enum
12338	*/
12339
12340	typedef enum AOUT_CRC_SOFT_RESET {
12341	AOUT_CRC_NO_RESET = 0x00000000,
12342	AOUT_CRC_RESET = 0x00000001,
12343	} AOUT_CRC_SOFT_RESET;
12344
12345	/*
12346	* AOUT_CRC_CONT_EN enum
12347	*/
12348
12349	typedef enum AOUT_CRC_CONT_EN {
12350	AOUT_CRC_ONE_SHOT = 0x00000000,
12351	AOUT_CRC_CONT = 0x00000001,
12352	} AOUT_CRC_CONT_EN;
12353
12354	/*
12355	* I2S_WORD_SIZE enum
12356	*/
12357
12358	typedef enum I2S_WORD_SIZE {
12359	I2S_WORD_SIZE_32 = 0x00000000,
12360	I2S_WORD_SIZE_16 = 0x00000001,
12361	} I2S_WORD_SIZE;
12362
12363	/*
12364	* I2S_SAMPLE_ALIGNMENT enum
12365	*/
12366
12367	typedef enum I2S_SAMPLE_ALIGNMENT {
12368	I2S_SAMPLE_LEFT_ALIGNED = 0x00000000,
12369	I2S_SAMPLE_RIGHT_ALIGNED = 0x00000001,
12370	} I2S_SAMPLE_ALIGNMENT;
12371
12372	/*
12373	* I2S_SAMPLE_BIT_ORDER enum
12374	*/
12375
12376	typedef enum I2S_SAMPLE_BIT_ORDER {
12377	I2S_SAMPLE_BIT_ORDER_MSB = 0x00000000,
12378	I2S_SAMPLE_BIT_ORDER_LSB = 0x00000001,
12379	} I2S_SAMPLE_BIT_ORDER;
12380
12381	/*
12382	* I2S_LRCLK_POLARITY enum
12383	*/
12384
12385	typedef enum I2S_LRCLK_POLARITY {
12386	I2S_LRCLK_LOW_LEFT = 0x00000000,
12387	I2S_LRCLK_HIGH_LEFT = 0x00000001,
12388	} I2S_LRCLK_POLARITY;
12389
12390	/*
12391	* I2S_WORD_ALIGNMENT enum
12392	*/
12393
12394	typedef enum I2S_WORD_ALIGNMENT {
12395	I2S_WORD_ALTERNATE_ALIGNMENT = 0x00000000,
12396	I2S_WORD_I2S_ALIGNMENT = 0x00000001,
12397	} I2S_WORD_ALIGNMENT;
12398
12399	/*
12400	* SPDIF_INVERT_EN enum
12401	*/
12402
12403	typedef enum SPDIF_INVERT_EN {
12404	SPDIF_INVERT_DISABLE = 0x00000000,
12405	SPDIF_INVERT_ENABLE = 0x00000001,
12406	} SPDIF_INVERT_EN;
12407
12408	/*******************************************************
12409	* DCO Enums
12410	*******************************************************/
12411
12412	/*
12413	* DPDBG_EN enum
12414	*/
12415
12416	typedef enum DPDBG_EN {
12417	DPDBG_DISABLE = 0x00000000,
12418	DPDBG_ENABLE = 0x00000001,
12419	} DPDBG_EN;
12420
12421	/*
12422	* DPDBG_INPUT_EN enum
12423	*/
12424
12425	typedef enum DPDBG_INPUT_EN {
12426	DPDBG_INPUT_DISABLE = 0x00000000,
12427	DPDBG_INPUT_ENABLE = 0x00000001,
12428	} DPDBG_INPUT_EN;
12429
12430	/*
12431	* DPDBG_ERROR_DETECTION_MODE enum
12432	*/
12433
12434	typedef enum DPDBG_ERROR_DETECTION_MODE {
12435	DPDBG_ERROR_DETECTION_MODE_CSC = 0x00000000,
12436	DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x00000001,
12437	} DPDBG_ERROR_DETECTION_MODE;
12438
12439	/*
12440	* DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK enum
12441	*/
12442
12443	typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
12444	DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x00000000,
12445	DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x00000001,
12446	} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
12447
12448	/*
12449	* DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE enum
12450	*/
12451
12452	typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
12453	DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x00000000,
12454	DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x00000001,
12455	} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
12456
12457	/*
12458	* DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK enum
12459	*/
12460
12461	typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
12462	DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x00000000,
12463	DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x00000001,
12464	} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
12465
12466	/*
12467	* PM_ASSERT_RESET enum
12468	*/
12469
12470	typedef enum PM_ASSERT_RESET {
12471	PM_ASSERT_RESET_0 = 0x00000000,
12472	PM_ASSERT_RESET_1 = 0x00000001,
12473	} PM_ASSERT_RESET;
12474
12475	/*
12476	* DAC_MUX_SELECT enum
12477	*/
12478
12479	typedef enum DAC_MUX_SELECT {
12480	DAC_MUX_SELECT_DACA = 0x00000000,
12481	DAC_MUX_SELECT_DACB = 0x00000001,
12482	} DAC_MUX_SELECT;
12483
12484	/*
12485	* TMDS_DVO_MUX_SELECT enum
12486	*/
12487
12488	typedef enum TMDS_DVO_MUX_SELECT {
12489	TMDS_DVO_MUX_SELECT_B = 0x00000000,
12490	TMDS_DVO_MUX_SELECT_G = 0x00000001,
12491	TMDS_DVO_MUX_SELECT_R = 0x00000002,
12492	TMDS_DVO_MUX_SELECT_RESERVED = 0x00000003,
12493	} TMDS_DVO_MUX_SELECT;
12494
12495	/*
12496	* DACA_SOFT_RESET enum
12497	*/
12498
12499	typedef enum DACA_SOFT_RESET {
12500	DACA_SOFT_RESET_0 = 0x00000000,
12501	DACA_SOFT_RESET_1 = 0x00000001,
12502	} DACA_SOFT_RESET;
12503
12504	/*
12505	* I2S0_SPDIF0_SOFT_RESET enum
12506	*/
12507
12508	typedef enum I2S0_SPDIF0_SOFT_RESET {
12509	I2S0_SPDIF0_SOFT_RESET_0 = 0x00000000,
12510	I2S0_SPDIF0_SOFT_RESET_1 = 0x00000001,
12511	} I2S0_SPDIF0_SOFT_RESET;
12512
12513	/*
12514	* I2S1_SOFT_RESET enum
12515	*/
12516
12517	typedef enum I2S1_SOFT_RESET {
12518	I2S1_SOFT_RESET_0 = 0x00000000,
12519	I2S1_SOFT_RESET_1 = 0x00000001,
12520	} I2S1_SOFT_RESET;
12521
12522	/*
12523	* SPDIF1_SOFT_RESET enum
12524	*/
12525
12526	typedef enum SPDIF1_SOFT_RESET {
12527	SPDIF1_SOFT_RESET_0 = 0x00000000,
12528	SPDIF1_SOFT_RESET_1 = 0x00000001,
12529	} SPDIF1_SOFT_RESET;
12530
12531	/*
12532	* DB_CLK_SOFT_RESET enum
12533	*/
12534
12535	typedef enum DB_CLK_SOFT_RESET {
12536	DB_CLK_SOFT_RESET_0 = 0x00000000,
12537	DB_CLK_SOFT_RESET_1 = 0x00000001,
12538	} DB_CLK_SOFT_RESET;
12539
12540	/*
12541	* FMT0_SOFT_RESET enum
12542	*/
12543
12544	typedef enum FMT0_SOFT_RESET {
12545	FMT0_SOFT_RESET_0 = 0x00000000,
12546	FMT0_SOFT_RESET_1 = 0x00000001,
12547	} FMT0_SOFT_RESET;
12548
12549	/*
12550	* FMT1_SOFT_RESET enum
12551	*/
12552
12553	typedef enum FMT1_SOFT_RESET {
12554	FMT1_SOFT_RESET_0 = 0x00000000,
12555	FMT1_SOFT_RESET_1 = 0x00000001,
12556	} FMT1_SOFT_RESET;
12557
12558	/*
12559	* FMT2_SOFT_RESET enum
12560	*/
12561
12562	typedef enum FMT2_SOFT_RESET {
12563	FMT2_SOFT_RESET_0 = 0x00000000,
12564	FMT2_SOFT_RESET_1 = 0x00000001,
12565	} FMT2_SOFT_RESET;
12566
12567	/*
12568	* FMT3_SOFT_RESET enum
12569	*/
12570
12571	typedef enum FMT3_SOFT_RESET {
12572	FMT3_SOFT_RESET_0 = 0x00000000,
12573	FMT3_SOFT_RESET_1 = 0x00000001,
12574	} FMT3_SOFT_RESET;
12575
12576	/*
12577	* FMT4_SOFT_RESET enum
12578	*/
12579
12580	typedef enum FMT4_SOFT_RESET {
12581	FMT4_SOFT_RESET_0 = 0x00000000,
12582	FMT4_SOFT_RESET_1 = 0x00000001,
12583	} FMT4_SOFT_RESET;
12584
12585	/*
12586	* FMT5_SOFT_RESET enum
12587	*/
12588
12589	typedef enum FMT5_SOFT_RESET {
12590	FMT5_SOFT_RESET_0 = 0x00000000,
12591	FMT5_SOFT_RESET_1 = 0x00000001,
12592	} FMT5_SOFT_RESET;
12593
12594	/*
12595	* MVP_SOFT_RESET enum
12596	*/
12597
12598	typedef enum MVP_SOFT_RESET {
12599	MVP_SOFT_RESET_0 = 0x00000000,
12600	MVP_SOFT_RESET_1 = 0x00000001,
12601	} MVP_SOFT_RESET;
12602
12603	/*
12604	* ABM_SOFT_RESET enum
12605	*/
12606
12607	typedef enum ABM_SOFT_RESET {
12608	ABM_SOFT_RESET_0 = 0x00000000,
12609	ABM_SOFT_RESET_1 = 0x00000001,
12610	} ABM_SOFT_RESET;
12611
12612	/*
12613	* DVO_SOFT_RESET enum
12614	*/
12615
12616	typedef enum DVO_SOFT_RESET {
12617	DVO_SOFT_RESET_0 = 0x00000000,
12618	DVO_SOFT_RESET_1 = 0x00000001,
12619	} DVO_SOFT_RESET;
12620
12621	/*
12622	* DIGA_FE_SOFT_RESET enum
12623	*/
12624
12625	typedef enum DIGA_FE_SOFT_RESET {
12626	DIGA_FE_SOFT_RESET_0 = 0x00000000,
12627	DIGA_FE_SOFT_RESET_1 = 0x00000001,
12628	} DIGA_FE_SOFT_RESET;
12629
12630	/*
12631	* DIGA_BE_SOFT_RESET enum
12632	*/
12633
12634	typedef enum DIGA_BE_SOFT_RESET {
12635	DIGA_BE_SOFT_RESET_0 = 0x00000000,
12636	DIGA_BE_SOFT_RESET_1 = 0x00000001,
12637	} DIGA_BE_SOFT_RESET;
12638
12639	/*
12640	* DIGB_FE_SOFT_RESET enum
12641	*/
12642
12643	typedef enum DIGB_FE_SOFT_RESET {
12644	DIGB_FE_SOFT_RESET_0 = 0x00000000,
12645	DIGB_FE_SOFT_RESET_1 = 0x00000001,
12646	} DIGB_FE_SOFT_RESET;
12647
12648	/*
12649	* DIGB_BE_SOFT_RESET enum
12650	*/
12651
12652	typedef enum DIGB_BE_SOFT_RESET {
12653	DIGB_BE_SOFT_RESET_0 = 0x00000000,
12654	DIGB_BE_SOFT_RESET_1 = 0x00000001,
12655	} DIGB_BE_SOFT_RESET;
12656
12657	/*
12658	* DIGC_FE_SOFT_RESET enum
12659	*/
12660
12661	typedef enum DIGC_FE_SOFT_RESET {
12662	DIGC_FE_SOFT_RESET_0 = 0x00000000,
12663	DIGC_FE_SOFT_RESET_1 = 0x00000001,
12664	} DIGC_FE_SOFT_RESET;
12665
12666	/*
12667	* DIGC_BE_SOFT_RESET enum
12668	*/
12669
12670	typedef enum DIGC_BE_SOFT_RESET {
12671	DIGC_BE_SOFT_RESET_0 = 0x00000000,
12672	DIGC_BE_SOFT_RESET_1 = 0x00000001,
12673	} DIGC_BE_SOFT_RESET;
12674
12675	/*
12676	* DIGD_FE_SOFT_RESET enum
12677	*/
12678
12679	typedef enum DIGD_FE_SOFT_RESET {
12680	DIGD_FE_SOFT_RESET_0 = 0x00000000,
12681	DIGD_FE_SOFT_RESET_1 = 0x00000001,
12682	} DIGD_FE_SOFT_RESET;
12683
12684	/*
12685	* DIGD_BE_SOFT_RESET enum
12686	*/
12687
12688	typedef enum DIGD_BE_SOFT_RESET {
12689	DIGD_BE_SOFT_RESET_0 = 0x00000000,
12690	DIGD_BE_SOFT_RESET_1 = 0x00000001,
12691	} DIGD_BE_SOFT_RESET;
12692
12693	/*
12694	* DIGE_FE_SOFT_RESET enum
12695	*/
12696
12697	typedef enum DIGE_FE_SOFT_RESET {
12698	DIGE_FE_SOFT_RESET_0 = 0x00000000,
12699	DIGE_FE_SOFT_RESET_1 = 0x00000001,
12700	} DIGE_FE_SOFT_RESET;
12701
12702	/*
12703	* DIGE_BE_SOFT_RESET enum
12704	*/
12705
12706	typedef enum DIGE_BE_SOFT_RESET {
12707	DIGE_BE_SOFT_RESET_0 = 0x00000000,
12708	DIGE_BE_SOFT_RESET_1 = 0x00000001,
12709	} DIGE_BE_SOFT_RESET;
12710
12711	/*
12712	* DIGF_FE_SOFT_RESET enum
12713	*/
12714
12715	typedef enum DIGF_FE_SOFT_RESET {
12716	DIGF_FE_SOFT_RESET_0 = 0x00000000,
12717	DIGF_FE_SOFT_RESET_1 = 0x00000001,
12718	} DIGF_FE_SOFT_RESET;
12719
12720	/*
12721	* DIGF_BE_SOFT_RESET enum
12722	*/
12723
12724	typedef enum DIGF_BE_SOFT_RESET {
12725	DIGF_BE_SOFT_RESET_0 = 0x00000000,
12726	DIGF_BE_SOFT_RESET_1 = 0x00000001,
12727	} DIGF_BE_SOFT_RESET;
12728
12729	/*
12730	* DIGG_FE_SOFT_RESET enum
12731	*/
12732
12733	typedef enum DIGG_FE_SOFT_RESET {
12734	DIGG_FE_SOFT_RESET_0 = 0x00000000,
12735	DIGG_FE_SOFT_RESET_1 = 0x00000001,
12736	} DIGG_FE_SOFT_RESET;
12737
12738	/*
12739	* DIGG_BE_SOFT_RESET enum
12740	*/
12741
12742	typedef enum DIGG_BE_SOFT_RESET {
12743	DIGG_BE_SOFT_RESET_0 = 0x00000000,
12744	DIGG_BE_SOFT_RESET_1 = 0x00000001,
12745	} DIGG_BE_SOFT_RESET;
12746
12747	/*
12748	* DPDBG_SOFT_RESET enum
12749	*/
12750
12751	typedef enum DPDBG_SOFT_RESET {
12752	DPDBG_SOFT_RESET_0 = 0x00000000,
12753	DPDBG_SOFT_RESET_1 = 0x00000001,
12754	} DPDBG_SOFT_RESET;
12755
12756	/*
12757	* DIGLPA_FE_SOFT_RESET enum
12758	*/
12759
12760	typedef enum DIGLPA_FE_SOFT_RESET {
12761	DIGLPA_FE_SOFT_RESET_0 = 0x00000000,
12762	DIGLPA_FE_SOFT_RESET_1 = 0x00000001,
12763	} DIGLPA_FE_SOFT_RESET;
12764
12765	/*
12766	* DIGLPA_BE_SOFT_RESET enum
12767	*/
12768
12769	typedef enum DIGLPA_BE_SOFT_RESET {
12770	DIGLPA_BE_SOFT_RESET_0 = 0x00000000,
12771	DIGLPA_BE_SOFT_RESET_1 = 0x00000001,
12772	} DIGLPA_BE_SOFT_RESET;
12773
12774	/*
12775	* DIGLPB_FE_SOFT_RESET enum
12776	*/
12777
12778	typedef enum DIGLPB_FE_SOFT_RESET {
12779	DIGLPB_FE_SOFT_RESET_0 = 0x00000000,
12780	DIGLPB_FE_SOFT_RESET_1 = 0x00000001,
12781	} DIGLPB_FE_SOFT_RESET;
12782
12783	/*
12784	* DIGLPB_BE_SOFT_RESET enum
12785	*/
12786
12787	typedef enum DIGLPB_BE_SOFT_RESET {
12788	DIGLPB_BE_SOFT_RESET_0 = 0x00000000,
12789	DIGLPB_BE_SOFT_RESET_1 = 0x00000001,
12790	} DIGLPB_BE_SOFT_RESET;
12791
12792	/*
12793	* GENERICA_STEREOSYNC_SEL enum
12794	*/
12795
12796	typedef enum GENERICA_STEREOSYNC_SEL {
12797	GENERICA_STEREOSYNC_SEL_D1 = 0x00000000,
12798	GENERICA_STEREOSYNC_SEL_D2 = 0x00000001,
12799	GENERICA_STEREOSYNC_SEL_D3 = 0x00000002,
12800	GENERICA_STEREOSYNC_SEL_D4 = 0x00000003,
12801	GENERICA_STEREOSYNC_SEL_D5 = 0x00000004,
12802	GENERICA_STEREOSYNC_SEL_D6 = 0x00000005,
12803	GENERICA_STEREOSYNC_SEL_RESERVED = 0x00000006,
12804	} GENERICA_STEREOSYNC_SEL;
12805
12806	/*
12807	* GENERICB_STEREOSYNC_SEL enum
12808	*/
12809
12810	typedef enum GENERICB_STEREOSYNC_SEL {
12811	GENERICB_STEREOSYNC_SEL_D1 = 0x00000000,
12812	GENERICB_STEREOSYNC_SEL_D2 = 0x00000001,
12813	GENERICB_STEREOSYNC_SEL_D3 = 0x00000002,
12814	GENERICB_STEREOSYNC_SEL_D4 = 0x00000003,
12815	GENERICB_STEREOSYNC_SEL_D5 = 0x00000004,
12816	GENERICB_STEREOSYNC_SEL_D6 = 0x00000005,
12817	GENERICB_STEREOSYNC_SEL_RESERVED = 0x00000006,
12818	} GENERICB_STEREOSYNC_SEL;
12819
12820	/*
12821	* DCO_DBG_BLOCK_SEL enum
12822	*/
12823
12824	typedef enum DCO_DBG_BLOCK_SEL {
12825	DCO_DBG_BLOCK_SEL_DCO = 0x00000000,
12826	DCO_DBG_BLOCK_SEL_ABM = 0x00000001,
12827	DCO_DBG_BLOCK_SEL_DVO = 0x00000002,
12828	DCO_DBG_BLOCK_SEL_DAC = 0x00000003,
12829	DCO_DBG_BLOCK_SEL_MVP = 0x00000004,
12830	DCO_DBG_BLOCK_SEL_FMT0 = 0x00000005,
12831	DCO_DBG_BLOCK_SEL_FMT1 = 0x00000006,
12832	DCO_DBG_BLOCK_SEL_FMT2 = 0x00000007,
12833	DCO_DBG_BLOCK_SEL_FMT3 = 0x00000008,
12834	DCO_DBG_BLOCK_SEL_FMT4 = 0x00000009,
12835	DCO_DBG_BLOCK_SEL_FMT5 = 0x0000000a,
12836	DCO_DBG_BLOCK_SEL_DIGFE_A = 0x0000000b,
12837	DCO_DBG_BLOCK_SEL_DIGFE_B = 0x0000000c,
12838	DCO_DBG_BLOCK_SEL_DIGFE_C = 0x0000000d,
12839	DCO_DBG_BLOCK_SEL_DIGFE_D = 0x0000000e,
12840	DCO_DBG_BLOCK_SEL_DIGFE_E = 0x0000000f,
12841	DCO_DBG_BLOCK_SEL_DIGFE_F = 0x00000010,
12842	DCO_DBG_BLOCK_SEL_DIGFE_G = 0x00000011,
12843	DCO_DBG_BLOCK_SEL_DIGA = 0x00000012,
12844	DCO_DBG_BLOCK_SEL_DIGB = 0x00000013,
12845	DCO_DBG_BLOCK_SEL_DIGC = 0x00000014,
12846	DCO_DBG_BLOCK_SEL_DIGD = 0x00000015,
12847	DCO_DBG_BLOCK_SEL_DIGE = 0x00000016,
12848	DCO_DBG_BLOCK_SEL_DIGF = 0x00000017,
12849	DCO_DBG_BLOCK_SEL_DIGG = 0x00000018,
12850	DCO_DBG_BLOCK_SEL_DPFE_A = 0x00000019,
12851	DCO_DBG_BLOCK_SEL_DPFE_B = 0x0000001a,
12852	DCO_DBG_BLOCK_SEL_DPFE_C = 0x0000001b,
12853	DCO_DBG_BLOCK_SEL_DPFE_D = 0x0000001c,
12854	DCO_DBG_BLOCK_SEL_DPFE_E = 0x0000001d,
12855	DCO_DBG_BLOCK_SEL_DPFE_F = 0x0000001e,
12856	DCO_DBG_BLOCK_SEL_DPFE_G = 0x0000001f,
12857	DCO_DBG_BLOCK_SEL_DPA = 0x00000020,
12858	DCO_DBG_BLOCK_SEL_DPB = 0x00000021,
12859	DCO_DBG_BLOCK_SEL_DPC = 0x00000022,
12860	DCO_DBG_BLOCK_SEL_DPD = 0x00000023,
12861	DCO_DBG_BLOCK_SEL_DPE = 0x00000024,
12862	DCO_DBG_BLOCK_SEL_DPF = 0x00000025,
12863	DCO_DBG_BLOCK_SEL_DPG = 0x00000026,
12864	DCO_DBG_BLOCK_SEL_AUX0 = 0x00000027,
12865	DCO_DBG_BLOCK_SEL_AUX1 = 0x00000028,
12866	DCO_DBG_BLOCK_SEL_AUX2 = 0x00000029,
12867	DCO_DBG_BLOCK_SEL_AUX3 = 0x0000002a,
12868	DCO_DBG_BLOCK_SEL_AUX4 = 0x0000002b,
12869	DCO_DBG_BLOCK_SEL_AUX5 = 0x0000002c,
12870	DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x0000002d,
12871	DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x0000002e,
12872	DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x0000002f,
12873	DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x00000030,
12874	DCO_DBG_BLOCK_SEL_DIGLPA = 0x00000031,
12875	DCO_DBG_BLOCK_SEL_DIGLPB = 0x00000032,
12876	DCO_DBG_BLOCK_SEL_DPLPFEA = 0x00000033,
12877	DCO_DBG_BLOCK_SEL_DPLPFEB = 0x00000034,
12878	DCO_DBG_BLOCK_SEL_DPLPA = 0x00000035,
12879	DCO_DBG_BLOCK_SEL_DPLPB = 0x00000036,
12880	} DCO_DBG_BLOCK_SEL;
12881
12882	/*
12883	* DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE enum
12884	*/
12885
12886	typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
12887	DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000,
12888	DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001,
12889	} DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE;
12890
12891	/*
12892	* FMT420_MEMORY_SOURCE_SEL enum
12893	*/
12894
12895	typedef enum FMT420_MEMORY_SOURCE_SEL {
12896	FMT420_MEMORY_SOURCE_SEL_FMT0 = 0x00000000,
12897	FMT420_MEMORY_SOURCE_SEL_FMT1 = 0x00000001,
12898	FMT420_MEMORY_SOURCE_SEL_FMT2 = 0x00000002,
12899	FMT420_MEMORY_SOURCE_SEL_FMT3 = 0x00000003,
12900	FMT420_MEMORY_SOURCE_SEL_FMT4 = 0x00000004,
12901	FMT420_MEMORY_SOURCE_SEL_FMT5 = 0x00000005,
12902	FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 0x00000006,
12903	} FMT420_MEMORY_SOURCE_SEL;
12904
12905	/*******************************************************
12906	* DOUT_I2C Enums
12907	*******************************************************/
12908
12909	/*
12910	* DOUT_I2C_CONTROL_GO enum
12911	*/
12912
12913	typedef enum DOUT_I2C_CONTROL_GO {
12914	DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000,
12915	DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001,
12916	} DOUT_I2C_CONTROL_GO;
12917
12918	/*
12919	* DOUT_I2C_CONTROL_SOFT_RESET enum
12920	*/
12921
12922	typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
12923	DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
12924	DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001,
12925	} DOUT_I2C_CONTROL_SOFT_RESET;
12926
12927	/*
12928	* DOUT_I2C_CONTROL_SEND_RESET enum
12929	*/
12930
12931	typedef enum DOUT_I2C_CONTROL_SEND_RESET {
12932	DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000,
12933	DOUT_I2C_CONTROL__SEND_RESET = 0x00000001,
12934	} DOUT_I2C_CONTROL_SEND_RESET;
12935
12936	/*
12937	* DOUT_I2C_CONTROL_SW_STATUS_RESET enum
12938	*/
12939
12940	typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
12941	DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000,
12942	DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001,
12943	} DOUT_I2C_CONTROL_SW_STATUS_RESET;
12944
12945	/*
12946	* DOUT_I2C_CONTROL_DDC_SELECT enum
12947	*/
12948
12949	typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
12950	DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000,
12951	DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001,
12952	DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002,
12953	DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003,
12954	DOUT_I2C_CONTROL_SELECT_DDC5 = 0x00000004,
12955	DOUT_I2C_CONTROL_SELECT_DDC6 = 0x00000005,
12956	DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000006,
12957	} DOUT_I2C_CONTROL_DDC_SELECT;
12958
12959	/*
12960	* DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
12961	*/
12962
12963	typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
12964	DOUT_I2C_CONTROL_TRANS0 = 0x00000000,
12965	DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001,
12966	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002,
12967	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003,
12968	} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
12969
12970	/*
12971	* DOUT_I2C_CONTROL_DBG_REF_SEL enum
12972	*/
12973
12974	typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
12975	DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x00000000,
12976	DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x00000001,
12977	} DOUT_I2C_CONTROL_DBG_REF_SEL;
12978
12979	/*
12980	* DOUT_I2C_ARBITRATION_SW_PRIORITY enum
12981	*/
12982
12983	typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
12984	DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000,
12985	DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001,
12986	DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
12987	DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
12988	} DOUT_I2C_ARBITRATION_SW_PRIORITY;
12989
12990	/*
12991	* DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
12992	*/
12993
12994	typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
12995	DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000,
12996	DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001,
12997	} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
12998
12999	/*
13000	* DOUT_I2C_ARBITRATION_ABORT_XFER enum
13001	*/
13002
13003	typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
13004	DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
13005	DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001,
13006	} DOUT_I2C_ARBITRATION_ABORT_XFER;
13007
13008	/*
13009	* DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
13010	*/
13011
13012	typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
13013	DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
13014	DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001,
13015	} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
13016
13017	/*
13018	* DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
13019	*/
13020
13021	typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
13022	DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
13023	DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001,
13024	} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
13025
13026	/*
13027	* DOUT_I2C_ACK enum
13028	*/
13029
13030	typedef enum DOUT_I2C_ACK {
13031	DOUT_I2C_NO_ACK = 0x00000000,
13032	DOUT_I2C_ACK_TO_CLEAN = 0x00000001,
13033	} DOUT_I2C_ACK;
13034
13035	/*
13036	* DOUT_I2C_DDC_SPEED_THRESHOLD enum
13037	*/
13038
13039	typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
13040	DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000,
13041	DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001,
13042	DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002,
13043	DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003,
13044	} DOUT_I2C_DDC_SPEED_THRESHOLD;
13045
13046	/*
13047	* DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
13048	*/
13049
13050	typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
13051	DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
13052	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001,
13053	} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
13054
13055	/*
13056	* DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
13057	*/
13058
13059	typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
13060	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000,
13061	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001,
13062	} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
13063
13064	/*
13065	* DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
13066	*/
13067
13068	typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
13069	DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000,
13070	DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001,
13071	} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
13072
13073	/*
13074	* DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
13075	*/
13076
13077	typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
13078	DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
13079	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001,
13080	} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
13081
13082	/*
13083	* DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
13084	*/
13085
13086	typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
13087	DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000,
13088	DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001,
13089	} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
13090
13091	/*
13092	* DOUT_I2C_DATA_INDEX_WRITE enum
13093	*/
13094
13095	typedef enum DOUT_I2C_DATA_INDEX_WRITE {
13096	DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000,
13097	DOUT_I2C_DATA__INDEX_WRITE = 0x00000001,
13098	} DOUT_I2C_DATA_INDEX_WRITE;
13099
13100	/*
13101	* DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
13102	*/
13103
13104	typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
13105	DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
13106	DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001,
13107	} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
13108
13109	/*
13110	* DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
13111	*/
13112
13113	typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
13114	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000,
13115	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001,
13116	} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
13117
13118	/*******************************************************
13119	* FBC Enums
13120	*******************************************************/
13121
13122	/*
13123	* FBC_IDLE_MASK_MASK_BITS enum
13124	*/
13125
13126	typedef enum FBC_IDLE_MASK_MASK_BITS {
13127	FBC_IDLE_MASK_DISP_REG_UPDATE = 0x00000000,
13128	FBC_IDLE_MASK_RESERVED1 = 0x00000001,
13129	FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 0x00000002,
13130	FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 0x00000003,
13131	FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 0x00000004,
13132	FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000005,
13133	FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 0x00000006,
13134	FBC_IDLE_MASK_RESERVED7 = 0x00000007,
13135	FBC_IDLE_MASK_RESERVED8 = 0x00000008,
13136	FBC_IDLE_MASK_RESERVED9 = 0x00000009,
13137	FBC_IDLE_MASK_RESERVED10 = 0x0000000a,
13138	FBC_IDLE_MASK_RESERVED11 = 0x0000000b,
13139	FBC_IDLE_MASK_RESERVED12 = 0x0000000c,
13140	FBC_IDLE_MASK_RESERVED13 = 0x0000000d,
13141	FBC_IDLE_MASK_RESERVED14 = 0x0000000e,
13142	FBC_IDLE_MASK_RESERVED15 = 0x0000000f,
13143	FBC_IDLE_MASK_RESERVED16 = 0x00000010,
13144	FBC_IDLE_MASK_RESERVED17 = 0x00000011,
13145	FBC_IDLE_MASK_RESERVED18 = 0x00000012,
13146	FBC_IDLE_MASK_RESERVED19 = 0x00000013,
13147	FBC_IDLE_MASK_RESERVED20 = 0x00000014,
13148	FBC_IDLE_MASK_RESERVED21 = 0x00000015,
13149	FBC_IDLE_MASK_RESERVED22 = 0x00000016,
13150	FBC_IDLE_MASK_RESERVED23 = 0x00000017,
13151	FBC_IDLE_MASK_MC_HIT_REGION_0 = 0x00000018,
13152	FBC_IDLE_MASK_MC_HIT_REGION_1 = 0x00000019,
13153	FBC_IDLE_MASK_MC_HIT_REGION_2 = 0x0000001a,
13154	FBC_IDLE_MASK_MC_HIT_REGION_3 = 0x0000001b,
13155	FBC_IDLE_MASK_MC_WRITE = 0x0000001c,
13156	FBC_IDLE_MASK_RESERVED29 = 0x0000001d,
13157	FBC_IDLE_MASK_RESERVED30 = 0x0000001e,
13158	FBC_IDLE_MASK_RESERVED31 = 0x0000001f,
13159	} FBC_IDLE_MASK_MASK_BITS;
13160
13161	/*******************************************************
13162	* DPCSRX Enums
13163	*******************************************************/
13164
13165	/*
13166	* DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
13167	*/
13168
13169	typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
13170	DPCSRX_BPHY_PCS_RX0_CLK = 0x00000000,
13171	DPCSRX_BPHY_PCS_RX1_CLK = 0x00000001,
13172	DPCSRX_BPHY_PCS_RX2_CLK = 0x00000002,
13173	DPCSRX_BPHY_PCS_RX3_CLK = 0x00000003,
13174	} DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL;
13175
13176	/*
13177	* DPCSRX_DBG_CFGCLK_SEL enum
13178	*/
13179
13180	typedef enum DPCSRX_DBG_CFGCLK_SEL {
13181	DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x00000000,
13182	DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x00000001,
13183	DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x00000002,
13184	DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x00000003,
13185	} DPCSRX_DBG_CFGCLK_SEL;
13186
13187	/*
13188	* DPCSRX_RX_SYMCLK_SEL enum
13189	*/
13190
13191	typedef enum DPCSRX_RX_SYMCLK_SEL {
13192	DPCSRX_DBG_RX_SYMCLK_SEL_OUT0 = 0x00000000,
13193	DPCSRX_DBG_RX_SYMCLK_SEL_OUT1 = 0x00000001,
13194	DPCSRX_DBG_RX_SYMCLK_SEL_INT = 0x00000002,
13195	} DPCSRX_RX_SYMCLK_SEL;
13196
13197	/*******************************************************
13198	* DPCSTX Enums
13199	*******************************************************/
13200
13201	/*
13202	* DPCSTX_DBG_CFGCLK_SEL enum
13203	*/
13204
13205	typedef enum DPCSTX_DBG_CFGCLK_SEL {
13206	DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x00000000,
13207	DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x00000001,
13208	DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x00000002,
13209	DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x00000003,
13210	} DPCSTX_DBG_CFGCLK_SEL;
13211
13212	/*
13213	* DPCSTX_TX_SYMCLK_SEL enum
13214	*/
13215
13216	typedef enum DPCSTX_TX_SYMCLK_SEL {
13217	DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0x00000000,
13218	DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 0x00000001,
13219	DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 0x00000002,
13220	} DPCSTX_TX_SYMCLK_SEL;
13221
13222	/*
13223	* DPCSTX_TX_SYMCLK_DIV2_SEL enum
13224	*/
13225
13226	typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
13227	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0x00000000,
13228	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 0x00000001,
13229	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 0x00000002,
13230	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 0x00000003,
13231	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 0x00000004,
13232	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 0x00000005,
13233	} DPCSTX_TX_SYMCLK_DIV2_SEL;
13234
13235	/*******************************************************
13236	* CB Enums
13237	*******************************************************/
13238
13239	/*
13240	* SurfaceNumber enum
13241	*/
13242
13243	typedef enum SurfaceNumber {
13244	NUMBER_UNORM = 0x00000000,
13245	NUMBER_SNORM = 0x00000001,
13246	NUMBER_USCALED = 0x00000002,
13247	NUMBER_SSCALED = 0x00000003,
13248	NUMBER_UINT = 0x00000004,
13249	NUMBER_SINT = 0x00000005,
13250	NUMBER_SRGB = 0x00000006,
13251	NUMBER_FLOAT = 0x00000007,
13252	} SurfaceNumber;
13253
13254	/*
13255	* SurfaceSwap enum
13256	*/
13257
13258	typedef enum SurfaceSwap {
13259	SWAP_STD = 0x00000000,
13260	SWAP_ALT = 0x00000001,
13261	SWAP_STD_REV = 0x00000002,
13262	SWAP_ALT_REV = 0x00000003,
13263	} SurfaceSwap;
13264
13265	/*
13266	* CBMode enum
13267	*/
13268
13269	typedef enum CBMode {
13270	CB_DISABLE = 0x00000000,
13271	CB_NORMAL = 0x00000001,
13272	CB_ELIMINATE_FAST_CLEAR = 0x00000002,
13273	CB_RESOLVE = 0x00000003,
13274	CB_DECOMPRESS = 0x00000004,
13275	CB_FMASK_DECOMPRESS = 0x00000005,
13276	CB_DCC_DECOMPRESS = 0x00000006,
13277	} CBMode;
13278
13279	/*
13280	* RoundMode enum
13281	*/
13282
13283	typedef enum RoundMode {
13284	ROUND_BY_HALF = 0x00000000,
13285	ROUND_TRUNCATE = 0x00000001,
13286	} RoundMode;
13287
13288	/*
13289	* SourceFormat enum
13290	*/
13291
13292	typedef enum SourceFormat {
13293	EXPORT_4C_32BPC = 0x00000000,
13294	EXPORT_4C_16BPC = 0x00000001,
13295	EXPORT_2C_32BPC_GR = 0x00000002,
13296	EXPORT_2C_32BPC_AR = 0x00000003,
13297	} SourceFormat;
13298
13299	/*
13300	* BlendOp enum
13301	*/
13302
13303	typedef enum BlendOp {
13304	BLEND_ZERO = 0x00000000,
13305	BLEND_ONE = 0x00000001,
13306	BLEND_SRC_COLOR = 0x00000002,
13307	BLEND_ONE_MINUS_SRC_COLOR = 0x00000003,
13308	BLEND_SRC_ALPHA = 0x00000004,
13309	BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005,
13310	BLEND_DST_ALPHA = 0x00000006,
13311	BLEND_ONE_MINUS_DST_ALPHA = 0x00000007,
13312	BLEND_DST_COLOR = 0x00000008,
13313	BLEND_ONE_MINUS_DST_COLOR = 0x00000009,
13314	BLEND_SRC_ALPHA_SATURATE = 0x0000000a,
13315	BLEND_BOTH_SRC_ALPHA = 0x0000000b,
13316	BLEND_BOTH_INV_SRC_ALPHA = 0x0000000c,
13317	BLEND_CONSTANT_COLOR = 0x0000000d,
13318	BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000e,
13319	BLEND_SRC1_COLOR = 0x0000000f,
13320	BLEND_INV_SRC1_COLOR = 0x00000010,
13321	BLEND_SRC1_ALPHA = 0x00000011,
13322	BLEND_INV_SRC1_ALPHA = 0x00000012,
13323	BLEND_CONSTANT_ALPHA = 0x00000013,
13324	BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000014,
13325	} BlendOp;
13326
13327	/*
13328	* CombFunc enum
13329	*/
13330
13331	typedef enum CombFunc {
13332	COMB_DST_PLUS_SRC = 0x00000000,
13333	COMB_SRC_MINUS_DST = 0x00000001,
13334	COMB_MIN_DST_SRC = 0x00000002,
13335	COMB_MAX_DST_SRC = 0x00000003,
13336	COMB_DST_MINUS_SRC = 0x00000004,
13337	} CombFunc;
13338
13339	/*
13340	* BlendOpt enum
13341	*/
13342
13343	typedef enum BlendOpt {
13344	FORCE_OPT_AUTO = 0x00000000,
13345	FORCE_OPT_DISABLE = 0x00000001,
13346	FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002,
13347	FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003,
13348	FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004,
13349	FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005,
13350	FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006,
13351	FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007,
13352	} BlendOpt;
13353
13354	/*
13355	* CmaskCode enum
13356	*/
13357
13358	typedef enum CmaskCode {
13359	CMASK_CLR00_F0 = 0x00000000,
13360	CMASK_CLR00_F1 = 0x00000001,
13361	CMASK_CLR00_F2 = 0x00000002,
13362	CMASK_CLR00_FX = 0x00000003,
13363	CMASK_CLR01_F0 = 0x00000004,
13364	CMASK_CLR01_F1 = 0x00000005,
13365	CMASK_CLR01_F2 = 0x00000006,
13366	CMASK_CLR01_FX = 0x00000007,
13367	CMASK_CLR10_F0 = 0x00000008,
13368	CMASK_CLR10_F1 = 0x00000009,
13369	CMASK_CLR10_F2 = 0x0000000a,
13370	CMASK_CLR10_FX = 0x0000000b,
13371	CMASK_CLR11_F0 = 0x0000000c,
13372	CMASK_CLR11_F1 = 0x0000000d,
13373	CMASK_CLR11_F2 = 0x0000000e,
13374	CMASK_CLR11_FX = 0x0000000f,
13375	} CmaskCode;
13376
13377	/*
13378	* CmaskAddr enum
13379	*/
13380
13381	typedef enum CmaskAddr {
13382	CMASK_ADDR_TILED = 0x00000000,
13383	CMASK_ADDR_LINEAR = 0x00000001,
13384	CMASK_ADDR_COMPATIBLE = 0x00000002,
13385	} CmaskAddr;
13386
13387	/*
13388	* MemArbMode enum
13389	*/
13390
13391	typedef enum MemArbMode {
13392	MEM_ARB_MODE_FIXED = 0x00000000,
13393	MEM_ARB_MODE_AGE = 0x00000001,
13394	MEM_ARB_MODE_WEIGHT = 0x00000002,
13395	MEM_ARB_MODE_BOTH = 0x00000003,
13396	} MemArbMode;
13397
13398	/*
13399	* CBPerfSel enum
13400	*/
13401
13402	typedef enum CBPerfSel {
13403	CB_PERF_SEL_NONE = 0x00000000,
13404	CB_PERF_SEL_BUSY = 0x00000001,
13405	CB_PERF_SEL_CORE_SCLK_VLD = 0x00000002,
13406	CB_PERF_SEL_REG_SCLK0_VLD = 0x00000003,
13407	CB_PERF_SEL_REG_SCLK1_VLD = 0x00000004,
13408	CB_PERF_SEL_DRAWN_QUAD = 0x00000005,
13409	CB_PERF_SEL_DRAWN_PIXEL = 0x00000006,
13410	CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000007,
13411	CB_PERF_SEL_DRAWN_TILE = 0x00000008,
13412	CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x00000009,
13413	CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0x0000000a,
13414	CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0x0000000b,
13415	CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0x0000000c,
13416	CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0x0000000d,
13417	CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0x0000000e,
13418	CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0x0000000f,
13419	CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x00000010,
13420	CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x00000011,
13421	CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012,
13422	CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x00000013,
13423	CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x00000014,
13424	CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x00000015,
13425	CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x00000016,
13426	CB_PERF_SEL_LQUAD_NO_TILE = 0x00000017,
13427	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x00000018,
13428	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019,
13429	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a,
13430	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b,
13431	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c,
13432	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d,
13433	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 0x0000001e,
13434	CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f,
13435	CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020,
13436	CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000021,
13437	CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022,
13438	CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023,
13439	CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x00000024,
13440	CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x00000025,
13441	CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x00000026,
13442	CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x00000027,
13443	CB_PERF_SEL_FOP_IN_VALID_READY = 0x00000028,
13444	CB_PERF_SEL_FOP_IN_VALID_READYB = 0x00000029,
13445	CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x0000002a,
13446	CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x0000002b,
13447	CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x0000002c,
13448	CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x0000002d,
13449	CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x0000002e,
13450	CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f,
13451	CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x00000030,
13452	CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x00000031,
13453	CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x00000032,
13454	CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x00000033,
13455	CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x00000034,
13456	CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x00000035,
13457	CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x00000036,
13458	CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x00000037,
13459	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038,
13460	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039,
13461	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a,
13462	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b,
13463	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c,
13464	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d,
13465	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e,
13466	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f,
13467	CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x00000040,
13468	CB_PERF_SEL_CM_CACHE_HIT = 0x00000041,
13469	CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x00000042,
13470	CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x00000043,
13471	CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x00000044,
13472	CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000045,
13473	CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046,
13474	CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000047,
13475	CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x00000048,
13476	CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x00000049,
13477	CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x0000004a,
13478	CB_PERF_SEL_CM_CACHE_STALL = 0x0000004b,
13479	CB_PERF_SEL_CM_CACHE_FLUSH = 0x0000004c,
13480	CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x0000004d,
13481	CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x0000004e,
13482	CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f,
13483	CB_PERF_SEL_FC_CACHE_HIT = 0x00000050,
13484	CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x00000051,
13485	CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x00000052,
13486	CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x00000053,
13487	CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000054,
13488	CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055,
13489	CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000056,
13490	CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x00000057,
13491	CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x00000058,
13492	CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x00000059,
13493	CB_PERF_SEL_FC_CACHE_STALL = 0x0000005a,
13494	CB_PERF_SEL_FC_CACHE_FLUSH = 0x0000005b,
13495	CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x0000005c,
13496	CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x0000005d,
13497	CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e,
13498	CB_PERF_SEL_CC_CACHE_HIT = 0x0000005f,
13499	CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000060,
13500	CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000061,
13501	CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000062,
13502	CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000063,
13503	CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064,
13504	CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000065,
13505	CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000066,
13506	CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000067,
13507	CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x00000068,
13508	CB_PERF_SEL_CC_CACHE_STALL = 0x00000069,
13509	CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000006a,
13510	CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x0000006b,
13511	CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000006c,
13512	CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d,
13513	CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e,
13514	CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x0000006f,
13515	CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x00000070,
13516	CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x00000071,
13517	CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x00000072,
13518	CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x00000073,
13519	CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x00000074,
13520	CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x00000075,
13521	CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x00000076,
13522	CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000077,
13523	CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000078,
13524	CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000079,
13525	CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x0000007a,
13526	CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x0000007b,
13527	CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x0000007c,
13528	CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x0000007d,
13529	CB_PERF_SEL_CM_MC_READ_REQUEST = 0x0000007e,
13530	CB_PERF_SEL_FC_MC_READ_REQUEST = 0x0000007f,
13531	CB_PERF_SEL_CC_MC_READ_REQUEST = 0x00000080,
13532	CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x00000081,
13533	CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000082,
13534	CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000083,
13535	CB_PERF_SEL_CM_TQ_FULL = 0x00000084,
13536	CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x00000085,
13537	CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x00000086,
13538	CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x00000087,
13539	CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000088,
13540	CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x00000089,
13541	CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x0000008a,
13542	CB_PERF_SEL_CC_SF_FULL = 0x0000008b,
13543	CB_PERF_SEL_CC_RB_FULL = 0x0000008c,
13544	CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x0000008d,
13545	CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x0000008e,
13546	CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x0000008f,
13547	CB_PERF_SEL_EVENT = 0x00000090,
13548	CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x00000091,
13549	CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x00000092,
13550	CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x00000093,
13551	CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000094,
13552	CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x00000095,
13553	CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000096,
13554	CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000097,
13555	CB_PERF_SEL_CC_SURFACE_SYNC = 0x00000098,
13556	CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x00000099,
13557	CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x0000009a,
13558	CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x0000009b,
13559	CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x0000009c,
13560	CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x0000009d,
13561	CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x0000009e,
13562	CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x0000009f,
13563	CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x000000a0,
13564	CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0x000000a1,
13565	CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x000000a2,
13566	CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0x000000a3,
13567	CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0x000000a4,
13568	CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0x000000a5,
13569	CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0x000000a6,
13570	CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0x000000a7,
13571	CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0x000000a8,
13572	CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0x000000a9,
13573	CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0x000000aa,
13574	CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0x000000ab,
13575	CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0x000000ac,
13576	CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0x000000ad,
13577	CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0x000000ae,
13578	CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0x000000af,
13579	CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0x000000b0,
13580	CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0x000000b1,
13581	CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0x000000b2,
13582	CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0x000000b3,
13583	CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0x000000b4,
13584	CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0x000000b5,
13585	CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0x000000b6,
13586	CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0x000000b7,
13587	CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0x000000b8,
13588	CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0x000000b9,
13589	CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0x000000ba,
13590	CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0x000000bb,
13591	CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0x000000bc,
13592	CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0x000000bd,
13593	CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0x000000be,
13594	CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0x000000bf,
13595	CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0x000000c0,
13596	CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0x000000c1,
13597	CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0x000000c2,
13598	CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0x000000c3,
13599	CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0x000000c4,
13600	CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0x000000c5,
13601	CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0x000000c6,
13602	CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0x000000c7,
13603	CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0x000000c8,
13604	CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0x000000c9,
13605	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0x000000ca,
13606	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0x000000cb,
13607	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0x000000cc,
13608	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0x000000cd,
13609	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0x000000ce,
13610	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0x000000cf,
13611	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0x000000d0,
13612	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0x000000d1,
13613	CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0x000000d2,
13614	CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0x000000d3,
13615	CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0x000000d4,
13616	CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000d5,
13617	CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000d6,
13618	CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000d7,
13619	CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000d8,
13620	CB_PERF_SEL_DRAWN_BUSY = 0x000000d9,
13621	CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0x000000da,
13622	CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0x000000db,
13623	CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0x000000dc,
13624	CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0x000000dd,
13625	CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 0x000000de,
13626	CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0x000000df,
13627	CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0x000000e0,
13628	CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0x000000e1,
13629	CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 0x000000e2,
13630	CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0x000000e3,
13631	CB_PERF_SEL_FC_DOC_IS_STALLED = 0x000000e4,
13632	CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0x000000e5,
13633	CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0x000000e6,
13634	CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0x000000e7,
13635	CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0x000000e8,
13636	CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0x000000e9,
13637	CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0x000000ea,
13638	CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0x000000eb,
13639	CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0x000000ec,
13640	CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0x000000ed,
13641	CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0x000000ee,
13642	CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0x000000ef,
13643	CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0x000000f0,
13644	CB_PERF_SEL_FC_DCC_CACHE_HIT = 0x000000f1,
13645	CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0x000000f2,
13646	CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0x000000f3,
13647	CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0x000000f4,
13648	CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x000000f5,
13649	CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x000000f6,
13650	CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x000000f7,
13651	CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0x000000f8,
13652	CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0x000000f9,
13653	CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0x000000fa,
13654	CB_PERF_SEL_FC_DCC_CACHE_STALL = 0x000000fb,
13655	CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0x000000fc,
13656	CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0x000000fd,
13657	CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0x000000fe,
13658	CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x000000ff,
13659	CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x00000100,
13660	CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x00000101,
13661	CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x00000102,
13662	CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x00000103,
13663	CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x00000104,
13664	CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x00000105,
13665	CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x00000106,
13666	CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x00000107,
13667	CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x00000108,
13668	CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x00000109,
13669	CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x0000010a,
13670	CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x0000010b,
13671	CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 0x0000010c,
13672	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x0000010d,
13673	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 0x0000010e,
13674	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 0x0000010f,
13675	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 0x00000110,
13676	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000111,
13677	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000112,
13678	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000113,
13679	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 0x00000114,
13680	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 0x00000115,
13681	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 0x00000116,
13682	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 0x00000117,
13683	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000118,
13684	CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000119,
13685	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x0000011a,
13686	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 0x0000011b,
13687	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 0x0000011c,
13688	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 0x0000011d,
13689	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 0x0000011e,
13690	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x0000011f,
13691	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 0x00000120,
13692	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 0x00000121,
13693	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 0x00000122,
13694	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 0x00000123,
13695	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x00000124,
13696	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 0x00000125,
13697	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 0x00000126,
13698	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 0x00000127,
13699	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 0x00000128,
13700	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 0x00000129,
13701	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 0x0000012a,
13702	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 0x0000012b,
13703	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 0x0000012c,
13704	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 0x0000012d,
13705	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 0x0000012e,
13706	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 0x0000012f,
13707	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 0x00000130,
13708	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 0x00000131,
13709	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 0x00000132,
13710	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 0x00000133,
13711	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 0x00000134,
13712	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 0x00000135,
13713	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 0x00000136,
13714	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 0x00000137,
13715	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 0x00000138,
13716	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 0x00000139,
13717	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013a,
13718	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013b,
13719	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 0x0000013c,
13720	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 0x0000013d,
13721	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013e,
13722	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013f,
13723	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000140,
13724	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000141,
13725	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000142,
13726	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 0x00000143,
13727	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000144,
13728	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000145,
13729	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000146,
13730	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 0x00000147,
13731	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 0x00000148,
13732	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 0x00000149,
13733	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 0x0000014a,
13734	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 0x0000014b,
13735	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 0x0000014c,
13736	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 0x0000014d,
13737	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014e,
13738	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014f,
13739	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000150,
13740	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000151,
13741	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000152,
13742	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000153,
13743	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000154,
13744	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000155,
13745	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 0x00000156,
13746	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 0x00000157,
13747	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 0x00000158,
13748	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 0x00000159,
13749	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 0x0000015a,
13750	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 0x0000015b,
13751	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x0000015c,
13752	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x0000015d,
13753	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 0x0000015e,
13754	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 0x0000015f,
13755	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 0x00000160,
13756	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 0x00000161,
13757	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 0x00000162,
13758	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x00000163,
13759	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x00000164,
13760	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 0x00000165,
13761	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 0x00000166,
13762	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 0x00000167,
13763	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 0x00000168,
13764	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 0x00000169,
13765	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 0x0000016a,
13766	CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x0000016b,
13767	CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x0000016c,
13768	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 0x0000016d,
13769	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 0x0000016e,
13770	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 0x0000016f,
13771	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 0x00000170,
13772	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 0x00000171,
13773	CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x00000172,
13774	CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x00000173,
13775	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x00000174,
13776	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x00000175,
13777	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x00000176,
13778	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x00000177,
13779	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x00000178,
13780	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x00000179,
13781	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x0000017a,
13782	CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x0000017b,
13783	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x0000017c,
13784	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x0000017d,
13785	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x0000017e,
13786	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x0000017f,
13787	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x00000180,
13788	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x00000181,
13789	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x00000182,
13790	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x00000183,
13791	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x00000184,
13792	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x00000185,
13793	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x00000186,
13794	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x00000187,
13795	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x00000188,
13796	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x00000189,
13797	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x0000018a,
13798	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x0000018b,
13799	CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x0000018c,
13800	CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x0000018d,
13801	CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x0000018e,
13802	CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x0000018f,
13803	CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x00000190,
13804	CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x00000191,
13805	CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x00000192,
13806	CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x00000193,
13807	CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x00000194,
13808	} CBPerfSel;
13809
13810	/*
13811	* CBPerfOpFilterSel enum
13812	*/
13813
13814	typedef enum CBPerfOpFilterSel {
13815	CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000,
13816	CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001,
13817	CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002,
13818	CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003,
13819	CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004,
13820	CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005,
13821	} CBPerfOpFilterSel;
13822
13823	/*
13824	* CBPerfClearFilterSel enum
13825	*/
13826
13827	typedef enum CBPerfClearFilterSel {
13828	CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000,
13829	CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001,
13830	} CBPerfClearFilterSel;
13831
13832	/*******************************************************
13833	* TC Enums
13834	*******************************************************/
13835
13836	/*
13837	* TC_OP_MASKS enum
13838	*/
13839
13840	typedef enum TC_OP_MASKS {
13841	TC_OP_MASK_FLUSH_DENROM = 0x00000008,
13842	TC_OP_MASK_64 = 0x00000020,
13843	TC_OP_MASK_NO_RTN = 0x00000040,
13844	} TC_OP_MASKS;
13845
13846	/*
13847	* TC_OP enum
13848	*/
13849
13850	typedef enum TC_OP {
13851	TC_OP_READ = 0x00000000,
13852	TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001,
13853	TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002,
13854	TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003,
13855	TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004,
13856	TC_OP_RESERVED_FOP_RTN_32_1 = 0x00000005,
13857	TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006,
13858	TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007,
13859	TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008,
13860	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
13861	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a,
13862	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b,
13863	TC_OP_PROBE_FILTER = 0x0000000c,
13864	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d,
13865	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
13866	TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f,
13867	TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010,
13868	TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011,
13869	TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012,
13870	TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013,
13871	TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014,
13872	TC_OP_ATOMIC_AND_RTN_32 = 0x00000015,
13873	TC_OP_ATOMIC_OR_RTN_32 = 0x00000016,
13874	TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017,
13875	TC_OP_ATOMIC_INC_RTN_32 = 0x00000018,
13876	TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019,
13877	TC_OP_WBINVL1_VOL = 0x0000001a,
13878	TC_OP_WBINVL1_SD = 0x0000001b,
13879	TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c,
13880	TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d,
13881	TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e,
13882	TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f,
13883	TC_OP_WRITE = 0x00000020,
13884	TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021,
13885	TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022,
13886	TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023,
13887	TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024,
13888	TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025,
13889	TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026,
13890	TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027,
13891	TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028,
13892	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
13893	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a,
13894	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b,
13895	TC_OP_WBINVL2_SD = 0x0000002c,
13896	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d,
13897	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e,
13898	TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f,
13899	TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030,
13900	TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031,
13901	TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032,
13902	TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033,
13903	TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034,
13904	TC_OP_ATOMIC_AND_RTN_64 = 0x00000035,
13905	TC_OP_ATOMIC_OR_RTN_64 = 0x00000036,
13906	TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037,
13907	TC_OP_ATOMIC_INC_RTN_64 = 0x00000038,
13908	TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039,
13909	TC_OP_WBL2_NC = 0x0000003a,
13910	TC_OP_WBL2_WC = 0x0000003b,
13911	TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c,
13912	TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d,
13913	TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e,
13914	TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f,
13915	TC_OP_WBINVL1 = 0x00000040,
13916	TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041,
13917	TC_OP_ATOMIC_FMIN_32 = 0x00000042,
13918	TC_OP_ATOMIC_FMAX_32 = 0x00000043,
13919	TC_OP_RESERVED_FOP_32_0 = 0x00000044,
13920	TC_OP_RESERVED_FOP_32_1 = 0x00000045,
13921	TC_OP_RESERVED_FOP_32_2 = 0x00000046,
13922	TC_OP_ATOMIC_SWAP_32 = 0x00000047,
13923	TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048,
13924	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049,
13925	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a,
13926	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b,
13927	TC_OP_INV_METADATA = 0x0000004c,
13928	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x0000004d,
13929	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e,
13930	TC_OP_ATOMIC_ADD_32 = 0x0000004f,
13931	TC_OP_ATOMIC_SUB_32 = 0x00000050,
13932	TC_OP_ATOMIC_SMIN_32 = 0x00000051,
13933	TC_OP_ATOMIC_UMIN_32 = 0x00000052,
13934	TC_OP_ATOMIC_SMAX_32 = 0x00000053,
13935	TC_OP_ATOMIC_UMAX_32 = 0x00000054,
13936	TC_OP_ATOMIC_AND_32 = 0x00000055,
13937	TC_OP_ATOMIC_OR_32 = 0x00000056,
13938	TC_OP_ATOMIC_XOR_32 = 0x00000057,
13939	TC_OP_ATOMIC_INC_32 = 0x00000058,
13940	TC_OP_ATOMIC_DEC_32 = 0x00000059,
13941	TC_OP_INVL2_NC = 0x0000005a,
13942	TC_OP_NOP_RTN0 = 0x0000005b,
13943	TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c,
13944	TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d,
13945	TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e,
13946	TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f,
13947	TC_OP_WBINVL2 = 0x00000060,
13948	TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061,
13949	TC_OP_ATOMIC_FMIN_64 = 0x00000062,
13950	TC_OP_ATOMIC_FMAX_64 = 0x00000063,
13951	TC_OP_RESERVED_FOP_64_0 = 0x00000064,
13952	TC_OP_RESERVED_FOP_64_1 = 0x00000065,
13953	TC_OP_RESERVED_FOP_64_2 = 0x00000066,
13954	TC_OP_ATOMIC_SWAP_64 = 0x00000067,
13955	TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068,
13956	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069,
13957	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a,
13958	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b,
13959	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c,
13960	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d,
13961	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e,
13962	TC_OP_ATOMIC_ADD_64 = 0x0000006f,
13963	TC_OP_ATOMIC_SUB_64 = 0x00000070,
13964	TC_OP_ATOMIC_SMIN_64 = 0x00000071,
13965	TC_OP_ATOMIC_UMIN_64 = 0x00000072,
13966	TC_OP_ATOMIC_SMAX_64 = 0x00000073,
13967	TC_OP_ATOMIC_UMAX_64 = 0x00000074,
13968	TC_OP_ATOMIC_AND_64 = 0x00000075,
13969	TC_OP_ATOMIC_OR_64 = 0x00000076,
13970	TC_OP_ATOMIC_XOR_64 = 0x00000077,
13971	TC_OP_ATOMIC_INC_64 = 0x00000078,
13972	TC_OP_ATOMIC_DEC_64 = 0x00000079,
13973	TC_OP_WBINVL2_NC = 0x0000007a,
13974	TC_OP_NOP_ACK = 0x0000007b,
13975	TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c,
13976	TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d,
13977	TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e,
13978	TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f,
13979	} TC_OP;
13980
13981	/*
13982	* TC_CHUB_REQ_CREDITS_ENUM enum
13983	*/
13984
13985	typedef enum TC_CHUB_REQ_CREDITS_ENUM {
13986	TC_CHUB_REQ_CREDITS = 0x00000010,
13987	} TC_CHUB_REQ_CREDITS_ENUM;
13988
13989	/*
13990	* CHUB_TC_RET_CREDITS_ENUM enum
13991	*/
13992
13993	typedef enum CHUB_TC_RET_CREDITS_ENUM {
13994	CHUB_TC_RET_CREDITS = 0x00000020,
13995	} CHUB_TC_RET_CREDITS_ENUM;
13996
13997	/*
13998	* TC_NACKS enum
13999	*/
14000
14001	typedef enum TC_NACKS {
14002	TC_NACK_NO_FAULT = 0x00000000,
14003	TC_NACK_PAGE_FAULT = 0x00000001,
14004	TC_NACK_PROTECTION_FAULT = 0x00000002,
14005	TC_NACK_DATA_ERROR = 0x00000003,
14006	} TC_NACKS;
14007
14008	/*
14009	* TC_EA_CID enum
14010	*/
14011
14012	typedef enum TC_EA_CID {
14013	TC_EA_CID_RT = 0x00000000,
14014	TC_EA_CID_FMASK = 0x00000001,
14015	TC_EA_CID_DCC = 0x00000002,
14016	TC_EA_CID_TCPMETA = 0x00000003,
14017	TC_EA_CID_Z = 0x00000004,
14018	TC_EA_CID_STENCIL = 0x00000005,
14019	TC_EA_CID_HTILE = 0x00000006,
14020	TC_EA_CID_MISC = 0x00000007,
14021	TC_EA_CID_TCP = 0x00000008,
14022	TC_EA_CID_SQC = 0x00000009,
14023	TC_EA_CID_CPF = 0x0000000a,
14024	TC_EA_CID_CPG = 0x0000000b,
14025	TC_EA_CID_IA = 0x0000000c,
14026	TC_EA_CID_WD = 0x0000000d,
14027	TC_EA_CID_PA = 0x0000000e,
14028	TC_EA_CID_UTCL2_TPI = 0x0000000f,
14029	} TC_EA_CID;
14030
14031	/*******************************************************
14032	* SPI Enums
14033	*******************************************************/
14034
14035	/*
14036	* SPI_SAMPLE_CNTL enum
14037	*/
14038
14039	typedef enum SPI_SAMPLE_CNTL {
14040	CENTROIDS_ONLY = 0x00000000,
14041	CENTERS_ONLY = 0x00000001,
14042	CENTROIDS_AND_CENTERS = 0x00000002,
14043	UNDEF = 0x00000003,
14044	} SPI_SAMPLE_CNTL;
14045
14046	/*
14047	* SPI_FOG_MODE enum
14048	*/
14049
14050	typedef enum SPI_FOG_MODE {
14051	SPI_FOG_NONE = 0x00000000,
14052	SPI_FOG_EXP = 0x00000001,
14053	SPI_FOG_EXP2 = 0x00000002,
14054	SPI_FOG_LINEAR = 0x00000003,
14055	} SPI_FOG_MODE;
14056
14057	/*
14058	* SPI_PNT_SPRITE_OVERRIDE enum
14059	*/
14060
14061	typedef enum SPI_PNT_SPRITE_OVERRIDE {
14062	SPI_PNT_SPRITE_SEL_0 = 0x00000000,
14063	SPI_PNT_SPRITE_SEL_1 = 0x00000001,
14064	SPI_PNT_SPRITE_SEL_S = 0x00000002,
14065	SPI_PNT_SPRITE_SEL_T = 0x00000003,
14066	SPI_PNT_SPRITE_SEL_NONE = 0x00000004,
14067	} SPI_PNT_SPRITE_OVERRIDE;
14068
14069	/*
14070	* SPI_PERFCNT_SEL enum
14071	*/
14072
14073	typedef enum SPI_PERFCNT_SEL {
14074	SPI_PERF_VS_WINDOW_VALID = 0x00000000,
14075	SPI_PERF_VS_BUSY = 0x00000001,
14076	SPI_PERF_VS_FIRST_WAVE = 0x00000002,
14077	SPI_PERF_VS_LAST_WAVE = 0x00000003,
14078	SPI_PERF_VS_LSHS_DEALLOC = 0x00000004,
14079	SPI_PERF_VS_PC_STALL = 0x00000005,
14080	SPI_PERF_VS_POS0_STALL = 0x00000006,
14081	SPI_PERF_VS_POS1_STALL = 0x00000007,
14082	SPI_PERF_VS_CRAWLER_STALL = 0x00000008,
14083	SPI_PERF_VS_EVENT_WAVE = 0x00000009,
14084	SPI_PERF_VS_WAVE = 0x0000000a,
14085	SPI_PERF_VS_PERS_UPD_FULL0 = 0x0000000b,
14086	SPI_PERF_VS_PERS_UPD_FULL1 = 0x0000000c,
14087	SPI_PERF_VS_LATE_ALLOC_FULL = 0x0000000d,
14088	SPI_PERF_VS_FIRST_SUBGRP = 0x0000000e,
14089	SPI_PERF_VS_LAST_SUBGRP = 0x0000000f,
14090	SPI_PERF_GS_WINDOW_VALID = 0x00000010,
14091	SPI_PERF_GS_BUSY = 0x00000011,
14092	SPI_PERF_GS_CRAWLER_STALL = 0x00000012,
14093	SPI_PERF_GS_EVENT_WAVE = 0x00000013,
14094	SPI_PERF_GS_WAVE = 0x00000014,
14095	SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000015,
14096	SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000016,
14097	SPI_PERF_GS_FIRST_SUBGRP = 0x00000017,
14098	SPI_PERF_GS_LAST_SUBGRP = 0x00000018,
14099	SPI_PERF_ES_WINDOW_VALID = 0x00000019,
14100	SPI_PERF_ES_BUSY = 0x0000001a,
14101	SPI_PERF_ES_CRAWLER_STALL = 0x0000001b,
14102	SPI_PERF_ES_FIRST_WAVE = 0x0000001c,
14103	SPI_PERF_ES_LAST_WAVE = 0x0000001d,
14104	SPI_PERF_ES_LSHS_DEALLOC = 0x0000001e,
14105	SPI_PERF_ES_EVENT_WAVE = 0x0000001f,
14106	SPI_PERF_ES_WAVE = 0x00000020,
14107	SPI_PERF_ES_PERS_UPD_FULL0 = 0x00000021,
14108	SPI_PERF_ES_PERS_UPD_FULL1 = 0x00000022,
14109	SPI_PERF_ES_FIRST_SUBGRP = 0x00000023,
14110	SPI_PERF_ES_LAST_SUBGRP = 0x00000024,
14111	SPI_PERF_HS_WINDOW_VALID = 0x00000025,
14112	SPI_PERF_HS_BUSY = 0x00000026,
14113	SPI_PERF_HS_CRAWLER_STALL = 0x00000027,
14114	SPI_PERF_HS_FIRST_WAVE = 0x00000028,
14115	SPI_PERF_HS_LAST_WAVE = 0x00000029,
14116	SPI_PERF_HS_LSHS_DEALLOC = 0x0000002a,
14117	SPI_PERF_HS_EVENT_WAVE = 0x0000002b,
14118	SPI_PERF_HS_WAVE = 0x0000002c,
14119	SPI_PERF_HS_PERS_UPD_FULL0 = 0x0000002d,
14120	SPI_PERF_HS_PERS_UPD_FULL1 = 0x0000002e,
14121	SPI_PERF_LS_WINDOW_VALID = 0x0000002f,
14122	SPI_PERF_LS_BUSY = 0x00000030,
14123	SPI_PERF_LS_CRAWLER_STALL = 0x00000031,
14124	SPI_PERF_LS_FIRST_WAVE = 0x00000032,
14125	SPI_PERF_LS_LAST_WAVE = 0x00000033,
14126	SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x00000034,
14127	SPI_PERF_LS_EVENT_WAVE = 0x00000035,
14128	SPI_PERF_LS_WAVE = 0x00000036,
14129	SPI_PERF_LS_PERS_UPD_FULL0 = 0x00000037,
14130	SPI_PERF_LS_PERS_UPD_FULL1 = 0x00000038,
14131	SPI_PERF_CSG_WINDOW_VALID = 0x00000039,
14132	SPI_PERF_CSG_BUSY = 0x0000003a,
14133	SPI_PERF_CSG_NUM_THREADGROUPS = 0x0000003b,
14134	SPI_PERF_CSG_CRAWLER_STALL = 0x0000003c,
14135	SPI_PERF_CSG_EVENT_WAVE = 0x0000003d,
14136	SPI_PERF_CSG_WAVE = 0x0000003e,
14137	SPI_PERF_CSN_WINDOW_VALID = 0x0000003f,
14138	SPI_PERF_CSN_BUSY = 0x00000040,
14139	SPI_PERF_CSN_NUM_THREADGROUPS = 0x00000041,
14140	SPI_PERF_CSN_CRAWLER_STALL = 0x00000042,
14141	SPI_PERF_CSN_EVENT_WAVE = 0x00000043,
14142	SPI_PERF_CSN_WAVE = 0x00000044,
14143	SPI_PERF_PS_CTL_WINDOW_VALID = 0x00000045,
14144	SPI_PERF_PS_CTL_BUSY = 0x00000046,
14145	SPI_PERF_PS_CTL_ACTIVE = 0x00000047,
14146	SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x00000048,
14147	SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x00000049,
14148	SPI_PERF_PS_CTL_EVENT_WAVE = 0x0000004a,
14149	SPI_PERF_PS_CTL_WAVE = 0x0000004b,
14150	SPI_PERF_PS_CTL_OPT_WAVE = 0x0000004c,
14151	SPI_PERF_PS_CTL_PASS_BIN0 = 0x0000004d,
14152	SPI_PERF_PS_CTL_PASS_BIN1 = 0x0000004e,
14153	SPI_PERF_PS_CTL_FPOS_BIN2 = 0x0000004f,
14154	SPI_PERF_PS_CTL_PRIM_BIN0 = 0x00000050,
14155	SPI_PERF_PS_CTL_PRIM_BIN1 = 0x00000051,
14156	SPI_PERF_PS_CTL_CNF_BIN2 = 0x00000052,
14157	SPI_PERF_PS_CTL_CNF_BIN3 = 0x00000053,
14158	SPI_PERF_PS_CTL_CRAWLER_STALL = 0x00000054,
14159	SPI_PERF_PS_CTL_LDS_RES_FULL = 0x00000055,
14160	SPI_PERF_PS_PERS_UPD_FULL0 = 0x00000056,
14161	SPI_PERF_PS_PERS_UPD_FULL1 = 0x00000057,
14162	SPI_PERF_PIX_ALLOC_PEND_CNT = 0x00000058,
14163	SPI_PERF_PIX_ALLOC_SCB_STALL = 0x00000059,
14164	SPI_PERF_PIX_ALLOC_DB0_STALL = 0x0000005a,
14165	SPI_PERF_PIX_ALLOC_DB1_STALL = 0x0000005b,
14166	SPI_PERF_PIX_ALLOC_DB2_STALL = 0x0000005c,
14167	SPI_PERF_PIX_ALLOC_DB3_STALL = 0x0000005d,
14168	SPI_PERF_LDS0_PC_VALID = 0x0000005e,
14169	SPI_PERF_LDS1_PC_VALID = 0x0000005f,
14170	SPI_PERF_RA_PIPE_REQ_BIN2 = 0x00000060,
14171	SPI_PERF_RA_TASK_REQ_BIN3 = 0x00000061,
14172	SPI_PERF_RA_WR_CTL_FULL = 0x00000062,
14173	SPI_PERF_RA_REQ_NO_ALLOC = 0x00000063,
14174	SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000064,
14175	SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x00000065,
14176	SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000066,
14177	SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x00000067,
14178	SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000068,
14179	SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x00000069,
14180	SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x0000006a,
14181	SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x0000006b,
14182	SPI_PERF_RA_RES_STALL_PS = 0x0000006c,
14183	SPI_PERF_RA_RES_STALL_VS = 0x0000006d,
14184	SPI_PERF_RA_RES_STALL_GS = 0x0000006e,
14185	SPI_PERF_RA_RES_STALL_ES = 0x0000006f,
14186	SPI_PERF_RA_RES_STALL_HS = 0x00000070,
14187	SPI_PERF_RA_RES_STALL_LS = 0x00000071,
14188	SPI_PERF_RA_RES_STALL_CSG = 0x00000072,
14189	SPI_PERF_RA_RES_STALL_CSN = 0x00000073,
14190	SPI_PERF_RA_TMP_STALL_PS = 0x00000074,
14191	SPI_PERF_RA_TMP_STALL_VS = 0x00000075,
14192	SPI_PERF_RA_TMP_STALL_GS = 0x00000076,
14193	SPI_PERF_RA_TMP_STALL_ES = 0x00000077,
14194	SPI_PERF_RA_TMP_STALL_HS = 0x00000078,
14195	SPI_PERF_RA_TMP_STALL_LS = 0x00000079,
14196	SPI_PERF_RA_TMP_STALL_CSG = 0x0000007a,
14197	SPI_PERF_RA_TMP_STALL_CSN = 0x0000007b,
14198	SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x0000007c,
14199	SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x0000007d,
14200	SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x0000007e,
14201	SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x0000007f,
14202	SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x00000080,
14203	SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x00000081,
14204	SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x00000082,
14205	SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x00000083,
14206	SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x00000084,
14207	SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x00000085,
14208	SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x00000086,
14209	SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x00000087,
14210	SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x00000088,
14211	SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x00000089,
14212	SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x0000008a,
14213	SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x0000008b,
14214	SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x0000008c,
14215	SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x0000008d,
14216	SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x0000008e,
14217	SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x0000008f,
14218	SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x00000090,
14219	SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x00000091,
14220	SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x00000092,
14221	SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x00000093,
14222	SPI_PERF_RA_LDS_CU_FULL_PS = 0x00000094,
14223	SPI_PERF_RA_LDS_CU_FULL_LS = 0x00000095,
14224	SPI_PERF_RA_LDS_CU_FULL_ES = 0x00000096,
14225	SPI_PERF_RA_LDS_CU_FULL_CSG = 0x00000097,
14226	SPI_PERF_RA_LDS_CU_FULL_CSN = 0x00000098,
14227	SPI_PERF_RA_BAR_CU_FULL_HS = 0x00000099,
14228	SPI_PERF_RA_BAR_CU_FULL_CSG = 0x0000009a,
14229	SPI_PERF_RA_BAR_CU_FULL_CSN = 0x0000009b,
14230	SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x0000009c,
14231	SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x0000009d,
14232	SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x0000009e,
14233	SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x0000009f,
14234	SPI_PERF_RA_WVLIM_STALL_PS = 0x000000a0,
14235	SPI_PERF_RA_WVLIM_STALL_VS = 0x000000a1,
14236	SPI_PERF_RA_WVLIM_STALL_GS = 0x000000a2,
14237	SPI_PERF_RA_WVLIM_STALL_ES = 0x000000a3,
14238	SPI_PERF_RA_WVLIM_STALL_HS = 0x000000a4,
14239	SPI_PERF_RA_WVLIM_STALL_LS = 0x000000a5,
14240	SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000a6,
14241	SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000a7,
14242	SPI_PERF_RA_PS_LOCK_NA = 0x000000a8,
14243	SPI_PERF_RA_VS_LOCK = 0x000000a9,
14244	SPI_PERF_RA_GS_LOCK = 0x000000aa,
14245	SPI_PERF_RA_ES_LOCK = 0x000000ab,
14246	SPI_PERF_RA_HS_LOCK = 0x000000ac,
14247	SPI_PERF_RA_LS_LOCK = 0x000000ad,
14248	SPI_PERF_RA_CSG_LOCK = 0x000000ae,
14249	SPI_PERF_RA_CSN_LOCK = 0x000000af,
14250	SPI_PERF_RA_RSV_UPD = 0x000000b0,
14251	SPI_PERF_EXP_ARB_COL_CNT = 0x000000b1,
14252	SPI_PERF_EXP_ARB_PAR_CNT = 0x000000b2,
14253	SPI_PERF_EXP_ARB_POS_CNT = 0x000000b3,
14254	SPI_PERF_EXP_ARB_GDS_CNT = 0x000000b4,
14255	SPI_PERF_CLKGATE_BUSY_STALL = 0x000000b5,
14256	SPI_PERF_CLKGATE_ACTIVE_STALL = 0x000000b6,
14257	SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0x000000b7,
14258	SPI_PERF_CLKGATE_CGTT_DYN_ON = 0x000000b8,
14259	SPI_PERF_CLKGATE_CGTT_REG_ON = 0x000000b9,
14260	SPI_PERF_NUM_VS_POS_EXPORTS = 0x000000ba,
14261	SPI_PERF_NUM_VS_PARAM_EXPORTS = 0x000000bb,
14262	SPI_PERF_NUM_PS_COL_EXPORTS = 0x000000bc,
14263	SPI_PERF_ES_GRP_FIFO_FULL = 0x000000bd,
14264	SPI_PERF_GS_GRP_FIFO_FULL = 0x000000be,
14265	SPI_PERF_HS_GRP_FIFO_FULL = 0x000000bf,
14266	SPI_PERF_LS_GRP_FIFO_FULL = 0x000000c0,
14267	SPI_PERF_VS_ALLOC_CNT = 0x000000c1,
14268	SPI_PERF_VS_LATE_ALLOC_ACCUM = 0x000000c2,
14269	SPI_PERF_PC_ALLOC_CNT = 0x000000c3,
14270	SPI_PERF_PC_ALLOC_ACCUM = 0x000000c4,
14271	} SPI_PERFCNT_SEL;
14272
14273	/*
14274	* SPI_SHADER_FORMAT enum
14275	*/
14276
14277	typedef enum SPI_SHADER_FORMAT {
14278	SPI_SHADER_NONE = 0x00000000,
14279	SPI_SHADER_1COMP = 0x00000001,
14280	SPI_SHADER_2COMP = 0x00000002,
14281	SPI_SHADER_4COMPRESS = 0x00000003,
14282	SPI_SHADER_4COMP = 0x00000004,
14283	} SPI_SHADER_FORMAT;
14284
14285	/*
14286	* SPI_SHADER_EX_FORMAT enum
14287	*/
14288
14289	typedef enum SPI_SHADER_EX_FORMAT {
14290	SPI_SHADER_ZERO = 0x00000000,
14291	SPI_SHADER_32_R = 0x00000001,
14292	SPI_SHADER_32_GR = 0x00000002,
14293	SPI_SHADER_32_AR = 0x00000003,
14294	SPI_SHADER_FP16_ABGR = 0x00000004,
14295	SPI_SHADER_UNORM16_ABGR = 0x00000005,
14296	SPI_SHADER_SNORM16_ABGR = 0x00000006,
14297	SPI_SHADER_UINT16_ABGR = 0x00000007,
14298	SPI_SHADER_SINT16_ABGR = 0x00000008,
14299	SPI_SHADER_32_ABGR = 0x00000009,
14300	} SPI_SHADER_EX_FORMAT;
14301
14302	/*
14303	* CLKGATE_SM_MODE enum
14304	*/
14305
14306	typedef enum CLKGATE_SM_MODE {
14307	ON_SEQ = 0x00000000,
14308	OFF_SEQ = 0x00000001,
14309	PROG_SEQ = 0x00000002,
14310	READ_SEQ = 0x00000003,
14311	SM_MODE_RESERVED = 0x00000004,
14312	} CLKGATE_SM_MODE;
14313
14314	/*
14315	* CLKGATE_BASE_MODE enum
14316	*/
14317
14318	typedef enum CLKGATE_BASE_MODE {
14319	MULT_8 = 0x00000000,
14320	MULT_16 = 0x00000001,
14321	} CLKGATE_BASE_MODE;
14322
14323	/*******************************************************
14324	* SQ Enums
14325	*******************************************************/
14326
14327	/*
14328	* SQ_TEX_CLAMP enum
14329	*/
14330
14331	typedef enum SQ_TEX_CLAMP {
14332	SQ_TEX_WRAP = 0x00000000,
14333	SQ_TEX_MIRROR = 0x00000001,
14334	SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002,
14335	SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003,
14336	SQ_TEX_CLAMP_HALF_BORDER = 0x00000004,
14337	SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005,
14338	SQ_TEX_CLAMP_BORDER = 0x00000006,
14339	SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007,
14340	} SQ_TEX_CLAMP;
14341
14342	/*
14343	* SQ_TEX_XY_FILTER enum
14344	*/
14345
14346	typedef enum SQ_TEX_XY_FILTER {
14347	SQ_TEX_XY_FILTER_POINT = 0x00000000,
14348	SQ_TEX_XY_FILTER_BILINEAR = 0x00000001,
14349	SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002,
14350	SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003,
14351	} SQ_TEX_XY_FILTER;
14352
14353	/*
14354	* SQ_TEX_Z_FILTER enum
14355	*/
14356
14357	typedef enum SQ_TEX_Z_FILTER {
14358	SQ_TEX_Z_FILTER_NONE = 0x00000000,
14359	SQ_TEX_Z_FILTER_POINT = 0x00000001,
14360	SQ_TEX_Z_FILTER_LINEAR = 0x00000002,
14361	} SQ_TEX_Z_FILTER;
14362
14363	/*
14364	* SQ_TEX_MIP_FILTER enum
14365	*/
14366
14367	typedef enum SQ_TEX_MIP_FILTER {
14368	SQ_TEX_MIP_FILTER_NONE = 0x00000000,
14369	SQ_TEX_MIP_FILTER_POINT = 0x00000001,
14370	SQ_TEX_MIP_FILTER_LINEAR = 0x00000002,
14371	SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003,
14372	} SQ_TEX_MIP_FILTER;
14373
14374	/*
14375	* SQ_TEX_ANISO_RATIO enum
14376	*/
14377
14378	typedef enum SQ_TEX_ANISO_RATIO {
14379	SQ_TEX_ANISO_RATIO_1 = 0x00000000,
14380	SQ_TEX_ANISO_RATIO_2 = 0x00000001,
14381	SQ_TEX_ANISO_RATIO_4 = 0x00000002,
14382	SQ_TEX_ANISO_RATIO_8 = 0x00000003,
14383	SQ_TEX_ANISO_RATIO_16 = 0x00000004,
14384	} SQ_TEX_ANISO_RATIO;
14385
14386	/*
14387	* SQ_TEX_DEPTH_COMPARE enum
14388	*/
14389
14390	typedef enum SQ_TEX_DEPTH_COMPARE {
14391	SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000,
14392	SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001,
14393	SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002,
14394	SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003,
14395	SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004,
14396	SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005,
14397	SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006,
14398	SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007,
14399	} SQ_TEX_DEPTH_COMPARE;
14400
14401	/*
14402	* SQ_TEX_BORDER_COLOR enum
14403	*/
14404
14405	typedef enum SQ_TEX_BORDER_COLOR {
14406	SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000,
14407	SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001,
14408	SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002,
14409	SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003,
14410	} SQ_TEX_BORDER_COLOR;
14411
14412	/*
14413	* SQ_RSRC_BUF_TYPE enum
14414	*/
14415
14416	typedef enum SQ_RSRC_BUF_TYPE {
14417	SQ_RSRC_BUF = 0x00000000,
14418	SQ_RSRC_BUF_RSVD_1 = 0x00000001,
14419	SQ_RSRC_BUF_RSVD_2 = 0x00000002,
14420	SQ_RSRC_BUF_RSVD_3 = 0x00000003,
14421	} SQ_RSRC_BUF_TYPE;
14422
14423	/*
14424	* SQ_RSRC_IMG_TYPE enum
14425	*/
14426
14427	typedef enum SQ_RSRC_IMG_TYPE {
14428	SQ_RSRC_IMG_RSVD_0 = 0x00000000,
14429	SQ_RSRC_IMG_RSVD_1 = 0x00000001,
14430	SQ_RSRC_IMG_RSVD_2 = 0x00000002,
14431	SQ_RSRC_IMG_RSVD_3 = 0x00000003,
14432	SQ_RSRC_IMG_RSVD_4 = 0x00000004,
14433	SQ_RSRC_IMG_RSVD_5 = 0x00000005,
14434	SQ_RSRC_IMG_RSVD_6 = 0x00000006,
14435	SQ_RSRC_IMG_RSVD_7 = 0x00000007,
14436	SQ_RSRC_IMG_1D = 0x00000008,
14437	SQ_RSRC_IMG_2D = 0x00000009,
14438	SQ_RSRC_IMG_3D = 0x0000000a,
14439	SQ_RSRC_IMG_CUBE = 0x0000000b,
14440	SQ_RSRC_IMG_1D_ARRAY = 0x0000000c,
14441	SQ_RSRC_IMG_2D_ARRAY = 0x0000000d,
14442	SQ_RSRC_IMG_2D_MSAA = 0x0000000e,
14443	SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f,
14444	} SQ_RSRC_IMG_TYPE;
14445
14446	/*
14447	* SQ_RSRC_FLAT_TYPE enum
14448	*/
14449
14450	typedef enum SQ_RSRC_FLAT_TYPE {
14451	SQ_RSRC_FLAT_RSVD_0 = 0x00000000,
14452	SQ_RSRC_FLAT = 0x00000001,
14453	SQ_RSRC_FLAT_RSVD_2 = 0x00000002,
14454	SQ_RSRC_FLAT_RSVD_3 = 0x00000003,
14455	} SQ_RSRC_FLAT_TYPE;
14456
14457	/*
14458	* SQ_IMG_FILTER_TYPE enum
14459	*/
14460
14461	typedef enum SQ_IMG_FILTER_TYPE {
14462	SQ_IMG_FILTER_MODE_BLEND = 0x00000000,
14463	SQ_IMG_FILTER_MODE_MIN = 0x00000001,
14464	SQ_IMG_FILTER_MODE_MAX = 0x00000002,
14465	} SQ_IMG_FILTER_TYPE;
14466
14467	/*
14468	* SQ_SEL_XYZW01 enum
14469	*/
14470
14471	typedef enum SQ_SEL_XYZW01 {
14472	SQ_SEL_0 = 0x00000000,
14473	SQ_SEL_1 = 0x00000001,
14474	SQ_SEL_RESERVED_0 = 0x00000002,
14475	SQ_SEL_RESERVED_1 = 0x00000003,
14476	SQ_SEL_X = 0x00000004,
14477	SQ_SEL_Y = 0x00000005,
14478	SQ_SEL_Z = 0x00000006,
14479	SQ_SEL_W = 0x00000007,
14480	} SQ_SEL_XYZW01;
14481
14482	/*
14483	* SQ_WAVE_TYPE enum
14484	*/
14485
14486	typedef enum SQ_WAVE_TYPE {
14487	SQ_WAVE_TYPE_PS = 0x00000000,
14488	SQ_WAVE_TYPE_VS = 0x00000001,
14489	SQ_WAVE_TYPE_GS = 0x00000002,
14490	SQ_WAVE_TYPE_ES = 0x00000003,
14491	SQ_WAVE_TYPE_HS = 0x00000004,
14492	SQ_WAVE_TYPE_LS = 0x00000005,
14493	SQ_WAVE_TYPE_CS = 0x00000006,
14494	SQ_WAVE_TYPE_PS1 = 0x00000007,
14495	} SQ_WAVE_TYPE;
14496
14497	/*
14498	* SQ_THREAD_TRACE_TOKEN_TYPE enum
14499	*/
14500
14501	typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
14502	SQ_THREAD_TRACE_TOKEN_MISC = 0x00000000,
14503	SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x00000001,
14504	SQ_THREAD_TRACE_TOKEN_REG = 0x00000002,
14505	SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x00000003,
14506	SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x00000004,
14507	SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x00000005,
14508	SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x00000006,
14509	SQ_THREAD_TRACE_TOKEN_EVENT = 0x00000007,
14510	SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x00000008,
14511	SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x00000009,
14512	SQ_THREAD_TRACE_TOKEN_INST = 0x0000000a,
14513	SQ_THREAD_TRACE_TOKEN_INST_PC = 0x0000000b,
14514	SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0x0000000c,
14515	SQ_THREAD_TRACE_TOKEN_ISSUE = 0x0000000d,
14516	SQ_THREAD_TRACE_TOKEN_PERF = 0x0000000e,
14517	SQ_THREAD_TRACE_TOKEN_REG_CS = 0x0000000f,
14518	} SQ_THREAD_TRACE_TOKEN_TYPE;
14519
14520	/*
14521	* SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum
14522	*/
14523
14524	typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
14525	SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x00000000,
14526	SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x00000001,
14527	SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x00000002,
14528	SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x00000003,
14529	SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x00000004,
14530	SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x00000005,
14531	SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x00000006,
14532	SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x00000007,
14533	} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
14534
14535	/*
14536	* SQ_THREAD_TRACE_INST_TYPE enum
14537	*/
14538
14539	typedef enum SQ_THREAD_TRACE_INST_TYPE {
14540	SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x00000000,
14541	SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x00000001,
14542	SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x00000002,
14543	SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x00000003,
14544	SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x00000004,
14545	SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x00000005,
14546	SQ_THREAD_TRACE_INST_TYPE_LDS = 0x00000006,
14547	SQ_THREAD_TRACE_INST_TYPE_PC = 0x00000007,
14548	SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x00000008,
14549	SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x00000009,
14550	SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0x0000000a,
14551	SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0x0000000b,
14552	SQ_THREAD_TRACE_INST_TYPE_JUMP = 0x0000000c,
14553	SQ_THREAD_TRACE_INST_TYPE_NEXT = 0x0000000d,
14554	SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0x0000000e,
14555	SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0x0000000f,
14556	SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x00000010,
14557	SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x00000011,
14558	SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x00000012,
14559	SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x00000013,
14560	SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x00000014,
14561	SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x00000015,
14562	SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x00000016,
14563	SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x00000017,
14564	SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x00000018,
14565	SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT = 0x00000019,
14566	} SQ_THREAD_TRACE_INST_TYPE;
14567
14568	/*
14569	* SQ_THREAD_TRACE_REG_TYPE enum
14570	*/
14571
14572	typedef enum SQ_THREAD_TRACE_REG_TYPE {
14573	SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x00000000,
14574	SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x00000001,
14575	SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x00000002,
14576	SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x00000003,
14577	SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x00000004,
14578	SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x00000005,
14579	SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x00000006,
14580	SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x00000007,
14581	} SQ_THREAD_TRACE_REG_TYPE;
14582
14583	/*
14584	* SQ_THREAD_TRACE_REG_OP enum
14585	*/
14586
14587	typedef enum SQ_THREAD_TRACE_REG_OP {
14588	SQ_THREAD_TRACE_REG_OP_READ = 0x00000000,
14589	SQ_THREAD_TRACE_REG_OP_WRITE = 0x00000001,
14590	} SQ_THREAD_TRACE_REG_OP;
14591
14592	/*
14593	* SQ_THREAD_TRACE_MODE_SEL enum
14594	*/
14595
14596	typedef enum SQ_THREAD_TRACE_MODE_SEL {
14597	SQ_THREAD_TRACE_MODE_OFF = 0x00000000,
14598	SQ_THREAD_TRACE_MODE_ON = 0x00000001,
14599	} SQ_THREAD_TRACE_MODE_SEL;
14600
14601	/*
14602	* SQ_THREAD_TRACE_CAPTURE_MODE enum
14603	*/
14604
14605	typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
14606	SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x00000000,
14607	SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x00000001,
14608	SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x00000002,
14609	} SQ_THREAD_TRACE_CAPTURE_MODE;
14610
14611	/*
14612	* SQ_THREAD_TRACE_VM_ID_MASK enum
14613	*/
14614
14615	typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
14616	SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x00000000,
14617	SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x00000001,
14618	SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x00000002,
14619	} SQ_THREAD_TRACE_VM_ID_MASK;
14620
14621	/*
14622	* SQ_THREAD_TRACE_WAVE_MASK enum
14623	*/
14624
14625	typedef enum SQ_THREAD_TRACE_WAVE_MASK {
14626	SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x00000000,
14627	SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x00000001,
14628	} SQ_THREAD_TRACE_WAVE_MASK;
14629
14630	/*
14631	* SQ_THREAD_TRACE_ISSUE enum
14632	*/
14633
14634	typedef enum SQ_THREAD_TRACE_ISSUE {
14635	SQ_THREAD_TRACE_ISSUE_NULL = 0x00000000,
14636	SQ_THREAD_TRACE_ISSUE_STALL = 0x00000001,
14637	SQ_THREAD_TRACE_ISSUE_INST = 0x00000002,
14638	SQ_THREAD_TRACE_ISSUE_IMMED = 0x00000003,
14639	} SQ_THREAD_TRACE_ISSUE;
14640
14641	/*
14642	* SQ_THREAD_TRACE_ISSUE_MASK enum
14643	*/
14644
14645	typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
14646	SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x00000000,
14647	SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x00000001,
14648	SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x00000002,
14649	SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x00000003,
14650	} SQ_THREAD_TRACE_ISSUE_MASK;
14651
14652	/*
14653	* SQ_PERF_SEL enum
14654	*/
14655
14656	typedef enum SQ_PERF_SEL {
14657	SQ_PERF_SEL_NONE = 0x00000000,
14658	SQ_PERF_SEL_ACCUM_PREV = 0x00000001,
14659	SQ_PERF_SEL_CYCLES = 0x00000002,
14660	SQ_PERF_SEL_BUSY_CYCLES = 0x00000003,
14661	SQ_PERF_SEL_WAVES = 0x00000004,
14662	SQ_PERF_SEL_LEVEL_WAVES = 0x00000005,
14663	SQ_PERF_SEL_WAVES_EQ_64 = 0x00000006,
14664	SQ_PERF_SEL_WAVES_LT_64 = 0x00000007,
14665	SQ_PERF_SEL_WAVES_LT_48 = 0x00000008,
14666	SQ_PERF_SEL_WAVES_LT_32 = 0x00000009,
14667	SQ_PERF_SEL_WAVES_LT_16 = 0x0000000a,
14668	SQ_PERF_SEL_WAVES_CU = 0x0000000b,
14669	SQ_PERF_SEL_LEVEL_WAVES_CU = 0x0000000c,
14670	SQ_PERF_SEL_BUSY_CU_CYCLES = 0x0000000d,
14671	SQ_PERF_SEL_ITEMS = 0x0000000e,
14672	SQ_PERF_SEL_QUADS = 0x0000000f,
14673	SQ_PERF_SEL_EVENTS = 0x00000010,
14674	SQ_PERF_SEL_SURF_SYNCS = 0x00000011,
14675	SQ_PERF_SEL_TTRACE_REQS = 0x00000012,
14676	SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x00000013,
14677	SQ_PERF_SEL_TTRACE_STALL = 0x00000014,
14678	SQ_PERF_SEL_MSG_CNTR = 0x00000015,
14679	SQ_PERF_SEL_MSG_PERF = 0x00000016,
14680	SQ_PERF_SEL_MSG_GSCNT = 0x00000017,
14681	SQ_PERF_SEL_MSG_INTERRUPT = 0x00000018,
14682	SQ_PERF_SEL_INSTS = 0x00000019,
14683	SQ_PERF_SEL_INSTS_VALU = 0x0000001a,
14684	SQ_PERF_SEL_INSTS_VMEM_WR = 0x0000001b,
14685	SQ_PERF_SEL_INSTS_VMEM_RD = 0x0000001c,
14686	SQ_PERF_SEL_INSTS_VMEM = 0x0000001d,
14687	SQ_PERF_SEL_INSTS_SALU = 0x0000001e,
14688	SQ_PERF_SEL_INSTS_SMEM = 0x0000001f,
14689	SQ_PERF_SEL_INSTS_FLAT = 0x00000020,
14690	SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x00000021,
14691	SQ_PERF_SEL_INSTS_LDS = 0x00000022,
14692	SQ_PERF_SEL_INSTS_GDS = 0x00000023,
14693	SQ_PERF_SEL_INSTS_EXP = 0x00000024,
14694	SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000025,
14695	SQ_PERF_SEL_INSTS_BRANCH = 0x00000026,
14696	SQ_PERF_SEL_INSTS_SENDMSG = 0x00000027,
14697	SQ_PERF_SEL_INSTS_VSKIPPED = 0x00000028,
14698	SQ_PERF_SEL_INST_LEVEL_VMEM = 0x00000029,
14699	SQ_PERF_SEL_INST_LEVEL_SMEM = 0x0000002a,
14700	SQ_PERF_SEL_INST_LEVEL_LDS = 0x0000002b,
14701	SQ_PERF_SEL_INST_LEVEL_GDS = 0x0000002c,
14702	SQ_PERF_SEL_INST_LEVEL_EXP = 0x0000002d,
14703	SQ_PERF_SEL_WAVE_CYCLES = 0x0000002e,
14704	SQ_PERF_SEL_WAVE_READY = 0x0000002f,
14705	SQ_PERF_SEL_WAIT_CNT_VM = 0x00000030,
14706	SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000031,
14707	SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000032,
14708	SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000033,
14709	SQ_PERF_SEL_WAIT_BARRIER = 0x00000034,
14710	SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x00000035,
14711	SQ_PERF_SEL_WAIT_SLEEP = 0x00000036,
14712	SQ_PERF_SEL_WAIT_SLEEP_XNACK = 0x00000037,
14713	SQ_PERF_SEL_WAIT_OTHER = 0x00000038,
14714	SQ_PERF_SEL_WAIT_ANY = 0x00000039,
14715	SQ_PERF_SEL_WAIT_TTRACE = 0x0000003a,
14716	SQ_PERF_SEL_WAIT_IFETCH = 0x0000003b,
14717	SQ_PERF_SEL_WAIT_INST_ANY = 0x0000003c,
14718	SQ_PERF_SEL_WAIT_INST_VMEM = 0x0000003d,
14719	SQ_PERF_SEL_WAIT_INST_SCA = 0x0000003e,
14720	SQ_PERF_SEL_WAIT_INST_LDS = 0x0000003f,
14721	SQ_PERF_SEL_WAIT_INST_VALU = 0x00000040,
14722	SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000041,
14723	SQ_PERF_SEL_WAIT_INST_MISC = 0x00000042,
14724	SQ_PERF_SEL_WAIT_INST_FLAT = 0x00000043,
14725	SQ_PERF_SEL_ACTIVE_INST_ANY = 0x00000044,
14726	SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x00000045,
14727	SQ_PERF_SEL_ACTIVE_INST_LDS = 0x00000046,
14728	SQ_PERF_SEL_ACTIVE_INST_VALU = 0x00000047,
14729	SQ_PERF_SEL_ACTIVE_INST_SCA = 0x00000048,
14730	SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x00000049,
14731	SQ_PERF_SEL_ACTIVE_INST_MISC = 0x0000004a,
14732	SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x0000004b,
14733	SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x0000004c,
14734	SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x0000004d,
14735	SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x0000004e,
14736	SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x0000004f,
14737	SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x00000050,
14738	SQ_PERF_SEL_INST_CYCLES_EXP = 0x00000051,
14739	SQ_PERF_SEL_INST_CYCLES_GDS = 0x00000052,
14740	SQ_PERF_SEL_INST_CYCLES_SMEM = 0x00000053,
14741	SQ_PERF_SEL_INST_CYCLES_SALU = 0x00000054,
14742	SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x00000055,
14743	SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x00000056,
14744	SQ_PERF_SEL_IFETCH = 0x00000057,
14745	SQ_PERF_SEL_IFETCH_LEVEL = 0x00000058,
14746	SQ_PERF_SEL_CBRANCH_FORK = 0x00000059,
14747	SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x0000005a,
14748	SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x0000005b,
14749	SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x0000005c,
14750	SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x0000005d,
14751	SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x0000005e,
14752	SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x0000005f,
14753	SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000060,
14754	SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000061,
14755	SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x00000062,
14756	SQ_PERF_SEL_VALU_DEP_STALL = 0x00000063,
14757	SQ_PERF_SEL_VALU_STARVE = 0x00000064,
14758	SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000065,
14759	SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x00000066,
14760	SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x00000067,
14761	SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x00000068,
14762	SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x00000069,
14763	SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x0000006a,
14764	SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x0000006b,
14765	SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x0000006c,
14766	SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x0000006d,
14767	SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x0000006e,
14768	SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x0000006f,
14769	SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x00000070,
14770	SQ_PERF_SEL_SRC_CD_BUSY = 0x00000071,
14771	SQ_PERF_SEL_PT_POWER_STALL = 0x00000072,
14772	SQ_PERF_SEL_USER0 = 0x00000073,
14773	SQ_PERF_SEL_USER1 = 0x00000074,
14774	SQ_PERF_SEL_USER2 = 0x00000075,
14775	SQ_PERF_SEL_USER3 = 0x00000076,
14776	SQ_PERF_SEL_USER4 = 0x00000077,
14777	SQ_PERF_SEL_USER5 = 0x00000078,
14778	SQ_PERF_SEL_USER6 = 0x00000079,
14779	SQ_PERF_SEL_USER7 = 0x0000007a,
14780	SQ_PERF_SEL_USER8 = 0x0000007b,
14781	SQ_PERF_SEL_USER9 = 0x0000007c,
14782	SQ_PERF_SEL_USER10 = 0x0000007d,
14783	SQ_PERF_SEL_USER11 = 0x0000007e,
14784	SQ_PERF_SEL_USER12 = 0x0000007f,
14785	SQ_PERF_SEL_USER13 = 0x00000080,
14786	SQ_PERF_SEL_USER14 = 0x00000081,
14787	SQ_PERF_SEL_USER15 = 0x00000082,
14788	SQ_PERF_SEL_USER_LEVEL0 = 0x00000083,
14789	SQ_PERF_SEL_USER_LEVEL1 = 0x00000084,
14790	SQ_PERF_SEL_USER_LEVEL2 = 0x00000085,
14791	SQ_PERF_SEL_USER_LEVEL3 = 0x00000086,
14792	SQ_PERF_SEL_USER_LEVEL4 = 0x00000087,
14793	SQ_PERF_SEL_USER_LEVEL5 = 0x00000088,
14794	SQ_PERF_SEL_USER_LEVEL6 = 0x00000089,
14795	SQ_PERF_SEL_USER_LEVEL7 = 0x0000008a,
14796	SQ_PERF_SEL_USER_LEVEL8 = 0x0000008b,
14797	SQ_PERF_SEL_USER_LEVEL9 = 0x0000008c,
14798	SQ_PERF_SEL_USER_LEVEL10 = 0x0000008d,
14799	SQ_PERF_SEL_USER_LEVEL11 = 0x0000008e,
14800	SQ_PERF_SEL_USER_LEVEL12 = 0x0000008f,
14801	SQ_PERF_SEL_USER_LEVEL13 = 0x00000090,
14802	SQ_PERF_SEL_USER_LEVEL14 = 0x00000091,
14803	SQ_PERF_SEL_USER_LEVEL15 = 0x00000092,
14804	SQ_PERF_SEL_POWER_VALU = 0x00000093,
14805	SQ_PERF_SEL_POWER_VALU0 = 0x00000094,
14806	SQ_PERF_SEL_POWER_VALU1 = 0x00000095,
14807	SQ_PERF_SEL_POWER_VALU2 = 0x00000096,
14808	SQ_PERF_SEL_POWER_GPR_RD = 0x00000097,
14809	SQ_PERF_SEL_POWER_GPR_WR = 0x00000098,
14810	SQ_PERF_SEL_POWER_LDS_BUSY = 0x00000099,
14811	SQ_PERF_SEL_POWER_ALU_BUSY = 0x0000009a,
14812	SQ_PERF_SEL_POWER_TEX_BUSY = 0x0000009b,
14813	SQ_PERF_SEL_ACCUM_PREV_HIRES = 0x0000009c,
14814	SQ_PERF_SEL_WAVES_RESTORED = 0x0000009d,
14815	SQ_PERF_SEL_WAVES_SAVED = 0x0000009e,
14816	SQ_PERF_SEL_INSTS_SMEM_NORM = 0x0000009f,
14817	SQ_PERF_SEL_ATC_INSTS_VMEM = 0x000000a0,
14818	SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x000000a1,
14819	SQ_PERF_SEL_ATC_XNACK_FIRST = 0x000000a2,
14820	SQ_PERF_SEL_ATC_XNACK_ALL = 0x000000a3,
14821	SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x000000a4,
14822	SQ_PERF_SEL_ATC_INSTS_SMEM = 0x000000a5,
14823	SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x000000a6,
14824	SQ_PERF_SEL_IFETCH_XNACK = 0x000000a7,
14825	SQ_PERF_SEL_TLB_SHOOTDOWN = 0x000000a8,
14826	SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x000000a9,
14827	SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x000000aa,
14828	SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x000000ab,
14829	SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x000000ac,
14830	SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x000000ad,
14831	SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x000000ae,
14832	SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x000000af,
14833	SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x000000b0,
14834	SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x000000b1,
14835	SQ_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000b2,
14836	SQ_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000b3,
14837	SQ_PERF_SEL_UTCL1_REQUEST = 0x000000b4,
14838	SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b5,
14839	SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b6,
14840	SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b7,
14841	SQ_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b8,
14842	SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b9,
14843	SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000ba,
14844	SQ_PERF_SEL_DUMMY_END = 0x000000bb,
14845	SQ_PERF_SEL_DUMMY_LAST = 0x000000ff,
14846	SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0x00000100,
14847	SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000101,
14848	SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0x00000102,
14849	SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0x00000103,
14850	SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000104,
14851	SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0x00000105,
14852	SQC_PERF_SEL_TC_REQ = 0x00000106,
14853	SQC_PERF_SEL_TC_INST_REQ = 0x00000107,
14854	SQC_PERF_SEL_TC_DATA_READ_REQ = 0x00000108,
14855	SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0x00000109,
14856	SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0x0000010a,
14857	SQC_PERF_SEL_TC_STALL = 0x0000010b,
14858	SQC_PERF_SEL_TC_STARVE = 0x0000010c,
14859	SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000010d,
14860	SQC_PERF_SEL_ICACHE_REQ = 0x0000010e,
14861	SQC_PERF_SEL_ICACHE_HITS = 0x0000010f,
14862	SQC_PERF_SEL_ICACHE_MISSES = 0x00000110,
14863	SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000111,
14864	SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000112,
14865	SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000113,
14866	SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000114,
14867	SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000115,
14868	SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000116,
14869	SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0x00000117,
14870	SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000118,
14871	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0x00000119,
14872	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000011a,
14873	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x0000011b,
14874	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0x0000011c,
14875	SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x0000011d,
14876	SQC_PERF_SEL_ICACHE_PREFETCH_1 = 0x0000011e,
14877	SQC_PERF_SEL_ICACHE_PREFETCH_2 = 0x0000011f,
14878	SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED = 0x00000120,
14879	SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000121,
14880	SQC_PERF_SEL_DCACHE_REQ = 0x00000122,
14881	SQC_PERF_SEL_DCACHE_HITS = 0x00000123,
14882	SQC_PERF_SEL_DCACHE_MISSES = 0x00000124,
14883	SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000125,
14884	SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x00000126,
14885	SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0x00000127,
14886	SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0x00000128,
14887	SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0x00000129,
14888	SQC_PERF_SEL_DCACHE_ATOMIC = 0x0000012a,
14889	SQC_PERF_SEL_DCACHE_VOLATILE = 0x0000012b,
14890	SQC_PERF_SEL_DCACHE_INVAL_INST = 0x0000012c,
14891	SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000012d,
14892	SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0x0000012e,
14893	SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0x0000012f,
14894	SQC_PERF_SEL_DCACHE_WB_INST = 0x00000130,
14895	SQC_PERF_SEL_DCACHE_WB_ASYNC = 0x00000131,
14896	SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0x00000132,
14897	SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0x00000133,
14898	SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000134,
14899	SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x00000135,
14900	SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x00000136,
14901	SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000137,
14902	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000138,
14903	SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0x00000139,
14904	SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0x0000013a,
14905	SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 0x0000013b,
14906	SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0x0000013c,
14907	SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0x0000013d,
14908	SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0x0000013e,
14909	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000013f,
14910	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x00000140,
14911	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0x00000141,
14912	SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000142,
14913	SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000143,
14914	SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000144,
14915	SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000145,
14916	SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000146,
14917	SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000147,
14918	SQC_PERF_SEL_DCACHE_REQ_TIME = 0x00000148,
14919	SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0x00000149,
14920	SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0x0000014a,
14921	SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0x0000014b,
14922	SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x0000014c,
14923	SQC_PERF_SEL_SQ_DCACHE_REQS = 0x0000014d,
14924	SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x0000014e,
14925	SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0x0000014f,
14926	SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000150,
14927	SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000151,
14928	SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000152,
14929	SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000153,
14930	SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000154,
14931	SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0x00000155,
14932	SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0x00000156,
14933	SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0x00000157,
14934	SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000158,
14935	SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000159,
14936	SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0x0000015a,
14937	SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x0000015b,
14938	SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x0000015c,
14939	SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x0000015d,
14940	SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x0000015e,
14941	SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x0000015f,
14942	SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x00000160,
14943	SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x00000161,
14944	SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000162,
14945	SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000163,
14946	SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x00000164,
14947	SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x00000165,
14948	SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x00000166,
14949	SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x00000167,
14950	SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x00000168,
14951	SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x00000169,
14952	SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x0000016a,
14953	SQC_PERF_SEL_DUMMY_LAST = 0x0000016b,
14954	} SQ_PERF_SEL;
14955
14956	/*
14957	* SQ_CAC_POWER_SEL enum
14958	*/
14959
14960	typedef enum SQ_CAC_POWER_SEL {
14961	SQ_CAC_POWER_VALU = 0x00000000,
14962	SQ_CAC_POWER_VALU0 = 0x00000001,
14963	SQ_CAC_POWER_VALU1 = 0x00000002,
14964	SQ_CAC_POWER_VALU2 = 0x00000003,
14965	SQ_CAC_POWER_GPR_RD = 0x00000004,
14966	SQ_CAC_POWER_GPR_WR = 0x00000005,
14967	SQ_CAC_POWER_LDS_BUSY = 0x00000006,
14968	SQ_CAC_POWER_ALU_BUSY = 0x00000007,
14969	SQ_CAC_POWER_TEX_BUSY = 0x00000008,
14970	} SQ_CAC_POWER_SEL;
14971
14972	/*
14973	* SQ_IND_CMD_CMD enum
14974	*/
14975
14976	typedef enum SQ_IND_CMD_CMD {
14977	SQ_IND_CMD_CMD_NULL = 0x00000000,
14978	SQ_IND_CMD_CMD_SETHALT = 0x00000001,
14979	SQ_IND_CMD_CMD_SAVECTX = 0x00000002,
14980	SQ_IND_CMD_CMD_KILL = 0x00000003,
14981	SQ_IND_CMD_CMD_DEBUG = 0x00000004,
14982	SQ_IND_CMD_CMD_TRAP = 0x00000005,
14983	SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006,
14984	SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007,
14985	} SQ_IND_CMD_CMD;
14986
14987	/*
14988	* SQ_IND_CMD_MODE enum
14989	*/
14990
14991	typedef enum SQ_IND_CMD_MODE {
14992	SQ_IND_CMD_MODE_SINGLE = 0x00000000,
14993	SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
14994	SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
14995	SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
14996	SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
14997	} SQ_IND_CMD_MODE;
14998
14999	/*
15000	* SQ_EDC_INFO_SOURCE enum
15001	*/
15002
15003	typedef enum SQ_EDC_INFO_SOURCE {
15004	SQ_EDC_INFO_SOURCE_INVALID = 0x00000000,
15005	SQ_EDC_INFO_SOURCE_INST = 0x00000001,
15006	SQ_EDC_INFO_SOURCE_SGPR = 0x00000002,
15007	SQ_EDC_INFO_SOURCE_VGPR = 0x00000003,
15008	SQ_EDC_INFO_SOURCE_LDS = 0x00000004,
15009	SQ_EDC_INFO_SOURCE_GDS = 0x00000005,
15010	SQ_EDC_INFO_SOURCE_TA = 0x00000006,
15011	} SQ_EDC_INFO_SOURCE;
15012
15013	/*
15014	* SQ_ROUND_MODE enum
15015	*/
15016
15017	typedef enum SQ_ROUND_MODE {
15018	SQ_ROUND_NEAREST_EVEN = 0x00000000,
15019	SQ_ROUND_PLUS_INFINITY = 0x00000001,
15020	SQ_ROUND_MINUS_INFINITY = 0x00000002,
15021	SQ_ROUND_TO_ZERO = 0x00000003,
15022	} SQ_ROUND_MODE;
15023
15024	/*
15025	* SQ_INTERRUPT_WORD_ENCODING enum
15026	*/
15027
15028	typedef enum SQ_INTERRUPT_WORD_ENCODING {
15029	SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x00000000,
15030	SQ_INTERRUPT_WORD_ENCODING_INST = 0x00000001,
15031	SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x00000002,
15032	} SQ_INTERRUPT_WORD_ENCODING;
15033
15034	/*
15035	* ENUM_SQ_EXPORT_RAT_INST enum
15036	*/
15037
15038	typedef enum ENUM_SQ_EXPORT_RAT_INST {
15039	SQ_EXPORT_RAT_INST_NOP = 0x00000000,
15040	SQ_EXPORT_RAT_INST_STORE_TYPED = 0x00000001,
15041	SQ_EXPORT_RAT_INST_STORE_RAW = 0x00000002,
15042	SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x00000003,
15043	SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x00000004,
15044	SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x00000005,
15045	SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x00000006,
15046	SQ_EXPORT_RAT_INST_ADD = 0x00000007,
15047	SQ_EXPORT_RAT_INST_SUB = 0x00000008,
15048	SQ_EXPORT_RAT_INST_RSUB = 0x00000009,
15049	SQ_EXPORT_RAT_INST_MIN_INT = 0x0000000a,
15050	SQ_EXPORT_RAT_INST_MIN_UINT = 0x0000000b,
15051	SQ_EXPORT_RAT_INST_MAX_INT = 0x0000000c,
15052	SQ_EXPORT_RAT_INST_MAX_UINT = 0x0000000d,
15053	SQ_EXPORT_RAT_INST_AND = 0x0000000e,
15054	SQ_EXPORT_RAT_INST_OR = 0x0000000f,
15055	SQ_EXPORT_RAT_INST_XOR = 0x00000010,
15056	SQ_EXPORT_RAT_INST_MSKOR = 0x00000011,
15057	SQ_EXPORT_RAT_INST_INC_UINT = 0x00000012,
15058	SQ_EXPORT_RAT_INST_DEC_UINT = 0x00000013,
15059	SQ_EXPORT_RAT_INST_STORE_DWORD = 0x00000014,
15060	SQ_EXPORT_RAT_INST_STORE_SHORT = 0x00000015,
15061	SQ_EXPORT_RAT_INST_STORE_BYTE = 0x00000016,
15062	SQ_EXPORT_RAT_INST_NOP_RTN = 0x00000020,
15063	SQ_EXPORT_RAT_INST_XCHG_RTN = 0x00000022,
15064	SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x00000023,
15065	SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x00000024,
15066	SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x00000025,
15067	SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x00000026,
15068	SQ_EXPORT_RAT_INST_ADD_RTN = 0x00000027,
15069	SQ_EXPORT_RAT_INST_SUB_RTN = 0x00000028,
15070	SQ_EXPORT_RAT_INST_RSUB_RTN = 0x00000029,
15071	SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x0000002a,
15072	SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x0000002b,
15073	SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x0000002c,
15074	SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x0000002d,
15075	SQ_EXPORT_RAT_INST_AND_RTN = 0x0000002e,
15076	SQ_EXPORT_RAT_INST_OR_RTN = 0x0000002f,
15077	SQ_EXPORT_RAT_INST_XOR_RTN = 0x00000030,
15078	SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x00000031,
15079	SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x00000032,
15080	SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x00000033,
15081	} ENUM_SQ_EXPORT_RAT_INST;
15082
15083	/*
15084	* SQ_IBUF_ST enum
15085	*/
15086
15087	typedef enum SQ_IBUF_ST {
15088	SQ_IBUF_IB_IDLE = 0x00000000,
15089	SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001,
15090	SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002,
15091	SQ_IBUF_IB_LE_4DW = 0x00000003,
15092	SQ_IBUF_IB_WAIT_DRET = 0x00000004,
15093	SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005,
15094	SQ_IBUF_IB_DRET = 0x00000006,
15095	SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007,
15096	} SQ_IBUF_ST;
15097
15098	/*
15099	* SQ_INST_STR_ST enum
15100	*/
15101
15102	typedef enum SQ_INST_STR_ST {
15103	SQ_INST_STR_IB_WAVE_NORML = 0x00000000,
15104	SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001,
15105	SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002,
15106	SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003,
15107	SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x00000004,
15108	SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x00000005,
15109	SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000006,
15110	SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007,
15111	} SQ_INST_STR_ST;
15112
15113	/*
15114	* SQ_WAVE_IB_ECC_ST enum
15115	*/
15116
15117	typedef enum SQ_WAVE_IB_ECC_ST {
15118	SQ_WAVE_IB_ECC_CLEAN = 0x00000000,
15119	SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001,
15120	SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002,
15121	SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003,
15122	} SQ_WAVE_IB_ECC_ST;
15123
15124	/*
15125	* SH_MEM_ADDRESS_MODE enum
15126	*/
15127
15128	typedef enum SH_MEM_ADDRESS_MODE {
15129	SH_MEM_ADDRESS_MODE_64 = 0x00000000,
15130	SH_MEM_ADDRESS_MODE_32 = 0x00000001,
15131	} SH_MEM_ADDRESS_MODE;
15132
15133	/*
15134	* SH_MEM_ALIGNMENT_MODE enum
15135	*/
15136
15137	typedef enum SH_MEM_ALIGNMENT_MODE {
15138	SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000,
15139	SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001,
15140	SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002,
15141	SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003,
15142	} SH_MEM_ALIGNMENT_MODE;
15143
15144	/*
15145	* SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum
15146	*/
15147
15148	typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
15149	SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x00000018,
15150	SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x00000019,
15151	} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
15152
15153	/*
15154	* SQ_LB_CTR_SEL_VALUES enum
15155	*/
15156
15157	typedef enum SQ_LB_CTR_SEL_VALUES {
15158	SQ_LB_CTR_SEL_ALU_CYCLES = 0x00000000,
15159	SQ_LB_CTR_SEL_ALU_STALLS = 0x00000001,
15160	SQ_LB_CTR_SEL_TEX_CYCLES = 0x00000002,
15161	SQ_LB_CTR_SEL_TEX_STALLS = 0x00000003,
15162	SQ_LB_CTR_SEL_SALU_CYCLES = 0x00000004,
15163	SQ_LB_CTR_SEL_SCALAR_STALLS = 0x00000005,
15164	SQ_LB_CTR_SEL_SMEM_CYCLES = 0x00000006,
15165	SQ_LB_CTR_SEL_ICACHE_STALLS = 0x00000007,
15166	SQ_LB_CTR_SEL_DCACHE_STALLS = 0x00000008,
15167	SQ_LB_CTR_SEL_RESERVED0 = 0x00000009,
15168	SQ_LB_CTR_SEL_RESERVED1 = 0x0000000a,
15169	SQ_LB_CTR_SEL_RESERVED2 = 0x0000000b,
15170	SQ_LB_CTR_SEL_RESERVED3 = 0x0000000c,
15171	SQ_LB_CTR_SEL_RESERVED4 = 0x0000000d,
15172	SQ_LB_CTR_SEL_RESERVED5 = 0x0000000e,
15173	SQ_LB_CTR_SEL_RESERVED6 = 0x0000000f,
15174	} SQ_LB_CTR_SEL_VALUES;
15175
15176	/*
15177	* SQ_WAVE_TYPE value
15178	*/
15179
15180	#define SQ_WAVE_TYPE_PS0 0x00000000
15181
15182	/*
15183	* SQIND_PARTITIONS value
15184	*/
15185
15186	#define SQIND_GLOBAL_REGS_OFFSET 0x00000000
15187	#define SQIND_GLOBAL_REGS_SIZE 0x00000008
15188	#define SQIND_LOCAL_REGS_OFFSET 0x00000008
15189	#define SQIND_LOCAL_REGS_SIZE 0x00000008
15190	#define SQIND_WAVE_HWREGS_OFFSET 0x00000010
15191	#define SQIND_WAVE_HWREGS_SIZE 0x000001f0
15192	#define SQIND_WAVE_SGPRS_OFFSET 0x00000200
15193	#define SQIND_WAVE_SGPRS_SIZE 0x00000200
15194	#define SQIND_WAVE_VGPRS_OFFSET 0x00000400
15195	#define SQIND_WAVE_VGPRS_SIZE 0x00000100
15196
15197	/*
15198	* SQ_GFXDEC value
15199	*/
15200
15201	#define SQ_GFXDEC_BEGIN 0x0000a000
15202	#define SQ_GFXDEC_END 0x0000c000
15203	#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a
15204
15205	/*
15206	* SQDEC value
15207	*/
15208
15209	#define SQDEC_BEGIN 0x00002300
15210	#define SQDEC_END 0x000023ff
15211
15212	/*
15213	* SQPERFSDEC value
15214	*/
15215
15216	#define SQPERFSDEC_BEGIN 0x0000d9c0
15217	#define SQPERFSDEC_END 0x0000da40
15218
15219	/*
15220	* SQPERFDDEC value
15221	*/
15222
15223	#define SQPERFDDEC_BEGIN 0x0000d1c0
15224	#define SQPERFDDEC_END 0x0000d240
15225
15226	/*
15227	* SQGFXUDEC value
15228	*/
15229
15230	#define SQGFXUDEC_BEGIN 0x0000c330
15231	#define SQGFXUDEC_END 0x0000c380
15232
15233	/*
15234	* SQPWRDEC value
15235	*/
15236
15237	#define SQPWRDEC_BEGIN 0x0000f08c
15238	#define SQPWRDEC_END 0x0000f094
15239
15240	/*
15241	* SQ_DISPATCHER value
15242	*/
15243
15244	#define SQ_DISPATCHER_GFX_MIN 0x00000010
15245	#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
15246
15247	/*
15248	* SQ_MAX value
15249	*/
15250
15251	#define SQ_MAX_PGM_SGPRS 0x00000068
15252	#define SQ_MAX_PGM_VGPRS 0x00000100
15253
15254	/*
15255	* SQ_THREAD_TRACE_TIME_UNIT value
15256	*/
15257
15258	#define SQ_THREAD_TRACE_TIME_UNIT 0x00000004
15259
15260	/*
15261	* SQ_EXCP_BITS value
15262	*/
15263
15264	#define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000
15265	#define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007
15266	#define SQ_EX_MODE_EXCP_INVALID 0x00000000
15267	#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001
15268	#define SQ_EX_MODE_EXCP_DIV0 0x00000002
15269	#define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003
15270	#define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004
15271	#define SQ_EX_MODE_EXCP_INEXACT 0x00000005
15272	#define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006
15273	#define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007
15274	#define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008
15275
15276	/*
15277	* SQ_EXCP_HI_BITS value
15278	*/
15279
15280	#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000
15281	#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001
15282	#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002
15283
15284	/*
15285	* HW_INSERTED_INST_ID value
15286	*/
15287
15288	#define INST_ID_PRIV_START 0x80000000
15289	#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0
15290	#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1
15291	#define INST_ID_HW_TRAP 0xfffffff2
15292	#define INST_ID_KILL_SEQ 0xfffffff3
15293	#define INST_ID_SPI_WREXEC 0xfffffff4
15294	#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe
15295
15296	/*
15297	* SIMM16_WAITCNT_PARTITIONS value
15298	*/
15299
15300	#define SIMM16_WAITCNT_VM_CNT_START 0x00000000
15301	#define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000004
15302	#define SIMM16_WAITCNT_EXP_CNT_START 0x00000004
15303	#define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003
15304	#define SIMM16_WAITCNT_LGKM_CNT_START 0x00000008
15305	#define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000004
15306	#define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e
15307	#define SIMM16_WAITCNT_VM_CNT_HI_SIZE 0x00000002
15308
15309	/*
15310	* SQ_EDC_FUE_CNTL_BITS value
15311	*/
15312
15313	#define SQ_EDC_FUE_CNTL_SQ 0x00000000
15314	#define SQ_EDC_FUE_CNTL_LDS 0x00000001
15315	#define SQ_EDC_FUE_CNTL_SIMD0 0x00000002
15316	#define SQ_EDC_FUE_CNTL_SIMD1 0x00000003
15317	#define SQ_EDC_FUE_CNTL_SIMD2 0x00000004
15318	#define SQ_EDC_FUE_CNTL_SIMD3 0x00000005
15319	#define SQ_EDC_FUE_CNTL_TA 0x00000006
15320	#define SQ_EDC_FUE_CNTL_TD 0x00000007
15321	#define SQ_EDC_FUE_CNTL_TCP 0x00000008
15322
15323	/*******************************************************
15324	* COMP Enums
15325	*******************************************************/
15326
15327	/*
15328	* CSDATA_TYPE enum
15329	*/
15330
15331	typedef enum CSDATA_TYPE {
15332	CSDATA_TYPE_TG = 0x00000000,
15333	CSDATA_TYPE_STATE = 0x00000001,
15334	CSDATA_TYPE_EVENT = 0x00000002,
15335	CSDATA_TYPE_PRIVATE = 0x00000003,
15336	} CSDATA_TYPE;
15337
15338	/*
15339	* CSDATA_TYPE_WIDTH value
15340	*/
15341
15342	#define CSDATA_TYPE_WIDTH 0x00000002
15343
15344	/*
15345	* CSDATA_ADDR_WIDTH value
15346	*/
15347
15348	#define CSDATA_ADDR_WIDTH 0x00000007
15349
15350	/*
15351	* CSDATA_DATA_WIDTH value
15352	*/
15353
15354	#define CSDATA_DATA_WIDTH 0x00000020
15355
15356	/*******************************************************
15357	* VGT Enums
15358	*******************************************************/
15359
15360	/*
15361	* VGT_OUT_PRIM_TYPE enum
15362	*/
15363
15364	typedef enum VGT_OUT_PRIM_TYPE {
15365	VGT_OUT_POINT = 0x00000000,
15366	VGT_OUT_LINE = 0x00000001,
15367	VGT_OUT_TRI = 0x00000002,
15368	VGT_OUT_RECT_V0 = 0x00000003,
15369	VGT_OUT_RECT_V1 = 0x00000004,
15370	VGT_OUT_RECT_V2 = 0x00000005,
15371	VGT_OUT_RECT_V3 = 0x00000006,
15372	VGT_OUT_2D_RECT = 0x00000007,
15373	VGT_TE_QUAD = 0x00000008,
15374	VGT_TE_PRIM_INDEX_LINE = 0x00000009,
15375	VGT_TE_PRIM_INDEX_TRI = 0x0000000a,
15376	VGT_TE_PRIM_INDEX_QUAD = 0x0000000b,
15377	VGT_OUT_LINE_ADJ = 0x0000000c,
15378	VGT_OUT_TRI_ADJ = 0x0000000d,
15379	VGT_OUT_PATCH = 0x0000000e,
15380	} VGT_OUT_PRIM_TYPE;
15381
15382	/*
15383	* VGT_DI_PRIM_TYPE enum
15384	*/
15385
15386	typedef enum VGT_DI_PRIM_TYPE {
15387	DI_PT_NONE = 0x00000000,
15388	DI_PT_POINTLIST = 0x00000001,
15389	DI_PT_LINELIST = 0x00000002,
15390	DI_PT_LINESTRIP = 0x00000003,
15391	DI_PT_TRILIST = 0x00000004,
15392	DI_PT_TRIFAN = 0x00000005,
15393	DI_PT_TRISTRIP = 0x00000006,
15394	DI_PT_2D_RECTANGLE = 0x00000007,
15395	DI_PT_UNUSED_1 = 0x00000008,
15396	DI_PT_PATCH = 0x00000009,
15397	DI_PT_LINELIST_ADJ = 0x0000000a,
15398	DI_PT_LINESTRIP_ADJ = 0x0000000b,
15399	DI_PT_TRILIST_ADJ = 0x0000000c,
15400	DI_PT_TRISTRIP_ADJ = 0x0000000d,
15401	DI_PT_UNUSED_3 = 0x0000000e,
15402	DI_PT_UNUSED_4 = 0x0000000f,
15403	DI_PT_TRI_WITH_WFLAGS = 0x00000010,
15404	DI_PT_RECTLIST = 0x00000011,
15405	DI_PT_LINELOOP = 0x00000012,
15406	DI_PT_QUADLIST = 0x00000013,
15407	DI_PT_QUADSTRIP = 0x00000014,
15408	DI_PT_POLYGON = 0x00000015,
15409	} VGT_DI_PRIM_TYPE;
15410
15411	/*
15412	* VGT_DI_SOURCE_SELECT enum
15413	*/
15414
15415	typedef enum VGT_DI_SOURCE_SELECT {
15416	DI_SRC_SEL_DMA = 0x00000000,
15417	DI_SRC_SEL_IMMEDIATE = 0x00000001,
15418	DI_SRC_SEL_AUTO_INDEX = 0x00000002,
15419	DI_SRC_SEL_RESERVED = 0x00000003,
15420	} VGT_DI_SOURCE_SELECT;
15421
15422	/*
15423	* VGT_DI_MAJOR_MODE_SELECT enum
15424	*/
15425
15426	typedef enum VGT_DI_MAJOR_MODE_SELECT {
15427	DI_MAJOR_MODE_0 = 0x00000000,
15428	DI_MAJOR_MODE_1 = 0x00000001,
15429	} VGT_DI_MAJOR_MODE_SELECT;
15430
15431	/*
15432	* VGT_DI_INDEX_SIZE enum
15433	*/
15434
15435	typedef enum VGT_DI_INDEX_SIZE {
15436	DI_INDEX_SIZE_16_BIT = 0x00000000,
15437	DI_INDEX_SIZE_32_BIT = 0x00000001,
15438	DI_INDEX_SIZE_8_BIT = 0x00000002,
15439	} VGT_DI_INDEX_SIZE;
15440
15441	/*
15442	* VGT_EVENT_TYPE enum
15443	*/
15444
15445	typedef enum VGT_EVENT_TYPE {
15446	Reserved_0x00 = 0x00000000,
15447	SAMPLE_STREAMOUTSTATS1 = 0x00000001,
15448	SAMPLE_STREAMOUTSTATS2 = 0x00000002,
15449	SAMPLE_STREAMOUTSTATS3 = 0x00000003,
15450	CACHE_FLUSH_TS = 0x00000004,
15451	CONTEXT_DONE = 0x00000005,
15452	CACHE_FLUSH = 0x00000006,
15453	CS_PARTIAL_FLUSH = 0x00000007,
15454	VGT_STREAMOUT_SYNC = 0x00000008,
15455	Reserved_0x09 = 0x00000009,
15456	VGT_STREAMOUT_RESET = 0x0000000a,
15457	END_OF_PIPE_INCR_DE = 0x0000000b,
15458	END_OF_PIPE_IB_END = 0x0000000c,
15459	RST_PIX_CNT = 0x0000000d,
15460	BREAK_BATCH = 0x0000000e,
15461	VS_PARTIAL_FLUSH = 0x0000000f,
15462	PS_PARTIAL_FLUSH = 0x00000010,
15463	FLUSH_HS_OUTPUT = 0x00000011,
15464	FLUSH_DFSM = 0x00000012,
15465	RESET_TO_LOWEST_VGT = 0x00000013,
15466	CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014,
15467	ZPASS_DONE = 0x00000015,
15468	CACHE_FLUSH_AND_INV_EVENT = 0x00000016,
15469	PERFCOUNTER_START = 0x00000017,
15470	PERFCOUNTER_STOP = 0x00000018,
15471	PIPELINESTAT_START = 0x00000019,
15472	PIPELINESTAT_STOP = 0x0000001a,
15473	PERFCOUNTER_SAMPLE = 0x0000001b,
15474	Available_0x1c = 0x0000001c,
15475	Available_0x1d = 0x0000001d,
15476	SAMPLE_PIPELINESTAT = 0x0000001e,
15477	SO_VGTSTREAMOUT_FLUSH = 0x0000001f,
15478	SAMPLE_STREAMOUTSTATS = 0x00000020,
15479	RESET_VTX_CNT = 0x00000021,
15480	BLOCK_CONTEXT_DONE = 0x00000022,
15481	CS_CONTEXT_DONE = 0x00000023,
15482	VGT_FLUSH = 0x00000024,
15483	TGID_ROLLOVER = 0x00000025,
15484	SQ_NON_EVENT = 0x00000026,
15485	SC_SEND_DB_VPZ = 0x00000027,
15486	BOTTOM_OF_PIPE_TS = 0x00000028,
15487	FLUSH_SX_TS = 0x00000029,
15488	DB_CACHE_FLUSH_AND_INV = 0x0000002a,
15489	FLUSH_AND_INV_DB_DATA_TS = 0x0000002b,
15490	FLUSH_AND_INV_DB_META = 0x0000002c,
15491	FLUSH_AND_INV_CB_DATA_TS = 0x0000002d,
15492	FLUSH_AND_INV_CB_META = 0x0000002e,
15493	CS_DONE = 0x0000002f,
15494	PS_DONE = 0x00000030,
15495	FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031,
15496	SX_CB_RAT_ACK_REQUEST = 0x00000032,
15497	THREAD_TRACE_START = 0x00000033,
15498	THREAD_TRACE_STOP = 0x00000034,
15499	THREAD_TRACE_MARKER = 0x00000035,
15500	THREAD_TRACE_FLUSH = 0x00000036,
15501	THREAD_TRACE_FINISH = 0x00000037,
15502	PIXEL_PIPE_STAT_CONTROL = 0x00000038,
15503	PIXEL_PIPE_STAT_DUMP = 0x00000039,
15504	PIXEL_PIPE_STAT_RESET = 0x0000003a,
15505	CONTEXT_SUSPEND = 0x0000003b,
15506	OFFCHIP_HS_DEALLOC = 0x0000003c,
15507	ENABLE_NGG_PIPELINE = 0x0000003d,
15508	ENABLE_LEGACY_PIPELINE = 0x0000003e,
15509	Reserved_0x3f = 0x0000003f,
15510	} VGT_EVENT_TYPE;
15511
15512	/*
15513	* VGT_DMA_SWAP_MODE enum
15514	*/
15515
15516	typedef enum VGT_DMA_SWAP_MODE {
15517	VGT_DMA_SWAP_NONE = 0x00000000,
15518	VGT_DMA_SWAP_16_BIT = 0x00000001,
15519	VGT_DMA_SWAP_32_BIT = 0x00000002,
15520	VGT_DMA_SWAP_WORD = 0x00000003,
15521	} VGT_DMA_SWAP_MODE;
15522
15523	/*
15524	* VGT_INDEX_TYPE_MODE enum
15525	*/
15526
15527	typedef enum VGT_INDEX_TYPE_MODE {
15528	VGT_INDEX_16 = 0x00000000,
15529	VGT_INDEX_32 = 0x00000001,
15530	VGT_INDEX_8 = 0x00000002,
15531	} VGT_INDEX_TYPE_MODE;
15532
15533	/*
15534	* VGT_DMA_BUF_TYPE enum
15535	*/
15536
15537	typedef enum VGT_DMA_BUF_TYPE {
15538	VGT_DMA_BUF_MEM = 0x00000000,
15539	VGT_DMA_BUF_RING = 0x00000001,
15540	VGT_DMA_BUF_SETUP = 0x00000002,
15541	VGT_DMA_PTR_UPDATE = 0x00000003,
15542	} VGT_DMA_BUF_TYPE;
15543
15544	/*
15545	* VGT_OUTPATH_SELECT enum
15546	*/
15547
15548	typedef enum VGT_OUTPATH_SELECT {
15549	VGT_OUTPATH_VTX_REUSE = 0x00000000,
15550	VGT_OUTPATH_TESS_EN = 0x00000001,
15551	VGT_OUTPATH_PASSTHRU = 0x00000002,
15552	VGT_OUTPATH_GS_BLOCK = 0x00000003,
15553	VGT_OUTPATH_HS_BLOCK = 0x00000004,
15554	VGT_OUTPATH_PRIM_GEN = 0x00000005,
15555	} VGT_OUTPATH_SELECT;
15556
15557	/*
15558	* VGT_GRP_PRIM_TYPE enum
15559	*/
15560
15561	typedef enum VGT_GRP_PRIM_TYPE {
15562	VGT_GRP_3D_POINT = 0x00000000,
15563	VGT_GRP_3D_LINE = 0x00000001,
15564	VGT_GRP_3D_TRI = 0x00000002,
15565	VGT_GRP_3D_RECT = 0x00000003,
15566	VGT_GRP_3D_QUAD = 0x00000004,
15567	VGT_GRP_2D_COPY_RECT_V0 = 0x00000005,
15568	VGT_GRP_2D_COPY_RECT_V1 = 0x00000006,
15569	VGT_GRP_2D_COPY_RECT_V2 = 0x00000007,
15570	VGT_GRP_2D_COPY_RECT_V3 = 0x00000008,
15571	VGT_GRP_2D_FILL_RECT = 0x00000009,
15572	VGT_GRP_2D_LINE = 0x0000000a,
15573	VGT_GRP_2D_TRI = 0x0000000b,
15574	VGT_GRP_PRIM_INDEX_LINE = 0x0000000c,
15575	VGT_GRP_PRIM_INDEX_TRI = 0x0000000d,
15576	VGT_GRP_PRIM_INDEX_QUAD = 0x0000000e,
15577	VGT_GRP_3D_LINE_ADJ = 0x0000000f,
15578	VGT_GRP_3D_TRI_ADJ = 0x00000010,
15579	VGT_GRP_3D_PATCH = 0x00000011,
15580	VGT_GRP_2D_RECT = 0x00000012,
15581	} VGT_GRP_PRIM_TYPE;
15582
15583	/*
15584	* VGT_GRP_PRIM_ORDER enum
15585	*/
15586
15587	typedef enum VGT_GRP_PRIM_ORDER {
15588	VGT_GRP_LIST = 0x00000000,
15589	VGT_GRP_STRIP = 0x00000001,
15590	VGT_GRP_FAN = 0x00000002,
15591	VGT_GRP_LOOP = 0x00000003,
15592	VGT_GRP_POLYGON = 0x00000004,
15593	} VGT_GRP_PRIM_ORDER;
15594
15595	/*
15596	* VGT_GROUP_CONV_SEL enum
15597	*/
15598
15599	typedef enum VGT_GROUP_CONV_SEL {
15600	VGT_GRP_INDEX_16 = 0x00000000,
15601	VGT_GRP_INDEX_32 = 0x00000001,
15602	VGT_GRP_UINT_16 = 0x00000002,
15603	VGT_GRP_UINT_32 = 0x00000003,
15604	VGT_GRP_SINT_16 = 0x00000004,
15605	VGT_GRP_SINT_32 = 0x00000005,
15606	VGT_GRP_FLOAT_32 = 0x00000006,
15607	VGT_GRP_AUTO_PRIM = 0x00000007,
15608	VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008,
15609	} VGT_GROUP_CONV_SEL;
15610
15611	/*
15612	* VGT_GS_MODE_TYPE enum
15613	*/
15614
15615	typedef enum VGT_GS_MODE_TYPE {
15616	GS_OFF = 0x00000000,
15617	GS_SCENARIO_A = 0x00000001,
15618	GS_SCENARIO_B = 0x00000002,
15619	GS_SCENARIO_G = 0x00000003,
15620	GS_SCENARIO_C = 0x00000004,
15621	SPRITE_EN = 0x00000005,
15622	} VGT_GS_MODE_TYPE;
15623
15624	/*
15625	* VGT_GS_CUT_MODE enum
15626	*/
15627
15628	typedef enum VGT_GS_CUT_MODE {
15629	GS_CUT_1024 = 0x00000000,
15630	GS_CUT_512 = 0x00000001,
15631	GS_CUT_256 = 0x00000002,
15632	GS_CUT_128 = 0x00000003,
15633	} VGT_GS_CUT_MODE;
15634
15635	/*
15636	* VGT_GS_OUTPRIM_TYPE enum
15637	*/
15638
15639	typedef enum VGT_GS_OUTPRIM_TYPE {
15640	POINTLIST = 0x00000000,
15641	LINESTRIP = 0x00000001,
15642	TRISTRIP = 0x00000002,
15643	RECTLIST = 0x00000003,
15644	} VGT_GS_OUTPRIM_TYPE;
15645
15646	/*
15647	* VGT_CACHE_INVALID_MODE enum
15648	*/
15649
15650	typedef enum VGT_CACHE_INVALID_MODE {
15651	VC_ONLY = 0x00000000,
15652	TC_ONLY = 0x00000001,
15653	VC_AND_TC = 0x00000002,
15654	} VGT_CACHE_INVALID_MODE;
15655
15656	/*
15657	* VGT_TESS_TYPE enum
15658	*/
15659
15660	typedef enum VGT_TESS_TYPE {
15661	TESS_ISOLINE = 0x00000000,
15662	TESS_TRIANGLE = 0x00000001,
15663	TESS_QUAD = 0x00000002,
15664	} VGT_TESS_TYPE;
15665
15666	/*
15667	* VGT_TESS_PARTITION enum
15668	*/
15669
15670	typedef enum VGT_TESS_PARTITION {
15671	PART_INTEGER = 0x00000000,
15672	PART_POW2 = 0x00000001,
15673	PART_FRAC_ODD = 0x00000002,
15674	PART_FRAC_EVEN = 0x00000003,
15675	} VGT_TESS_PARTITION;
15676
15677	/*
15678	* VGT_TESS_TOPOLOGY enum
15679	*/
15680
15681	typedef enum VGT_TESS_TOPOLOGY {
15682	OUTPUT_POINT = 0x00000000,
15683	OUTPUT_LINE = 0x00000001,
15684	OUTPUT_TRIANGLE_CW = 0x00000002,
15685	OUTPUT_TRIANGLE_CCW = 0x00000003,
15686	} VGT_TESS_TOPOLOGY;
15687
15688	/*
15689	* VGT_RDREQ_POLICY enum
15690	*/
15691
15692	typedef enum VGT_RDREQ_POLICY {
15693	VGT_POLICY_LRU = 0x00000000,
15694	VGT_POLICY_STREAM = 0x00000001,
15695	} VGT_RDREQ_POLICY;
15696
15697	/*
15698	* VGT_DIST_MODE enum
15699	*/
15700
15701	typedef enum VGT_DIST_MODE {
15702	NO_DIST = 0x00000000,
15703	PATCHES = 0x00000001,
15704	DONUTS = 0x00000002,
15705	TRAPEZOIDS = 0x00000003,
15706	} VGT_DIST_MODE;
15707
15708	/*
15709	* VGT_STAGES_LS_EN enum
15710	*/
15711
15712	typedef enum VGT_STAGES_LS_EN {
15713	LS_STAGE_OFF = 0x00000000,
15714	LS_STAGE_ON = 0x00000001,
15715	CS_STAGE_ON = 0x00000002,
15716	RESERVED_LS = 0x00000003,
15717	} VGT_STAGES_LS_EN;
15718
15719	/*
15720	* VGT_STAGES_HS_EN enum
15721	*/
15722
15723	typedef enum VGT_STAGES_HS_EN {
15724	HS_STAGE_OFF = 0x00000000,
15725	HS_STAGE_ON = 0x00000001,
15726	} VGT_STAGES_HS_EN;
15727
15728	/*
15729	* VGT_STAGES_ES_EN enum
15730	*/
15731
15732	typedef enum VGT_STAGES_ES_EN {
15733	ES_STAGE_OFF = 0x00000000,
15734	ES_STAGE_DS = 0x00000001,
15735	ES_STAGE_REAL = 0x00000002,
15736	RESERVED_ES = 0x00000003,
15737	} VGT_STAGES_ES_EN;
15738
15739	/*
15740	* VGT_STAGES_GS_EN enum
15741	*/
15742
15743	typedef enum VGT_STAGES_GS_EN {
15744	GS_STAGE_OFF = 0x00000000,
15745	GS_STAGE_ON = 0x00000001,
15746	} VGT_STAGES_GS_EN;
15747
15748	/*
15749	* VGT_STAGES_VS_EN enum
15750	*/
15751
15752	typedef enum VGT_STAGES_VS_EN {
15753	VS_STAGE_REAL = 0x00000000,
15754	VS_STAGE_DS = 0x00000001,
15755	VS_STAGE_COPY_SHADER = 0x00000002,
15756	RESERVED_VS = 0x00000003,
15757	} VGT_STAGES_VS_EN;
15758
15759	/*
15760	* VGT_PERFCOUNT_SELECT enum
15761	*/
15762
15763	typedef enum VGT_PERFCOUNT_SELECT {
15764	vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x00000000,
15765	vgt_perf_VGT_SPI_ESVERT_VALID = 0x00000001,
15766	vgt_perf_VGT_SPI_ESVERT_EOV = 0x00000002,
15767	vgt_perf_VGT_SPI_ESVERT_STALLED = 0x00000003,
15768	vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x00000004,
15769	vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x00000005,
15770	vgt_perf_VGT_SPI_ESVERT_STATIC = 0x00000006,
15771	vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x00000007,
15772	vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x00000008,
15773	vgt_perf_VGT_SPI_GSPRIM_VALID = 0x00000009,
15774	vgt_perf_VGT_SPI_GSPRIM_EOV = 0x0000000a,
15775	vgt_perf_VGT_SPI_GSPRIM_CONT = 0x0000000b,
15776	vgt_perf_VGT_SPI_GSPRIM_STALLED = 0x0000000c,
15777	vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0x0000000d,
15778	vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0x0000000e,
15779	vgt_perf_VGT_SPI_GSPRIM_STATIC = 0x0000000f,
15780	vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000010,
15781	vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x00000011,
15782	vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x00000012,
15783	vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000013,
15784	vgt_perf_VGT_SPI_VSVERT_SEND = 0x00000014,
15785	vgt_perf_VGT_SPI_VSVERT_EOV = 0x00000015,
15786	vgt_perf_VGT_SPI_VSVERT_STALLED = 0x00000016,
15787	vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x00000017,
15788	vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x00000018,
15789	vgt_perf_VGT_SPI_VSVERT_STATIC = 0x00000019,
15790	vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x0000001a,
15791	vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x0000001b,
15792	vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x0000001c,
15793	vgt_perf_VGT_PA_CLIPV_SEND = 0x0000001d,
15794	vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x0000001e,
15795	vgt_perf_VGT_PA_CLIPV_STALLED = 0x0000001f,
15796	vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x00000020,
15797	vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x00000021,
15798	vgt_perf_VGT_PA_CLIPV_STATIC = 0x00000022,
15799	vgt_perf_VGT_PA_CLIPP_SEND = 0x00000023,
15800	vgt_perf_VGT_PA_CLIPP_EOP = 0x00000024,
15801	vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x00000025,
15802	vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x00000026,
15803	vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x00000027,
15804	vgt_perf_VGT_PA_CLIPP_STALLED = 0x00000028,
15805	vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x00000029,
15806	vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x0000002a,
15807	vgt_perf_VGT_PA_CLIPP_STATIC = 0x0000002b,
15808	vgt_perf_VGT_PA_CLIPS_SEND = 0x0000002c,
15809	vgt_perf_VGT_PA_CLIPS_STALLED = 0x0000002d,
15810	vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x0000002e,
15811	vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x0000002f,
15812	vgt_perf_VGT_PA_CLIPS_STATIC = 0x00000030,
15813	vgt_perf_vsvert_ds_send = 0x00000031,
15814	vgt_perf_vsvert_api_send = 0x00000032,
15815	vgt_perf_hs_tif_stall = 0x00000033,
15816	vgt_perf_hs_input_stall = 0x00000034,
15817	vgt_perf_hs_interface_stall = 0x00000035,
15818	vgt_perf_hs_tfm_stall = 0x00000036,
15819	vgt_perf_te11_starved = 0x00000037,
15820	vgt_perf_gs_event_stall = 0x00000038,
15821	vgt_perf_vgt_pa_clipp_send_not_event = 0x00000039,
15822	vgt_perf_vgt_pa_clipp_valid_prim = 0x0000003a,
15823	vgt_perf_reused_es_indices = 0x0000003b,
15824	vgt_perf_vs_cache_hits = 0x0000003c,
15825	vgt_perf_gs_cache_hits = 0x0000003d,
15826	vgt_perf_ds_cache_hits = 0x0000003e,
15827	vgt_perf_total_cache_hits = 0x0000003f,
15828	vgt_perf_vgt_busy = 0x00000040,
15829	vgt_perf_vgt_gs_busy = 0x00000041,
15830	vgt_perf_esvert_stalled_es_tbl = 0x00000042,
15831	vgt_perf_esvert_stalled_gs_tbl = 0x00000043,
15832	vgt_perf_esvert_stalled_gs_event = 0x00000044,
15833	vgt_perf_esvert_stalled_gsprim = 0x00000045,
15834	vgt_perf_gsprim_stalled_es_tbl = 0x00000046,
15835	vgt_perf_gsprim_stalled_gs_tbl = 0x00000047,
15836	vgt_perf_gsprim_stalled_gs_event = 0x00000048,
15837	vgt_perf_gsprim_stalled_esvert = 0x00000049,
15838	vgt_perf_esthread_stalled_es_rb_full = 0x0000004a,
15839	vgt_perf_esthread_stalled_spi_bp = 0x0000004b,
15840	vgt_perf_counters_avail_stalled = 0x0000004c,
15841	vgt_perf_gs_rb_space_avail_stalled = 0x0000004d,
15842	vgt_perf_gs_issue_rtr_stalled = 0x0000004e,
15843	vgt_perf_gsthread_stalled = 0x0000004f,
15844	vgt_perf_strmout_stalled = 0x00000050,
15845	vgt_perf_wait_for_es_done_stalled = 0x00000051,
15846	vgt_perf_cm_stalled_by_gog = 0x00000052,
15847	vgt_perf_cm_reading_stalled = 0x00000053,
15848	vgt_perf_cm_stalled_by_gsfetch_done = 0x00000054,
15849	vgt_perf_gog_vs_tbl_stalled = 0x00000055,
15850	vgt_perf_gog_out_indx_stalled = 0x00000056,
15851	vgt_perf_gog_out_prim_stalled = 0x00000057,
15852	vgt_perf_waveid_stalled = 0x00000058,
15853	vgt_perf_gog_busy = 0x00000059,
15854	vgt_perf_reused_vs_indices = 0x0000005a,
15855	vgt_perf_sclk_reg_vld_event = 0x0000005b,
15856	vgt_perf_vs_conflicting_indices = 0x0000005c,
15857	vgt_perf_sclk_core_vld_event = 0x0000005d,
15858	vgt_perf_hswave_stalled = 0x0000005e,
15859	vgt_perf_sclk_gs_vld_event = 0x0000005f,
15860	vgt_perf_VGT_SPI_LSVERT_VALID = 0x00000060,
15861	vgt_perf_VGT_SPI_LSVERT_EOV = 0x00000061,
15862	vgt_perf_VGT_SPI_LSVERT_STALLED = 0x00000062,
15863	vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x00000063,
15864	vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x00000064,
15865	vgt_perf_VGT_SPI_LSVERT_STATIC = 0x00000065,
15866	vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x00000066,
15867	vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x00000067,
15868	vgt_perf_VGT_SPI_LSWAVE_SEND = 0x00000068,
15869	vgt_perf_VGT_SPI_HSVERT_VALID = 0x00000069,
15870	vgt_perf_VGT_SPI_HSVERT_EOV = 0x0000006a,
15871	vgt_perf_VGT_SPI_HSVERT_STALLED = 0x0000006b,
15872	vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x0000006c,
15873	vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x0000006d,
15874	vgt_perf_VGT_SPI_HSVERT_STATIC = 0x0000006e,
15875	vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x0000006f,
15876	vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x00000070,
15877	vgt_perf_VGT_SPI_HSWAVE_SEND = 0x00000071,
15878	vgt_perf_ds_prims = 0x00000072,
15879	vgt_perf_ds_RESERVED = 0x00000073,
15880	vgt_perf_ls_thread_groups = 0x00000074,
15881	vgt_perf_hs_thread_groups = 0x00000075,
15882	vgt_perf_es_thread_groups = 0x00000076,
15883	vgt_perf_vs_thread_groups = 0x00000077,
15884	vgt_perf_ls_done_latency = 0x00000078,
15885	vgt_perf_hs_done_latency = 0x00000079,
15886	vgt_perf_es_done_latency = 0x0000007a,
15887	vgt_perf_gs_done_latency = 0x0000007b,
15888	vgt_perf_vgt_hs_busy = 0x0000007c,
15889	vgt_perf_vgt_te11_busy = 0x0000007d,
15890	vgt_perf_ls_flush = 0x0000007e,
15891	vgt_perf_hs_flush = 0x0000007f,
15892	vgt_perf_es_flush = 0x00000080,
15893	vgt_perf_vgt_pa_clipp_eopg = 0x00000081,
15894	vgt_perf_ls_done = 0x00000082,
15895	vgt_perf_hs_done = 0x00000083,
15896	vgt_perf_es_done = 0x00000084,
15897	vgt_perf_gs_done = 0x00000085,
15898	vgt_perf_vsfetch_done = 0x00000086,
15899	vgt_perf_gs_done_received = 0x00000087,
15900	vgt_perf_es_ring_high_water_mark = 0x00000088,
15901	vgt_perf_gs_ring_high_water_mark = 0x00000089,
15902	vgt_perf_vs_table_high_water_mark = 0x0000008a,
15903	vgt_perf_hs_tgs_active_high_water_mark = 0x0000008b,
15904	vgt_perf_pa_clipp_dealloc = 0x0000008c,
15905	vgt_perf_cut_mem_flush_stalled = 0x0000008d,
15906	vgt_perf_vsvert_work_received = 0x0000008e,
15907	vgt_perf_vgt_pa_clipp_starved_after_work = 0x0000008f,
15908	vgt_perf_te11_con_starved_after_work = 0x00000090,
15909	vgt_perf_hs_waiting_on_ls_done_stall = 0x00000091,
15910	vgt_spi_vsvert_valid = 0x00000092,
15911	} VGT_PERFCOUNT_SELECT;
15912
15913	/*
15914	* IA_PERFCOUNT_SELECT enum
15915	*/
15916
15917	typedef enum IA_PERFCOUNT_SELECT {
15918	ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x00000000,
15919	ia_perf_dma_data_fifo_full = 0x00000001,
15920	ia_perf_RESERVED1 = 0x00000002,
15921	ia_perf_RESERVED2 = 0x00000003,
15922	ia_perf_RESERVED3 = 0x00000004,
15923	ia_perf_RESERVED4 = 0x00000005,
15924	ia_perf_RESERVED5 = 0x00000006,
15925	ia_perf_MC_LAT_BIN_0 = 0x00000007,
15926	ia_perf_MC_LAT_BIN_1 = 0x00000008,
15927	ia_perf_MC_LAT_BIN_2 = 0x00000009,
15928	ia_perf_MC_LAT_BIN_3 = 0x0000000a,
15929	ia_perf_MC_LAT_BIN_4 = 0x0000000b,
15930	ia_perf_MC_LAT_BIN_5 = 0x0000000c,
15931	ia_perf_MC_LAT_BIN_6 = 0x0000000d,
15932	ia_perf_MC_LAT_BIN_7 = 0x0000000e,
15933	ia_perf_ia_busy = 0x0000000f,
15934	ia_perf_ia_sclk_reg_vld_event = 0x00000010,
15935	ia_perf_RESERVED6 = 0x00000011,
15936	ia_perf_ia_sclk_core_vld_event = 0x00000012,
15937	ia_perf_RESERVED7 = 0x00000013,
15938	ia_perf_ia_dma_return = 0x00000014,
15939	ia_perf_ia_stalled = 0x00000015,
15940	ia_perf_shift_starved_pipe0_event = 0x00000016,
15941	ia_perf_shift_starved_pipe1_event = 0x00000017,
15942	} IA_PERFCOUNT_SELECT;
15943
15944	/*
15945	* WD_PERFCOUNT_SELECT enum
15946	*/
15947
15948	typedef enum WD_PERFCOUNT_SELECT {
15949	wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x00000000,
15950	wd_perf_RBIU_DR_FIFO_STARVED = 0x00000001,
15951	wd_perf_RBIU_DR_FIFO_STALLED = 0x00000002,
15952	wd_perf_RBIU_DI_FIFO_STARVED = 0x00000003,
15953	wd_perf_RBIU_DI_FIFO_STALLED = 0x00000004,
15954	wd_perf_wd_busy = 0x00000005,
15955	wd_perf_wd_sclk_reg_vld_event = 0x00000006,
15956	wd_perf_wd_sclk_input_vld_event = 0x00000007,
15957	wd_perf_wd_sclk_core_vld_event = 0x00000008,
15958	wd_perf_wd_stalled = 0x00000009,
15959	wd_perf_inside_tf_bin_0 = 0x0000000a,
15960	wd_perf_inside_tf_bin_1 = 0x0000000b,
15961	wd_perf_inside_tf_bin_2 = 0x0000000c,
15962	wd_perf_inside_tf_bin_3 = 0x0000000d,
15963	wd_perf_inside_tf_bin_4 = 0x0000000e,
15964	wd_perf_inside_tf_bin_5 = 0x0000000f,
15965	wd_perf_inside_tf_bin_6 = 0x00000010,
15966	wd_perf_inside_tf_bin_7 = 0x00000011,
15967	wd_perf_inside_tf_bin_8 = 0x00000012,
15968	wd_perf_tfreq_lat_bin_0 = 0x00000013,
15969	wd_perf_tfreq_lat_bin_1 = 0x00000014,
15970	wd_perf_tfreq_lat_bin_2 = 0x00000015,
15971	wd_perf_tfreq_lat_bin_3 = 0x00000016,
15972	wd_perf_tfreq_lat_bin_4 = 0x00000017,
15973	wd_perf_tfreq_lat_bin_5 = 0x00000018,
15974	wd_perf_tfreq_lat_bin_6 = 0x00000019,
15975	wd_perf_tfreq_lat_bin_7 = 0x0000001a,
15976	wd_starved_on_hs_done = 0x0000001b,
15977	wd_perf_se0_hs_done_latency = 0x0000001c,
15978	wd_perf_se1_hs_done_latency = 0x0000001d,
15979	wd_perf_se2_hs_done_latency = 0x0000001e,
15980	wd_perf_se3_hs_done_latency = 0x0000001f,
15981	wd_perf_hs_done_se0 = 0x00000020,
15982	wd_perf_hs_done_se1 = 0x00000021,
15983	wd_perf_hs_done_se2 = 0x00000022,
15984	wd_perf_hs_done_se3 = 0x00000023,
15985	wd_perf_null_patches = 0x00000024,
15986	} WD_PERFCOUNT_SELECT;
15987
15988	/*
15989	* WD_IA_DRAW_TYPE enum
15990	*/
15991
15992	typedef enum WD_IA_DRAW_TYPE {
15993	WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000,
15994	WD_IA_DRAW_TYPE_REG_XFER = 0x00000001,
15995	WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002,
15996	WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003,
15997	WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004,
15998	WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005,
15999	WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006,
16000	WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007,
16001	} WD_IA_DRAW_TYPE;
16002
16003	/*
16004	* WD_IA_DRAW_REG_XFER enum
16005	*/
16006
16007	typedef enum WD_IA_DRAW_REG_XFER {
16008	WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000,
16009	WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
16010	} WD_IA_DRAW_REG_XFER;
16011
16012	/*
16013	* WD_IA_DRAW_SOURCE enum
16014	*/
16015
16016	typedef enum WD_IA_DRAW_SOURCE {
16017	WD_IA_DRAW_SOURCE_DMA = 0x00000000,
16018	WD_IA_DRAW_SOURCE_IMMD = 0x00000001,
16019	WD_IA_DRAW_SOURCE_AUTO = 0x00000002,
16020	WD_IA_DRAW_SOURCE_OPAQ = 0x00000003,
16021	} WD_IA_DRAW_SOURCE;
16022
16023	/*
16024	* GS_THREADID_SIZE value
16025	*/
16026
16027	#define GSTHREADID_SIZE 0x00000002
16028
16029	/*******************************************************
16030	* GB Enums
16031	*******************************************************/
16032
16033	/*
16034	* GB_EDC_DED_MODE enum
16035	*/
16036
16037	typedef enum GB_EDC_DED_MODE {
16038	GB_EDC_DED_MODE_LOG = 0x00000000,
16039	GB_EDC_DED_MODE_HALT = 0x00000001,
16040	GB_EDC_DED_MODE_INT_HALT = 0x00000002,
16041	} GB_EDC_DED_MODE;
16042
16043	/*
16044	* VALUE_GB_TILING_CONFIG_TABLE_SIZE value
16045	*/
16046
16047	#define GB_TILING_CONFIG_TABLE_SIZE 0x00000020
16048
16049	/*
16050	* VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value
16051	*/
16052
16053	#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010
16054
16055	/*******************************************************
16056	* TP Enums
16057	*******************************************************/
16058
16059	/*
16060	* TA_TC_ADDR_MODES enum
16061	*/
16062
16063	typedef enum TA_TC_ADDR_MODES {
16064	TA_TC_ADDR_MODE_DEFAULT = 0x00000000,
16065	TA_TC_ADDR_MODE_COMP0 = 0x00000001,
16066	TA_TC_ADDR_MODE_COMP1 = 0x00000002,
16067	TA_TC_ADDR_MODE_COMP2 = 0x00000003,
16068	TA_TC_ADDR_MODE_COMP3 = 0x00000004,
16069	TA_TC_ADDR_MODE_UNALIGNED = 0x00000005,
16070	TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006,
16071	} TA_TC_ADDR_MODES;
16072
16073	/*
16074	* TA_PERFCOUNT_SEL enum
16075	*/
16076
16077	typedef enum TA_PERFCOUNT_SEL {
16078	TA_PERF_SEL_NULL = 0x00000000,
16079	TA_PERF_SEL_sh_fifo_busy = 0x00000001,
16080	TA_PERF_SEL_sh_fifo_cmd_busy = 0x00000002,
16081	TA_PERF_SEL_sh_fifo_addr_busy = 0x00000003,
16082	TA_PERF_SEL_sh_fifo_data_busy = 0x00000004,
16083	TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x00000005,
16084	TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x00000006,
16085	TA_PERF_SEL_gradient_busy = 0x00000007,
16086	TA_PERF_SEL_gradient_fifo_busy = 0x00000008,
16087	TA_PERF_SEL_lod_busy = 0x00000009,
16088	TA_PERF_SEL_lod_fifo_busy = 0x0000000a,
16089	TA_PERF_SEL_addresser_busy = 0x0000000b,
16090	TA_PERF_SEL_addresser_fifo_busy = 0x0000000c,
16091	TA_PERF_SEL_aligner_busy = 0x0000000d,
16092	TA_PERF_SEL_write_path_busy = 0x0000000e,
16093	TA_PERF_SEL_ta_busy = 0x0000000f,
16094	TA_PERF_SEL_sq_ta_cmd_cycles = 0x00000010,
16095	TA_PERF_SEL_sp_ta_addr_cycles = 0x00000011,
16096	TA_PERF_SEL_sp_ta_data_cycles = 0x00000012,
16097	TA_PERF_SEL_ta_fa_data_state_cycles = 0x00000013,
16098	TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014,
16099	TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015,
16100	TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 0x00000016,
16101	TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 0x00000017,
16102	TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 0x00000018,
16103	TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 0x00000019,
16104	TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 0x0000001a,
16105	TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 0x0000001b,
16106	TA_PERF_SEL_RESERVED_28 = 0x0000001c,
16107	TA_PERF_SEL_RESERVED_29 = 0x0000001d,
16108	TA_PERF_SEL_sh_fifo_addr_cycles = 0x0000001e,
16109	TA_PERF_SEL_sh_fifo_data_cycles = 0x0000001f,
16110	TA_PERF_SEL_total_wavefronts = 0x00000020,
16111	TA_PERF_SEL_gradient_cycles = 0x00000021,
16112	TA_PERF_SEL_walker_cycles = 0x00000022,
16113	TA_PERF_SEL_aligner_cycles = 0x00000023,
16114	TA_PERF_SEL_image_wavefronts = 0x00000024,
16115	TA_PERF_SEL_image_read_wavefronts = 0x00000025,
16116	TA_PERF_SEL_image_write_wavefronts = 0x00000026,
16117	TA_PERF_SEL_image_atomic_wavefronts = 0x00000027,
16118	TA_PERF_SEL_image_total_cycles = 0x00000028,
16119	TA_PERF_SEL_RESERVED_41 = 0x00000029,
16120	TA_PERF_SEL_RESERVED_42 = 0x0000002a,
16121	TA_PERF_SEL_RESERVED_43 = 0x0000002b,
16122	TA_PERF_SEL_buffer_wavefronts = 0x0000002c,
16123	TA_PERF_SEL_buffer_read_wavefronts = 0x0000002d,
16124	TA_PERF_SEL_buffer_write_wavefronts = 0x0000002e,
16125	TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f,
16126	TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030,
16127	TA_PERF_SEL_buffer_total_cycles = 0x00000031,
16128	TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 0x00000032,
16129	TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 0x00000033,
16130	TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034,
16131	TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035,
16132	TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036,
16133	TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037,
16134	TA_PERF_SEL_data_stalled_by_tc_cycles = 0x00000038,
16135	TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039,
16136	TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a,
16137	TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b,
16138	TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c,
16139	TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d,
16140	TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e,
16141	TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f,
16142	TA_PERF_SEL_color_1_cycle_pixels = 0x00000040,
16143	TA_PERF_SEL_color_2_cycle_pixels = 0x00000041,
16144	TA_PERF_SEL_color_3_cycle_pixels = 0x00000042,
16145	TA_PERF_SEL_color_4_cycle_pixels = 0x00000043,
16146	TA_PERF_SEL_mip_1_cycle_pixels = 0x00000044,
16147	TA_PERF_SEL_mip_2_cycle_pixels = 0x00000045,
16148	TA_PERF_SEL_vol_1_cycle_pixels = 0x00000046,
16149	TA_PERF_SEL_vol_2_cycle_pixels = 0x00000047,
16150	TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x00000048,
16151	TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049,
16152	TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a,
16153	TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b,
16154	TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c,
16155	TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d,
16156	TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e,
16157	TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f,
16158	TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050,
16159	TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051,
16160	TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052,
16161	TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053,
16162	TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054,
16163	TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055,
16164	TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056,
16165	TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057,
16166	TA_PERF_SEL_mipmap_invalid_samples = 0x00000058,
16167	TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059,
16168	TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a,
16169	TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b,
16170	TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c,
16171	TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d,
16172	TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e,
16173	TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f,
16174	TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060,
16175	TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061,
16176	TA_PERF_SEL_write_path_input_cycles = 0x00000062,
16177	TA_PERF_SEL_write_path_output_cycles = 0x00000063,
16178	TA_PERF_SEL_flat_wavefronts = 0x00000064,
16179	TA_PERF_SEL_flat_read_wavefronts = 0x00000065,
16180	TA_PERF_SEL_flat_write_wavefronts = 0x00000066,
16181	TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067,
16182	TA_PERF_SEL_flat_coalesceable_wavefronts = 0x00000068,
16183	TA_PERF_SEL_reg_sclk_vld = 0x00000069,
16184	TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x0000006a,
16185	TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x0000006b,
16186	TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x0000006c,
16187	TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x0000006d,
16188	TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x0000006e,
16189	TA_PERF_SEL_xnack_on_phase0 = 0x0000006f,
16190	TA_PERF_SEL_xnack_on_phase1 = 0x00000070,
16191	TA_PERF_SEL_xnack_on_phase2 = 0x00000071,
16192	TA_PERF_SEL_xnack_on_phase3 = 0x00000072,
16193	TA_PERF_SEL_first_xnack_on_phase0 = 0x00000073,
16194	TA_PERF_SEL_first_xnack_on_phase1 = 0x00000074,
16195	TA_PERF_SEL_first_xnack_on_phase2 = 0x00000075,
16196	TA_PERF_SEL_first_xnack_on_phase3 = 0x00000076,
16197	} TA_PERFCOUNT_SEL;
16198
16199	/*
16200	* TD_PERFCOUNT_SEL enum
16201	*/
16202
16203	typedef enum TD_PERFCOUNT_SEL {
16204	TD_PERF_SEL_none = 0x00000000,
16205	TD_PERF_SEL_td_busy = 0x00000001,
16206	TD_PERF_SEL_input_busy = 0x00000002,
16207	TD_PERF_SEL_output_busy = 0x00000003,
16208	TD_PERF_SEL_lerp_busy = 0x00000004,
16209	TD_PERF_SEL_reg_sclk_vld = 0x00000005,
16210	TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x00000006,
16211	TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x00000007,
16212	TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x00000008,
16213	TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x00000009,
16214	TD_PERF_SEL_tc_td_fifo_full = 0x0000000a,
16215	TD_PERF_SEL_constant_state_full = 0x0000000b,
16216	TD_PERF_SEL_sample_state_full = 0x0000000c,
16217	TD_PERF_SEL_output_fifo_full = 0x0000000d,
16218	TD_PERF_SEL_RESERVED_14 = 0x0000000e,
16219	TD_PERF_SEL_tc_stall = 0x0000000f,
16220	TD_PERF_SEL_pc_stall = 0x00000010,
16221	TD_PERF_SEL_gds_stall = 0x00000011,
16222	TD_PERF_SEL_RESERVED_18 = 0x00000012,
16223	TD_PERF_SEL_RESERVED_19 = 0x00000013,
16224	TD_PERF_SEL_gather4_wavefront = 0x00000014,
16225	TD_PERF_SEL_gather4h_wavefront = 0x00000015,
16226	TD_PERF_SEL_gather4h_packed_wavefront = 0x00000016,
16227	TD_PERF_SEL_gather8h_packed_wavefront = 0x00000017,
16228	TD_PERF_SEL_sample_c_wavefront = 0x00000018,
16229	TD_PERF_SEL_load_wavefront = 0x00000019,
16230	TD_PERF_SEL_atomic_wavefront = 0x0000001a,
16231	TD_PERF_SEL_store_wavefront = 0x0000001b,
16232	TD_PERF_SEL_ldfptr_wavefront = 0x0000001c,
16233	TD_PERF_SEL_d16_en_wavefront = 0x0000001d,
16234	TD_PERF_SEL_bypass_filter_wavefront = 0x0000001e,
16235	TD_PERF_SEL_min_max_filter_wavefront = 0x0000001f,
16236	TD_PERF_SEL_coalescable_wavefront = 0x00000020,
16237	TD_PERF_SEL_coalesced_phase = 0x00000021,
16238	TD_PERF_SEL_four_phase_wavefront = 0x00000022,
16239	TD_PERF_SEL_eight_phase_wavefront = 0x00000023,
16240	TD_PERF_SEL_sixteen_phase_wavefront = 0x00000024,
16241	TD_PERF_SEL_four_phase_forward_wavefront = 0x00000025,
16242	TD_PERF_SEL_write_ack_wavefront = 0x00000026,
16243	TD_PERF_SEL_RESERVED_39 = 0x00000027,
16244	TD_PERF_SEL_user_defined_border = 0x00000028,
16245	TD_PERF_SEL_white_border = 0x00000029,
16246	TD_PERF_SEL_opaque_black_border = 0x0000002a,
16247	TD_PERF_SEL_RESERVED_43 = 0x0000002b,
16248	TD_PERF_SEL_RESERVED_44 = 0x0000002c,
16249	TD_PERF_SEL_nack = 0x0000002d,
16250	TD_PERF_SEL_td_sp_traffic = 0x0000002e,
16251	TD_PERF_SEL_consume_gds_traffic = 0x0000002f,
16252	TD_PERF_SEL_addresscmd_poison = 0x00000030,
16253	TD_PERF_SEL_data_poison = 0x00000031,
16254	TD_PERF_SEL_start_cycle_0 = 0x00000032,
16255	TD_PERF_SEL_start_cycle_1 = 0x00000033,
16256	TD_PERF_SEL_start_cycle_2 = 0x00000034,
16257	TD_PERF_SEL_start_cycle_3 = 0x00000035,
16258	TD_PERF_SEL_null_cycle_output = 0x00000036,
16259	TD_PERF_SEL_d16_data_packed = 0x00000037,
16260	TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt = 0x00000038,
16261	} TD_PERFCOUNT_SEL;
16262
16263	/*
16264	* TCP_PERFCOUNT_SELECT enum
16265	*/
16266
16267	typedef enum TCP_PERFCOUNT_SELECT {
16268	TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x00000000,
16269	TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x00000001,
16270	TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x00000002,
16271	TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x00000003,
16272	TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x00000004,
16273	TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x00000005,
16274	TCP_PERF_SEL_LOD_STALL_CYCLES = 0x00000006,
16275	TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x00000007,
16276	TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x00000008,
16277	TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x00000009,
16278	TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0x0000000a,
16279	TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0x0000000b,
16280	TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0x0000000c,
16281	TCP_PERF_SEL_TCR_RDRET_STALL = 0x0000000d,
16282	TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0x0000000e,
16283	TCP_PERF_SEL_HOLE_READ_STALL = 0x0000000f,
16284	TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x00000010,
16285	TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x00000011,
16286	TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x00000012,
16287	TCP_PERF_SEL_TCP_LATENCY = 0x00000013,
16288	TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x00000014,
16289	TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x00000015,
16290	TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x00000016,
16291	TCP_PERF_SEL_TCC_READ_REQ = 0x00000017,
16292	TCP_PERF_SEL_TCC_WRITE_REQ = 0x00000018,
16293	TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x00000019,
16294	TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x0000001a,
16295	TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x0000001b,
16296	TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x0000001c,
16297	TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x0000001d,
16298	TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x0000001e,
16299	TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x0000001f,
16300	TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x00000020,
16301	TCP_PERF_SEL_TOTAL_WBINVL1 = 0x00000021,
16302	TCP_PERF_SEL_IMG_READ_FMT_1 = 0x00000022,
16303	TCP_PERF_SEL_IMG_READ_FMT_8 = 0x00000023,
16304	TCP_PERF_SEL_IMG_READ_FMT_16 = 0x00000024,
16305	TCP_PERF_SEL_IMG_READ_FMT_32 = 0x00000025,
16306	TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x00000026,
16307	TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x00000027,
16308	TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x00000028,
16309	TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x00000029,
16310	TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x0000002a,
16311	TCP_PERF_SEL_IMG_READ_FMT_96 = 0x0000002b,
16312	TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x0000002c,
16313	TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x0000002d,
16314	TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x0000002e,
16315	TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x0000002f,
16316	TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x00000030,
16317	TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x00000031,
16318	TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x00000032,
16319	TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x00000033,
16320	TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x00000034,
16321	TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x00000035,
16322	TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x00000036,
16323	TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x00000037,
16324	TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x00000038,
16325	TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x00000039,
16326	TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x0000003a,
16327	TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x0000003b,
16328	TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x0000003c,
16329	TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x0000003d,
16330	TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x0000003e,
16331	TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x0000003f,
16332	TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x00000040,
16333	TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x00000041,
16334	TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x00000042,
16335	TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x00000043,
16336	TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x00000044,
16337	TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x00000045,
16338	TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x00000046,
16339	TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x00000047,
16340	TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x00000048,
16341	TCP_PERF_SEL_BUF_READ_FMT_8 = 0x00000049,
16342	TCP_PERF_SEL_BUF_READ_FMT_16 = 0x0000004a,
16343	TCP_PERF_SEL_BUF_READ_FMT_32 = 0x0000004b,
16344	TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x0000004c,
16345	TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x0000004d,
16346	TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x0000004e,
16347	TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x0000004f,
16348	TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x00000050,
16349	TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x00000051,
16350	TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x00000052,
16351	TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x00000053,
16352	TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x00000054,
16353	TCP_PERF_SEL_ARR_1D_THIN1 = 0x00000055,
16354	TCP_PERF_SEL_ARR_1D_THICK = 0x00000056,
16355	TCP_PERF_SEL_ARR_2D_THIN1 = 0x00000057,
16356	TCP_PERF_SEL_ARR_2D_THICK = 0x00000058,
16357	TCP_PERF_SEL_ARR_2D_XTHICK = 0x00000059,
16358	TCP_PERF_SEL_ARR_3D_THIN1 = 0x0000005a,
16359	TCP_PERF_SEL_ARR_3D_THICK = 0x0000005b,
16360	TCP_PERF_SEL_ARR_3D_XTHICK = 0x0000005c,
16361	TCP_PERF_SEL_DIM_1D = 0x0000005d,
16362	TCP_PERF_SEL_DIM_2D = 0x0000005e,
16363	TCP_PERF_SEL_DIM_3D = 0x0000005f,
16364	TCP_PERF_SEL_DIM_1D_ARRAY = 0x00000060,
16365	TCP_PERF_SEL_DIM_2D_ARRAY = 0x00000061,
16366	TCP_PERF_SEL_DIM_2D_MSAA = 0x00000062,
16367	TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x00000063,
16368	TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x00000064,
16369	TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x00000065,
16370	TCP_PERF_SEL_TA_TCP_STATE_READ = 0x00000066,
16371	TCP_PERF_SEL_TAGRAM0_REQ = 0x00000067,
16372	TCP_PERF_SEL_TAGRAM1_REQ = 0x00000068,
16373	TCP_PERF_SEL_TAGRAM2_REQ = 0x00000069,
16374	TCP_PERF_SEL_TAGRAM3_REQ = 0x0000006a,
16375	TCP_PERF_SEL_GATE_EN1 = 0x0000006b,
16376	TCP_PERF_SEL_GATE_EN2 = 0x0000006c,
16377	TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x0000006d,
16378	TCP_PERF_SEL_TCC_REQ = 0x0000006e,
16379	TCP_PERF_SEL_TCC_NON_READ_REQ = 0x0000006f,
16380	TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x00000070,
16381	TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x00000071,
16382	TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x00000072,
16383	TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x00000073,
16384	TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x00000074,
16385	TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x00000075,
16386	TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x00000076,
16387	TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x00000077,
16388	TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x00000078,
16389	TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x00000079,
16390	TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x0000007a,
16391	TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x0000007b,
16392	TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x0000007c,
16393	TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x0000007d,
16394	TCP_PERF_SEL_TOTAL_ACCESSES = 0x0000007e,
16395	TCP_PERF_SEL_TOTAL_READ = 0x0000007f,
16396	TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x00000080,
16397	TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x00000081,
16398	TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x00000082,
16399	TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x00000083,
16400	TCP_PERF_SEL_TOTAL_NON_READ = 0x00000084,
16401	TCP_PERF_SEL_TOTAL_WRITE = 0x00000085,
16402	TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x00000086,
16403	TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x00000087,
16404	TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x00000088,
16405	TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x00000089,
16406	TCP_PERF_SEL_DISPLAY_MICROTILING = 0x0000008a,
16407	TCP_PERF_SEL_THIN_MICROTILING = 0x0000008b,
16408	TCP_PERF_SEL_DEPTH_MICROTILING = 0x0000008c,
16409	TCP_PERF_SEL_ARR_PRT_THIN1 = 0x0000008d,
16410	TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x0000008e,
16411	TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x0000008f,
16412	TCP_PERF_SEL_ARR_PRT_THICK = 0x00000090,
16413	TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x00000091,
16414	TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x00000092,
16415	TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x00000093,
16416	TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x00000094,
16417	TCP_PERF_SEL_UNALIGNED = 0x00000095,
16418	TCP_PERF_SEL_ROTATED_MICROTILING = 0x00000096,
16419	TCP_PERF_SEL_THICK_MICROTILING = 0x00000097,
16420	TCP_PERF_SEL_ATC = 0x00000098,
16421	TCP_PERF_SEL_POWER_STALL = 0x00000099,
16422	TCP_PERF_SEL_RESERVED_154 = 0x0000009a,
16423	TCP_PERF_SEL_TCC_LRU_REQ = 0x0000009b,
16424	TCP_PERF_SEL_TCC_STREAM_REQ = 0x0000009c,
16425	TCP_PERF_SEL_TCC_NC_READ_REQ = 0x0000009d,
16426	TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x0000009e,
16427	TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x0000009f,
16428	TCP_PERF_SEL_TCC_UC_READ_REQ = 0x000000a0,
16429	TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0x000000a1,
16430	TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0x000000a2,
16431	TCP_PERF_SEL_TCC_CC_READ_REQ = 0x000000a3,
16432	TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0x000000a4,
16433	TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0x000000a5,
16434	TCP_PERF_SEL_TCC_DCC_REQ = 0x000000a6,
16435	TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0x000000a7,
16436	TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x000000a8,
16437	TCP_PERF_SEL_VOLATILE = 0x000000a9,
16438	TCP_PERF_SEL_TC_TA_XNACK_STALL = 0x000000aa,
16439	TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL = 0x000000ab,
16440	TCP_PERF_SEL_SHOOTDOWN = 0x000000ac,
16441	TCP_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000ad,
16442	TCP_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000ae,
16443	TCP_PERF_SEL_UTCL1_REQUEST = 0x000000af,
16444	TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b0,
16445	TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b1,
16446	TCP_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b2,
16447	TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b3,
16448	TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000b4,
16449	TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT = 0x000000b5,
16450	TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b6,
16451	TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 0x000000b7,
16452	TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 0x000000b8,
16453	TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 0x000000b9,
16454	TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 0x000000ba,
16455	TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 0x000000bb,
16456	TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 0x000000bc,
16457	TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 0x000000bd,
16458	TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 0x000000be,
16459	TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 0x000000bf,
16460	TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 0x000000c0,
16461	TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 0x000000c1,
16462	TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 0x000000c2,
16463	TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 0x000000c3,
16464	} TCP_PERFCOUNT_SELECT;
16465
16466	/*
16467	* TCP_CACHE_POLICIES enum
16468	*/
16469
16470	typedef enum TCP_CACHE_POLICIES {
16471	TCP_CACHE_POLICY_MISS_LRU = 0x00000000,
16472	TCP_CACHE_POLICY_MISS_EVICT = 0x00000001,
16473	TCP_CACHE_POLICY_HIT_LRU = 0x00000002,
16474	TCP_CACHE_POLICY_HIT_EVICT = 0x00000003,
16475	} TCP_CACHE_POLICIES;
16476
16477	/*
16478	* TCP_CACHE_STORE_POLICIES enum
16479	*/
16480
16481	typedef enum TCP_CACHE_STORE_POLICIES {
16482	TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000,
16483	TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001,
16484	} TCP_CACHE_STORE_POLICIES;
16485
16486	/*
16487	* TCP_WATCH_MODES enum
16488	*/
16489
16490	typedef enum TCP_WATCH_MODES {
16491	TCP_WATCH_MODE_READ = 0x00000000,
16492	TCP_WATCH_MODE_NONREAD = 0x00000001,
16493	TCP_WATCH_MODE_ATOMIC = 0x00000002,
16494	TCP_WATCH_MODE_ALL = 0x00000003,
16495	} TCP_WATCH_MODES;
16496
16497	/*
16498	* TCP_DSM_DATA_SEL enum
16499	*/
16500
16501	typedef enum TCP_DSM_DATA_SEL {
16502	TCP_DSM_DISABLE = 0x00000000,
16503	TCP_DSM_SEL0 = 0x00000001,
16504	TCP_DSM_SEL1 = 0x00000002,
16505	TCP_DSM_SEL_BOTH = 0x00000003,
16506	} TCP_DSM_DATA_SEL;
16507
16508	/*
16509	* TCP_DSM_SINGLE_WRITE enum
16510	*/
16511
16512	typedef enum TCP_DSM_SINGLE_WRITE {
16513	TCP_DSM_SINGLE_WRITE_DIS = 0x00000000,
16514	TCP_DSM_SINGLE_WRITE_EN = 0x00000001,
16515	} TCP_DSM_SINGLE_WRITE;
16516
16517	/*
16518	* TCP_DSM_INJECT_SEL enum
16519	*/
16520
16521	typedef enum TCP_DSM_INJECT_SEL {
16522	TCP_DSM_INJECT_SEL0 = 0x00000000,
16523	TCP_DSM_INJECT_SEL1 = 0x00000001,
16524	TCP_DSM_INJECT_SEL2 = 0x00000002,
16525	TCP_DSM_INJECT_SEL3 = 0x00000003,
16526	} TCP_DSM_INJECT_SEL;
16527
16528	/*******************************************************
16529	* TCC Enums
16530	*******************************************************/
16531
16532	/*
16533	* TCC_PERF_SEL enum
16534	*/
16535
16536	typedef enum TCC_PERF_SEL {
16537	TCC_PERF_SEL_NONE = 0x00000000,
16538	TCC_PERF_SEL_CYCLE = 0x00000001,
16539	TCC_PERF_SEL_BUSY = 0x00000002,
16540	TCC_PERF_SEL_REQ = 0x00000003,
16541	TCC_PERF_SEL_STREAMING_REQ = 0x00000004,
16542	TCC_PERF_SEL_EXE_REQ = 0x00000005,
16543	TCC_PERF_SEL_COMPRESSED_REQ = 0x00000006,
16544	TCC_PERF_SEL_COMPRESSED_0_REQ = 0x00000007,
16545	TCC_PERF_SEL_METADATA_REQ = 0x00000008,
16546	TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x00000009,
16547	TCC_PERF_SEL_UC_VIRTUAL_REQ = 0x0000000a,
16548	TCC_PERF_SEL_CC_PHYSICAL_REQ = 0x0000000b,
16549	TCC_PERF_SEL_PROBE = 0x0000000c,
16550	TCC_PERF_SEL_PROBE_ALL = 0x0000000d,
16551	TCC_PERF_SEL_READ = 0x0000000e,
16552	TCC_PERF_SEL_WRITE = 0x0000000f,
16553	TCC_PERF_SEL_ATOMIC = 0x00000010,
16554	TCC_PERF_SEL_HIT = 0x00000011,
16555	TCC_PERF_SEL_SECTOR_HIT = 0x00000012,
16556	TCC_PERF_SEL_MISS = 0x00000013,
16557	TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000014,
16558	TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000015,
16559	TCC_PERF_SEL_WRITEBACK = 0x00000016,
16560	TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x00000017,
16561	TCC_PERF_SEL_SRC_FIFO_FULL = 0x00000018,
16562	TCC_PERF_SEL_HOLE_FIFO_FULL = 0x00000019,
16563	TCC_PERF_SEL_EA_WRREQ = 0x0000001a,
16564	TCC_PERF_SEL_EA_WRREQ_64B = 0x0000001b,
16565	TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x0000001c,
16566	TCC_PERF_SEL_EA_WR_UNCACHED_32B = 0x0000001d,
16567	TCC_PERF_SEL_EA_WRREQ_STALL = 0x0000001e,
16568	TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL = 0x0000001f,
16569	TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x00000020,
16570	TCC_PERF_SEL_EA_WRREQ_LEVEL = 0x00000021,
16571	TCC_PERF_SEL_EA_ATOMIC = 0x00000022,
16572	TCC_PERF_SEL_EA_ATOMIC_LEVEL = 0x00000023,
16573	TCC_PERF_SEL_EA_RDREQ = 0x00000024,
16574	TCC_PERF_SEL_EA_RDREQ_32B = 0x00000025,
16575	TCC_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000026,
16576	TCC_PERF_SEL_EA_RD_MDC_32B = 0x00000027,
16577	TCC_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000028,
16578	TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL = 0x00000029,
16579	TCC_PERF_SEL_EA_RDREQ_LEVEL = 0x0000002a,
16580	TCC_PERF_SEL_TAG_STALL = 0x0000002b,
16581	TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000002c,
16582	TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000002d,
16583	TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000002e,
16584	TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000002f,
16585	TCC_PERF_SEL_TAG_PROBE_STALL = 0x00000030,
16586	TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000031,
16587	TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x00000032,
16588	TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x00000033,
16589	TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x00000034,
16590	TCC_PERF_SEL_BUBBLE = 0x00000035,
16591	TCC_PERF_SEL_RETURN_ACK = 0x00000036,
16592	TCC_PERF_SEL_RETURN_DATA = 0x00000037,
16593	TCC_PERF_SEL_RETURN_HOLE = 0x00000038,
16594	TCC_PERF_SEL_RETURN_ACK_HOLE = 0x00000039,
16595	TCC_PERF_SEL_IB_REQ = 0x0000003a,
16596	TCC_PERF_SEL_IB_STALL = 0x0000003b,
16597	TCC_PERF_SEL_IB_TAG_STALL = 0x0000003c,
16598	TCC_PERF_SEL_IB_MDC_STALL = 0x0000003d,
16599	TCC_PERF_SEL_TCA_LEVEL = 0x0000003e,
16600	TCC_PERF_SEL_HOLE_LEVEL = 0x0000003f,
16601	TCC_PERF_SEL_NORMAL_WRITEBACK = 0x00000040,
16602	TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x00000041,
16603	TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK = 0x00000042,
16604	TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x00000043,
16605	TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x00000044,
16606	TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x00000045,
16607	TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x00000046,
16608	TCC_PERF_SEL_NORMAL_EVICT = 0x00000047,
16609	TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x00000048,
16610	TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT = 0x00000049,
16611	TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x0000004a,
16612	TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x0000004b,
16613	TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x0000004c,
16614	TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x0000004d,
16615	TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x0000004e,
16616	TCC_PERF_SEL_PROBE_EVICT = 0x0000004f,
16617	TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x00000050,
16618	TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE = 0x00000051,
16619	TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x00000052,
16620	TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x00000053,
16621	TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x00000054,
16622	TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x00000055,
16623	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x00000056,
16624	TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x00000057,
16625	TCC_PERF_SEL_TC_OP_WBL2_WC_START = 0x00000058,
16626	TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x00000059,
16627	TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x0000005a,
16628	TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x0000005b,
16629	TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x0000005c,
16630	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x0000005d,
16631	TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x0000005e,
16632	TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH = 0x0000005f,
16633	TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x00000060,
16634	TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x00000061,
16635	TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x00000062,
16636	TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x00000063,
16637	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x00000064,
16638	TCC_PERF_SEL_MDC_REQ = 0x00000065,
16639	TCC_PERF_SEL_MDC_LEVEL = 0x00000066,
16640	TCC_PERF_SEL_MDC_TAG_HIT = 0x00000067,
16641	TCC_PERF_SEL_MDC_SECTOR_HIT = 0x00000068,
16642	TCC_PERF_SEL_MDC_SECTOR_MISS = 0x00000069,
16643	TCC_PERF_SEL_MDC_TAG_STALL = 0x0000006a,
16644	TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x0000006b,
16645	TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x0000006c,
16646	TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x0000006d,
16647	TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x0000006e,
16648	TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x0000006f,
16649	TCC_PERF_SEL_CLIENT0_REQ = 0x00000080,
16650	TCC_PERF_SEL_CLIENT1_REQ = 0x00000081,
16651	TCC_PERF_SEL_CLIENT2_REQ = 0x00000082,
16652	TCC_PERF_SEL_CLIENT3_REQ = 0x00000083,
16653	TCC_PERF_SEL_CLIENT4_REQ = 0x00000084,
16654	TCC_PERF_SEL_CLIENT5_REQ = 0x00000085,
16655	TCC_PERF_SEL_CLIENT6_REQ = 0x00000086,
16656	TCC_PERF_SEL_CLIENT7_REQ = 0x00000087,
16657	TCC_PERF_SEL_CLIENT8_REQ = 0x00000088,
16658	TCC_PERF_SEL_CLIENT9_REQ = 0x00000089,
16659	TCC_PERF_SEL_CLIENT10_REQ = 0x0000008a,
16660	TCC_PERF_SEL_CLIENT11_REQ = 0x0000008b,
16661	TCC_PERF_SEL_CLIENT12_REQ = 0x0000008c,
16662	TCC_PERF_SEL_CLIENT13_REQ = 0x0000008d,
16663	TCC_PERF_SEL_CLIENT14_REQ = 0x0000008e,
16664	TCC_PERF_SEL_CLIENT15_REQ = 0x0000008f,
16665	TCC_PERF_SEL_CLIENT16_REQ = 0x00000090,
16666	TCC_PERF_SEL_CLIENT17_REQ = 0x00000091,
16667	TCC_PERF_SEL_CLIENT18_REQ = 0x00000092,
16668	TCC_PERF_SEL_CLIENT19_REQ = 0x00000093,
16669	TCC_PERF_SEL_CLIENT20_REQ = 0x00000094,
16670	TCC_PERF_SEL_CLIENT21_REQ = 0x00000095,
16671	TCC_PERF_SEL_CLIENT22_REQ = 0x00000096,
16672	TCC_PERF_SEL_CLIENT23_REQ = 0x00000097,
16673	TCC_PERF_SEL_CLIENT24_REQ = 0x00000098,
16674	TCC_PERF_SEL_CLIENT25_REQ = 0x00000099,
16675	TCC_PERF_SEL_CLIENT26_REQ = 0x0000009a,
16676	TCC_PERF_SEL_CLIENT27_REQ = 0x0000009b,
16677	TCC_PERF_SEL_CLIENT28_REQ = 0x0000009c,
16678	TCC_PERF_SEL_CLIENT29_REQ = 0x0000009d,
16679	TCC_PERF_SEL_CLIENT30_REQ = 0x0000009e,
16680	TCC_PERF_SEL_CLIENT31_REQ = 0x0000009f,
16681	TCC_PERF_SEL_CLIENT32_REQ = 0x000000a0,
16682	TCC_PERF_SEL_CLIENT33_REQ = 0x000000a1,
16683	TCC_PERF_SEL_CLIENT34_REQ = 0x000000a2,
16684	TCC_PERF_SEL_CLIENT35_REQ = 0x000000a3,
16685	TCC_PERF_SEL_CLIENT36_REQ = 0x000000a4,
16686	TCC_PERF_SEL_CLIENT37_REQ = 0x000000a5,
16687	TCC_PERF_SEL_CLIENT38_REQ = 0x000000a6,
16688	TCC_PERF_SEL_CLIENT39_REQ = 0x000000a7,
16689	TCC_PERF_SEL_CLIENT40_REQ = 0x000000a8,
16690	TCC_PERF_SEL_CLIENT41_REQ = 0x000000a9,
16691	TCC_PERF_SEL_CLIENT42_REQ = 0x000000aa,
16692	TCC_PERF_SEL_CLIENT43_REQ = 0x000000ab,
16693	TCC_PERF_SEL_CLIENT44_REQ = 0x000000ac,
16694	TCC_PERF_SEL_CLIENT45_REQ = 0x000000ad,
16695	TCC_PERF_SEL_CLIENT46_REQ = 0x000000ae,
16696	TCC_PERF_SEL_CLIENT47_REQ = 0x000000af,
16697	TCC_PERF_SEL_CLIENT48_REQ = 0x000000b0,
16698	TCC_PERF_SEL_CLIENT49_REQ = 0x000000b1,
16699	TCC_PERF_SEL_CLIENT50_REQ = 0x000000b2,
16700	TCC_PERF_SEL_CLIENT51_REQ = 0x000000b3,
16701	TCC_PERF_SEL_CLIENT52_REQ = 0x000000b4,
16702	TCC_PERF_SEL_CLIENT53_REQ = 0x000000b5,
16703	TCC_PERF_SEL_CLIENT54_REQ = 0x000000b6,
16704	TCC_PERF_SEL_CLIENT55_REQ = 0x000000b7,
16705	TCC_PERF_SEL_CLIENT56_REQ = 0x000000b8,
16706	TCC_PERF_SEL_CLIENT57_REQ = 0x000000b9,
16707	TCC_PERF_SEL_CLIENT58_REQ = 0x000000ba,
16708	TCC_PERF_SEL_CLIENT59_REQ = 0x000000bb,
16709	TCC_PERF_SEL_CLIENT60_REQ = 0x000000bc,
16710	TCC_PERF_SEL_CLIENT61_REQ = 0x000000bd,
16711	TCC_PERF_SEL_CLIENT62_REQ = 0x000000be,
16712	TCC_PERF_SEL_CLIENT63_REQ = 0x000000bf,
16713	TCC_PERF_SEL_CLIENT64_REQ = 0x000000c0,
16714	TCC_PERF_SEL_CLIENT65_REQ = 0x000000c1,
16715	TCC_PERF_SEL_CLIENT66_REQ = 0x000000c2,
16716	TCC_PERF_SEL_CLIENT67_REQ = 0x000000c3,
16717	TCC_PERF_SEL_CLIENT68_REQ = 0x000000c4,
16718	TCC_PERF_SEL_CLIENT69_REQ = 0x000000c5,
16719	TCC_PERF_SEL_CLIENT70_REQ = 0x000000c6,
16720	TCC_PERF_SEL_CLIENT71_REQ = 0x000000c7,
16721	TCC_PERF_SEL_CLIENT72_REQ = 0x000000c8,
16722	TCC_PERF_SEL_CLIENT73_REQ = 0x000000c9,
16723	TCC_PERF_SEL_CLIENT74_REQ = 0x000000ca,
16724	TCC_PERF_SEL_CLIENT75_REQ = 0x000000cb,
16725	TCC_PERF_SEL_CLIENT76_REQ = 0x000000cc,
16726	TCC_PERF_SEL_CLIENT77_REQ = 0x000000cd,
16727	TCC_PERF_SEL_CLIENT78_REQ = 0x000000ce,
16728	TCC_PERF_SEL_CLIENT79_REQ = 0x000000cf,
16729	TCC_PERF_SEL_CLIENT80_REQ = 0x000000d0,
16730	TCC_PERF_SEL_CLIENT81_REQ = 0x000000d1,
16731	TCC_PERF_SEL_CLIENT82_REQ = 0x000000d2,
16732	TCC_PERF_SEL_CLIENT83_REQ = 0x000000d3,
16733	TCC_PERF_SEL_CLIENT84_REQ = 0x000000d4,
16734	TCC_PERF_SEL_CLIENT85_REQ = 0x000000d5,
16735	TCC_PERF_SEL_CLIENT86_REQ = 0x000000d6,
16736	TCC_PERF_SEL_CLIENT87_REQ = 0x000000d7,
16737	TCC_PERF_SEL_CLIENT88_REQ = 0x000000d8,
16738	TCC_PERF_SEL_CLIENT89_REQ = 0x000000d9,
16739	TCC_PERF_SEL_CLIENT90_REQ = 0x000000da,
16740	TCC_PERF_SEL_CLIENT91_REQ = 0x000000db,
16741	TCC_PERF_SEL_CLIENT92_REQ = 0x000000dc,
16742	TCC_PERF_SEL_CLIENT93_REQ = 0x000000dd,
16743	TCC_PERF_SEL_CLIENT94_REQ = 0x000000de,
16744	TCC_PERF_SEL_CLIENT95_REQ = 0x000000df,
16745	TCC_PERF_SEL_CLIENT96_REQ = 0x000000e0,
16746	TCC_PERF_SEL_CLIENT97_REQ = 0x000000e1,
16747	TCC_PERF_SEL_CLIENT98_REQ = 0x000000e2,
16748	TCC_PERF_SEL_CLIENT99_REQ = 0x000000e3,
16749	TCC_PERF_SEL_CLIENT100_REQ = 0x000000e4,
16750	TCC_PERF_SEL_CLIENT101_REQ = 0x000000e5,
16751	TCC_PERF_SEL_CLIENT102_REQ = 0x000000e6,
16752	TCC_PERF_SEL_CLIENT103_REQ = 0x000000e7,
16753	TCC_PERF_SEL_CLIENT104_REQ = 0x000000e8,
16754	TCC_PERF_SEL_CLIENT105_REQ = 0x000000e9,
16755	TCC_PERF_SEL_CLIENT106_REQ = 0x000000ea,
16756	TCC_PERF_SEL_CLIENT107_REQ = 0x000000eb,
16757	TCC_PERF_SEL_CLIENT108_REQ = 0x000000ec,
16758	TCC_PERF_SEL_CLIENT109_REQ = 0x000000ed,
16759	TCC_PERF_SEL_CLIENT110_REQ = 0x000000ee,
16760	TCC_PERF_SEL_CLIENT111_REQ = 0x000000ef,
16761	TCC_PERF_SEL_CLIENT112_REQ = 0x000000f0,
16762	TCC_PERF_SEL_CLIENT113_REQ = 0x000000f1,
16763	TCC_PERF_SEL_CLIENT114_REQ = 0x000000f2,
16764	TCC_PERF_SEL_CLIENT115_REQ = 0x000000f3,
16765	TCC_PERF_SEL_CLIENT116_REQ = 0x000000f4,
16766	TCC_PERF_SEL_CLIENT117_REQ = 0x000000f5,
16767	TCC_PERF_SEL_CLIENT118_REQ = 0x000000f6,
16768	TCC_PERF_SEL_CLIENT119_REQ = 0x000000f7,
16769	TCC_PERF_SEL_CLIENT120_REQ = 0x000000f8,
16770	TCC_PERF_SEL_CLIENT121_REQ = 0x000000f9,
16771	TCC_PERF_SEL_CLIENT122_REQ = 0x000000fa,
16772	TCC_PERF_SEL_CLIENT123_REQ = 0x000000fb,
16773	TCC_PERF_SEL_CLIENT124_REQ = 0x000000fc,
16774	TCC_PERF_SEL_CLIENT125_REQ = 0x000000fd,
16775	TCC_PERF_SEL_CLIENT126_REQ = 0x000000fe,
16776	TCC_PERF_SEL_CLIENT127_REQ = 0x000000ff,
16777	} TCC_PERF_SEL;
16778
16779	/*
16780	* TCA_PERF_SEL enum
16781	*/
16782
16783	typedef enum TCA_PERF_SEL {
16784	TCA_PERF_SEL_NONE = 0x00000000,
16785	TCA_PERF_SEL_CYCLE = 0x00000001,
16786	TCA_PERF_SEL_BUSY = 0x00000002,
16787	TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x00000003,
16788	TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x00000004,
16789	TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x00000005,
16790	TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x00000006,
16791	TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x00000007,
16792	TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x00000008,
16793	TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x00000009,
16794	TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0x0000000a,
16795	TCA_PERF_SEL_REQ_TCC0 = 0x0000000b,
16796	TCA_PERF_SEL_REQ_TCC1 = 0x0000000c,
16797	TCA_PERF_SEL_REQ_TCC2 = 0x0000000d,
16798	TCA_PERF_SEL_REQ_TCC3 = 0x0000000e,
16799	TCA_PERF_SEL_REQ_TCC4 = 0x0000000f,
16800	TCA_PERF_SEL_REQ_TCC5 = 0x00000010,
16801	TCA_PERF_SEL_REQ_TCC6 = 0x00000011,
16802	TCA_PERF_SEL_REQ_TCC7 = 0x00000012,
16803	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x00000013,
16804	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x00000014,
16805	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x00000015,
16806	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x00000016,
16807	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x00000017,
16808	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x00000018,
16809	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x00000019,
16810	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x0000001a,
16811	TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x0000001b,
16812	TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x0000001c,
16813	TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x0000001d,
16814	TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x0000001e,
16815	TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x0000001f,
16816	TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x00000020,
16817	TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x00000021,
16818	TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x00000022,
16819	} TCA_PERF_SEL;
16820
16821	/*******************************************************
16822	* GRBM Enums
16823	*******************************************************/
16824
16825	/*
16826	* GRBM_PERF_SEL enum
16827	*/
16828
16829	typedef enum GRBM_PERF_SEL {
16830	GRBM_PERF_SEL_COUNT = 0x00000000,
16831	GRBM_PERF_SEL_USER_DEFINED = 0x00000001,
16832	GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002,
16833	GRBM_PERF_SEL_CP_BUSY = 0x00000003,
16834	GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004,
16835	GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005,
16836	GRBM_PERF_SEL_CB_BUSY = 0x00000006,
16837	GRBM_PERF_SEL_DB_BUSY = 0x00000007,
16838	GRBM_PERF_SEL_PA_BUSY = 0x00000008,
16839	GRBM_PERF_SEL_SC_BUSY = 0x00000009,
16840	GRBM_PERF_SEL_RESERVED_6 = 0x0000000a,
16841	GRBM_PERF_SEL_SPI_BUSY = 0x0000000b,
16842	GRBM_PERF_SEL_SX_BUSY = 0x0000000c,
16843	GRBM_PERF_SEL_TA_BUSY = 0x0000000d,
16844	GRBM_PERF_SEL_CB_CLEAN = 0x0000000e,
16845	GRBM_PERF_SEL_DB_CLEAN = 0x0000000f,
16846	GRBM_PERF_SEL_RESERVED_5 = 0x00000010,
16847	GRBM_PERF_SEL_VGT_BUSY = 0x00000011,
16848	GRBM_PERF_SEL_RESERVED_4 = 0x00000012,
16849	GRBM_PERF_SEL_RESERVED_3 = 0x00000013,
16850	GRBM_PERF_SEL_RESERVED_2 = 0x00000014,
16851	GRBM_PERF_SEL_RESERVED_1 = 0x00000015,
16852	GRBM_PERF_SEL_RESERVED_0 = 0x00000016,
16853	GRBM_PERF_SEL_IA_BUSY = 0x00000017,
16854	GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x00000018,
16855	GRBM_PERF_SEL_GDS_BUSY = 0x00000019,
16856	GRBM_PERF_SEL_BCI_BUSY = 0x0000001a,
16857	GRBM_PERF_SEL_RLC_BUSY = 0x0000001b,
16858	GRBM_PERF_SEL_TC_BUSY = 0x0000001c,
16859	GRBM_PERF_SEL_CPG_BUSY = 0x0000001d,
16860	GRBM_PERF_SEL_CPC_BUSY = 0x0000001e,
16861	GRBM_PERF_SEL_CPF_BUSY = 0x0000001f,
16862	GRBM_PERF_SEL_WD_BUSY = 0x00000020,
16863	GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x00000021,
16864	GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022,
16865	GRBM_PERF_SEL_EA_BUSY = 0x00000023,
16866	GRBM_PERF_SEL_RMI_BUSY = 0x00000024,
16867	GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025,
16868	} GRBM_PERF_SEL;
16869
16870	/*
16871	* GRBM_SE0_PERF_SEL enum
16872	*/
16873
16874	typedef enum GRBM_SE0_PERF_SEL {
16875	GRBM_SE0_PERF_SEL_COUNT = 0x00000000,
16876	GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001,
16877	GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002,
16878	GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003,
16879	GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004,
16880	GRBM_SE0_PERF_SEL_RESERVED_1 = 0x00000005,
16881	GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006,
16882	GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007,
16883	GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008,
16884	GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009,
16885	GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a,
16886	GRBM_SE0_PERF_SEL_RESERVED_0 = 0x0000000b,
16887	GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c,
16888	GRBM_SE0_PERF_SEL_VGT_BUSY = 0x0000000d,
16889	GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e,
16890	GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f,
16891	} GRBM_SE0_PERF_SEL;
16892
16893	/*
16894	* GRBM_SE1_PERF_SEL enum
16895	*/
16896
16897	typedef enum GRBM_SE1_PERF_SEL {
16898	GRBM_SE1_PERF_SEL_COUNT = 0x00000000,
16899	GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001,
16900	GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002,
16901	GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003,
16902	GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004,
16903	GRBM_SE1_PERF_SEL_RESERVED_1 = 0x00000005,
16904	GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006,
16905	GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007,
16906	GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008,
16907	GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009,
16908	GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a,
16909	GRBM_SE1_PERF_SEL_RESERVED_0 = 0x0000000b,
16910	GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c,
16911	GRBM_SE1_PERF_SEL_VGT_BUSY = 0x0000000d,
16912	GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e,
16913	GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f,
16914	} GRBM_SE1_PERF_SEL;
16915
16916	/*
16917	* GRBM_SE2_PERF_SEL enum
16918	*/
16919
16920	typedef enum GRBM_SE2_PERF_SEL {
16921	GRBM_SE2_PERF_SEL_COUNT = 0x00000000,
16922	GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001,
16923	GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002,
16924	GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003,
16925	GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004,
16926	GRBM_SE2_PERF_SEL_RESERVED_1 = 0x00000005,
16927	GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006,
16928	GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007,
16929	GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008,
16930	GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009,
16931	GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a,
16932	GRBM_SE2_PERF_SEL_RESERVED_0 = 0x0000000b,
16933	GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c,
16934	GRBM_SE2_PERF_SEL_VGT_BUSY = 0x0000000d,
16935	GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e,
16936	GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f,
16937	} GRBM_SE2_PERF_SEL;
16938
16939	/*
16940	* GRBM_SE3_PERF_SEL enum
16941	*/
16942
16943	typedef enum GRBM_SE3_PERF_SEL {
16944	GRBM_SE3_PERF_SEL_COUNT = 0x00000000,
16945	GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001,
16946	GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002,
16947	GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003,
16948	GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004,
16949	GRBM_SE3_PERF_SEL_RESERVED_1 = 0x00000005,
16950	GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006,
16951	GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007,
16952	GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008,
16953	GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009,
16954	GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a,
16955	GRBM_SE3_PERF_SEL_RESERVED_0 = 0x0000000b,
16956	GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c,
16957	GRBM_SE3_PERF_SEL_VGT_BUSY = 0x0000000d,
16958	GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e,
16959	GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f,
16960	} GRBM_SE3_PERF_SEL;
16961
16962	/*******************************************************
16963	* CP Enums
16964	*******************************************************/
16965
16966	/*
16967	* CP_RING_ID enum
16968	*/
16969
16970	typedef enum CP_RING_ID {
16971	RINGID0 = 0x00000000,
16972	RINGID1 = 0x00000001,
16973	RINGID2 = 0x00000002,
16974	RINGID3 = 0x00000003,
16975	} CP_RING_ID;
16976
16977	/*
16978	* CP_PIPE_ID enum
16979	*/
16980
16981	typedef enum CP_PIPE_ID {
16982	PIPE_ID0 = 0x00000000,
16983	PIPE_ID1 = 0x00000001,
16984	PIPE_ID2 = 0x00000002,
16985	PIPE_ID3 = 0x00000003,
16986	} CP_PIPE_ID;
16987
16988	/*
16989	* CP_ME_ID enum
16990	*/
16991
16992	typedef enum CP_ME_ID {
16993	ME_ID0 = 0x00000000,
16994	ME_ID1 = 0x00000001,
16995	ME_ID2 = 0x00000002,
16996	ME_ID3 = 0x00000003,
16997	} CP_ME_ID;
16998
16999	/*
17000	* SPM_PERFMON_STATE enum
17001	*/
17002
17003	typedef enum SPM_PERFMON_STATE {
17004	STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
17005	STRM_PERFMON_STATE_START_COUNTING = 0x00000001,
17006	STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002,
17007	STRM_PERFMON_STATE_RESERVED_3 = 0x00000003,
17008	STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
17009	STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
17010	} SPM_PERFMON_STATE;
17011
17012	/*
17013	* CP_PERFMON_STATE enum
17014	*/
17015
17016	typedef enum CP_PERFMON_STATE {
17017	CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
17018	CP_PERFMON_STATE_START_COUNTING = 0x00000001,
17019	CP_PERFMON_STATE_STOP_COUNTING = 0x00000002,
17020	CP_PERFMON_STATE_RESERVED_3 = 0x00000003,
17021	CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
17022	CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
17023	} CP_PERFMON_STATE;
17024
17025	/*
17026	* CP_PERFMON_ENABLE_MODE enum
17027	*/
17028
17029	typedef enum CP_PERFMON_ENABLE_MODE {
17030	CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000,
17031	CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001,
17032	CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
17033	CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
17034	} CP_PERFMON_ENABLE_MODE;
17035
17036	/*
17037	* CPG_PERFCOUNT_SEL enum
17038	*/
17039
17040	typedef enum CPG_PERFCOUNT_SEL {
17041	CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000,
17042	CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001,
17043	CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002,
17044	CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003,
17045	CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004,
17046	CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005,
17047	CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006,
17048	CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007,
17049	CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008,
17050	CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009,
17051	CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a,
17052	CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b,
17053	CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c,
17054	CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d,
17055	CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e,
17056	CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f,
17057	CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010,
17058	CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011,
17059	CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012,
17060	CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013,
17061	CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014,
17062	CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015,
17063	CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016,
17064	CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017,
17065	CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018,
17066	CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019,
17067	CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a,
17068	CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b,
17069	CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c,
17070	CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d,
17071	CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e,
17072	CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f,
17073	CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020,
17074	CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021,
17075	CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x00000022,
17076	CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x00000023,
17077	CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024,
17078	CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025,
17079	CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026,
17080	CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027,
17081	CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028,
17082	CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029,
17083	CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a,
17084	CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b,
17085	CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c,
17086	CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d,
17087	CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e,
17088	CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f,
17089	CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030,
17090	} CPG_PERFCOUNT_SEL;
17091
17092	/*
17093	* CPF_PERFCOUNT_SEL enum
17094	*/
17095
17096	typedef enum CPF_PERFCOUNT_SEL {
17097	CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000,
17098	CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001,
17099	CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002,
17100	CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003,
17101	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004,
17102	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005,
17103	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006,
17104	CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007,
17105	CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008,
17106	CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x00000009,
17107	CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a,
17108	CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b,
17109	CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c,
17110	CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d,
17111	CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e,
17112	CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0x0000000f,
17113	CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x00000010,
17114	CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011,
17115	CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012,
17116	CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000013,
17117	CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000014,
17118	} CPF_PERFCOUNT_SEL;
17119
17120	/*
17121	* CPC_PERFCOUNT_SEL enum
17122	*/
17123
17124	typedef enum CPC_PERFCOUNT_SEL {
17125	CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000,
17126	CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001,
17127	CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002,
17128	CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x00000003,
17129	CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x00000004,
17130	CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005,
17131	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006,
17132	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007,
17133	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008,
17134	CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x00000009,
17135	CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0x0000000a,
17136	CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b,
17137	CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c,
17138	CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d,
17139	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e,
17140	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f,
17141	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010,
17142	CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x00000011,
17143	CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x00000012,
17144	CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013,
17145	CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014,
17146	CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015,
17147	CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016,
17148	CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017,
17149	CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018,
17150	} CPC_PERFCOUNT_SEL;
17151
17152	/*
17153	* CP_ALPHA_TAG_RAM_SEL enum
17154	*/
17155
17156	typedef enum CP_ALPHA_TAG_RAM_SEL {
17157	CPG_TAG_RAM = 0x00000000,
17158	CPC_TAG_RAM = 0x00000001,
17159	CPF_TAG_RAM = 0x00000002,
17160	RSV_TAG_RAM = 0x00000003,
17161	} CP_ALPHA_TAG_RAM_SEL;
17162
17163	/*
17164	* SEM_RESPONSE value
17165	*/
17166
17167	#define SEM_ECC_ERROR 0x00000000
17168	#define SEM_TRANS_ERROR 0x00000001
17169	#define SEM_FAILED 0x00000002
17170	#define SEM_PASSED 0x00000003
17171
17172	/*
17173	* IQ_RETRY_TYPE value
17174	*/
17175
17176	#define IQ_QUEUE_SLEEP 0x00000000
17177	#define IQ_OFFLOAD_RETRY 0x00000001
17178	#define IQ_SCH_WAVE_MSG 0x00000002
17179	#define IQ_SEM_REARM 0x00000003
17180	#define IQ_DEQUEUE_RETRY 0x00000004
17181
17182	/*
17183	* IQ_INTR_TYPE value
17184	*/
17185
17186	#define IQ_INTR_TYPE_PQ 0x00000000
17187	#define IQ_INTR_TYPE_IB 0x00000001
17188	#define IQ_INTR_TYPE_MQD 0x00000002
17189
17190	/*
17191	* VMID_SIZE value
17192	*/
17193
17194	#define VMID_SZ 0x00000004
17195
17196	/*
17197	* CONFIG_SPACE value
17198	*/
17199
17200	#define CONFIG_SPACE_START 0x00002000
17201	#define CONFIG_SPACE_END 0x00009fff
17202
17203	/*
17204	* CONFIG_SPACE1 value
17205	*/
17206
17207	#define CONFIG_SPACE1_START 0x00002000
17208	#define CONFIG_SPACE1_END 0x00002bff
17209
17210	/*
17211	* CONFIG_SPACE2 value
17212	*/
17213
17214	#define CONFIG_SPACE2_START 0x00003000
17215	#define CONFIG_SPACE2_END 0x00009fff
17216
17217	/*
17218	* UCONFIG_SPACE value
17219	*/
17220
17221	#define UCONFIG_SPACE_START 0x0000c000
17222	#define UCONFIG_SPACE_END 0x0000ffff
17223
17224	/*
17225	* PERSISTENT_SPACE value
17226	*/
17227
17228	#define PERSISTENT_SPACE_START 0x00002c00
17229	#define PERSISTENT_SPACE_END 0x00002fff
17230
17231	/*
17232	* CONTEXT_SPACE value
17233	*/
17234
17235	#define CONTEXT_SPACE_START 0x0000a000
17236	#define CONTEXT_SPACE_END 0x0000bfff
17237
17238	/*******************************************************
17239	* SQ_UC Enums
17240	*******************************************************/
17241
17242	/*
17243	* VALUE_SQ_ENC_SOP1 value
17244	*/
17245
17246	#define SQ_ENC_SOP1_BITS 0xbe800000
17247	#define SQ_ENC_SOP1_MASK 0xff800000
17248	#define SQ_ENC_SOP1_FIELD 0x0000017d
17249
17250	/*
17251	* VALUE_SQ_ENC_SOPC value
17252	*/
17253
17254	#define SQ_ENC_SOPC_BITS 0xbf000000
17255	#define SQ_ENC_SOPC_MASK 0xff800000
17256	#define SQ_ENC_SOPC_FIELD 0x0000017e
17257
17258	/*
17259	* VALUE_SQ_ENC_SOPP value
17260	*/
17261
17262	#define SQ_ENC_SOPP_BITS 0xbf800000
17263	#define SQ_ENC_SOPP_MASK 0xff800000
17264	#define SQ_ENC_SOPP_FIELD 0x0000017f
17265
17266	/*
17267	* VALUE_SQ_ENC_SOPK value
17268	*/
17269
17270	#define SQ_ENC_SOPK_BITS 0xb0000000
17271	#define SQ_ENC_SOPK_MASK 0xf0000000
17272	#define SQ_ENC_SOPK_FIELD 0x0000000b
17273
17274	/*
17275	* VALUE_SQ_ENC_SOP2 value
17276	*/
17277
17278	#define SQ_ENC_SOP2_BITS 0x80000000
17279	#define SQ_ENC_SOP2_MASK 0xc0000000
17280	#define SQ_ENC_SOP2_FIELD 0x00000002
17281
17282	/*
17283	* VALUE_SQ_ENC_SMEM value
17284	*/
17285
17286	#define SQ_ENC_SMEM_BITS 0xc0000000
17287	#define SQ_ENC_SMEM_MASK 0xfc000000
17288	#define SQ_ENC_SMEM_FIELD 0x00000030
17289
17290	/*
17291	* VALUE_SQ_ENC_VOP1 value
17292	*/
17293
17294	#define SQ_ENC_VOP1_BITS 0x7e000000
17295	#define SQ_ENC_VOP1_MASK 0xfe000000
17296	#define SQ_ENC_VOP1_FIELD 0x0000003f
17297
17298	/*
17299	* VALUE_SQ_ENC_VOPC value
17300	*/
17301
17302	#define SQ_ENC_VOPC_BITS 0x7c000000
17303	#define SQ_ENC_VOPC_MASK 0xfe000000
17304	#define SQ_ENC_VOPC_FIELD 0x0000003e
17305
17306	/*
17307	* VALUE_SQ_ENC_VOP2 value
17308	*/
17309
17310	#define SQ_ENC_VOP2_BITS 0x00000000
17311	#define SQ_ENC_VOP2_MASK 0x80000000
17312	#define SQ_ENC_VOP2_FIELD 0x00000000
17313
17314	/*
17315	* VALUE_SQ_ENC_VINTRP value
17316	*/
17317
17318	#define SQ_ENC_VINTRP_BITS 0xd4000000
17319	#define SQ_ENC_VINTRP_MASK 0xfc000000
17320	#define SQ_ENC_VINTRP_FIELD 0x00000035
17321
17322	/*
17323	* VALUE_SQ_ENC_VOP3P value
17324	*/
17325
17326	#define SQ_ENC_VOP3P_BITS 0xd3800000
17327	#define SQ_ENC_VOP3P_MASK 0xff800000
17328	#define SQ_ENC_VOP3P_FIELD 0x000001a7
17329
17330	/*
17331	* VALUE_SQ_ENC_VOP3 value
17332	*/
17333
17334	#define SQ_ENC_VOP3_BITS 0xd0000000
17335	#define SQ_ENC_VOP3_MASK 0xfc000000
17336	#define SQ_ENC_VOP3_FIELD 0x00000034
17337
17338	/*
17339	* VALUE_SQ_ENC_DS value
17340	*/
17341
17342	#define SQ_ENC_DS_BITS 0xd8000000
17343	#define SQ_ENC_DS_MASK 0xfc000000
17344	#define SQ_ENC_DS_FIELD 0x00000036
17345
17346	/*
17347	* VALUE_SQ_ENC_MUBUF value
17348	*/
17349
17350	#define SQ_ENC_MUBUF_BITS 0xe0000000
17351	#define SQ_ENC_MUBUF_MASK 0xfc000000
17352	#define SQ_ENC_MUBUF_FIELD 0x00000038
17353
17354	/*
17355	* VALUE_SQ_ENC_MTBUF value
17356	*/
17357
17358	#define SQ_ENC_MTBUF_BITS 0xe8000000
17359	#define SQ_ENC_MTBUF_MASK 0xfc000000
17360	#define SQ_ENC_MTBUF_FIELD 0x0000003a
17361
17362	/*
17363	* VALUE_SQ_ENC_MIMG value
17364	*/
17365
17366	#define SQ_ENC_MIMG_BITS 0xf0000000
17367	#define SQ_ENC_MIMG_MASK 0xfc000000
17368	#define SQ_ENC_MIMG_FIELD 0x0000003c
17369
17370	/*
17371	* VALUE_SQ_ENC_EXP value
17372	*/
17373
17374	#define SQ_ENC_EXP_BITS 0xc4000000
17375	#define SQ_ENC_EXP_MASK 0xfc000000
17376	#define SQ_ENC_EXP_FIELD 0x00000031
17377
17378	/*
17379	* VALUE_SQ_ENC_FLAT value
17380	*/
17381
17382	#define SQ_ENC_FLAT_BITS 0xdc000000
17383	#define SQ_ENC_FLAT_MASK 0xfc000000
17384	#define SQ_ENC_FLAT_FIELD 0x00000037
17385
17386	/*
17387	* VALUE_SQ_V_OP3_INTRP_COUNT value
17388	*/
17389
17390	#define SQ_V_OP3_INTRP_COUNT 0x0000000c
17391
17392	/*
17393	* VALUE_SQ_SENDMSG_SYSTEM_SIZE value
17394	*/
17395
17396	#define SQ_SENDMSG_SYSTEM_SIZE 0x00000003
17397
17398	/*
17399	* VALUE_SQ_HWREG_ID_SIZE value
17400	*/
17401
17402	#define SQ_HWREG_ID_SIZE 0x00000006
17403
17404	/*
17405	* VALUE_SQ_V_OPC_COUNT value
17406	*/
17407
17408	#define SQ_V_OPC_COUNT 0x00000100
17409
17410	/*
17411	* VALUE_SQ_NUM_VGPR value
17412	*/
17413
17414	#define SQ_NUM_VGPR 0x00000100
17415
17416	/*
17417	* VALUE_SQ_WAITCNT_LGKM_SHIFT value
17418	*/
17419
17420	#define SQ_WAITCNT_LGKM_SHIFT 0x00000008
17421
17422	/*
17423	* VALUE_SQ_HWREG_ID_SHIFT value
17424	*/
17425
17426	#define SQ_HWREG_ID_SHIFT 0x00000000
17427
17428	/*
17429	* VALUE_SQ_EXP_NUM_POS value
17430	*/
17431
17432	#define SQ_EXP_NUM_POS 0x00000004
17433
17434	/*
17435	* VALUE_SQ_XLATE_VOP3_TO_VOPC_OFFSET value
17436	*/
17437
17438	#define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x00000000
17439
17440	/*
17441	* VALUE_SQ_V_OP3_2IN_OFFSET value
17442	*/
17443
17444	#define SQ_V_OP3_2IN_OFFSET 0x00000280
17445
17446	/*
17447	* VALUE_SQ_XLATE_VOP3_TO_VOP2_OFFSET value
17448	*/
17449
17450	#define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x00000100
17451
17452	/*
17453	* VALUE_SQ_EXP_NUM_MRT value
17454	*/
17455
17456	#define SQ_EXP_NUM_MRT 0x00000008
17457
17458	/*
17459	* VALUE_SQ_NUM_TTMP value
17460	*/
17461
17462	#define SQ_NUM_TTMP 0x00000010
17463
17464	/*
17465	* VALUE_SQ_SENDMSG_STREAMID_SHIFT value
17466	*/
17467
17468	#define SQ_SENDMSG_STREAMID_SHIFT 0x00000008
17469
17470	/*
17471	* VALUE_SQ_V_OP1_COUNT value
17472	*/
17473
17474	#define SQ_V_OP1_COUNT 0x00000080
17475
17476	/*
17477	* VALUE_SQ_WAITCNT_LGKM_SIZE value
17478	*/
17479
17480	#define SQ_WAITCNT_LGKM_SIZE 0x00000004
17481
17482	/*
17483	* VALUE_SQ_XLATE_VOP3_TO_VOPC_COUNT value
17484	*/
17485
17486	#define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x00000100
17487
17488	/*
17489	* VALUE_SQ_SENDMSG_MSG_SHIFT value
17490	*/
17491
17492	#define SQ_SENDMSG_MSG_SHIFT 0x00000000
17493
17494	/*
17495	* VALUE_SQ_V_OP3_3IN_OFFSET value
17496	*/
17497
17498	#define SQ_V_OP3_3IN_OFFSET 0x000001c0
17499
17500	/*
17501	* VALUE_SQ_HWREG_OFFSET_SHIFT value
17502	*/
17503
17504	#define SQ_HWREG_OFFSET_SHIFT 0x00000006
17505
17506	/*
17507	* VALUE_SQ_HWREG_SIZE_SHIFT value
17508	*/
17509
17510	#define SQ_HWREG_SIZE_SHIFT 0x0000000b
17511
17512	/*
17513	* VALUE_SQ_HWREG_OFFSET_SIZE value
17514	*/
17515
17516	#define SQ_HWREG_OFFSET_SIZE 0x00000005
17517
17518	/*
17519	* VALUE_SQ_V_OP3_3IN_COUNT value
17520	*/
17521
17522	#define SQ_V_OP3_3IN_COUNT 0x000000b0
17523
17524	/*
17525	* VALUE_SQ_SENDMSG_MSG_SIZE value
17526	*/
17527
17528	#define SQ_SENDMSG_MSG_SIZE 0x00000004
17529
17530	/*
17531	* VALUE_SQ_XLATE_VOP3_TO_VOP1_COUNT value
17532	*/
17533
17534	#define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x00000080
17535
17536	/*
17537	* VALUE_SQ_EXP_NUM_GDS value
17538	*/
17539
17540	#define SQ_EXP_NUM_GDS 0x00000005
17541
17542	/*
17543	* VALUE_SQ_V_OP2_COUNT value
17544	*/
17545
17546	#define SQ_V_OP2_COUNT 0x00000040
17547
17548	/*
17549	* VALUE_SQ_SENDMSG_GSOP_SIZE value
17550	*/
17551
17552	#define SQ_SENDMSG_GSOP_SIZE 0x00000002
17553
17554	/*
17555	* VALUE_SQ_WAITCNT_VM_SHIFT value
17556	*/
17557
17558	#define SQ_WAITCNT_VM_SHIFT 0x00000000
17559
17560	/*
17561	* VALUE_SQ_XLATE_VOP3_TO_VOP3P_COUNT value
17562	*/
17563
17564	#define SQ_XLATE_VOP3_TO_VOP3P_COUNT 0x00000080
17565
17566	/*
17567	* VALUE_SQ_V_OP3_2IN_COUNT value
17568	*/
17569
17570	#define SQ_V_OP3_2IN_COUNT 0x00000080
17571
17572	/*
17573	* VALUE_SQ_SENDMSG_SYSTEM_SHIFT value
17574	*/
17575
17576	#define SQ_SENDMSG_SYSTEM_SHIFT 0x00000004
17577
17578	/*
17579	* VALUE_SQ_WAITCNT_VM_SIZE value
17580	*/
17581
17582	#define SQ_WAITCNT_VM_SIZE 0x00000004
17583
17584	/*
17585	* VALUE_SQ_XLATE_VOP3_TO_VOP3P_OFFSET value
17586	*/
17587
17588	#define SQ_XLATE_VOP3_TO_VOP3P_OFFSET 0x00000380
17589
17590	/*
17591	* VALUE_SQ_WAITCNT_EXP_SHIFT value
17592	*/
17593
17594	#define SQ_WAITCNT_EXP_SHIFT 0x00000004
17595
17596	/*
17597	* VALUE_SQ_XLATE_VOP3_TO_VOP2_COUNT value
17598	*/
17599
17600	#define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x00000040
17601
17602	/*
17603	* VALUE_SQ_EXP_NUM_PARAM value
17604	*/
17605
17606	#define SQ_EXP_NUM_PARAM 0x00000020
17607
17608	/*
17609	* VALUE_SQ_HWREG_SIZE_SIZE value
17610	*/
17611
17612	#define SQ_HWREG_SIZE_SIZE 0x00000005
17613
17614	/*
17615	* VALUE_SQ_WAITCNT_EXP_SIZE value
17616	*/
17617
17618	#define SQ_WAITCNT_EXP_SIZE 0x00000003
17619
17620	/*
17621	* VALUE_SQ_V_OP3_INTRP_OFFSET value
17622	*/
17623
17624	#define SQ_V_OP3_INTRP_OFFSET 0x00000274
17625
17626	/*
17627	* VALUE_SQ_SENDMSG_GSOP_SHIFT value
17628	*/
17629
17630	#define SQ_SENDMSG_GSOP_SHIFT 0x00000004
17631
17632	/*
17633	* VALUE_SQ_XLATE_VOP3_TO_VINTRP_OFFSET value
17634	*/
17635
17636	#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x00000270
17637
17638	/*
17639	* VALUE_SQ_NUM_ATTR value
17640	*/
17641
17642	#define SQ_NUM_ATTR 0x00000021
17643
17644	/*
17645	* VALUE_SQ_NUM_SGPR value
17646	*/
17647
17648	#define SQ_NUM_SGPR 0x00000066
17649
17650	/*
17651	* VALUE_SQ_SRC_VGPR_BIT value
17652	*/
17653
17654	#define SQ_SRC_VGPR_BIT 0x00000100
17655
17656	/*
17657	* VALUE_SQ_V_INTRP_COUNT value
17658	*/
17659
17660	#define SQ_V_INTRP_COUNT 0x00000004
17661
17662	/*
17663	* VALUE_SQ_SENDMSG_STREAMID_SIZE value
17664	*/
17665
17666	#define SQ_SENDMSG_STREAMID_SIZE 0x00000002
17667
17668	/*
17669	* VALUE_SQ_V_OP3P_COUNT value
17670	*/
17671
17672	#define SQ_V_OP3P_COUNT 0x00000080
17673
17674	/*
17675	* VALUE_SQ_XLATE_VOP3_TO_VOP1_OFFSET value
17676	*/
17677
17678	#define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x00000140
17679
17680	/*
17681	* VALUE_SQ_XLATE_VOP3_TO_VINTRP_COUNT value
17682	*/
17683
17684	#define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x00000004
17685
17686	/*
17687	* VALUE_SQ_SSRC_SPECIAL_DPP value
17688	*/
17689
17690	#define SQ_SRC_DPP 0x000000fa
17691
17692	/*
17693	* VALUE_SQ_OP_MTBUF value
17694	*/
17695
17696	#define SQ_TBUFFER_LOAD_FORMAT_X 0x00000000
17697	#define SQ_TBUFFER_LOAD_FORMAT_XY 0x00000001
17698	#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x00000002
17699	#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x00000003
17700	#define SQ_TBUFFER_STORE_FORMAT_X 0x00000004
17701	#define SQ_TBUFFER_STORE_FORMAT_XY 0x00000005
17702	#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x00000006
17703	#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x00000007
17704	#define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x00000008
17705	#define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x00000009
17706	#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a
17707	#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
17708	#define SQ_TBUFFER_STORE_FORMAT_D16_X 0x0000000c
17709	#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0x0000000d
17710	#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
17711	#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
17712
17713	/*
17714	* VALUE_SQ_OP_FLAT_GLBL value
17715	*/
17716
17717	#define SQ_GLOBAL_LOAD_UBYTE 0x00000010
17718	#define SQ_GLOBAL_LOAD_SBYTE 0x00000011
17719	#define SQ_GLOBAL_LOAD_USHORT 0x00000012
17720	#define SQ_GLOBAL_LOAD_SSHORT 0x00000013
17721	#define SQ_GLOBAL_LOAD_DWORD 0x00000014
17722	#define SQ_GLOBAL_LOAD_DWORDX2 0x00000015
17723	#define SQ_GLOBAL_LOAD_DWORDX3 0x00000016
17724	#define SQ_GLOBAL_LOAD_DWORDX4 0x00000017
17725	#define SQ_GLOBAL_STORE_BYTE 0x00000018
17726	#define SQ_GLOBAL_STORE_SHORT 0x0000001a
17727	#define SQ_GLOBAL_STORE_DWORD 0x0000001c
17728	#define SQ_GLOBAL_STORE_DWORDX2 0x0000001d
17729	#define SQ_GLOBAL_STORE_DWORDX3 0x0000001e
17730	#define SQ_GLOBAL_STORE_DWORDX4 0x0000001f
17731	#define SQ_GLOBAL_ATOMIC_SWAP 0x00000040
17732	#define SQ_GLOBAL_ATOMIC_CMPSWAP 0x00000041
17733	#define SQ_GLOBAL_ATOMIC_ADD 0x00000042
17734	#define SQ_GLOBAL_ATOMIC_SUB 0x00000043
17735	#define SQ_GLOBAL_ATOMIC_SMIN 0x00000044
17736	#define SQ_GLOBAL_ATOMIC_UMIN 0x00000045
17737	#define SQ_GLOBAL_ATOMIC_SMAX 0x00000046
17738	#define SQ_GLOBAL_ATOMIC_UMAX 0x00000047
17739	#define SQ_GLOBAL_ATOMIC_AND 0x00000048
17740	#define SQ_GLOBAL_ATOMIC_OR 0x00000049
17741	#define SQ_GLOBAL_ATOMIC_XOR 0x0000004a
17742	#define SQ_GLOBAL_ATOMIC_INC 0x0000004b
17743	#define SQ_GLOBAL_ATOMIC_DEC 0x0000004c
17744	#define SQ_GLOBAL_ATOMIC_SWAP_X2 0x00000060
17745	#define SQ_GLOBAL_ATOMIC_CMPSWAP_X2 0x00000061
17746	#define SQ_GLOBAL_ATOMIC_ADD_X2 0x00000062
17747	#define SQ_GLOBAL_ATOMIC_SUB_X2 0x00000063
17748	#define SQ_GLOBAL_ATOMIC_SMIN_X2 0x00000064
17749	#define SQ_GLOBAL_ATOMIC_UMIN_X2 0x00000065
17750	#define SQ_GLOBAL_ATOMIC_SMAX_X2 0x00000066
17751	#define SQ_GLOBAL_ATOMIC_UMAX_X2 0x00000067
17752	#define SQ_GLOBAL_ATOMIC_AND_X2 0x00000068
17753	#define SQ_GLOBAL_ATOMIC_OR_X2 0x00000069
17754	#define SQ_GLOBAL_ATOMIC_XOR_X2 0x0000006a
17755	#define SQ_GLOBAL_ATOMIC_INC_X2 0x0000006b
17756	#define SQ_GLOBAL_ATOMIC_DEC_X2 0x0000006c
17757
17758	/*
17759	* VALUE_SQ_VGPR value
17760	*/
17761
17762	#define SQ_VGPR0 0x00000000
17763
17764	/*
17765	* VALUE_SQ_OP_FLAT_SCRATCH value
17766	*/
17767
17768	#define SQ_SCRATCH_LOAD_UBYTE 0x00000010
17769	#define SQ_SCRATCH_LOAD_SBYTE 0x00000011
17770	#define SQ_SCRATCH_LOAD_USHORT 0x00000012
17771	#define SQ_SCRATCH_LOAD_SSHORT 0x00000013
17772	#define SQ_SCRATCH_LOAD_DWORD 0x00000014
17773	#define SQ_SCRATCH_LOAD_DWORDX2 0x00000015
17774	#define SQ_SCRATCH_LOAD_DWORDX3 0x00000016
17775	#define SQ_SCRATCH_LOAD_DWORDX4 0x00000017
17776	#define SQ_SCRATCH_STORE_BYTE 0x00000018
17777	#define SQ_SCRATCH_STORE_SHORT 0x0000001a
17778	#define SQ_SCRATCH_STORE_DWORD 0x0000001c
17779	#define SQ_SCRATCH_STORE_DWORDX2 0x0000001d
17780	#define SQ_SCRATCH_STORE_DWORDX3 0x0000001e
17781	#define SQ_SCRATCH_STORE_DWORDX4 0x0000001f
17782
17783	/*
17784	* VALUE_SQ_VCC value
17785	*/
17786
17787	#define SQ_VCC_ALL 0x00000000
17788
17789	/*
17790	* VALUE_SQ_SSRC_0_63_INLINES value
17791	*/
17792
17793	#define SQ_SRC_0 0x00000080
17794	#define SQ_SRC_1_INT 0x00000081
17795	#define SQ_SRC_2_INT 0x00000082
17796	#define SQ_SRC_3_INT 0x00000083
17797	#define SQ_SRC_4_INT 0x00000084
17798	#define SQ_SRC_5_INT 0x00000085
17799	#define SQ_SRC_6_INT 0x00000086
17800	#define SQ_SRC_7_INT 0x00000087
17801	#define SQ_SRC_8_INT 0x00000088
17802	#define SQ_SRC_9_INT 0x00000089
17803	#define SQ_SRC_10_INT 0x0000008a
17804	#define SQ_SRC_11_INT 0x0000008b
17805	#define SQ_SRC_12_INT 0x0000008c
17806	#define SQ_SRC_13_INT 0x0000008d
17807	#define SQ_SRC_14_INT 0x0000008e
17808	#define SQ_SRC_15_INT 0x0000008f
17809	#define SQ_SRC_16_INT 0x00000090
17810	#define SQ_SRC_17_INT 0x00000091
17811	#define SQ_SRC_18_INT 0x00000092
17812	#define SQ_SRC_19_INT 0x00000093
17813	#define SQ_SRC_20_INT 0x00000094
17814	#define SQ_SRC_21_INT 0x00000095
17815	#define SQ_SRC_22_INT 0x00000096
17816	#define SQ_SRC_23_INT 0x00000097
17817	#define SQ_SRC_24_INT 0x00000098
17818	#define SQ_SRC_25_INT 0x00000099
17819	#define SQ_SRC_26_INT 0x0000009a
17820	#define SQ_SRC_27_INT 0x0000009b
17821	#define SQ_SRC_28_INT 0x0000009c
17822	#define SQ_SRC_29_INT 0x0000009d
17823	#define SQ_SRC_30_INT 0x0000009e
17824	#define SQ_SRC_31_INT 0x0000009f
17825	#define SQ_SRC_32_INT 0x000000a0
17826	#define SQ_SRC_33_INT 0x000000a1
17827	#define SQ_SRC_34_INT 0x000000a2
17828	#define SQ_SRC_35_INT 0x000000a3
17829	#define SQ_SRC_36_INT 0x000000a4
17830	#define SQ_SRC_37_INT 0x000000a5
17831	#define SQ_SRC_38_INT 0x000000a6
17832	#define SQ_SRC_39_INT 0x000000a7
17833	#define SQ_SRC_40_INT 0x000000a8
17834	#define SQ_SRC_41_INT 0x000000a9
17835	#define SQ_SRC_42_INT 0x000000aa
17836	#define SQ_SRC_43_INT 0x000000ab
17837	#define SQ_SRC_44_INT 0x000000ac
17838	#define SQ_SRC_45_INT 0x000000ad
17839	#define SQ_SRC_46_INT 0x000000ae
17840	#define SQ_SRC_47_INT 0x000000af
17841	#define SQ_SRC_48_INT 0x000000b0
17842	#define SQ_SRC_49_INT 0x000000b1
17843	#define SQ_SRC_50_INT 0x000000b2
17844	#define SQ_SRC_51_INT 0x000000b3
17845	#define SQ_SRC_52_INT 0x000000b4
17846	#define SQ_SRC_53_INT 0x000000b5
17847	#define SQ_SRC_54_INT 0x000000b6
17848	#define SQ_SRC_55_INT 0x000000b7
17849	#define SQ_SRC_56_INT 0x000000b8
17850	#define SQ_SRC_57_INT 0x000000b9
17851	#define SQ_SRC_58_INT 0x000000ba
17852	#define SQ_SRC_59_INT 0x000000bb
17853	#define SQ_SRC_60_INT 0x000000bc
17854	#define SQ_SRC_61_INT 0x000000bd
17855	#define SQ_SRC_62_INT 0x000000be
17856	#define SQ_SRC_63_INT 0x000000bf
17857
17858	/*
17859	* VALUE_SQ_OP_MIMG value
17860	*/
17861
17862	#define SQ_IMAGE_LOAD 0x00000000
17863	#define SQ_IMAGE_LOAD_MIP 0x00000001
17864	#define SQ_IMAGE_LOAD_PCK 0x00000002
17865	#define SQ_IMAGE_LOAD_PCK_SGN 0x00000003
17866	#define SQ_IMAGE_LOAD_MIP_PCK 0x00000004
17867	#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x00000005
17868	#define SQ_IMAGE_STORE 0x00000008
17869	#define SQ_IMAGE_STORE_MIP 0x00000009
17870	#define SQ_IMAGE_STORE_PCK 0x0000000a
17871	#define SQ_IMAGE_STORE_MIP_PCK 0x0000000b
17872	#define SQ_IMAGE_GET_RESINFO 0x0000000e
17873	#define SQ_IMAGE_ATOMIC_SWAP 0x00000010
17874	#define SQ_IMAGE_ATOMIC_CMPSWAP 0x00000011
17875	#define SQ_IMAGE_ATOMIC_ADD 0x00000012
17876	#define SQ_IMAGE_ATOMIC_SUB 0x00000013
17877	#define SQ_IMAGE_ATOMIC_SMIN 0x00000014
17878	#define SQ_IMAGE_ATOMIC_UMIN 0x00000015
17879	#define SQ_IMAGE_ATOMIC_SMAX 0x00000016
17880	#define SQ_IMAGE_ATOMIC_UMAX 0x00000017
17881	#define SQ_IMAGE_ATOMIC_AND 0x00000018
17882	#define SQ_IMAGE_ATOMIC_OR 0x00000019
17883	#define SQ_IMAGE_ATOMIC_XOR 0x0000001a
17884	#define SQ_IMAGE_ATOMIC_INC 0x0000001b
17885	#define SQ_IMAGE_ATOMIC_DEC 0x0000001c
17886	#define SQ_IMAGE_SAMPLE 0x00000020
17887	#define SQ_IMAGE_SAMPLE_CL 0x00000021
17888	#define SQ_IMAGE_SAMPLE_D 0x00000022
17889	#define SQ_IMAGE_SAMPLE_D_CL 0x00000023
17890	#define SQ_IMAGE_SAMPLE_L 0x00000024
17891	#define SQ_IMAGE_SAMPLE_B 0x00000025
17892	#define SQ_IMAGE_SAMPLE_B_CL 0x00000026
17893	#define SQ_IMAGE_SAMPLE_LZ 0x00000027
17894	#define SQ_IMAGE_SAMPLE_C 0x00000028
17895	#define SQ_IMAGE_SAMPLE_C_CL 0x00000029
17896	#define SQ_IMAGE_SAMPLE_C_D 0x0000002a
17897	#define SQ_IMAGE_SAMPLE_C_D_CL 0x0000002b
17898	#define SQ_IMAGE_SAMPLE_C_L 0x0000002c
17899	#define SQ_IMAGE_SAMPLE_C_B 0x0000002d
17900	#define SQ_IMAGE_SAMPLE_C_B_CL 0x0000002e
17901	#define SQ_IMAGE_SAMPLE_C_LZ 0x0000002f
17902	#define SQ_IMAGE_SAMPLE_O 0x00000030
17903	#define SQ_IMAGE_SAMPLE_CL_O 0x00000031
17904	#define SQ_IMAGE_SAMPLE_D_O 0x00000032
17905	#define SQ_IMAGE_SAMPLE_D_CL_O 0x00000033
17906	#define SQ_IMAGE_SAMPLE_L_O 0x00000034
17907	#define SQ_IMAGE_SAMPLE_B_O 0x00000035
17908	#define SQ_IMAGE_SAMPLE_B_CL_O 0x00000036
17909	#define SQ_IMAGE_SAMPLE_LZ_O 0x00000037
17910	#define SQ_IMAGE_SAMPLE_C_O 0x00000038
17911	#define SQ_IMAGE_SAMPLE_C_CL_O 0x00000039
17912	#define SQ_IMAGE_SAMPLE_C_D_O 0x0000003a
17913	#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x0000003b
17914	#define SQ_IMAGE_SAMPLE_C_L_O 0x0000003c
17915	#define SQ_IMAGE_SAMPLE_C_B_O 0x0000003d
17916	#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x0000003e
17917	#define SQ_IMAGE_SAMPLE_C_LZ_O 0x0000003f
17918	#define SQ_IMAGE_GATHER4 0x00000040
17919	#define SQ_IMAGE_GATHER4_CL 0x00000041
17920	#define SQ_IMAGE_GATHER4H 0x00000042
17921	#define SQ_IMAGE_GATHER4_L 0x00000044
17922	#define SQ_IMAGE_GATHER4_B 0x00000045
17923	#define SQ_IMAGE_GATHER4_B_CL 0x00000046
17924	#define SQ_IMAGE_GATHER4_LZ 0x00000047
17925	#define SQ_IMAGE_GATHER4_C 0x00000048
17926	#define SQ_IMAGE_GATHER4_C_CL 0x00000049
17927	#define SQ_IMAGE_GATHER4H_PCK 0x0000004a
17928	#define SQ_IMAGE_GATHER8H_PCK 0x0000004b
17929	#define SQ_IMAGE_GATHER4_C_L 0x0000004c
17930	#define SQ_IMAGE_GATHER4_C_B 0x0000004d
17931	#define SQ_IMAGE_GATHER4_C_B_CL 0x0000004e
17932	#define SQ_IMAGE_GATHER4_C_LZ 0x0000004f
17933	#define SQ_IMAGE_GATHER4_O 0x00000050
17934	#define SQ_IMAGE_GATHER4_CL_O 0x00000051
17935	#define SQ_IMAGE_GATHER4_L_O 0x00000054
17936	#define SQ_IMAGE_GATHER4_B_O 0x00000055
17937	#define SQ_IMAGE_GATHER4_B_CL_O 0x00000056
17938	#define SQ_IMAGE_GATHER4_LZ_O 0x00000057
17939	#define SQ_IMAGE_GATHER4_C_O 0x00000058
17940	#define SQ_IMAGE_GATHER4_C_CL_O 0x00000059
17941	#define SQ_IMAGE_GATHER4_C_L_O 0x0000005c
17942	#define SQ_IMAGE_GATHER4_C_B_O 0x0000005d
17943	#define SQ_IMAGE_GATHER4_C_B_CL_O 0x0000005e
17944	#define SQ_IMAGE_GATHER4_C_LZ_O 0x0000005f
17945	#define SQ_IMAGE_GET_LOD 0x00000060
17946	#define SQ_IMAGE_SAMPLE_CD 0x00000068
17947	#define SQ_IMAGE_SAMPLE_CD_CL 0x00000069
17948	#define SQ_IMAGE_SAMPLE_C_CD 0x0000006a
17949	#define SQ_IMAGE_SAMPLE_C_CD_CL 0x0000006b
17950	#define SQ_IMAGE_SAMPLE_CD_O 0x0000006c
17951	#define SQ_IMAGE_SAMPLE_CD_CL_O 0x0000006d
17952	#define SQ_IMAGE_SAMPLE_C_CD_O 0x0000006e
17953	#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x0000006f
17954	#define SQ_IMAGE_RSRC256 0x0000007e
17955	#define SQ_IMAGE_SAMPLER 0x0000007f
17956
17957	/*
17958	* VALUE_SQ_HW_REG value
17959	*/
17960
17961	#define SQ_HW_REG_MODE 0x00000001
17962	#define SQ_HW_REG_STATUS 0x00000002
17963	#define SQ_HW_REG_TRAPSTS 0x00000003
17964	#define SQ_HW_REG_HW_ID 0x00000004
17965	#define SQ_HW_REG_GPR_ALLOC 0x00000005
17966	#define SQ_HW_REG_LDS_ALLOC 0x00000006
17967	#define SQ_HW_REG_IB_STS 0x00000007
17968	#define SQ_HW_REG_PC_LO 0x00000008
17969	#define SQ_HW_REG_PC_HI 0x00000009
17970	#define SQ_HW_REG_INST_DW0 0x0000000a
17971	#define SQ_HW_REG_INST_DW1 0x0000000b
17972	#define SQ_HW_REG_IB_DBG0 0x0000000c
17973	#define SQ_HW_REG_IB_DBG1 0x0000000d
17974	#define SQ_HW_REG_FLUSH_IB 0x0000000e
17975	#define SQ_HW_REG_SH_MEM_BASES 0x0000000f
17976	#define SQ_HW_REG_SQ_SHADER_TBA_LO 0x00000010
17977	#define SQ_HW_REG_SQ_SHADER_TBA_HI 0x00000011
17978	#define SQ_HW_REG_SQ_SHADER_TMA_LO 0x00000012
17979	#define SQ_HW_REG_SQ_SHADER_TMA_HI 0x00000013
17980
17981	/*
17982	* VALUE_SQ_OP_SOP1 value
17983	*/
17984
17985	#define SQ_S_MOV_B32 0x00000000
17986	#define SQ_S_MOV_B64 0x00000001
17987	#define SQ_S_CMOV_B32 0x00000002
17988	#define SQ_S_CMOV_B64 0x00000003
17989	#define SQ_S_NOT_B32 0x00000004
17990	#define SQ_S_NOT_B64 0x00000005
17991	#define SQ_S_WQM_B32 0x00000006
17992	#define SQ_S_WQM_B64 0x00000007
17993	#define SQ_S_BREV_B32 0x00000008
17994	#define SQ_S_BREV_B64 0x00000009
17995	#define SQ_S_BCNT0_I32_B32 0x0000000a
17996	#define SQ_S_BCNT0_I32_B64 0x0000000b
17997	#define SQ_S_BCNT1_I32_B32 0x0000000c
17998	#define SQ_S_BCNT1_I32_B64 0x0000000d
17999	#define SQ_S_FF0_I32_B32 0x0000000e
18000	#define SQ_S_FF0_I32_B64 0x0000000f
18001	#define SQ_S_FF1_I32_B32 0x00000010
18002	#define SQ_S_FF1_I32_B64 0x00000011
18003	#define SQ_S_FLBIT_I32_B32 0x00000012
18004	#define SQ_S_FLBIT_I32_B64 0x00000013
18005	#define SQ_S_FLBIT_I32 0x00000014
18006	#define SQ_S_FLBIT_I32_I64 0x00000015
18007	#define SQ_S_SEXT_I32_I8 0x00000016
18008	#define SQ_S_SEXT_I32_I16 0x00000017
18009	#define SQ_S_BITSET0_B32 0x00000018
18010	#define SQ_S_BITSET0_B64 0x00000019
18011	#define SQ_S_BITSET1_B32 0x0000001a
18012	#define SQ_S_BITSET1_B64 0x0000001b
18013	#define SQ_S_GETPC_B64 0x0000001c
18014	#define SQ_S_SETPC_B64 0x0000001d
18015	#define SQ_S_SWAPPC_B64 0x0000001e
18016	#define SQ_S_RFE_B64 0x0000001f
18017	#define SQ_S_AND_SAVEEXEC_B64 0x00000020
18018	#define SQ_S_OR_SAVEEXEC_B64 0x00000021
18019	#define SQ_S_XOR_SAVEEXEC_B64 0x00000022
18020	#define SQ_S_ANDN2_SAVEEXEC_B64 0x00000023
18021	#define SQ_S_ORN2_SAVEEXEC_B64 0x00000024
18022	#define SQ_S_NAND_SAVEEXEC_B64 0x00000025
18023	#define SQ_S_NOR_SAVEEXEC_B64 0x00000026
18024	#define SQ_S_XNOR_SAVEEXEC_B64 0x00000027
18025	#define SQ_S_QUADMASK_B32 0x00000028
18026	#define SQ_S_QUADMASK_B64 0x00000029
18027	#define SQ_S_MOVRELS_B32 0x0000002a
18028	#define SQ_S_MOVRELS_B64 0x0000002b
18029	#define SQ_S_MOVRELD_B32 0x0000002c
18030	#define SQ_S_MOVRELD_B64 0x0000002d
18031	#define SQ_S_CBRANCH_JOIN 0x0000002e
18032	#define SQ_S_MOV_REGRD_B32 0x0000002f
18033	#define SQ_S_ABS_I32 0x00000030
18034	#define SQ_S_MOV_FED_B32 0x00000031
18035	#define SQ_S_SET_GPR_IDX_IDX 0x00000032
18036	#define SQ_S_ANDN1_SAVEEXEC_B64 0x00000033
18037	#define SQ_S_ORN1_SAVEEXEC_B64 0x00000034
18038	#define SQ_S_ANDN1_WREXEC_B64 0x00000035
18039	#define SQ_S_ANDN2_WREXEC_B64 0x00000036
18040	#define SQ_S_BITREPLICATE_B64_B32 0x00000037
18041
18042	/*
18043	* VALUE_SQ_CNT value
18044	*/
18045
18046	#define SQ_CNT1 0x00000000
18047	#define SQ_CNT2 0x00000001
18048	#define SQ_CNT3 0x00000002
18049	#define SQ_CNT4 0x00000003
18050
18051	/*
18052	* VALUE_SQ_OP_VOP3 value
18053	*/
18054
18055	#define SQ_V_MAD_LEGACY_F32 0x000001c0
18056	#define SQ_V_MAD_F32 0x000001c1
18057	#define SQ_V_MAD_I32_I24 0x000001c2
18058	#define SQ_V_MAD_U32_U24 0x000001c3
18059	#define SQ_V_CUBEID_F32 0x000001c4
18060	#define SQ_V_CUBESC_F32 0x000001c5
18061	#define SQ_V_CUBETC_F32 0x000001c6
18062	#define SQ_V_CUBEMA_F32 0x000001c7
18063	#define SQ_V_BFE_U32 0x000001c8
18064	#define SQ_V_BFE_I32 0x000001c9
18065	#define SQ_V_BFI_B32 0x000001ca
18066	#define SQ_V_FMA_F32 0x000001cb
18067	#define SQ_V_FMA_F64 0x000001cc
18068	#define SQ_V_LERP_U8 0x000001cd
18069	#define SQ_V_ALIGNBIT_B32 0x000001ce
18070	#define SQ_V_ALIGNBYTE_B32 0x000001cf
18071	#define SQ_V_MIN3_F32 0x000001d0
18072	#define SQ_V_MIN3_I32 0x000001d1
18073	#define SQ_V_MIN3_U32 0x000001d2
18074	#define SQ_V_MAX3_F32 0x000001d3
18075	#define SQ_V_MAX3_I32 0x000001d4
18076	#define SQ_V_MAX3_U32 0x000001d5
18077	#define SQ_V_MED3_F32 0x000001d6
18078	#define SQ_V_MED3_I32 0x000001d7
18079	#define SQ_V_MED3_U32 0x000001d8
18080	#define SQ_V_SAD_U8 0x000001d9
18081	#define SQ_V_SAD_HI_U8 0x000001da
18082	#define SQ_V_SAD_U16 0x000001db
18083	#define SQ_V_SAD_U32 0x000001dc
18084	#define SQ_V_CVT_PK_U8_F32 0x000001dd
18085	#define SQ_V_DIV_FIXUP_F32 0x000001de
18086	#define SQ_V_DIV_FIXUP_F64 0x000001df
18087	#define SQ_V_DIV_SCALE_F32 0x000001e0
18088	#define SQ_V_DIV_SCALE_F64 0x000001e1
18089	#define SQ_V_DIV_FMAS_F32 0x000001e2
18090	#define SQ_V_DIV_FMAS_F64 0x000001e3
18091	#define SQ_V_MSAD_U8 0x000001e4
18092	#define SQ_V_QSAD_PK_U16_U8 0x000001e5
18093	#define SQ_V_MQSAD_PK_U16_U8 0x000001e6
18094	#define SQ_V_MQSAD_U32_U8 0x000001e7
18095	#define SQ_V_MAD_U64_U32 0x000001e8
18096	#define SQ_V_MAD_I64_I32 0x000001e9
18097	#define SQ_V_MAD_LEGACY_F16 0x000001ea
18098	#define SQ_V_MAD_LEGACY_U16 0x000001eb
18099	#define SQ_V_MAD_LEGACY_I16 0x000001ec
18100	#define SQ_V_PERM_B32 0x000001ed
18101	#define SQ_V_FMA_LEGACY_F16 0x000001ee
18102	#define SQ_V_DIV_FIXUP_LEGACY_F16 0x000001ef
18103	#define SQ_V_CVT_PKACCUM_U8_F32 0x000001f0
18104	#define SQ_V_MAD_U32_U16 0x000001f1
18105	#define SQ_V_MAD_I32_I16 0x000001f2
18106	#define SQ_V_XAD_U32 0x000001f3
18107	#define SQ_V_MIN3_F16 0x000001f4
18108	#define SQ_V_MIN3_I16 0x000001f5
18109	#define SQ_V_MIN3_U16 0x000001f6
18110	#define SQ_V_MAX3_F16 0x000001f7
18111	#define SQ_V_MAX3_I16 0x000001f8
18112	#define SQ_V_MAX3_U16 0x000001f9
18113	#define SQ_V_MED3_F16 0x000001fa
18114	#define SQ_V_MED3_I16 0x000001fb
18115	#define SQ_V_MED3_U16 0x000001fc
18116	#define SQ_V_LSHL_ADD_U32 0x000001fd
18117	#define SQ_V_ADD_LSHL_U32 0x000001fe
18118	#define SQ_V_ADD3_U32 0x000001ff
18119	#define SQ_V_LSHL_OR_B32 0x00000200
18120	#define SQ_V_AND_OR_B32 0x00000201
18121	#define SQ_V_OR3_B32 0x00000202
18122	#define SQ_V_MAD_F16 0x00000203
18123	#define SQ_V_MAD_U16 0x00000204
18124	#define SQ_V_MAD_I16 0x00000205
18125	#define SQ_V_FMA_F16 0x00000206
18126	#define SQ_V_DIV_FIXUP_F16 0x00000207
18127	#define SQ_V_INTERP_P1LL_F16 0x00000274
18128	#define SQ_V_INTERP_P1LV_F16 0x00000275
18129	#define SQ_V_INTERP_P2_LEGACY_F16 0x00000276
18130	#define SQ_V_INTERP_P2_F16 0x00000277
18131	#define SQ_V_ADD_F64 0x00000280
18132	#define SQ_V_MUL_F64 0x00000281
18133	#define SQ_V_MIN_F64 0x00000282
18134	#define SQ_V_MAX_F64 0x00000283
18135	#define SQ_V_LDEXP_F64 0x00000284
18136	#define SQ_V_MUL_LO_U32 0x00000285
18137	#define SQ_V_MUL_HI_U32 0x00000286
18138	#define SQ_V_MUL_HI_I32 0x00000287
18139	#define SQ_V_LDEXP_F32 0x00000288
18140	#define SQ_V_READLANE_B32 0x00000289
18141	#define SQ_V_WRITELANE_B32 0x0000028a
18142	#define SQ_V_BCNT_U32_B32 0x0000028b
18143	#define SQ_V_MBCNT_LO_U32_B32 0x0000028c
18144	#define SQ_V_MBCNT_HI_U32_B32 0x0000028d
18145	#define SQ_V_MAC_LEGACY_F32 0x0000028e
18146	#define SQ_V_LSHLREV_B64 0x0000028f
18147	#define SQ_V_LSHRREV_B64 0x00000290
18148	#define SQ_V_ASHRREV_I64 0x00000291
18149	#define SQ_V_TRIG_PREOP_F64 0x00000292
18150	#define SQ_V_BFM_B32 0x00000293
18151	#define SQ_V_CVT_PKNORM_I16_F32 0x00000294
18152	#define SQ_V_CVT_PKNORM_U16_F32 0x00000295
18153	#define SQ_V_CVT_PKRTZ_F16_F32 0x00000296
18154	#define SQ_V_CVT_PK_U16_U32 0x00000297
18155	#define SQ_V_CVT_PK_I16_I32 0x00000298
18156	#define SQ_V_CVT_PKNORM_I16_F16 0x00000299
18157	#define SQ_V_CVT_PKNORM_U16_F16 0x0000029a
18158	#define SQ_V_READLANE_REGRD_B32 0x0000029b
18159	#define SQ_V_ADD_I32 0x0000029c
18160	#define SQ_V_SUB_I32 0x0000029d
18161	#define SQ_V_ADD_I16 0x0000029e
18162	#define SQ_V_SUB_I16 0x0000029f
18163	#define SQ_V_PACK_B32_F16 0x000002a0
18164
18165	/*
18166	* VALUE_SQ_SSRC_SPECIAL_LIT value
18167	*/
18168
18169	#define SQ_SRC_LITERAL 0x000000ff
18170
18171	/*
18172	* VALUE_SQ_DPP_CTRL value
18173	*/
18174
18175	#define SQ_DPP_QUAD_PERM 0x00000000
18176	#define SQ_DPP_ROW_SL1 0x00000101
18177	#define SQ_DPP_ROW_SL2 0x00000102
18178	#define SQ_DPP_ROW_SL3 0x00000103
18179	#define SQ_DPP_ROW_SL4 0x00000104
18180	#define SQ_DPP_ROW_SL5 0x00000105
18181	#define SQ_DPP_ROW_SL6 0x00000106
18182	#define SQ_DPP_ROW_SL7 0x00000107
18183	#define SQ_DPP_ROW_SL8 0x00000108
18184	#define SQ_DPP_ROW_SL9 0x00000109
18185	#define SQ_DPP_ROW_SL10 0x0000010a
18186	#define SQ_DPP_ROW_SL11 0x0000010b
18187	#define SQ_DPP_ROW_SL12 0x0000010c
18188	#define SQ_DPP_ROW_SL13 0x0000010d
18189	#define SQ_DPP_ROW_SL14 0x0000010e
18190	#define SQ_DPP_ROW_SL15 0x0000010f
18191	#define SQ_DPP_ROW_SR1 0x00000111
18192	#define SQ_DPP_ROW_SR2 0x00000112
18193	#define SQ_DPP_ROW_SR3 0x00000113
18194	#define SQ_DPP_ROW_SR4 0x00000114
18195	#define SQ_DPP_ROW_SR5 0x00000115
18196	#define SQ_DPP_ROW_SR6 0x00000116
18197	#define SQ_DPP_ROW_SR7 0x00000117
18198	#define SQ_DPP_ROW_SR8 0x00000118
18199	#define SQ_DPP_ROW_SR9 0x00000119
18200	#define SQ_DPP_ROW_SR10 0x0000011a
18201	#define SQ_DPP_ROW_SR11 0x0000011b
18202	#define SQ_DPP_ROW_SR12 0x0000011c
18203	#define SQ_DPP_ROW_SR13 0x0000011d
18204	#define SQ_DPP_ROW_SR14 0x0000011e
18205	#define SQ_DPP_ROW_SR15 0x0000011f
18206	#define SQ_DPP_ROW_RR1 0x00000121
18207	#define SQ_DPP_ROW_RR2 0x00000122
18208	#define SQ_DPP_ROW_RR3 0x00000123
18209	#define SQ_DPP_ROW_RR4 0x00000124
18210	#define SQ_DPP_ROW_RR5 0x00000125
18211	#define SQ_DPP_ROW_RR6 0x00000126
18212	#define SQ_DPP_ROW_RR7 0x00000127
18213	#define SQ_DPP_ROW_RR8 0x00000128
18214	#define SQ_DPP_ROW_RR9 0x00000129
18215	#define SQ_DPP_ROW_RR10 0x0000012a
18216	#define SQ_DPP_ROW_RR11 0x0000012b
18217	#define SQ_DPP_ROW_RR12 0x0000012c
18218	#define SQ_DPP_ROW_RR13 0x0000012d
18219	#define SQ_DPP_ROW_RR14 0x0000012e
18220	#define SQ_DPP_ROW_RR15 0x0000012f
18221	#define SQ_DPP_WF_SL1 0x00000130
18222	#define SQ_DPP_WF_RL1 0x00000134
18223	#define SQ_DPP_WF_SR1 0x00000138
18224	#define SQ_DPP_WF_RR1 0x0000013c
18225	#define SQ_DPP_ROW_MIRROR 0x00000140
18226	#define SQ_DPP_ROW_HALF_MIRROR 0x00000141
18227	#define SQ_DPP_ROW_BCAST15 0x00000142
18228	#define SQ_DPP_ROW_BCAST31 0x00000143
18229
18230	/*
18231	* VALUE_SQ_FLAT_SCRATCH_LOHI value
18232	*/
18233
18234	#define SQ_FLAT_SCRATCH_LO 0x00000066
18235	#define SQ_FLAT_SCRATCH_HI 0x00000067
18236
18237	/*
18238	* VALUE_SQ_OP_VOP1 value
18239	*/
18240
18241	#define SQ_V_NOP 0x00000000
18242	#define SQ_V_MOV_B32 0x00000001
18243	#define SQ_V_READFIRSTLANE_B32 0x00000002
18244	#define SQ_V_CVT_I32_F64 0x00000003
18245	#define SQ_V_CVT_F64_I32 0x00000004
18246	#define SQ_V_CVT_F32_I32 0x00000005
18247	#define SQ_V_CVT_F32_U32 0x00000006
18248	#define SQ_V_CVT_U32_F32 0x00000007
18249	#define SQ_V_CVT_I32_F32 0x00000008
18250	#define SQ_V_MOV_FED_B32 0x00000009
18251	#define SQ_V_CVT_F16_F32 0x0000000a
18252	#define SQ_V_CVT_F32_F16 0x0000000b
18253	#define SQ_V_CVT_RPI_I32_F32 0x0000000c
18254	#define SQ_V_CVT_FLR_I32_F32 0x0000000d
18255	#define SQ_V_CVT_OFF_F32_I4 0x0000000e
18256	#define SQ_V_CVT_F32_F64 0x0000000f
18257	#define SQ_V_CVT_F64_F32 0x00000010
18258	#define SQ_V_CVT_F32_UBYTE0 0x00000011
18259	#define SQ_V_CVT_F32_UBYTE1 0x00000012
18260	#define SQ_V_CVT_F32_UBYTE2 0x00000013
18261	#define SQ_V_CVT_F32_UBYTE3 0x00000014
18262	#define SQ_V_CVT_U32_F64 0x00000015
18263	#define SQ_V_CVT_F64_U32 0x00000016
18264	#define SQ_V_TRUNC_F64 0x00000017
18265	#define SQ_V_CEIL_F64 0x00000018
18266	#define SQ_V_RNDNE_F64 0x00000019
18267	#define SQ_V_FLOOR_F64 0x0000001a
18268	#define SQ_V_FRACT_F32 0x0000001b
18269	#define SQ_V_TRUNC_F32 0x0000001c
18270	#define SQ_V_CEIL_F32 0x0000001d
18271	#define SQ_V_RNDNE_F32 0x0000001e
18272	#define SQ_V_FLOOR_F32 0x0000001f
18273	#define SQ_V_EXP_F32 0x00000020
18274	#define SQ_V_LOG_F32 0x00000021
18275	#define SQ_V_RCP_F32 0x00000022
18276	#define SQ_V_RCP_IFLAG_F32 0x00000023
18277	#define SQ_V_RSQ_F32 0x00000024
18278	#define SQ_V_RCP_F64 0x00000025
18279	#define SQ_V_RSQ_F64 0x00000026
18280	#define SQ_V_SQRT_F32 0x00000027
18281	#define SQ_V_SQRT_F64 0x00000028
18282	#define SQ_V_SIN_F32 0x00000029
18283	#define SQ_V_COS_F32 0x0000002a
18284	#define SQ_V_NOT_B32 0x0000002b
18285	#define SQ_V_BFREV_B32 0x0000002c
18286	#define SQ_V_FFBH_U32 0x0000002d
18287	#define SQ_V_FFBL_B32 0x0000002e
18288	#define SQ_V_FFBH_I32 0x0000002f
18289	#define SQ_V_FREXP_EXP_I32_F64 0x00000030
18290	#define SQ_V_FREXP_MANT_F64 0x00000031
18291	#define SQ_V_FRACT_F64 0x00000032
18292	#define SQ_V_FREXP_EXP_I32_F32 0x00000033
18293	#define SQ_V_FREXP_MANT_F32 0x00000034
18294	#define SQ_V_CLREXCP 0x00000035
18295	#define SQ_V_MOV_PRSV_B32 0x00000036
18296	#define SQ_V_CVT_F16_U16 0x00000039
18297	#define SQ_V_CVT_F16_I16 0x0000003a
18298	#define SQ_V_CVT_U16_F16 0x0000003b
18299	#define SQ_V_CVT_I16_F16 0x0000003c
18300	#define SQ_V_RCP_F16 0x0000003d
18301	#define SQ_V_SQRT_F16 0x0000003e
18302	#define SQ_V_RSQ_F16 0x0000003f
18303	#define SQ_V_LOG_F16 0x00000040
18304	#define SQ_V_EXP_F16 0x00000041
18305	#define SQ_V_FREXP_MANT_F16 0x00000042
18306	#define SQ_V_FREXP_EXP_I16_F16 0x00000043
18307	#define SQ_V_FLOOR_F16 0x00000044
18308	#define SQ_V_CEIL_F16 0x00000045
18309	#define SQ_V_TRUNC_F16 0x00000046
18310	#define SQ_V_RNDNE_F16 0x00000047
18311	#define SQ_V_FRACT_F16 0x00000048
18312	#define SQ_V_SIN_F16 0x00000049
18313	#define SQ_V_COS_F16 0x0000004a
18314	#define SQ_V_EXP_LEGACY_F32 0x0000004b
18315	#define SQ_V_LOG_LEGACY_F32 0x0000004c
18316	#define SQ_V_CVT_NORM_I16_F16 0x0000004d
18317	#define SQ_V_CVT_NORM_U16_F16 0x0000004e
18318	#define SQ_V_SAT_PK_U8_I16 0x0000004f
18319	#define SQ_V_WRITELANE_IMM32 0x00000050
18320	#define SQ_V_SWAP_B32 0x00000051
18321
18322	/*
18323	* VALUE_SQ_OP_FLAT value
18324	*/
18325
18326	#define SQ_FLAT_LOAD_UBYTE 0x00000010
18327	#define SQ_FLAT_LOAD_SBYTE 0x00000011
18328	#define SQ_FLAT_LOAD_USHORT 0x00000012
18329	#define SQ_FLAT_LOAD_SSHORT 0x00000013
18330	#define SQ_FLAT_LOAD_DWORD 0x00000014
18331	#define SQ_FLAT_LOAD_DWORDX2 0x00000015
18332	#define SQ_FLAT_LOAD_DWORDX3 0x00000016
18333	#define SQ_FLAT_LOAD_DWORDX4 0x00000017
18334	#define SQ_FLAT_STORE_BYTE 0x00000018
18335	#define SQ_FLAT_STORE_SHORT 0x0000001a
18336	#define SQ_FLAT_STORE_DWORD 0x0000001c
18337	#define SQ_FLAT_STORE_DWORDX2 0x0000001d
18338	#define SQ_FLAT_STORE_DWORDX3 0x0000001e
18339	#define SQ_FLAT_STORE_DWORDX4 0x0000001f
18340	#define SQ_FLAT_ATOMIC_SWAP 0x00000040
18341	#define SQ_FLAT_ATOMIC_CMPSWAP 0x00000041
18342	#define SQ_FLAT_ATOMIC_ADD 0x00000042
18343	#define SQ_FLAT_ATOMIC_SUB 0x00000043
18344	#define SQ_FLAT_ATOMIC_SMIN 0x00000044
18345	#define SQ_FLAT_ATOMIC_UMIN 0x00000045
18346	#define SQ_FLAT_ATOMIC_SMAX 0x00000046
18347	#define SQ_FLAT_ATOMIC_UMAX 0x00000047
18348	#define SQ_FLAT_ATOMIC_AND 0x00000048
18349	#define SQ_FLAT_ATOMIC_OR 0x00000049
18350	#define SQ_FLAT_ATOMIC_XOR 0x0000004a
18351	#define SQ_FLAT_ATOMIC_INC 0x0000004b
18352	#define SQ_FLAT_ATOMIC_DEC 0x0000004c
18353	#define SQ_FLAT_ATOMIC_SWAP_X2 0x00000060
18354	#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x00000061
18355	#define SQ_FLAT_ATOMIC_ADD_X2 0x00000062
18356	#define SQ_FLAT_ATOMIC_SUB_X2 0x00000063
18357	#define SQ_FLAT_ATOMIC_SMIN_X2 0x00000064
18358	#define SQ_FLAT_ATOMIC_UMIN_X2 0x00000065
18359	#define SQ_FLAT_ATOMIC_SMAX_X2 0x00000066
18360	#define SQ_FLAT_ATOMIC_UMAX_X2 0x00000067
18361	#define SQ_FLAT_ATOMIC_AND_X2 0x00000068
18362	#define SQ_FLAT_ATOMIC_OR_X2 0x00000069
18363	#define SQ_FLAT_ATOMIC_XOR_X2 0x0000006a
18364	#define SQ_FLAT_ATOMIC_INC_X2 0x0000006b
18365	#define SQ_FLAT_ATOMIC_DEC_X2 0x0000006c
18366
18367	/*
18368	* VALUE_SQ_OP_DS value
18369	*/
18370
18371	#define SQ_DS_ADD_U32 0x00000000
18372	#define SQ_DS_SUB_U32 0x00000001
18373	#define SQ_DS_RSUB_U32 0x00000002
18374	#define SQ_DS_INC_U32 0x00000003
18375	#define SQ_DS_DEC_U32 0x00000004
18376	#define SQ_DS_MIN_I32 0x00000005
18377	#define SQ_DS_MAX_I32 0x00000006
18378	#define SQ_DS_MIN_U32 0x00000007
18379	#define SQ_DS_MAX_U32 0x00000008
18380	#define SQ_DS_AND_B32 0x00000009
18381	#define SQ_DS_OR_B32 0x0000000a
18382	#define SQ_DS_XOR_B32 0x0000000b
18383	#define SQ_DS_MSKOR_B32 0x0000000c
18384	#define SQ_DS_WRITE_B32 0x0000000d
18385	#define SQ_DS_WRITE2_B32 0x0000000e
18386	#define SQ_DS_WRITE2ST64_B32 0x0000000f
18387	#define SQ_DS_CMPST_B32 0x00000010
18388	#define SQ_DS_CMPST_F32 0x00000011
18389	#define SQ_DS_MIN_F32 0x00000012
18390	#define SQ_DS_MAX_F32 0x00000013
18391	#define SQ_DS_NOP 0x00000014
18392	#define SQ_DS_ADD_F32 0x00000015
18393	#define SQ_DS_WRITE_ADDTID_B32 0x0000001d
18394	#define SQ_DS_WRITE_B8 0x0000001e
18395	#define SQ_DS_WRITE_B16 0x0000001f
18396	#define SQ_DS_ADD_RTN_U32 0x00000020
18397	#define SQ_DS_SUB_RTN_U32 0x00000021
18398	#define SQ_DS_RSUB_RTN_U32 0x00000022
18399	#define SQ_DS_INC_RTN_U32 0x00000023
18400	#define SQ_DS_DEC_RTN_U32 0x00000024
18401	#define SQ_DS_MIN_RTN_I32 0x00000025
18402	#define SQ_DS_MAX_RTN_I32 0x00000026
18403	#define SQ_DS_MIN_RTN_U32 0x00000027
18404	#define SQ_DS_MAX_RTN_U32 0x00000028
18405	#define SQ_DS_AND_RTN_B32 0x00000029
18406	#define SQ_DS_OR_RTN_B32 0x0000002a
18407	#define SQ_DS_XOR_RTN_B32 0x0000002b
18408	#define SQ_DS_MSKOR_RTN_B32 0x0000002c
18409	#define SQ_DS_WRXCHG_RTN_B32 0x0000002d
18410	#define SQ_DS_WRXCHG2_RTN_B32 0x0000002e
18411	#define SQ_DS_WRXCHG2ST64_RTN_B32 0x0000002f
18412	#define SQ_DS_CMPST_RTN_B32 0x00000030
18413	#define SQ_DS_CMPST_RTN_F32 0x00000031
18414	#define SQ_DS_MIN_RTN_F32 0x00000032
18415	#define SQ_DS_MAX_RTN_F32 0x00000033
18416	#define SQ_DS_WRAP_RTN_B32 0x00000034
18417	#define SQ_DS_ADD_RTN_F32 0x00000035
18418	#define SQ_DS_READ_B32 0x00000036
18419	#define SQ_DS_READ2_B32 0x00000037
18420	#define SQ_DS_READ2ST64_B32 0x00000038
18421	#define SQ_DS_READ_I8 0x00000039
18422	#define SQ_DS_READ_U8 0x0000003a
18423	#define SQ_DS_READ_I16 0x0000003b
18424	#define SQ_DS_READ_U16 0x0000003c
18425	#define SQ_DS_SWIZZLE_B32 0x0000003d
18426	#define SQ_DS_PERMUTE_B32 0x0000003e
18427	#define SQ_DS_BPERMUTE_B32 0x0000003f
18428	#define SQ_DS_ADD_U64 0x00000040
18429	#define SQ_DS_SUB_U64 0x00000041
18430	#define SQ_DS_RSUB_U64 0x00000042
18431	#define SQ_DS_INC_U64 0x00000043
18432	#define SQ_DS_DEC_U64 0x00000044
18433	#define SQ_DS_MIN_I64 0x00000045
18434	#define SQ_DS_MAX_I64 0x00000046
18435	#define SQ_DS_MIN_U64 0x00000047
18436	#define SQ_DS_MAX_U64 0x00000048
18437	#define SQ_DS_AND_B64 0x00000049
18438	#define SQ_DS_OR_B64 0x0000004a
18439	#define SQ_DS_XOR_B64 0x0000004b
18440	#define SQ_DS_MSKOR_B64 0x0000004c
18441	#define SQ_DS_WRITE_B64 0x0000004d
18442	#define SQ_DS_WRITE2_B64 0x0000004e
18443	#define SQ_DS_WRITE2ST64_B64 0x0000004f
18444	#define SQ_DS_CMPST_B64 0x00000050
18445	#define SQ_DS_CMPST_F64 0x00000051
18446	#define SQ_DS_MIN_F64 0x00000052
18447	#define SQ_DS_MAX_F64 0x00000053
18448	#define SQ_DS_ADD_RTN_U64 0x00000060
18449	#define SQ_DS_SUB_RTN_U64 0x00000061
18450	#define SQ_DS_RSUB_RTN_U64 0x00000062
18451	#define SQ_DS_INC_RTN_U64 0x00000063
18452	#define SQ_DS_DEC_RTN_U64 0x00000064
18453	#define SQ_DS_MIN_RTN_I64 0x00000065
18454	#define SQ_DS_MAX_RTN_I64 0x00000066
18455	#define SQ_DS_MIN_RTN_U64 0x00000067
18456	#define SQ_DS_MAX_RTN_U64 0x00000068
18457	#define SQ_DS_AND_RTN_B64 0x00000069
18458	#define SQ_DS_OR_RTN_B64 0x0000006a
18459	#define SQ_DS_XOR_RTN_B64 0x0000006b
18460	#define SQ_DS_MSKOR_RTN_B64 0x0000006c
18461	#define SQ_DS_WRXCHG_RTN_B64 0x0000006d
18462	#define SQ_DS_WRXCHG2_RTN_B64 0x0000006e
18463	#define SQ_DS_WRXCHG2ST64_RTN_B64 0x0000006f
18464	#define SQ_DS_CMPST_RTN_B64 0x00000070
18465	#define SQ_DS_CMPST_RTN_F64 0x00000071
18466	#define SQ_DS_MIN_RTN_F64 0x00000072
18467	#define SQ_DS_MAX_RTN_F64 0x00000073
18468	#define SQ_DS_READ_B64 0x00000076
18469	#define SQ_DS_READ2_B64 0x00000077
18470	#define SQ_DS_READ2ST64_B64 0x00000078
18471	#define SQ_DS_CONDXCHG32_RTN_B64 0x0000007e
18472	#define SQ_DS_ADD_SRC2_U32 0x00000080
18473	#define SQ_DS_SUB_SRC2_U32 0x00000081
18474	#define SQ_DS_RSUB_SRC2_U32 0x00000082
18475	#define SQ_DS_INC_SRC2_U32 0x00000083
18476	#define SQ_DS_DEC_SRC2_U32 0x00000084
18477	#define SQ_DS_MIN_SRC2_I32 0x00000085
18478	#define SQ_DS_MAX_SRC2_I32 0x00000086
18479	#define SQ_DS_MIN_SRC2_U32 0x00000087
18480	#define SQ_DS_MAX_SRC2_U32 0x00000088
18481	#define SQ_DS_AND_SRC2_B32 0x00000089
18482	#define SQ_DS_OR_SRC2_B32 0x0000008a
18483	#define SQ_DS_XOR_SRC2_B32 0x0000008b
18484	#define SQ_DS_WRITE_SRC2_B32 0x0000008d
18485	#define SQ_DS_MIN_SRC2_F32 0x00000092
18486	#define SQ_DS_MAX_SRC2_F32 0x00000093
18487	#define SQ_DS_ADD_SRC2_F32 0x00000095
18488	#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x00000098
18489	#define SQ_DS_GWS_INIT 0x00000099
18490	#define SQ_DS_GWS_SEMA_V 0x0000009a
18491	#define SQ_DS_GWS_SEMA_BR 0x0000009b
18492	#define SQ_DS_GWS_SEMA_P 0x0000009c
18493	#define SQ_DS_GWS_BARRIER 0x0000009d
18494	#define SQ_DS_READ_ADDTID_B32 0x000000b6
18495	#define SQ_DS_CONSUME 0x000000bd
18496	#define SQ_DS_APPEND 0x000000be
18497	#define SQ_DS_ORDERED_COUNT 0x000000bf
18498	#define SQ_DS_ADD_SRC2_U64 0x000000c0
18499	#define SQ_DS_SUB_SRC2_U64 0x000000c1
18500	#define SQ_DS_RSUB_SRC2_U64 0x000000c2
18501	#define SQ_DS_INC_SRC2_U64 0x000000c3
18502	#define SQ_DS_DEC_SRC2_U64 0x000000c4
18503	#define SQ_DS_MIN_SRC2_I64 0x000000c5
18504	#define SQ_DS_MAX_SRC2_I64 0x000000c6
18505	#define SQ_DS_MIN_SRC2_U64 0x000000c7
18506	#define SQ_DS_MAX_SRC2_U64 0x000000c8
18507	#define SQ_DS_AND_SRC2_B64 0x000000c9
18508	#define SQ_DS_OR_SRC2_B64 0x000000ca
18509	#define SQ_DS_XOR_SRC2_B64 0x000000cb
18510	#define SQ_DS_WRITE_SRC2_B64 0x000000cd
18511	#define SQ_DS_MIN_SRC2_F64 0x000000d2
18512	#define SQ_DS_MAX_SRC2_F64 0x000000d3
18513	#define SQ_DS_WRITE_B96 0x000000de
18514	#define SQ_DS_WRITE_B128 0x000000df
18515	#define SQ_DS_CONDXCHG32_RTN_B128 0x000000fd
18516	#define SQ_DS_READ_B96 0x000000fe
18517	#define SQ_DS_READ_B128 0x000000ff
18518
18519	/*
18520	* VALUE_SQ_OP_SMEM value
18521	*/
18522
18523	#define SQ_S_LOAD_DWORD 0x00000000
18524	#define SQ_S_LOAD_DWORDX2 0x00000001
18525	#define SQ_S_LOAD_DWORDX4 0x00000002
18526	#define SQ_S_LOAD_DWORDX8 0x00000003
18527	#define SQ_S_LOAD_DWORDX16 0x00000004
18528	#define SQ_S_SCRATCH_LOAD_DWORD 0x00000005
18529	#define SQ_S_SCRATCH_LOAD_DWORDX2 0x00000006
18530	#define SQ_S_SCRATCH_LOAD_DWORDX4 0x00000007
18531	#define SQ_S_BUFFER_LOAD_DWORD 0x00000008
18532	#define SQ_S_BUFFER_LOAD_DWORDX2 0x00000009
18533	#define SQ_S_BUFFER_LOAD_DWORDX4 0x0000000a
18534	#define SQ_S_BUFFER_LOAD_DWORDX8 0x0000000b
18535	#define SQ_S_BUFFER_LOAD_DWORDX16 0x0000000c
18536	#define SQ_S_STORE_DWORD 0x00000010
18537	#define SQ_S_STORE_DWORDX2 0x00000011
18538	#define SQ_S_STORE_DWORDX4 0x00000012
18539	#define SQ_S_SCRATCH_STORE_DWORD 0x00000015
18540	#define SQ_S_SCRATCH_STORE_DWORDX2 0x00000016
18541	#define SQ_S_SCRATCH_STORE_DWORDX4 0x00000017
18542	#define SQ_S_BUFFER_STORE_DWORD 0x00000018
18543	#define SQ_S_BUFFER_STORE_DWORDX2 0x00000019
18544	#define SQ_S_BUFFER_STORE_DWORDX4 0x0000001a
18545	#define SQ_S_DCACHE_INV 0x00000020
18546	#define SQ_S_DCACHE_WB 0x00000021
18547	#define SQ_S_DCACHE_INV_VOL 0x00000022
18548	#define SQ_S_DCACHE_WB_VOL 0x00000023
18549	#define SQ_S_MEMTIME 0x00000024
18550	#define SQ_S_MEMREALTIME 0x00000025
18551	#define SQ_S_ATC_PROBE 0x00000026
18552	#define SQ_S_ATC_PROBE_BUFFER 0x00000027
18553	#define SQ_S_BUFFER_ATOMIC_SWAP 0x00000040
18554	#define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x00000041
18555	#define SQ_S_BUFFER_ATOMIC_ADD 0x00000042
18556	#define SQ_S_BUFFER_ATOMIC_SUB 0x00000043
18557	#define SQ_S_BUFFER_ATOMIC_SMIN 0x00000044
18558	#define SQ_S_BUFFER_ATOMIC_UMIN 0x00000045
18559	#define SQ_S_BUFFER_ATOMIC_SMAX 0x00000046
18560	#define SQ_S_BUFFER_ATOMIC_UMAX 0x00000047
18561	#define SQ_S_BUFFER_ATOMIC_AND 0x00000048
18562	#define SQ_S_BUFFER_ATOMIC_OR 0x00000049
18563	#define SQ_S_BUFFER_ATOMIC_XOR 0x0000004a
18564	#define SQ_S_BUFFER_ATOMIC_INC 0x0000004b
18565	#define SQ_S_BUFFER_ATOMIC_DEC 0x0000004c
18566	#define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x00000060
18567	#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061
18568	#define SQ_S_BUFFER_ATOMIC_ADD_X2 0x00000062
18569	#define SQ_S_BUFFER_ATOMIC_SUB_X2 0x00000063
18570	#define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x00000064
18571	#define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x00000065
18572	#define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x00000066
18573	#define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x00000067
18574	#define SQ_S_BUFFER_ATOMIC_AND_X2 0x00000068
18575	#define SQ_S_BUFFER_ATOMIC_OR_X2 0x00000069
18576	#define SQ_S_BUFFER_ATOMIC_XOR_X2 0x0000006a
18577	#define SQ_S_BUFFER_ATOMIC_INC_X2 0x0000006b
18578	#define SQ_S_BUFFER_ATOMIC_DEC_X2 0x0000006c
18579	#define SQ_S_ATOMIC_SWAP 0x00000080
18580	#define SQ_S_ATOMIC_CMPSWAP 0x00000081
18581	#define SQ_S_ATOMIC_ADD 0x00000082
18582	#define SQ_S_ATOMIC_SUB 0x00000083
18583	#define SQ_S_ATOMIC_SMIN 0x00000084
18584	#define SQ_S_ATOMIC_UMIN 0x00000085
18585	#define SQ_S_ATOMIC_SMAX 0x00000086
18586	#define SQ_S_ATOMIC_UMAX 0x00000087
18587	#define SQ_S_ATOMIC_AND 0x00000088
18588	#define SQ_S_ATOMIC_OR 0x00000089
18589	#define SQ_S_ATOMIC_XOR 0x0000008a
18590	#define SQ_S_ATOMIC_INC 0x0000008b
18591	#define SQ_S_ATOMIC_DEC 0x0000008c
18592	#define SQ_S_ATOMIC_SWAP_X2 0x000000a0
18593	#define SQ_S_ATOMIC_CMPSWAP_X2 0x000000a1
18594	#define SQ_S_ATOMIC_ADD_X2 0x000000a2
18595	#define SQ_S_ATOMIC_SUB_X2 0x000000a3
18596	#define SQ_S_ATOMIC_SMIN_X2 0x000000a4
18597	#define SQ_S_ATOMIC_UMIN_X2 0x000000a5
18598	#define SQ_S_ATOMIC_SMAX_X2 0x000000a6
18599	#define SQ_S_ATOMIC_UMAX_X2 0x000000a7
18600	#define SQ_S_ATOMIC_AND_X2 0x000000a8
18601	#define SQ_S_ATOMIC_OR_X2 0x000000a9
18602	#define SQ_S_ATOMIC_XOR_X2 0x000000aa
18603	#define SQ_S_ATOMIC_INC_X2 0x000000ab
18604	#define SQ_S_ATOMIC_DEC_X2 0x000000ac
18605
18606	/*
18607	* VALUE_SQ_OP_VOP2 value
18608	*/
18609
18610	#define SQ_V_CNDMASK_B32 0x00000000
18611	#define SQ_V_ADD_F32 0x00000001
18612	#define SQ_V_SUB_F32 0x00000002
18613	#define SQ_V_SUBREV_F32 0x00000003
18614	#define SQ_V_MUL_LEGACY_F32 0x00000004
18615	#define SQ_V_MUL_F32 0x00000005
18616	#define SQ_V_MUL_I32_I24 0x00000006
18617	#define SQ_V_MUL_HI_I32_I24 0x00000007
18618	#define SQ_V_MUL_U32_U24 0x00000008
18619	#define SQ_V_MUL_HI_U32_U24 0x00000009
18620	#define SQ_V_MIN_F32 0x0000000a
18621	#define SQ_V_MAX_F32 0x0000000b
18622	#define SQ_V_MIN_I32 0x0000000c
18623	#define SQ_V_MAX_I32 0x0000000d
18624	#define SQ_V_MIN_U32 0x0000000e
18625	#define SQ_V_MAX_U32 0x0000000f
18626	#define SQ_V_LSHRREV_B32 0x00000010
18627	#define SQ_V_ASHRREV_I32 0x00000011
18628	#define SQ_V_LSHLREV_B32 0x00000012
18629	#define SQ_V_AND_B32 0x00000013
18630	#define SQ_V_OR_B32 0x00000014
18631	#define SQ_V_XOR_B32 0x00000015
18632	#define SQ_V_MAC_F32 0x00000016
18633	#define SQ_V_MADMK_F32 0x00000017
18634	#define SQ_V_MADAK_F32 0x00000018
18635	#define SQ_V_ADD_CO_U32 0x00000019
18636	#define SQ_V_SUB_CO_U32 0x0000001a
18637	#define SQ_V_SUBREV_CO_U32 0x0000001b
18638	#define SQ_V_ADDC_CO_U32 0x0000001c
18639	#define SQ_V_SUBB_CO_U32 0x0000001d
18640	#define SQ_V_SUBBREV_CO_U32 0x0000001e
18641	#define SQ_V_ADD_F16 0x0000001f
18642	#define SQ_V_SUB_F16 0x00000020
18643	#define SQ_V_SUBREV_F16 0x00000021
18644	#define SQ_V_MUL_F16 0x00000022
18645	#define SQ_V_MAC_F16 0x00000023
18646	#define SQ_V_MADMK_F16 0x00000024
18647	#define SQ_V_MADAK_F16 0x00000025
18648	#define SQ_V_ADD_U16 0x00000026
18649	#define SQ_V_SUB_U16 0x00000027
18650	#define SQ_V_SUBREV_U16 0x00000028
18651	#define SQ_V_MUL_LO_U16 0x00000029
18652	#define SQ_V_LSHLREV_B16 0x0000002a
18653	#define SQ_V_LSHRREV_B16 0x0000002b
18654	#define SQ_V_ASHRREV_I16 0x0000002c
18655	#define SQ_V_MAX_F16 0x0000002d
18656	#define SQ_V_MIN_F16 0x0000002e
18657	#define SQ_V_MAX_U16 0x0000002f
18658	#define SQ_V_MAX_I16 0x00000030
18659	#define SQ_V_MIN_U16 0x00000031
18660	#define SQ_V_MIN_I16 0x00000032
18661	#define SQ_V_LDEXP_F16 0x00000033
18662	#define SQ_V_ADD_U32 0x00000034
18663	#define SQ_V_SUB_U32 0x00000035
18664	#define SQ_V_SUBREV_U32 0x00000036
18665
18666	/*
18667	* VALUE_SQ_SYSMSG_OP value
18668	*/
18669
18670	#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001
18671	#define SQ_SYSMSG_OP_REG_RD 0x00000002
18672	#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x00000003
18673	#define SQ_SYSMSG_OP_TTRACE_PC 0x00000004
18674	#define SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT 0x00000005
18675	#define SQ_SYSMSG_OP_MEMVIOL_INTERRUPT 0x00000006
18676
18677	/*
18678	* VALUE_SQ_SSRC_SPECIAL_VCCZ value
18679	*/
18680
18681	#define SQ_SRC_VCCZ 0x000000fb
18682
18683	/*
18684	* VALUE_SQ_CHAN value
18685	*/
18686
18687	#define SQ_CHAN_X 0x00000000
18688	#define SQ_CHAN_Y 0x00000001
18689	#define SQ_CHAN_Z 0x00000002
18690	#define SQ_CHAN_W 0x00000003
18691
18692	/*
18693	* VALUE_SQ_OP_SOPK value
18694	*/
18695
18696	#define SQ_S_MOVK_I32 0x00000000
18697	#define SQ_S_CMOVK_I32 0x00000001
18698	#define SQ_S_CMPK_EQ_I32 0x00000002
18699	#define SQ_S_CMPK_LG_I32 0x00000003
18700	#define SQ_S_CMPK_GT_I32 0x00000004
18701	#define SQ_S_CMPK_GE_I32 0x00000005
18702	#define SQ_S_CMPK_LT_I32 0x00000006
18703	#define SQ_S_CMPK_LE_I32 0x00000007
18704	#define SQ_S_CMPK_EQ_U32 0x00000008
18705	#define SQ_S_CMPK_LG_U32 0x00000009
18706	#define SQ_S_CMPK_GT_U32 0x0000000a
18707	#define SQ_S_CMPK_GE_U32 0x0000000b
18708	#define SQ_S_CMPK_LT_U32 0x0000000c
18709	#define SQ_S_CMPK_LE_U32 0x0000000d
18710	#define SQ_S_ADDK_I32 0x0000000e
18711	#define SQ_S_MULK_I32 0x0000000f
18712	#define SQ_S_CBRANCH_I_FORK 0x00000010
18713	#define SQ_S_GETREG_B32 0x00000011
18714	#define SQ_S_SETREG_B32 0x00000012
18715	#define SQ_S_GETREG_REGRD_B32 0x00000013
18716	#define SQ_S_SETREG_IMM32_B32 0x00000014
18717	#define SQ_S_CALL_B64 0x00000015
18718
18719	/*
18720	* VALUE_SQ_DPP_CTRL_L_1_15 value
18721	*/
18722
18723	#define SQ_L1 0x00000001
18724	#define SQ_L2 0x00000002
18725	#define SQ_L3 0x00000003
18726	#define SQ_L4 0x00000004
18727	#define SQ_L5 0x00000005
18728	#define SQ_L6 0x00000006
18729	#define SQ_L7 0x00000007
18730	#define SQ_L8 0x00000008
18731	#define SQ_L9 0x00000009
18732	#define SQ_L10 0x0000000a
18733	#define SQ_L11 0x0000000b
18734	#define SQ_L12 0x0000000c
18735	#define SQ_L13 0x0000000d
18736	#define SQ_L14 0x0000000e
18737	#define SQ_L15 0x0000000f
18738
18739	/*
18740	* VALUE_SQ_SGPR value
18741	*/
18742
18743	#define SQ_SGPR0 0x00000000
18744
18745	/*
18746	* VALUE_SQ_OP_VOP3P value
18747	*/
18748
18749	#define SQ_V_PK_MAD_I16 0x00000000
18750	#define SQ_V_PK_MUL_LO_U16 0x00000001
18751	#define SQ_V_PK_ADD_I16 0x00000002
18752	#define SQ_V_PK_SUB_I16 0x00000003
18753	#define SQ_V_PK_LSHLREV_B16 0x00000004
18754	#define SQ_V_PK_LSHRREV_B16 0x00000005
18755	#define SQ_V_PK_ASHRREV_I16 0x00000006
18756	#define SQ_V_PK_MAX_I16 0x00000007
18757	#define SQ_V_PK_MIN_I16 0x00000008
18758	#define SQ_V_PK_MAD_U16 0x00000009
18759	#define SQ_V_PK_ADD_U16 0x0000000a
18760	#define SQ_V_PK_SUB_U16 0x0000000b
18761	#define SQ_V_PK_MAX_U16 0x0000000c
18762	#define SQ_V_PK_MIN_U16 0x0000000d
18763	#define SQ_V_PK_MAD_F16 0x0000000e
18764	#define SQ_V_PK_ADD_F16 0x0000000f
18765	#define SQ_V_PK_MUL_F16 0x00000010
18766	#define SQ_V_PK_MIN_F16 0x00000011
18767	#define SQ_V_PK_MAX_F16 0x00000012
18768	#define SQ_V_MAD_MIX_F32 0x00000020
18769	#define SQ_V_MAD_MIXLO_F16 0x00000021
18770	#define SQ_V_MAD_MIXHI_F16 0x00000022
18771
18772	/*
18773	* VALUE_SQ_OP_VINTRP value
18774	*/
18775
18776	#define SQ_V_INTERP_P1_F32 0x00000000
18777	#define SQ_V_INTERP_P2_F32 0x00000001
18778	#define SQ_V_INTERP_MOV_F32 0x00000002
18779
18780	/*
18781	* VALUE_SQ_DPP_CTRL_R_1_15 value
18782	*/
18783
18784	#define SQ_R1 0x00000001
18785	#define SQ_R2 0x00000002
18786	#define SQ_R3 0x00000003
18787	#define SQ_R4 0x00000004
18788	#define SQ_R5 0x00000005
18789	#define SQ_R6 0x00000006
18790	#define SQ_R7 0x00000007
18791	#define SQ_R8 0x00000008
18792	#define SQ_R9 0x00000009
18793	#define SQ_R10 0x0000000a
18794	#define SQ_R11 0x0000000b
18795	#define SQ_R12 0x0000000c
18796	#define SQ_R13 0x0000000d
18797	#define SQ_R14 0x0000000e
18798	#define SQ_R15 0x0000000f
18799
18800	/*
18801	* VALUE_SQ_OP_SOP2 value
18802	*/
18803
18804	#define SQ_S_ADD_U32 0x00000000
18805	#define SQ_S_SUB_U32 0x00000001
18806	#define SQ_S_ADD_I32 0x00000002
18807	#define SQ_S_SUB_I32 0x00000003
18808	#define SQ_S_ADDC_U32 0x00000004
18809	#define SQ_S_SUBB_U32 0x00000005
18810	#define SQ_S_MIN_I32 0x00000006
18811	#define SQ_S_MIN_U32 0x00000007
18812	#define SQ_S_MAX_I32 0x00000008
18813	#define SQ_S_MAX_U32 0x00000009
18814	#define SQ_S_CSELECT_B32 0x0000000a
18815	#define SQ_S_CSELECT_B64 0x0000000b
18816	#define SQ_S_AND_B32 0x0000000c
18817	#define SQ_S_AND_B64 0x0000000d
18818	#define SQ_S_OR_B32 0x0000000e
18819	#define SQ_S_OR_B64 0x0000000f
18820	#define SQ_S_XOR_B32 0x00000010
18821	#define SQ_S_XOR_B64 0x00000011
18822	#define SQ_S_ANDN2_B32 0x00000012
18823	#define SQ_S_ANDN2_B64 0x00000013
18824	#define SQ_S_ORN2_B32 0x00000014
18825	#define SQ_S_ORN2_B64 0x00000015
18826	#define SQ_S_NAND_B32 0x00000016
18827	#define SQ_S_NAND_B64 0x00000017
18828	#define SQ_S_NOR_B32 0x00000018
18829	#define SQ_S_NOR_B64 0x00000019
18830	#define SQ_S_XNOR_B32 0x0000001a
18831	#define SQ_S_XNOR_B64 0x0000001b
18832	#define SQ_S_LSHL_B32 0x0000001c
18833	#define SQ_S_LSHL_B64 0x0000001d
18834	#define SQ_S_LSHR_B32 0x0000001e
18835	#define SQ_S_LSHR_B64 0x0000001f
18836	#define SQ_S_ASHR_I32 0x00000020
18837	#define SQ_S_ASHR_I64 0x00000021
18838	#define SQ_S_BFM_B32 0x00000022
18839	#define SQ_S_BFM_B64 0x00000023
18840	#define SQ_S_MUL_I32 0x00000024
18841	#define SQ_S_BFE_U32 0x00000025
18842	#define SQ_S_BFE_I32 0x00000026
18843	#define SQ_S_BFE_U64 0x00000027
18844	#define SQ_S_BFE_I64 0x00000028
18845	#define SQ_S_CBRANCH_G_FORK 0x00000029
18846	#define SQ_S_ABSDIFF_I32 0x0000002a
18847	#define SQ_S_RFE_RESTORE_B64 0x0000002b
18848	#define SQ_S_MUL_HI_U32 0x0000002c
18849	#define SQ_S_MUL_HI_I32 0x0000002d
18850	#define SQ_S_LSHL1_ADD_U32 0x0000002e
18851	#define SQ_S_LSHL2_ADD_U32 0x0000002f
18852	#define SQ_S_LSHL3_ADD_U32 0x00000030
18853	#define SQ_S_LSHL4_ADD_U32 0x00000031
18854	#define SQ_S_PACK_LL_B32_B16 0x00000032
18855	#define SQ_S_PACK_LH_B32_B16 0x00000033
18856	#define SQ_S_PACK_HH_B32_B16 0x00000034
18857
18858	/*
18859	* VALUE_SQ_SEG value
18860	*/
18861
18862	#define SQ_FLAT 0x00000000
18863	#define SQ_SCRATCH 0x00000001
18864	#define SQ_GLOBAL 0x00000002
18865
18866	/*
18867	* VALUE_SQ_SDST_EXEC value
18868	*/
18869
18870	#define SQ_EXEC_LO 0x0000007e
18871	#define SQ_EXEC_HI 0x0000007f
18872
18873	/*
18874	* VALUE_SQ_SSRC_SPECIAL_NOLIT value
18875	*/
18876
18877	#define SQ_SRC_64_INT 0x000000c0
18878	#define SQ_SRC_M_1_INT 0x000000c1
18879	#define SQ_SRC_M_2_INT 0x000000c2
18880	#define SQ_SRC_M_3_INT 0x000000c3
18881	#define SQ_SRC_M_4_INT 0x000000c4
18882	#define SQ_SRC_M_5_INT 0x000000c5
18883	#define SQ_SRC_M_6_INT 0x000000c6
18884	#define SQ_SRC_M_7_INT 0x000000c7
18885	#define SQ_SRC_M_8_INT 0x000000c8
18886	#define SQ_SRC_M_9_INT 0x000000c9
18887	#define SQ_SRC_M_10_INT 0x000000ca
18888	#define SQ_SRC_M_11_INT 0x000000cb
18889	#define SQ_SRC_M_12_INT 0x000000cc
18890	#define SQ_SRC_M_13_INT 0x000000cd
18891	#define SQ_SRC_M_14_INT 0x000000ce
18892	#define SQ_SRC_M_15_INT 0x000000cf
18893	#define SQ_SRC_M_16_INT 0x000000d0
18894	#define SQ_SRC_0_5 0x000000f0
18895	#define SQ_SRC_M_0_5 0x000000f1
18896	#define SQ_SRC_1 0x000000f2
18897	#define SQ_SRC_M_1 0x000000f3
18898	#define SQ_SRC_2 0x000000f4
18899	#define SQ_SRC_M_2 0x000000f5
18900	#define SQ_SRC_4 0x000000f6
18901	#define SQ_SRC_M_4 0x000000f7
18902	#define SQ_SRC_INV_2PI 0x000000f8
18903
18904	/*
18905	* VALUE_SQ_VCC_LOHI value
18906	*/
18907
18908	#define SQ_VCC_LO 0x0000006a
18909	#define SQ_VCC_HI 0x0000006b
18910
18911	/*
18912	* VALUE_SQ_TGT value
18913	*/
18914
18915	#define SQ_EXP_MRT0 0x00000000
18916	#define SQ_EXP_MRTZ 0x00000008
18917	#define SQ_EXP_NULL 0x00000009
18918	#define SQ_EXP_POS0 0x0000000c
18919	#define SQ_EXP_PARAM0 0x00000020
18920
18921	/*
18922	* VALUE_SQ_OP_SOPP value
18923	*/
18924
18925	#define SQ_S_NOP 0x00000000
18926	#define SQ_S_ENDPGM 0x00000001
18927	#define SQ_S_BRANCH 0x00000002
18928	#define SQ_S_WAKEUP 0x00000003
18929	#define SQ_S_CBRANCH_SCC0 0x00000004
18930	#define SQ_S_CBRANCH_SCC1 0x00000005
18931	#define SQ_S_CBRANCH_VCCZ 0x00000006
18932	#define SQ_S_CBRANCH_VCCNZ 0x00000007
18933	#define SQ_S_CBRANCH_EXECZ 0x00000008
18934	#define SQ_S_CBRANCH_EXECNZ 0x00000009
18935	#define SQ_S_BARRIER 0x0000000a
18936	#define SQ_S_SETKILL 0x0000000b
18937	#define SQ_S_WAITCNT 0x0000000c
18938	#define SQ_S_SETHALT 0x0000000d
18939	#define SQ_S_SLEEP 0x0000000e
18940	#define SQ_S_SETPRIO 0x0000000f
18941	#define SQ_S_SENDMSG 0x00000010
18942	#define SQ_S_SENDMSGHALT 0x00000011
18943	#define SQ_S_TRAP 0x00000012
18944	#define SQ_S_ICACHE_INV 0x00000013
18945	#define SQ_S_INCPERFLEVEL 0x00000014
18946	#define SQ_S_DECPERFLEVEL 0x00000015
18947	#define SQ_S_TTRACEDATA 0x00000016
18948	#define SQ_S_CBRANCH_CDBGSYS 0x00000017
18949	#define SQ_S_CBRANCH_CDBGUSER 0x00000018
18950	#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x00000019
18951	#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x0000001a
18952	#define SQ_S_ENDPGM_SAVED 0x0000001b
18953	#define SQ_S_SET_GPR_IDX_OFF 0x0000001c
18954	#define SQ_S_SET_GPR_IDX_MODE 0x0000001d
18955	#define SQ_S_ENDPGM_ORDERED_PS_DONE 0x0000001e
18956
18957	/*
18958	* VALUE_SQ_OP_EXP value
18959	*/
18960
18961	#define SQ_EXP 0x00000000
18962
18963	/*
18964	* VALUE_SQ_SSRC_SPECIAL_POPS_EXITING_WAVE_ID value
18965	*/
18966
18967	#define SQ_SRC_POPS_EXITING_WAVE_ID 0x000000ef
18968
18969	/*
18970	* VALUE_SQ_XNACK_MASK_LOHI value
18971	*/
18972
18973	#define SQ_XNACK_MASK_LO 0x00000068
18974	#define SQ_XNACK_MASK_HI 0x00000069
18975
18976	/*
18977	* VALUE_SQ_OMOD value
18978	*/
18979
18980	#define SQ_OMOD_OFF 0x00000000
18981	#define SQ_OMOD_M2 0x00000001
18982	#define SQ_OMOD_M4 0x00000002
18983	#define SQ_OMOD_D2 0x00000003
18984
18985	/*
18986	* VALUE_SQ_SSRC_SPECIAL_EXECZ value
18987	*/
18988
18989	#define SQ_SRC_EXECZ 0x000000fc
18990
18991	/*
18992	* VALUE_SQ_COMPI value
18993	*/
18994
18995	#define SQ_F 0x00000000
18996	#define SQ_LT 0x00000001
18997	#define SQ_EQ 0x00000002
18998	#define SQ_LE 0x00000003
18999	#define SQ_GT 0x00000004
19000	#define SQ_NE 0x00000005
19001	#define SQ_GE 0x00000006
19002	#define SQ_T 0x00000007
19003
19004	/*
19005	* VALUE_SQ_DPP_BOUND_CTRL value
19006	*/
19007
19008	#define SQ_DPP_BOUND_OFF 0x00000000
19009	#define SQ_DPP_BOUND_ZERO 0x00000001
19010
19011	/*
19012	* VALUE_SQ_SDST_M0 value
19013	*/
19014
19015	#define SQ_M0 0x0000007c
19016
19017	/*
19018	* VALUE_SQ_MSG value
19019	*/
19020
19021	#define SQ_MSG_INTERRUPT 0x00000001
19022	#define SQ_MSG_GS 0x00000002
19023	#define SQ_MSG_GS_DONE 0x00000003
19024	#define SQ_MSG_SAVEWAVE 0x00000004
19025	#define SQ_MSG_STALL_WAVE_GEN 0x00000005
19026	#define SQ_MSG_HALT_WAVES 0x00000006
19027	#define SQ_MSG_ORDERED_PS_DONE 0x00000007
19028	#define SQ_MSG_EARLY_PRIM_DEALLOC 0x00000008
19029	#define SQ_MSG_GS_ALLOC_REQ 0x00000009
19030	#define SQ_MSG_SYSMSG 0x0000000f
19031
19032	/*
19033	* VALUE_SQ_PARAM value
19034	*/
19035
19036	#define SQ_PARAM_P10 0x00000000
19037	#define SQ_PARAM_P20 0x00000001
19038	#define SQ_PARAM_P0 0x00000002
19039
19040	/*
19041	* VALUE_SQ_OPU_VOP3 value
19042	*/
19043
19044	#define SQ_V_OPC_OFFSET 0x00000000
19045	#define SQ_V_OP2_OFFSET 0x00000100
19046	#define SQ_V_OP1_OFFSET 0x00000140
19047	#define SQ_V_INTRP_OFFSET 0x00000270
19048	#define SQ_V_OP3P_OFFSET 0x00000380
19049
19050	/*
19051	* VALUE_SQ_SSRC_SPECIAL_SDWA value
19052	*/
19053
19054	#define SQ_SRC_SDWA 0x000000f9
19055
19056	/*
19057	* VALUE_SQ_SSRC_SPECIAL_APERTURE value
19058	*/
19059
19060	#define SQ_SRC_SHARED_BASE 0x000000eb
19061	#define SQ_SRC_SHARED_LIMIT 0x000000ec
19062	#define SQ_SRC_PRIVATE_BASE 0x000000ed
19063	#define SQ_SRC_PRIVATE_LIMIT 0x000000ee
19064
19065	/*
19066	* VALUE_SQ_COMPF value
19067	*/
19068
19069	#define SQ_F 0x00000000
19070	#define SQ_LT 0x00000001
19071	#define SQ_EQ 0x00000002
19072	#define SQ_LE 0x00000003
19073	#define SQ_GT 0x00000004
19074	#define SQ_LG 0x00000005
19075	#define SQ_GE 0x00000006
19076	#define SQ_O 0x00000007
19077	#define SQ_U 0x00000008
19078	#define SQ_NGE 0x00000009
19079	#define SQ_NLG 0x0000000a
19080	#define SQ_NGT 0x0000000b
19081	#define SQ_NLE 0x0000000c
19082	#define SQ_NEQ 0x0000000d
19083	#define SQ_NLT 0x0000000e
19084	#define SQ_TRU 0x0000000f
19085
19086	/*
19087	* VALUE_SQ_SDWA_UNUSED value
19088	*/
19089
19090	#define SQ_SDWA_UNUSED_PAD 0x00000000
19091	#define SQ_SDWA_UNUSED_SEXT 0x00000001
19092	#define SQ_SDWA_UNUSED_PRESERVE 0x00000002
19093
19094	/*
19095	* VALUE_SQ_SSRC_SPECIAL_SCC value
19096	*/
19097
19098	#define SQ_SRC_SCC 0x000000fd
19099
19100	/*
19101	* VALUE_SQ_OP_VOPC value
19102	*/
19103
19104	#define SQ_V_CMP_CLASS_F32 0x00000010
19105	#define SQ_V_CMPX_CLASS_F32 0x00000011
19106	#define SQ_V_CMP_CLASS_F64 0x00000012
19107	#define SQ_V_CMPX_CLASS_F64 0x00000013
19108	#define SQ_V_CMP_CLASS_F16 0x00000014
19109	#define SQ_V_CMPX_CLASS_F16 0x00000015
19110	#define SQ_V_CMP_F_F16 0x00000020
19111	#define SQ_V_CMP_LT_F16 0x00000021
19112	#define SQ_V_CMP_EQ_F16 0x00000022
19113	#define SQ_V_CMP_LE_F16 0x00000023
19114	#define SQ_V_CMP_GT_F16 0x00000024
19115	#define SQ_V_CMP_LG_F16 0x00000025
19116	#define SQ_V_CMP_GE_F16 0x00000026
19117	#define SQ_V_CMP_O_F16 0x00000027
19118	#define SQ_V_CMP_U_F16 0x00000028
19119	#define SQ_V_CMP_NGE_F16 0x00000029
19120	#define SQ_V_CMP_NLG_F16 0x0000002a
19121	#define SQ_V_CMP_NGT_F16 0x0000002b
19122	#define SQ_V_CMP_NLE_F16 0x0000002c
19123	#define SQ_V_CMP_NEQ_F16 0x0000002d
19124	#define SQ_V_CMP_NLT_F16 0x0000002e
19125	#define SQ_V_CMP_TRU_F16 0x0000002f
19126	#define SQ_V_CMPX_F_F16 0x00000030
19127	#define SQ_V_CMPX_LT_F16 0x00000031
19128	#define SQ_V_CMPX_EQ_F16 0x00000032
19129	#define SQ_V_CMPX_LE_F16 0x00000033
19130	#define SQ_V_CMPX_GT_F16 0x00000034
19131	#define SQ_V_CMPX_LG_F16 0x00000035
19132	#define SQ_V_CMPX_GE_F16 0x00000036
19133	#define SQ_V_CMPX_O_F16 0x00000037
19134	#define SQ_V_CMPX_U_F16 0x00000038
19135	#define SQ_V_CMPX_NGE_F16 0x00000039
19136	#define SQ_V_CMPX_NLG_F16 0x0000003a
19137	#define SQ_V_CMPX_NGT_F16 0x0000003b
19138	#define SQ_V_CMPX_NLE_F16 0x0000003c
19139	#define SQ_V_CMPX_NEQ_F16 0x0000003d
19140	#define SQ_V_CMPX_NLT_F16 0x0000003e
19141	#define SQ_V_CMPX_TRU_F16 0x0000003f
19142	#define SQ_V_CMP_F_F32 0x00000040
19143	#define SQ_V_CMP_LT_F32 0x00000041
19144	#define SQ_V_CMP_EQ_F32 0x00000042
19145	#define SQ_V_CMP_LE_F32 0x00000043
19146	#define SQ_V_CMP_GT_F32 0x00000044
19147	#define SQ_V_CMP_LG_F32 0x00000045
19148	#define SQ_V_CMP_GE_F32 0x00000046
19149	#define SQ_V_CMP_O_F32 0x00000047
19150	#define SQ_V_CMP_U_F32 0x00000048
19151	#define SQ_V_CMP_NGE_F32 0x00000049
19152	#define SQ_V_CMP_NLG_F32 0x0000004a
19153	#define SQ_V_CMP_NGT_F32 0x0000004b
19154	#define SQ_V_CMP_NLE_F32 0x0000004c
19155	#define SQ_V_CMP_NEQ_F32 0x0000004d
19156	#define SQ_V_CMP_NLT_F32 0x0000004e
19157	#define SQ_V_CMP_TRU_F32 0x0000004f
19158	#define SQ_V_CMPX_F_F32 0x00000050
19159	#define SQ_V_CMPX_LT_F32 0x00000051
19160	#define SQ_V_CMPX_EQ_F32 0x00000052
19161	#define SQ_V_CMPX_LE_F32 0x00000053
19162	#define SQ_V_CMPX_GT_F32 0x00000054
19163	#define SQ_V_CMPX_LG_F32 0x00000055
19164	#define SQ_V_CMPX_GE_F32 0x00000056
19165	#define SQ_V_CMPX_O_F32 0x00000057
19166	#define SQ_V_CMPX_U_F32 0x00000058
19167	#define SQ_V_CMPX_NGE_F32 0x00000059
19168	#define SQ_V_CMPX_NLG_F32 0x0000005a
19169	#define SQ_V_CMPX_NGT_F32 0x0000005b
19170	#define SQ_V_CMPX_NLE_F32 0x0000005c
19171	#define SQ_V_CMPX_NEQ_F32 0x0000005d
19172	#define SQ_V_CMPX_NLT_F32 0x0000005e
19173	#define SQ_V_CMPX_TRU_F32 0x0000005f
19174	#define SQ_V_CMP_F_F64 0x00000060
19175	#define SQ_V_CMP_LT_F64 0x00000061
19176	#define SQ_V_CMP_EQ_F64 0x00000062
19177	#define SQ_V_CMP_LE_F64 0x00000063
19178	#define SQ_V_CMP_GT_F64 0x00000064
19179	#define SQ_V_CMP_LG_F64 0x00000065
19180	#define SQ_V_CMP_GE_F64 0x00000066
19181	#define SQ_V_CMP_O_F64 0x00000067
19182	#define SQ_V_CMP_U_F64 0x00000068
19183	#define SQ_V_CMP_NGE_F64 0x00000069
19184	#define SQ_V_CMP_NLG_F64 0x0000006a
19185	#define SQ_V_CMP_NGT_F64 0x0000006b
19186	#define SQ_V_CMP_NLE_F64 0x0000006c
19187	#define SQ_V_CMP_NEQ_F64 0x0000006d
19188	#define SQ_V_CMP_NLT_F64 0x0000006e
19189	#define SQ_V_CMP_TRU_F64 0x0000006f
19190	#define SQ_V_CMPX_F_F64 0x00000070
19191	#define SQ_V_CMPX_LT_F64 0x00000071
19192	#define SQ_V_CMPX_EQ_F64 0x00000072
19193	#define SQ_V_CMPX_LE_F64 0x00000073
19194	#define SQ_V_CMPX_GT_F64 0x00000074
19195	#define SQ_V_CMPX_LG_F64 0x00000075
19196	#define SQ_V_CMPX_GE_F64 0x00000076
19197	#define SQ_V_CMPX_O_F64 0x00000077
19198	#define SQ_V_CMPX_U_F64 0x00000078
19199	#define SQ_V_CMPX_NGE_F64 0x00000079
19200	#define SQ_V_CMPX_NLG_F64 0x0000007a
19201	#define SQ_V_CMPX_NGT_F64 0x0000007b
19202	#define SQ_V_CMPX_NLE_F64 0x0000007c
19203	#define SQ_V_CMPX_NEQ_F64 0x0000007d
19204	#define SQ_V_CMPX_NLT_F64 0x0000007e
19205	#define SQ_V_CMPX_TRU_F64 0x0000007f
19206	#define SQ_V_CMP_F_I16 0x000000a0
19207	#define SQ_V_CMP_LT_I16 0x000000a1
19208	#define SQ_V_CMP_EQ_I16 0x000000a2
19209	#define SQ_V_CMP_LE_I16 0x000000a3
19210	#define SQ_V_CMP_GT_I16 0x000000a4
19211	#define SQ_V_CMP_NE_I16 0x000000a5
19212	#define SQ_V_CMP_GE_I16 0x000000a6
19213	#define SQ_V_CMP_T_I16 0x000000a7
19214	#define SQ_V_CMP_F_U16 0x000000a8
19215	#define SQ_V_CMP_LT_U16 0x000000a9
19216	#define SQ_V_CMP_EQ_U16 0x000000aa
19217	#define SQ_V_CMP_LE_U16 0x000000ab
19218	#define SQ_V_CMP_GT_U16 0x000000ac
19219	#define SQ_V_CMP_NE_U16 0x000000ad
19220	#define SQ_V_CMP_GE_U16 0x000000ae
19221	#define SQ_V_CMP_T_U16 0x000000af
19222	#define SQ_V_CMPX_F_I16 0x000000b0
19223	#define SQ_V_CMPX_LT_I16 0x000000b1
19224	#define SQ_V_CMPX_EQ_I16 0x000000b2
19225	#define SQ_V_CMPX_LE_I16 0x000000b3
19226	#define SQ_V_CMPX_GT_I16 0x000000b4
19227	#define SQ_V_CMPX_NE_I16 0x000000b5
19228	#define SQ_V_CMPX_GE_I16 0x000000b6
19229	#define SQ_V_CMPX_T_I16 0x000000b7
19230	#define SQ_V_CMPX_F_U16 0x000000b8
19231	#define SQ_V_CMPX_LT_U16 0x000000b9
19232	#define SQ_V_CMPX_EQ_U16 0x000000ba
19233	#define SQ_V_CMPX_LE_U16 0x000000bb
19234	#define SQ_V_CMPX_GT_U16 0x000000bc
19235	#define SQ_V_CMPX_NE_U16 0x000000bd
19236	#define SQ_V_CMPX_GE_U16 0x000000be
19237	#define SQ_V_CMPX_T_U16 0x000000bf
19238	#define SQ_V_CMP_F_I32 0x000000c0
19239	#define SQ_V_CMP_LT_I32 0x000000c1
19240	#define SQ_V_CMP_EQ_I32 0x000000c2
19241	#define SQ_V_CMP_LE_I32 0x000000c3
19242	#define SQ_V_CMP_GT_I32 0x000000c4
19243	#define SQ_V_CMP_NE_I32 0x000000c5
19244	#define SQ_V_CMP_GE_I32 0x000000c6
19245	#define SQ_V_CMP_T_I32 0x000000c7
19246	#define SQ_V_CMP_F_U32 0x000000c8
19247	#define SQ_V_CMP_LT_U32 0x000000c9
19248	#define SQ_V_CMP_EQ_U32 0x000000ca
19249	#define SQ_V_CMP_LE_U32 0x000000cb
19250	#define SQ_V_CMP_GT_U32 0x000000cc
19251	#define SQ_V_CMP_NE_U32 0x000000cd
19252	#define SQ_V_CMP_GE_U32 0x000000ce
19253	#define SQ_V_CMP_T_U32 0x000000cf
19254	#define SQ_V_CMPX_F_I32 0x000000d0
19255	#define SQ_V_CMPX_LT_I32 0x000000d1
19256	#define SQ_V_CMPX_EQ_I32 0x000000d2
19257	#define SQ_V_CMPX_LE_I32 0x000000d3
19258	#define SQ_V_CMPX_GT_I32 0x000000d4
19259	#define SQ_V_CMPX_NE_I32 0x000000d5
19260	#define SQ_V_CMPX_GE_I32 0x000000d6
19261	#define SQ_V_CMPX_T_I32 0x000000d7
19262	#define SQ_V_CMPX_F_U32 0x000000d8
19263	#define SQ_V_CMPX_LT_U32 0x000000d9
19264	#define SQ_V_CMPX_EQ_U32 0x000000da
19265	#define SQ_V_CMPX_LE_U32 0x000000db
19266	#define SQ_V_CMPX_GT_U32 0x000000dc
19267	#define SQ_V_CMPX_NE_U32 0x000000dd
19268	#define SQ_V_CMPX_GE_U32 0x000000de
19269	#define SQ_V_CMPX_T_U32 0x000000df
19270	#define SQ_V_CMP_F_I64 0x000000e0
19271	#define SQ_V_CMP_LT_I64 0x000000e1
19272	#define SQ_V_CMP_EQ_I64 0x000000e2
19273	#define SQ_V_CMP_LE_I64 0x000000e3
19274	#define SQ_V_CMP_GT_I64 0x000000e4
19275	#define SQ_V_CMP_NE_I64 0x000000e5
19276	#define SQ_V_CMP_GE_I64 0x000000e6
19277	#define SQ_V_CMP_T_I64 0x000000e7
19278	#define SQ_V_CMP_F_U64 0x000000e8
19279	#define SQ_V_CMP_LT_U64 0x000000e9
19280	#define SQ_V_CMP_EQ_U64 0x000000ea
19281	#define SQ_V_CMP_LE_U64 0x000000eb
19282	#define SQ_V_CMP_GT_U64 0x000000ec
19283	#define SQ_V_CMP_NE_U64 0x000000ed
19284	#define SQ_V_CMP_GE_U64 0x000000ee
19285	#define SQ_V_CMP_T_U64 0x000000ef
19286	#define SQ_V_CMPX_F_I64 0x000000f0
19287	#define SQ_V_CMPX_LT_I64 0x000000f1
19288	#define SQ_V_CMPX_EQ_I64 0x000000f2
19289	#define SQ_V_CMPX_LE_I64 0x000000f3
19290	#define SQ_V_CMPX_GT_I64 0x000000f4
19291	#define SQ_V_CMPX_NE_I64 0x000000f5
19292	#define SQ_V_CMPX_GE_I64 0x000000f6
19293	#define SQ_V_CMPX_T_I64 0x000000f7
19294	#define SQ_V_CMPX_F_U64 0x000000f8
19295	#define SQ_V_CMPX_LT_U64 0x000000f9
19296	#define SQ_V_CMPX_EQ_U64 0x000000fa
19297	#define SQ_V_CMPX_LE_U64 0x000000fb
19298	#define SQ_V_CMPX_GT_U64 0x000000fc
19299	#define SQ_V_CMPX_NE_U64 0x000000fd
19300	#define SQ_V_CMPX_GE_U64 0x000000fe
19301	#define SQ_V_CMPX_T_U64 0x000000ff
19302
19303	/*
19304	* VALUE_SQ_GS_OP value
19305	*/
19306
19307	#define SQ_GS_OP_NOP 0x00000000
19308	#define SQ_GS_OP_CUT 0x00000001
19309	#define SQ_GS_OP_EMIT 0x00000002
19310	#define SQ_GS_OP_EMIT_CUT 0x00000003
19311
19312	/*
19313	* VALUE_SQ_SSRC_SPECIAL_LDS value
19314	*/
19315
19316	#define SQ_SRC_LDS_DIRECT 0x000000fe
19317
19318	/*
19319	* VALUE_SQ_ATTR value
19320	*/
19321
19322	#define SQ_ATTR0 0x00000000
19323
19324	/*
19325	* VALUE_SQ_TGT_INTERNAL value
19326	*/
19327
19328	#define SQ_EXP_GDS0 0x00000018
19329
19330	/*
19331	* VALUE_SQ_OP_SOPC value
19332	*/
19333
19334	#define SQ_S_CMP_EQ_I32 0x00000000
19335	#define SQ_S_CMP_LG_I32 0x00000001
19336	#define SQ_S_CMP_GT_I32 0x00000002
19337	#define SQ_S_CMP_GE_I32 0x00000003
19338	#define SQ_S_CMP_LT_I32 0x00000004
19339	#define SQ_S_CMP_LE_I32 0x00000005
19340	#define SQ_S_CMP_EQ_U32 0x00000006
19341	#define SQ_S_CMP_LG_U32 0x00000007
19342	#define SQ_S_CMP_GT_U32 0x00000008
19343	#define SQ_S_CMP_GE_U32 0x00000009
19344	#define SQ_S_CMP_LT_U32 0x0000000a
19345	#define SQ_S_CMP_LE_U32 0x0000000b
19346	#define SQ_S_BITCMP0_B32 0x0000000c
19347	#define SQ_S_BITCMP1_B32 0x0000000d
19348	#define SQ_S_BITCMP0_B64 0x0000000e
19349	#define SQ_S_BITCMP1_B64 0x0000000f
19350	#define SQ_S_SETVSKIP 0x00000010
19351	#define SQ_S_SET_GPR_IDX_ON 0x00000011
19352	#define SQ_S_CMP_EQ_U64 0x00000012
19353	#define SQ_S_CMP_LG_U64 0x00000013
19354
19355	/*
19356	* VALUE_SQ_TRAP value
19357	*/
19358
19359	#define SQ_TTMP0 0x0000006c
19360	#define SQ_TTMP1 0x0000006d
19361	#define SQ_TTMP2 0x0000006e
19362	#define SQ_TTMP3 0x0000006f
19363	#define SQ_TTMP4 0x00000070
19364	#define SQ_TTMP5 0x00000071
19365	#define SQ_TTMP6 0x00000072
19366	#define SQ_TTMP7 0x00000073
19367	#define SQ_TTMP8 0x00000074
19368	#define SQ_TTMP9 0x00000075
19369	#define SQ_TTMP10 0x00000076
19370	#define SQ_TTMP11 0x00000077
19371	#define SQ_TTMP12 0x00000078
19372	#define SQ_TTMP13 0x00000079
19373	#define SQ_TTMP14 0x0000007a
19374	#define SQ_TTMP15 0x0000007b
19375
19376	/*
19377	* VALUE_SQ_SRC_VGPR value
19378	*/
19379
19380	#define SQ_SRC_VGPR0 0x00000100
19381
19382	/*
19383	* VALUE_SQ_OP_MUBUF value
19384	*/
19385
19386	#define SQ_BUFFER_LOAD_FORMAT_X 0x00000000
19387	#define SQ_BUFFER_LOAD_FORMAT_XY 0x00000001
19388	#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x00000002
19389	#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x00000003
19390	#define SQ_BUFFER_STORE_FORMAT_X 0x00000004
19391	#define SQ_BUFFER_STORE_FORMAT_XY 0x00000005
19392	#define SQ_BUFFER_STORE_FORMAT_XYZ 0x00000006
19393	#define SQ_BUFFER_STORE_FORMAT_XYZW 0x00000007
19394	#define SQ_BUFFER_LOAD_FORMAT_D16_X 0x00000008
19395	#define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x00000009
19396	#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a
19397	#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
19398	#define SQ_BUFFER_STORE_FORMAT_D16_X 0x0000000c
19399	#define SQ_BUFFER_STORE_FORMAT_D16_XY 0x0000000d
19400	#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
19401	#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
19402	#define SQ_BUFFER_LOAD_UBYTE 0x00000010
19403	#define SQ_BUFFER_LOAD_SBYTE 0x00000011
19404	#define SQ_BUFFER_LOAD_USHORT 0x00000012
19405	#define SQ_BUFFER_LOAD_SSHORT 0x00000013
19406	#define SQ_BUFFER_LOAD_DWORD 0x00000014
19407	#define SQ_BUFFER_LOAD_DWORDX2 0x00000015
19408	#define SQ_BUFFER_LOAD_DWORDX3 0x00000016
19409	#define SQ_BUFFER_LOAD_DWORDX4 0x00000017
19410	#define SQ_BUFFER_STORE_BYTE 0x00000018
19411	#define SQ_BUFFER_STORE_SHORT 0x0000001a
19412	#define SQ_BUFFER_STORE_DWORD 0x0000001c
19413	#define SQ_BUFFER_STORE_DWORDX2 0x0000001d
19414	#define SQ_BUFFER_STORE_DWORDX3 0x0000001e
19415	#define SQ_BUFFER_STORE_DWORDX4 0x0000001f
19416	#define SQ_BUFFER_STORE_LDS_DWORD 0x0000003d
19417	#define SQ_BUFFER_WBINVL1 0x0000003e
19418	#define SQ_BUFFER_WBINVL1_VOL 0x0000003f
19419	#define SQ_BUFFER_ATOMIC_SWAP 0x00000040
19420	#define SQ_BUFFER_ATOMIC_CMPSWAP 0x00000041
19421	#define SQ_BUFFER_ATOMIC_ADD 0x00000042
19422	#define SQ_BUFFER_ATOMIC_SUB 0x00000043
19423	#define SQ_BUFFER_ATOMIC_SMIN 0x00000044
19424	#define SQ_BUFFER_ATOMIC_UMIN 0x00000045
19425	#define SQ_BUFFER_ATOMIC_SMAX 0x00000046
19426	#define SQ_BUFFER_ATOMIC_UMAX 0x00000047
19427	#define SQ_BUFFER_ATOMIC_AND 0x00000048
19428	#define SQ_BUFFER_ATOMIC_OR 0x00000049
19429	#define SQ_BUFFER_ATOMIC_XOR 0x0000004a
19430	#define SQ_BUFFER_ATOMIC_INC 0x0000004b
19431	#define SQ_BUFFER_ATOMIC_DEC 0x0000004c
19432	#define SQ_BUFFER_ATOMIC_SWAP_X2 0x00000060
19433	#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061
19434	#define SQ_BUFFER_ATOMIC_ADD_X2 0x00000062
19435	#define SQ_BUFFER_ATOMIC_SUB_X2 0x00000063
19436	#define SQ_BUFFER_ATOMIC_SMIN_X2 0x00000064
19437	#define SQ_BUFFER_ATOMIC_UMIN_X2 0x00000065
19438	#define SQ_BUFFER_ATOMIC_SMAX_X2 0x00000066
19439	#define SQ_BUFFER_ATOMIC_UMAX_X2 0x00000067
19440	#define SQ_BUFFER_ATOMIC_AND_X2 0x00000068
19441	#define SQ_BUFFER_ATOMIC_OR_X2 0x00000069
19442	#define SQ_BUFFER_ATOMIC_XOR_X2 0x0000006a
19443	#define SQ_BUFFER_ATOMIC_INC_X2 0x0000006b
19444	#define SQ_BUFFER_ATOMIC_DEC_X2 0x0000006c
19445
19446	/*
19447	* VALUE_SQ_SDWA_SEL value
19448	*/
19449
19450	#define SQ_SDWA_BYTE_0 0x00000000
19451	#define SQ_SDWA_BYTE_1 0x00000001
19452	#define SQ_SDWA_BYTE_2 0x00000002
19453	#define SQ_SDWA_BYTE_3 0x00000003
19454	#define SQ_SDWA_WORD_0 0x00000004
19455	#define SQ_SDWA_WORD_1 0x00000005
19456	#define SQ_SDWA_DWORD 0x00000006
19457
19458	/*******************************************************
19459	* SX Enums
19460	*******************************************************/
19461
19462	/*
19463	* SX_BLEND_OPT enum
19464	*/
19465
19466	typedef enum SX_BLEND_OPT {
19467	BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000,
19468	BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001,
19469	BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002,
19470	BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003,
19471	BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004,
19472	BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005,
19473	BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006,
19474	BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007,
19475	} SX_BLEND_OPT;
19476
19477	/*
19478	* SX_OPT_COMB_FCN enum
19479	*/
19480
19481	typedef enum SX_OPT_COMB_FCN {
19482	OPT_COMB_NONE = 0x00000000,
19483	OPT_COMB_ADD = 0x00000001,
19484	OPT_COMB_SUBTRACT = 0x00000002,
19485	OPT_COMB_MIN = 0x00000003,
19486	OPT_COMB_MAX = 0x00000004,
19487	OPT_COMB_REVSUBTRACT = 0x00000005,
19488	OPT_COMB_BLEND_DISABLED = 0x00000006,
19489	OPT_COMB_SAFE_ADD = 0x00000007,
19490	} SX_OPT_COMB_FCN;
19491
19492	/*
19493	* SX_DOWNCONVERT_FORMAT enum
19494	*/
19495
19496	typedef enum SX_DOWNCONVERT_FORMAT {
19497	SX_RT_EXPORT_NO_CONVERSION = 0x00000000,
19498	SX_RT_EXPORT_32_R = 0x00000001,
19499	SX_RT_EXPORT_32_A = 0x00000002,
19500	SX_RT_EXPORT_10_11_11 = 0x00000003,
19501	SX_RT_EXPORT_2_10_10_10 = 0x00000004,
19502	SX_RT_EXPORT_8_8_8_8 = 0x00000005,
19503	SX_RT_EXPORT_5_6_5 = 0x00000006,
19504	SX_RT_EXPORT_1_5_5_5 = 0x00000007,
19505	SX_RT_EXPORT_4_4_4_4 = 0x00000008,
19506	SX_RT_EXPORT_16_16_GR = 0x00000009,
19507	SX_RT_EXPORT_16_16_AR = 0x0000000a,
19508	} SX_DOWNCONVERT_FORMAT;
19509
19510	/*
19511	* SX_PERFCOUNTER_VALS enum
19512	*/
19513
19514	typedef enum SX_PERFCOUNTER_VALS {
19515	SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000,
19516	SX_PERF_SEL_PA_REQ = 0x00000001,
19517	SX_PERF_SEL_PA_POS = 0x00000002,
19518	SX_PERF_SEL_CLOCK = 0x00000003,
19519	SX_PERF_SEL_GATE_EN1 = 0x00000004,
19520	SX_PERF_SEL_GATE_EN2 = 0x00000005,
19521	SX_PERF_SEL_GATE_EN3 = 0x00000006,
19522	SX_PERF_SEL_GATE_EN4 = 0x00000007,
19523	SX_PERF_SEL_SH_POS_STARVE = 0x00000008,
19524	SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009,
19525	SX_PERF_SEL_SH_POS_STALL = 0x0000000a,
19526	SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b,
19527	SX_PERF_SEL_DB0_PIXELS = 0x0000000c,
19528	SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d,
19529	SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e,
19530	SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f,
19531	SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010,
19532	SX_PERF_SEL_DB1_PIXELS = 0x00000011,
19533	SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012,
19534	SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013,
19535	SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014,
19536	SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015,
19537	SX_PERF_SEL_DB2_PIXELS = 0x00000016,
19538	SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017,
19539	SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018,
19540	SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019,
19541	SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a,
19542	SX_PERF_SEL_DB3_PIXELS = 0x0000001b,
19543	SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c,
19544	SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d,
19545	SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e,
19546	SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f,
19547	SX_PERF_SEL_COL_BUSY = 0x00000020,
19548	SX_PERF_SEL_POS_BUSY = 0x00000021,
19549	SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 0x00000022,
19550	SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 0x00000023,
19551	SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 0x00000024,
19552	SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 0x00000025,
19553	SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 0x00000026,
19554	SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 0x00000027,
19555	SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 0x00000028,
19556	SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 0x00000029,
19557	SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 0x0000002a,
19558	SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 0x0000002b,
19559	SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 0x0000002c,
19560	SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 0x0000002d,
19561	SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 0x0000002e,
19562	SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 0x0000002f,
19563	SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 0x00000030,
19564	SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 0x00000031,
19565	SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 0x00000032,
19566	SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 0x00000033,
19567	SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 0x00000034,
19568	SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 0x00000035,
19569	SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 0x00000036,
19570	SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 0x00000037,
19571	SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 0x00000038,
19572	SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 0x00000039,
19573	SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 0x0000003a,
19574	SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 0x0000003b,
19575	SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 0x0000003c,
19576	SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 0x0000003d,
19577	SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 0x0000003e,
19578	SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 0x0000003f,
19579	SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 0x00000040,
19580	SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 0x00000041,
19581	SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 0x00000042,
19582	SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 0x00000043,
19583	SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 0x00000044,
19584	SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 0x00000045,
19585	SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 0x00000046,
19586	SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 0x00000047,
19587	SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 0x00000048,
19588	SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 0x00000049,
19589	SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 0x0000004a,
19590	SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 0x0000004b,
19591	SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 0x0000004c,
19592	SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 0x0000004d,
19593	SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 0x0000004e,
19594	SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 0x0000004f,
19595	SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 0x00000050,
19596	SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 0x00000051,
19597	SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 0x00000052,
19598	SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 0x00000053,
19599	SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 0x00000054,
19600	SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 0x00000055,
19601	SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 0x00000056,
19602	SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 0x00000057,
19603	SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 0x00000058,
19604	SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 0x00000059,
19605	SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 0x0000005a,
19606	SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 0x0000005b,
19607	SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 0x0000005c,
19608	SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 0x0000005d,
19609	SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 0x0000005e,
19610	SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 0x0000005f,
19611	SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 0x00000060,
19612	SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 0x00000061,
19613	SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 0x00000062,
19614	SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 0x00000063,
19615	SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 0x00000064,
19616	SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 0x00000065,
19617	SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 0x00000066,
19618	SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 0x00000067,
19619	SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 0x00000068,
19620	SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 0x00000069,
19621	SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 0x0000006a,
19622	SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 0x0000006b,
19623	SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 0x0000006c,
19624	SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 0x0000006d,
19625	SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 0x0000006e,
19626	SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 0x0000006f,
19627	SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 0x00000070,
19628	SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 0x00000071,
19629	SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 0x00000072,
19630	SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 0x00000073,
19631	SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 0x00000074,
19632	SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 0x00000075,
19633	SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 0x00000076,
19634	SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 0x00000077,
19635	SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 0x00000078,
19636	SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 0x00000079,
19637	SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 0x0000007a,
19638	SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 0x0000007b,
19639	SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 0x0000007c,
19640	SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 0x0000007d,
19641	SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 0x0000007e,
19642	SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 0x0000007f,
19643	SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 0x00000080,
19644	SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 0x00000081,
19645	SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 0x00000082,
19646	SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 0x00000083,
19647	SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 0x00000084,
19648	SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 0x00000085,
19649	SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 0x00000086,
19650	SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 0x00000087,
19651	SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 0x00000088,
19652	SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 0x00000089,
19653	SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 0x0000008a,
19654	SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 0x0000008b,
19655	SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 0x0000008c,
19656	SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 0x0000008d,
19657	SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 0x0000008e,
19658	SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 0x0000008f,
19659	SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 0x00000090,
19660	SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 0x00000091,
19661	SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 0x00000092,
19662	SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 0x00000093,
19663	SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 0x00000094,
19664	SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 0x00000095,
19665	SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 0x00000096,
19666	SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 0x00000097,
19667	SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 0x00000098,
19668	SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 0x00000099,
19669	SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 0x0000009a,
19670	SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 0x0000009b,
19671	SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 0x0000009c,
19672	SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 0x0000009d,
19673	SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 0x0000009e,
19674	SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 0x0000009f,
19675	SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 0x000000a0,
19676	SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 0x000000a1,
19677	SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 0x000000a2,
19678	SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 0x000000a3,
19679	SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 0x000000a4,
19680	SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 0x000000a5,
19681	SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 0x000000a6,
19682	SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 0x000000a7,
19683	SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 0x000000a8,
19684	SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 0x000000a9,
19685	SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 0x000000aa,
19686	SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 0x000000ab,
19687	SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 0x000000ac,
19688	SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 0x000000ad,
19689	SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 0x000000ae,
19690	SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 0x000000af,
19691	SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 0x000000b0,
19692	SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 0x000000b1,
19693	SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 0x000000b2,
19694	SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 0x000000b3,
19695	SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 0x000000b4,
19696	SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 0x000000b5,
19697	SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 0x000000b6,
19698	SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 0x000000b7,
19699	SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 0x000000b8,
19700	SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 0x000000b9,
19701	SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 0x000000ba,
19702	SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 0x000000bb,
19703	SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 0x000000bc,
19704	SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 0x000000bd,
19705	SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 0x000000be,
19706	SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 0x000000bf,
19707	SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 0x000000c0,
19708	SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 0x000000c1,
19709	SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 0x000000c2,
19710	SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 0x000000c3,
19711	SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 0x000000c4,
19712	SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 0x000000c5,
19713	} SX_PERFCOUNTER_VALS;
19714
19715	/*******************************************************
19716	* DB Enums
19717	*******************************************************/
19718
19719	/*
19720	* ForceControl enum
19721	*/
19722
19723	typedef enum ForceControl {
19724	FORCE_OFF = 0x00000000,
19725	FORCE_ENABLE = 0x00000001,
19726	FORCE_DISABLE = 0x00000002,
19727	FORCE_RESERVED = 0x00000003,
19728	} ForceControl;
19729
19730	/*
19731	* ZSamplePosition enum
19732	*/
19733
19734	typedef enum ZSamplePosition {
19735	Z_SAMPLE_CENTER = 0x00000000,
19736	Z_SAMPLE_CENTROID = 0x00000001,
19737	} ZSamplePosition;
19738
19739	/*
19740	* ZOrder enum
19741	*/
19742
19743	typedef enum ZOrder {
19744	LATE_Z = 0x00000000,
19745	EARLY_Z_THEN_LATE_Z = 0x00000001,
19746	RE_Z = 0x00000002,
19747	EARLY_Z_THEN_RE_Z = 0x00000003,
19748	} ZOrder;
19749
19750	/*
19751	* ZpassControl enum
19752	*/
19753
19754	typedef enum ZpassControl {
19755	ZPASS_DISABLE = 0x00000000,
19756	ZPASS_SAMPLES = 0x00000001,
19757	ZPASS_PIXELS = 0x00000002,
19758	} ZpassControl;
19759
19760	/*
19761	* ZModeForce enum
19762	*/
19763
19764	typedef enum ZModeForce {
19765	NO_FORCE = 0x00000000,
19766	FORCE_EARLY_Z = 0x00000001,
19767	FORCE_LATE_Z = 0x00000002,
19768	FORCE_RE_Z = 0x00000003,
19769	} ZModeForce;
19770
19771	/*
19772	* ZLimitSumm enum
19773	*/
19774
19775	typedef enum ZLimitSumm {
19776	FORCE_SUMM_OFF = 0x00000000,
19777	FORCE_SUMM_MINZ = 0x00000001,
19778	FORCE_SUMM_MAXZ = 0x00000002,
19779	FORCE_SUMM_BOTH = 0x00000003,
19780	} ZLimitSumm;
19781
19782	/*
19783	* CompareFrag enum
19784	*/
19785
19786	typedef enum CompareFrag {
19787	FRAG_NEVER = 0x00000000,
19788	FRAG_LESS = 0x00000001,
19789	FRAG_EQUAL = 0x00000002,
19790	FRAG_LEQUAL = 0x00000003,
19791	FRAG_GREATER = 0x00000004,
19792	FRAG_NOTEQUAL = 0x00000005,
19793	FRAG_GEQUAL = 0x00000006,
19794	FRAG_ALWAYS = 0x00000007,
19795	} CompareFrag;
19796
19797	/*
19798	* StencilOp enum
19799	*/
19800
19801	typedef enum StencilOp {
19802	STENCIL_KEEP = 0x00000000,
19803	STENCIL_ZERO = 0x00000001,
19804	STENCIL_ONES = 0x00000002,
19805	STENCIL_REPLACE_TEST = 0x00000003,
19806	STENCIL_REPLACE_OP = 0x00000004,
19807	STENCIL_ADD_CLAMP = 0x00000005,
19808	STENCIL_SUB_CLAMP = 0x00000006,
19809	STENCIL_INVERT = 0x00000007,
19810	STENCIL_ADD_WRAP = 0x00000008,
19811	STENCIL_SUB_WRAP = 0x00000009,
19812	STENCIL_AND = 0x0000000a,
19813	STENCIL_OR = 0x0000000b,
19814	STENCIL_XOR = 0x0000000c,
19815	STENCIL_NAND = 0x0000000d,
19816	STENCIL_NOR = 0x0000000e,
19817	STENCIL_XNOR = 0x0000000f,
19818	} StencilOp;
19819
19820	/*
19821	* ConservativeZExport enum
19822	*/
19823
19824	typedef enum ConservativeZExport {
19825	EXPORT_ANY_Z = 0x00000000,
19826	EXPORT_LESS_THAN_Z = 0x00000001,
19827	EXPORT_GREATER_THAN_Z = 0x00000002,
19828	EXPORT_RESERVED = 0x00000003,
19829	} ConservativeZExport;
19830
19831	/*
19832	* DbPSLControl enum
19833	*/
19834
19835	typedef enum DbPSLControl {
19836	PSLC_AUTO = 0x00000000,
19837	PSLC_ON_HANG_ONLY = 0x00000001,
19838	PSLC_ASAP = 0x00000002,
19839	PSLC_COUNTDOWN = 0x00000003,
19840	} DbPSLControl;
19841
19842	/*
19843	* DbPRTFaultBehavior enum
19844	*/
19845
19846	typedef enum DbPRTFaultBehavior {
19847	FAULT_ZERO = 0x00000000,
19848	FAULT_ONE = 0x00000001,
19849	FAULT_FAIL = 0x00000002,
19850	FAULT_PASS = 0x00000003,
19851	} DbPRTFaultBehavior;
19852
19853	/*
19854	* PerfCounter_Vals enum
19855	*/
19856
19857	typedef enum PerfCounter_Vals {
19858	DB_PERF_SEL_SC_DB_tile_sends = 0x00000000,
19859	DB_PERF_SEL_SC_DB_tile_busy = 0x00000001,
19860	DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002,
19861	DB_PERF_SEL_SC_DB_tile_events = 0x00000003,
19862	DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004,
19863	DB_PERF_SEL_SC_DB_tile_covered = 0x00000005,
19864	DB_PERF_SEL_hiz_tc_read_starved = 0x00000006,
19865	DB_PERF_SEL_hiz_tc_write_stall = 0x00000007,
19866	DB_PERF_SEL_hiz_qtiles_culled = 0x00000008,
19867	DB_PERF_SEL_his_qtiles_culled = 0x00000009,
19868	DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a,
19869	DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b,
19870	DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c,
19871	DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d,
19872	DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e,
19873	DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f,
19874	DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010,
19875	DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011,
19876	DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012,
19877	DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013,
19878	DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014,
19879	DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015,
19880	DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016,
19881	DB_PERF_SEL_SC_DB_quad_sends = 0x00000017,
19882	DB_PERF_SEL_SC_DB_quad_busy = 0x00000018,
19883	DB_PERF_SEL_SC_DB_quad_squads = 0x00000019,
19884	DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a,
19885	DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b,
19886	DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c,
19887	DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d,
19888	DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e,
19889	DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f,
19890	DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020,
19891	DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021,
19892	DB_PERF_SEL_DB_CB_tile_sends = 0x00000022,
19893	DB_PERF_SEL_DB_CB_tile_busy = 0x00000023,
19894	DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024,
19895	DB_PERF_SEL_SX_DB_quad_sends = 0x00000025,
19896	DB_PERF_SEL_SX_DB_quad_busy = 0x00000026,
19897	DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027,
19898	DB_PERF_SEL_SX_DB_quad_quads = 0x00000028,
19899	DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029,
19900	DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a,
19901	DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b,
19902	DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c,
19903	DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d,
19904	DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e,
19905	DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f,
19906	DB_PERF_SEL_tile_rd_sends = 0x00000030,
19907	DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031,
19908	DB_PERF_SEL_quad_rd_sends = 0x00000032,
19909	DB_PERF_SEL_quad_rd_busy = 0x00000033,
19910	DB_PERF_SEL_quad_rd_mi_stall = 0x00000034,
19911	DB_PERF_SEL_quad_rd_rw_collision = 0x00000035,
19912	DB_PERF_SEL_quad_rd_tag_stall = 0x00000036,
19913	DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037,
19914	DB_PERF_SEL_quad_rd_panic = 0x00000038,
19915	DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039,
19916	DB_PERF_SEL_quad_rdret_sends = 0x0000003a,
19917	DB_PERF_SEL_quad_rdret_busy = 0x0000003b,
19918	DB_PERF_SEL_tile_wr_sends = 0x0000003c,
19919	DB_PERF_SEL_tile_wr_acks = 0x0000003d,
19920	DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e,
19921	DB_PERF_SEL_quad_wr_sends = 0x0000003f,
19922	DB_PERF_SEL_quad_wr_busy = 0x00000040,
19923	DB_PERF_SEL_quad_wr_mi_stall = 0x00000041,
19924	DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042,
19925	DB_PERF_SEL_quad_wr_acks = 0x00000043,
19926	DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044,
19927	DB_PERF_SEL_Tile_Cache_misses = 0x00000045,
19928	DB_PERF_SEL_Tile_Cache_hits = 0x00000046,
19929	DB_PERF_SEL_Tile_Cache_flushes = 0x00000047,
19930	DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048,
19931	DB_PERF_SEL_Tile_Cache_starves = 0x00000049,
19932	DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a,
19933	DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b,
19934	DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c,
19935	DB_PERF_SEL_tcp_preloader_reads = 0x0000004d,
19936	DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e,
19937	DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f,
19938	DB_PERF_SEL_tcp_preloader_flushes = 0x00000050,
19939	DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051,
19940	DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052,
19941	DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053,
19942	DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054,
19943	DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055,
19944	DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056,
19945	DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057,
19946	DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058,
19947	DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059,
19948	DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a,
19949	DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b,
19950	DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c,
19951	DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d,
19952	DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e,
19953	DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f,
19954	DB_PERF_SEL_Stencil_Cache_hits = 0x00000060,
19955	DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061,
19956	DB_PERF_SEL_Stencil_Cache_starves = 0x00000062,
19957	DB_PERF_SEL_Stencil_Cache_frees = 0x00000063,
19958	DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064,
19959	DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065,
19960	DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066,
19961	DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067,
19962	DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068,
19963	DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069,
19964	DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a,
19965	DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b,
19966	DB_PERF_SEL_Z_Cache_frees = 0x0000006c,
19967	DB_PERF_SEL_Plane_Cache_misses = 0x0000006d,
19968	DB_PERF_SEL_Plane_Cache_hits = 0x0000006e,
19969	DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f,
19970	DB_PERF_SEL_Plane_Cache_starves = 0x00000070,
19971	DB_PERF_SEL_Plane_Cache_frees = 0x00000071,
19972	DB_PERF_SEL_flush_expanded_stencil = 0x00000072,
19973	DB_PERF_SEL_flush_compressed_stencil = 0x00000073,
19974	DB_PERF_SEL_flush_single_stencil = 0x00000074,
19975	DB_PERF_SEL_planes_flushed = 0x00000075,
19976	DB_PERF_SEL_flush_1plane = 0x00000076,
19977	DB_PERF_SEL_flush_2plane = 0x00000077,
19978	DB_PERF_SEL_flush_3plane = 0x00000078,
19979	DB_PERF_SEL_flush_4plane = 0x00000079,
19980	DB_PERF_SEL_flush_5plane = 0x0000007a,
19981	DB_PERF_SEL_flush_6plane = 0x0000007b,
19982	DB_PERF_SEL_flush_7plane = 0x0000007c,
19983	DB_PERF_SEL_flush_8plane = 0x0000007d,
19984	DB_PERF_SEL_flush_9plane = 0x0000007e,
19985	DB_PERF_SEL_flush_10plane = 0x0000007f,
19986	DB_PERF_SEL_flush_11plane = 0x00000080,
19987	DB_PERF_SEL_flush_12plane = 0x00000081,
19988	DB_PERF_SEL_flush_13plane = 0x00000082,
19989	DB_PERF_SEL_flush_14plane = 0x00000083,
19990	DB_PERF_SEL_flush_15plane = 0x00000084,
19991	DB_PERF_SEL_flush_16plane = 0x00000085,
19992	DB_PERF_SEL_flush_expanded_z = 0x00000086,
19993	DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087,
19994	DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088,
19995	DB_PERF_SEL_dk_tile_sends = 0x00000089,
19996	DB_PERF_SEL_dk_tile_busy = 0x0000008a,
19997	DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b,
19998	DB_PERF_SEL_dk_tile_stalls = 0x0000008c,
19999	DB_PERF_SEL_dk_squad_sends = 0x0000008d,
20000	DB_PERF_SEL_dk_squad_busy = 0x0000008e,
20001	DB_PERF_SEL_dk_squad_stalls = 0x0000008f,
20002	DB_PERF_SEL_Op_Pipe_Busy = 0x00000090,
20003	DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091,
20004	DB_PERF_SEL_qc_busy = 0x00000092,
20005	DB_PERF_SEL_qc_xfc = 0x00000093,
20006	DB_PERF_SEL_qc_conflicts = 0x00000094,
20007	DB_PERF_SEL_qc_full_stall = 0x00000095,
20008	DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096,
20009	DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097,
20010	DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098,
20011	DB_PERF_SEL_tl_busy = 0x00000099,
20012	DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a,
20013	DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b,
20014	DB_PERF_SEL_tl_stencil_stall = 0x0000009c,
20015	DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d,
20016	DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e,
20017	DB_PERF_SEL_tl_events = 0x0000009f,
20018	DB_PERF_SEL_tl_summarize_squads = 0x000000a0,
20019	DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1,
20020	DB_PERF_SEL_tl_expand_squads = 0x000000a2,
20021	DB_PERF_SEL_tl_preZ_squads = 0x000000a3,
20022	DB_PERF_SEL_tl_postZ_squads = 0x000000a4,
20023	DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5,
20024	DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6,
20025	DB_PERF_SEL_tl_tile_ops = 0x000000a7,
20026	DB_PERF_SEL_tl_in_xfc = 0x000000a8,
20027	DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9,
20028	DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa,
20029	DB_PERF_SEL_tl_out_xfc = 0x000000ab,
20030	DB_PERF_SEL_tl_out_squads = 0x000000ac,
20031	DB_PERF_SEL_zf_plane_multicycle = 0x000000ad,
20032	DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae,
20033	DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af,
20034	DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0,
20035	DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1,
20036	DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2,
20037	DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3,
20038	DB_PERF_SEL_ts_tc_update_stall = 0x000000b4,
20039	DB_PERF_SEL_sc_kick_start = 0x000000b5,
20040	DB_PERF_SEL_sc_kick_end = 0x000000b6,
20041	DB_PERF_SEL_clock_reg_active = 0x000000b7,
20042	DB_PERF_SEL_clock_main_active = 0x000000b8,
20043	DB_PERF_SEL_clock_mem_export_active = 0x000000b9,
20044	DB_PERF_SEL_esr_ps_out_busy = 0x000000ba,
20045	DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb,
20046	DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc,
20047	DB_PERF_SEL_etr_out_send = 0x000000bd,
20048	DB_PERF_SEL_etr_out_busy = 0x000000be,
20049	DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf,
20050	DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0,
20051	DB_PERF_SEL_etr_out_esr_stall = 0x000000c1,
20052	DB_PERF_SEL_esr_ps_sqq_busy = 0x000000c2,
20053	DB_PERF_SEL_esr_ps_sqq_stall = 0x000000c3,
20054	DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4,
20055	DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5,
20056	DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6,
20057	DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7,
20058	DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8,
20059	DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9,
20060	DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca,
20061	DB_PERF_SEL_postzl_se_busy = 0x000000cb,
20062	DB_PERF_SEL_postzl_se_stall = 0x000000cc,
20063	DB_PERF_SEL_postzl_partial_launch = 0x000000cd,
20064	DB_PERF_SEL_postzl_full_launch = 0x000000ce,
20065	DB_PERF_SEL_postzl_partial_waiting = 0x000000cf,
20066	DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0,
20067	DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1,
20068	DB_PEFF_SEL_prezl_tile_mem_stall = 0x000000d2,
20069	DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3,
20070	DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4,
20071	DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5,
20072	DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6,
20073	DB_PERF_SEL_mi_rdreq_busy = 0x000000d7,
20074	DB_PERF_SEL_mi_rdreq_stall = 0x000000d8,
20075	DB_PERF_SEL_mi_wrreq_busy = 0x000000d9,
20076	DB_PERF_SEL_mi_wrreq_stall = 0x000000da,
20077	DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db,
20078	DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc,
20079	DB_PERF_SEL_prezl_src_in_sends = 0x000000dd,
20080	DB_PERF_SEL_prezl_src_in_stall = 0x000000de,
20081	DB_PERF_SEL_prezl_src_in_squads = 0x000000df,
20082	DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0,
20083	DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1,
20084	DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2,
20085	DB_PERF_SEL_prezl_src_out_stall = 0x000000e3,
20086	DB_PERF_SEL_postzl_src_in_sends = 0x000000e4,
20087	DB_PERF_SEL_postzl_src_in_stall = 0x000000e5,
20088	DB_PERF_SEL_postzl_src_in_squads = 0x000000e6,
20089	DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7,
20090	DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8,
20091	DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9,
20092	DB_PERF_SEL_postzl_src_out_stall = 0x000000ea,
20093	DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb,
20094	DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec,
20095	DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed,
20096	DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee,
20097	DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef,
20098	DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0,
20099	DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1,
20100	DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2,
20101	DB_PERF_SEL_depth_bounds_qtiles_culled = 0x000000f3,
20102	DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4,
20103	DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5,
20104	DB_PERF_SEL_flush_compressed = 0x000000f6,
20105	DB_PERF_SEL_flush_plane_le4 = 0x000000f7,
20106	DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8,
20107	DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9,
20108	DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa,
20109	DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb,
20110	DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc,
20111	DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd,
20112	DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe,
20113	DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff,
20114	DB_PERF_SEL_di_dt_stall = 0x00000100,
20115	DB_PERF_SEL_DB_SC_quad_double_quad = 0x00000101,
20116	DB_PERF_SEL_SX_DB_quad_export_quads = 0x00000102,
20117	DB_PERF_SEL_SX_DB_quad_double_format = 0x00000103,
20118	DB_PERF_SEL_SX_DB_quad_fast_format = 0x00000104,
20119	DB_PERF_SEL_SX_DB_quad_slow_format = 0x00000105,
20120	DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000106,
20121	DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000107,
20122	DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000108,
20123	DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000109,
20124	DB_PERF_SEL_CB_DB_rdreq_sends = 0x0000010a,
20125	DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010b,
20126	DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010c,
20127	DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010d,
20128	DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010e,
20129	DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010f,
20130	DB_PERF_SEL_DB_CB_wrret_ack = 0x00000110,
20131	DB_PERF_SEL_DB_CB_wrret_nack = 0x00000111,
20132	DB_PERF_SEL_DFSM_squads_in = 0x00000112,
20133	DB_PERF_SEL_DFSM_full_cleared_squads_out = 0x00000113,
20134	DB_PERF_SEL_DFSM_quads_in = 0x00000114,
20135	DB_PERF_SEL_DFSM_fully_cleared_quads_out = 0x00000115,
20136	DB_PERF_SEL_DFSM_lit_pixels_in = 0x00000116,
20137	DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 0x00000117,
20138	DB_PERF_SEL_DFSM_lit_samples_in = 0x00000118,
20139	DB_PERF_SEL_DFSM_lit_samples_out = 0x00000119,
20140	DB_PERF_SEL_DFSM_cycles_above_watermark = 0x0000011a,
20141	DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 0x0000011b,
20142	DB_PERF_SEL_DFSM_stalled_by_downstream = 0x0000011c,
20143	DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 0x0000011d,
20144	DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 0x0000011e,
20145	DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 0x0000011f,
20146	DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 0x00000120,
20147	} PerfCounter_Vals;
20148
20149	/*
20150	* RingCounterControl enum
20151	*/
20152
20153	typedef enum RingCounterControl {
20154	COUNTER_RING_SPLIT = 0x00000000,
20155	COUNTER_RING_0 = 0x00000001,
20156	COUNTER_RING_1 = 0x00000002,
20157	} RingCounterControl;
20158
20159	/*
20160	* DbMemArbWatermarks enum
20161	*/
20162
20163	typedef enum DbMemArbWatermarks {
20164	TRANSFERRED_64_BYTES = 0x00000000,
20165	TRANSFERRED_128_BYTES = 0x00000001,
20166	TRANSFERRED_256_BYTES = 0x00000002,
20167	TRANSFERRED_512_BYTES = 0x00000003,
20168	TRANSFERRED_1024_BYTES = 0x00000004,
20169	TRANSFERRED_2048_BYTES = 0x00000005,
20170	TRANSFERRED_4096_BYTES = 0x00000006,
20171	TRANSFERRED_8192_BYTES = 0x00000007,
20172	} DbMemArbWatermarks;
20173
20174	/*
20175	* DFSMFlushEvents enum
20176	*/
20177
20178	typedef enum DFSMFlushEvents {
20179	DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000,
20180	DB_FLUSH_AND_INV_DB_META = 0x00000001,
20181	DB_CACHE_FLUSH = 0x00000002,
20182	DB_CACHE_FLUSH_TS = 0x00000003,
20183	DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004,
20184	DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005,
20185	} DFSMFlushEvents;
20186
20187	/*
20188	* PixelPipeCounterId enum
20189	*/
20190
20191	typedef enum PixelPipeCounterId {
20192	PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000,
20193	PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001,
20194	PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002,
20195	PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003,
20196	PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004,
20197	PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005,
20198	PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006,
20199	PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007,
20200	} PixelPipeCounterId;
20201
20202	/*
20203	* PixelPipeStride enum
20204	*/
20205
20206	typedef enum PixelPipeStride {
20207	PIXEL_PIPE_STRIDE_32_BITS = 0x00000000,
20208	PIXEL_PIPE_STRIDE_64_BITS = 0x00000001,
20209	PIXEL_PIPE_STRIDE_128_BITS = 0x00000002,
20210	PIXEL_PIPE_STRIDE_256_BITS = 0x00000003,
20211	} PixelPipeStride;
20212
20213	/*******************************************************
20214	* TA Enums
20215	*******************************************************/
20216
20217	/*
20218	* TEX_BORDER_COLOR_TYPE enum
20219	*/
20220
20221	typedef enum TEX_BORDER_COLOR_TYPE {
20222	TEX_BorderColor_TransparentBlack = 0x00000000,
20223	TEX_BorderColor_OpaqueBlack = 0x00000001,
20224	TEX_BorderColor_OpaqueWhite = 0x00000002,
20225	TEX_BorderColor_Register = 0x00000003,
20226	} TEX_BORDER_COLOR_TYPE;
20227
20228	/*
20229	* TEX_CHROMA_KEY enum
20230	*/
20231
20232	typedef enum TEX_CHROMA_KEY {
20233	TEX_ChromaKey_Disabled = 0x00000000,
20234	TEX_ChromaKey_Kill = 0x00000001,
20235	TEX_ChromaKey_Blend = 0x00000002,
20236	TEX_ChromaKey_RESERVED_3 = 0x00000003,
20237	} TEX_CHROMA_KEY;
20238
20239	/*
20240	* TEX_CLAMP enum
20241	*/
20242
20243	typedef enum TEX_CLAMP {
20244	TEX_Clamp_Repeat = 0x00000000,
20245	TEX_Clamp_Mirror = 0x00000001,
20246	TEX_Clamp_ClampToLast = 0x00000002,
20247	TEX_Clamp_MirrorOnceToLast = 0x00000003,
20248	TEX_Clamp_ClampHalfToBorder = 0x00000004,
20249	TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005,
20250	TEX_Clamp_ClampToBorder = 0x00000006,
20251	TEX_Clamp_MirrorOnceToBorder = 0x00000007,
20252	} TEX_CLAMP;
20253
20254	/*
20255	* TEX_COORD_TYPE enum
20256	*/
20257
20258	typedef enum TEX_COORD_TYPE {
20259	TEX_CoordType_Unnormalized = 0x00000000,
20260	TEX_CoordType_Normalized = 0x00000001,
20261	} TEX_COORD_TYPE;
20262
20263	/*
20264	* TEX_DEPTH_COMPARE_FUNCTION enum
20265	*/
20266
20267	typedef enum TEX_DEPTH_COMPARE_FUNCTION {
20268	TEX_DepthCompareFunction_Never = 0x00000000,
20269	TEX_DepthCompareFunction_Less = 0x00000001,
20270	TEX_DepthCompareFunction_Equal = 0x00000002,
20271	TEX_DepthCompareFunction_LessEqual = 0x00000003,
20272	TEX_DepthCompareFunction_Greater = 0x00000004,
20273	TEX_DepthCompareFunction_NotEqual = 0x00000005,
20274	TEX_DepthCompareFunction_GreaterEqual = 0x00000006,
20275	TEX_DepthCompareFunction_Always = 0x00000007,
20276	} TEX_DEPTH_COMPARE_FUNCTION;
20277
20278	/*
20279	* TEX_DIM enum
20280	*/
20281
20282	typedef enum TEX_DIM {
20283	TEX_Dim_1D = 0x00000000,
20284	TEX_Dim_2D = 0x00000001,
20285	TEX_Dim_3D = 0x00000002,
20286	TEX_Dim_CubeMap = 0x00000003,
20287	TEX_Dim_1DArray = 0x00000004,
20288	TEX_Dim_2DArray = 0x00000005,
20289	TEX_Dim_2D_MSAA = 0x00000006,
20290	TEX_Dim_2DArray_MSAA = 0x00000007,
20291	} TEX_DIM;
20292
20293	/*
20294	* TEX_FORMAT_COMP enum
20295	*/
20296
20297	typedef enum TEX_FORMAT_COMP {
20298	TEX_FormatComp_Unsigned = 0x00000000,
20299	TEX_FormatComp_Signed = 0x00000001,
20300	TEX_FormatComp_UnsignedBiased = 0x00000002,
20301	TEX_FormatComp_RESERVED_3 = 0x00000003,
20302	} TEX_FORMAT_COMP;
20303
20304	/*
20305	* TEX_MAX_ANISO_RATIO enum
20306	*/
20307
20308	typedef enum TEX_MAX_ANISO_RATIO {
20309	TEX_MaxAnisoRatio_1to1 = 0x00000000,
20310	TEX_MaxAnisoRatio_2to1 = 0x00000001,
20311	TEX_MaxAnisoRatio_4to1 = 0x00000002,
20312	TEX_MaxAnisoRatio_8to1 = 0x00000003,
20313	TEX_MaxAnisoRatio_16to1 = 0x00000004,
20314	TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005,
20315	TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006,
20316	TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007,
20317	} TEX_MAX_ANISO_RATIO;
20318
20319	/*
20320	* TEX_MIP_FILTER enum
20321	*/
20322
20323	typedef enum TEX_MIP_FILTER {
20324	TEX_MipFilter_None = 0x00000000,
20325	TEX_MipFilter_Point = 0x00000001,
20326	TEX_MipFilter_Linear = 0x00000002,
20327	TEX_MipFilter_Point_Aniso_Adj = 0x00000003,
20328	} TEX_MIP_FILTER;
20329
20330	/*
20331	* TEX_REQUEST_SIZE enum
20332	*/
20333
20334	typedef enum TEX_REQUEST_SIZE {
20335	TEX_RequestSize_32B = 0x00000000,
20336	TEX_RequestSize_64B = 0x00000001,
20337	TEX_RequestSize_128B = 0x00000002,
20338	TEX_RequestSize_2X64B = 0x00000003,
20339	} TEX_REQUEST_SIZE;
20340
20341	/*
20342	* TEX_SAMPLER_TYPE enum
20343	*/
20344
20345	typedef enum TEX_SAMPLER_TYPE {
20346	TEX_SamplerType_Invalid = 0x00000000,
20347	TEX_SamplerType_Valid = 0x00000001,
20348	} TEX_SAMPLER_TYPE;
20349
20350	/*
20351	* TEX_XY_FILTER enum
20352	*/
20353
20354	typedef enum TEX_XY_FILTER {
20355	TEX_XYFilter_Point = 0x00000000,
20356	TEX_XYFilter_Linear = 0x00000001,
20357	TEX_XYFilter_AnisoPoint = 0x00000002,
20358	TEX_XYFilter_AnisoLinear = 0x00000003,
20359	} TEX_XY_FILTER;
20360
20361	/*
20362	* TEX_Z_FILTER enum
20363	*/
20364
20365	typedef enum TEX_Z_FILTER {
20366	TEX_ZFilter_None = 0x00000000,
20367	TEX_ZFilter_Point = 0x00000001,
20368	TEX_ZFilter_Linear = 0x00000002,
20369	TEX_ZFilter_RESERVED_3 = 0x00000003,
20370	} TEX_Z_FILTER;
20371
20372	/*
20373	* VTX_CLAMP enum
20374	*/
20375
20376	typedef enum VTX_CLAMP {
20377	VTX_Clamp_ClampToZero = 0x00000000,
20378	VTX_Clamp_ClampToNAN = 0x00000001,
20379	} VTX_CLAMP;
20380
20381	/*
20382	* VTX_FETCH_TYPE enum
20383	*/
20384
20385	typedef enum VTX_FETCH_TYPE {
20386	VTX_FetchType_VertexData = 0x00000000,
20387	VTX_FetchType_InstanceData = 0x00000001,
20388	VTX_FetchType_NoIndexOffset = 0x00000002,
20389	VTX_FetchType_RESERVED_3 = 0x00000003,
20390	} VTX_FETCH_TYPE;
20391
20392	/*
20393	* VTX_FORMAT_COMP_ALL enum
20394	*/
20395
20396	typedef enum VTX_FORMAT_COMP_ALL {
20397	VTX_FormatCompAll_Unsigned = 0x00000000,
20398	VTX_FormatCompAll_Signed = 0x00000001,
20399	} VTX_FORMAT_COMP_ALL;
20400
20401	/*
20402	* VTX_MEM_REQUEST_SIZE enum
20403	*/
20404
20405	typedef enum VTX_MEM_REQUEST_SIZE {
20406	VTX_MemRequestSize_32B = 0x00000000,
20407	VTX_MemRequestSize_64B = 0x00000001,
20408	} VTX_MEM_REQUEST_SIZE;
20409
20410	/*
20411	* TVX_DATA_FORMAT enum
20412	*/
20413
20414	typedef enum TVX_DATA_FORMAT {
20415	TVX_FMT_INVALID = 0x00000000,
20416	TVX_FMT_8 = 0x00000001,
20417	TVX_FMT_4_4 = 0x00000002,
20418	TVX_FMT_3_3_2 = 0x00000003,
20419	TVX_FMT_RESERVED_4 = 0x00000004,
20420	TVX_FMT_16 = 0x00000005,
20421	TVX_FMT_16_FLOAT = 0x00000006,
20422	TVX_FMT_8_8 = 0x00000007,
20423	TVX_FMT_5_6_5 = 0x00000008,
20424	TVX_FMT_6_5_5 = 0x00000009,
20425	TVX_FMT_1_5_5_5 = 0x0000000a,
20426	TVX_FMT_4_4_4_4 = 0x0000000b,
20427	TVX_FMT_5_5_5_1 = 0x0000000c,
20428	TVX_FMT_32 = 0x0000000d,
20429	TVX_FMT_32_FLOAT = 0x0000000e,
20430	TVX_FMT_16_16 = 0x0000000f,
20431	TVX_FMT_16_16_FLOAT = 0x00000010,
20432	TVX_FMT_8_24 = 0x00000011,
20433	TVX_FMT_8_24_FLOAT = 0x00000012,
20434	TVX_FMT_24_8 = 0x00000013,
20435	TVX_FMT_24_8_FLOAT = 0x00000014,
20436	TVX_FMT_10_11_11 = 0x00000015,
20437	TVX_FMT_10_11_11_FLOAT = 0x00000016,
20438	TVX_FMT_11_11_10 = 0x00000017,
20439	TVX_FMT_11_11_10_FLOAT = 0x00000018,
20440	TVX_FMT_2_10_10_10 = 0x00000019,
20441	TVX_FMT_8_8_8_8 = 0x0000001a,
20442	TVX_FMT_10_10_10_2 = 0x0000001b,
20443	TVX_FMT_X24_8_32_FLOAT = 0x0000001c,
20444	TVX_FMT_32_32 = 0x0000001d,
20445	TVX_FMT_32_32_FLOAT = 0x0000001e,
20446	TVX_FMT_16_16_16_16 = 0x0000001f,
20447	TVX_FMT_16_16_16_16_FLOAT = 0x00000020,
20448	TVX_FMT_RESERVED_33 = 0x00000021,
20449	TVX_FMT_32_32_32_32 = 0x00000022,
20450	TVX_FMT_32_32_32_32_FLOAT = 0x00000023,
20451	TVX_FMT_RESERVED_36 = 0x00000024,
20452	TVX_FMT_1 = 0x00000025,
20453	TVX_FMT_1_REVERSED = 0x00000026,
20454	TVX_FMT_GB_GR = 0x00000027,
20455	TVX_FMT_BG_RG = 0x00000028,
20456	TVX_FMT_32_AS_8 = 0x00000029,
20457	TVX_FMT_32_AS_8_8 = 0x0000002a,
20458	TVX_FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
20459	TVX_FMT_8_8_8 = 0x0000002c,
20460	TVX_FMT_16_16_16 = 0x0000002d,
20461	TVX_FMT_16_16_16_FLOAT = 0x0000002e,
20462	TVX_FMT_32_32_32 = 0x0000002f,
20463	TVX_FMT_32_32_32_FLOAT = 0x00000030,
20464	TVX_FMT_BC1 = 0x00000031,
20465	TVX_FMT_BC2 = 0x00000032,
20466	TVX_FMT_BC3 = 0x00000033,
20467	TVX_FMT_BC4 = 0x00000034,
20468	TVX_FMT_BC5 = 0x00000035,
20469	TVX_FMT_APC0 = 0x00000036,
20470	TVX_FMT_APC1 = 0x00000037,
20471	TVX_FMT_APC2 = 0x00000038,
20472	TVX_FMT_APC3 = 0x00000039,
20473	TVX_FMT_APC4 = 0x0000003a,
20474	TVX_FMT_APC5 = 0x0000003b,
20475	TVX_FMT_APC6 = 0x0000003c,
20476	TVX_FMT_APC7 = 0x0000003d,
20477	TVX_FMT_CTX1 = 0x0000003e,
20478	TVX_FMT_RESERVED_63 = 0x0000003f,
20479	} TVX_DATA_FORMAT;
20480
20481	/*
20482	* TVX_DST_SEL enum
20483	*/
20484
20485	typedef enum TVX_DST_SEL {
20486	TVX_DstSel_X = 0x00000000,
20487	TVX_DstSel_Y = 0x00000001,
20488	TVX_DstSel_Z = 0x00000002,
20489	TVX_DstSel_W = 0x00000003,
20490	TVX_DstSel_0f = 0x00000004,
20491	TVX_DstSel_1f = 0x00000005,
20492	TVX_DstSel_RESERVED_6 = 0x00000006,
20493	TVX_DstSel_Mask = 0x00000007,
20494	} TVX_DST_SEL;
20495
20496	/*
20497	* TVX_ENDIAN_SWAP enum
20498	*/
20499
20500	typedef enum TVX_ENDIAN_SWAP {
20501	TVX_EndianSwap_None = 0x00000000,
20502	TVX_EndianSwap_8in16 = 0x00000001,
20503	TVX_EndianSwap_8in32 = 0x00000002,
20504	TVX_EndianSwap_8in64 = 0x00000003,
20505	} TVX_ENDIAN_SWAP;
20506
20507	/*
20508	* TVX_INST enum
20509	*/
20510
20511	typedef enum TVX_INST {
20512	TVX_Inst_NormalVertexFetch = 0x00000000,
20513	TVX_Inst_SemanticVertexFetch = 0x00000001,
20514	TVX_Inst_RESERVED_2 = 0x00000002,
20515	TVX_Inst_LD = 0x00000003,
20516	TVX_Inst_GetTextureResInfo = 0x00000004,
20517	TVX_Inst_GetNumberOfSamples = 0x00000005,
20518	TVX_Inst_GetLOD = 0x00000006,
20519	TVX_Inst_GetGradientsH = 0x00000007,
20520	TVX_Inst_GetGradientsV = 0x00000008,
20521	TVX_Inst_SetTextureOffsets = 0x00000009,
20522	TVX_Inst_KeepGradients = 0x0000000a,
20523	TVX_Inst_SetGradientsH = 0x0000000b,
20524	TVX_Inst_SetGradientsV = 0x0000000c,
20525	TVX_Inst_Pass = 0x0000000d,
20526	TVX_Inst_GetBufferResInfo = 0x0000000e,
20527	TVX_Inst_RESERVED_15 = 0x0000000f,
20528	TVX_Inst_Sample = 0x00000010,
20529	TVX_Inst_Sample_L = 0x00000011,
20530	TVX_Inst_Sample_LB = 0x00000012,
20531	TVX_Inst_Sample_LZ = 0x00000013,
20532	TVX_Inst_Sample_G = 0x00000014,
20533	TVX_Inst_Gather4 = 0x00000015,
20534	TVX_Inst_Sample_G_LB = 0x00000016,
20535	TVX_Inst_Gather4_O = 0x00000017,
20536	TVX_Inst_Sample_C = 0x00000018,
20537	TVX_Inst_Sample_C_L = 0x00000019,
20538	TVX_Inst_Sample_C_LB = 0x0000001a,
20539	TVX_Inst_Sample_C_LZ = 0x0000001b,
20540	TVX_Inst_Sample_C_G = 0x0000001c,
20541	TVX_Inst_Gather4_C = 0x0000001d,
20542	TVX_Inst_Sample_C_G_LB = 0x0000001e,
20543	TVX_Inst_Gather4_C_O = 0x0000001f,
20544	} TVX_INST;
20545
20546	/*
20547	* TVX_NUM_FORMAT_ALL enum
20548	*/
20549
20550	typedef enum TVX_NUM_FORMAT_ALL {
20551	TVX_NumFormatAll_Norm = 0x00000000,
20552	TVX_NumFormatAll_Int = 0x00000001,
20553	TVX_NumFormatAll_Scaled = 0x00000002,
20554	TVX_NumFormatAll_RESERVED_3 = 0x00000003,
20555	} TVX_NUM_FORMAT_ALL;
20556
20557	/*
20558	* TVX_SRC_SEL enum
20559	*/
20560
20561	typedef enum TVX_SRC_SEL {
20562	TVX_SrcSel_X = 0x00000000,
20563	TVX_SrcSel_Y = 0x00000001,
20564	TVX_SrcSel_Z = 0x00000002,
20565	TVX_SrcSel_W = 0x00000003,
20566	TVX_SrcSel_0f = 0x00000004,
20567	TVX_SrcSel_1f = 0x00000005,
20568	} TVX_SRC_SEL;
20569
20570	/*
20571	* TVX_SRF_MODE_ALL enum
20572	*/
20573
20574	typedef enum TVX_SRF_MODE_ALL {
20575	TVX_SRFModeAll_ZCMO = 0x00000000,
20576	TVX_SRFModeAll_NZ = 0x00000001,
20577	} TVX_SRF_MODE_ALL;
20578
20579	/*
20580	* TVX_TYPE enum
20581	*/
20582
20583	typedef enum TVX_TYPE {
20584	TVX_Type_InvalidTextureResource = 0x00000000,
20585	TVX_Type_InvalidVertexBuffer = 0x00000001,
20586	TVX_Type_ValidTextureResource = 0x00000002,
20587	TVX_Type_ValidVertexBuffer = 0x00000003,
20588	} TVX_TYPE;
20589
20590	/*******************************************************
20591	* PA Enums
20592	*******************************************************/
20593
20594	/*
20595	* SU_PERFCNT_SEL enum
20596	*/
20597
20598	typedef enum SU_PERFCNT_SEL {
20599	PERF_PAPC_PASX_REQ = 0x00000000,
20600	PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001,
20601	PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002,
20602	PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003,
20603	PERF_PAPC_PASX_FIRST_DEAD = 0x00000004,
20604	PERF_PAPC_PASX_SECOND_DEAD = 0x00000005,
20605	PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006,
20606	PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007,
20607	PERF_PAPC_PA_INPUT_PRIM = 0x00000008,
20608	PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009,
20609	PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a,
20610	PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b,
20611	PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c,
20612	PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d,
20613	PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e,
20614	PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f,
20615	PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010,
20616	PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011,
20617	PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012,
20618	PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013,
20619	PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014,
20620	PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015,
20621	PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016,
20622	PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017,
20623	PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018,
20624	PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019,
20625	PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a,
20626	PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b,
20627	PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c,
20628	PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d,
20629	PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e,
20630	PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f,
20631	PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020,
20632	PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021,
20633	PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022,
20634	PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023,
20635	PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024,
20636	PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025,
20637	PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026,
20638	PERF_PAPC_CLSM_NULL_PRIM = 0x00000027,
20639	PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028,
20640	PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029,
20641	PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a,
20642	PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b,
20643	PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c,
20644	PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d,
20645	PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e,
20646	PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f,
20647	PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030,
20648	PERF_PAPC_SU_INPUT_PRIM = 0x00000031,
20649	PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032,
20650	PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033,
20651	PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034,
20652	PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035,
20653	PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036,
20654	PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037,
20655	PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038,
20656	PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039,
20657	PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a,
20658	PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b,
20659	PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c,
20660	PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d,
20661	PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e,
20662	PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f,
20663	PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040,
20664	PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041,
20665	PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042,
20666	PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043,
20667	PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044,
20668	PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045,
20669	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046,
20670	PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047,
20671	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048,
20672	PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049,
20673	PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a,
20674	PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b,
20675	PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c,
20676	PERF_PAPC_PASX_REQ_IDLE = 0x0000004d,
20677	PERF_PAPC_PASX_REQ_BUSY = 0x0000004e,
20678	PERF_PAPC_PASX_REQ_STALLED = 0x0000004f,
20679	PERF_PAPC_PASX_REC_IDLE = 0x00000050,
20680	PERF_PAPC_PASX_REC_BUSY = 0x00000051,
20681	PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052,
20682	PERF_PAPC_PASX_REC_STALLED = 0x00000053,
20683	PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054,
20684	PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055,
20685	PERF_PAPC_CCGSM_IDLE = 0x00000056,
20686	PERF_PAPC_CCGSM_BUSY = 0x00000057,
20687	PERF_PAPC_CCGSM_STALLED = 0x00000058,
20688	PERF_PAPC_CLPRIM_IDLE = 0x00000059,
20689	PERF_PAPC_CLPRIM_BUSY = 0x0000005a,
20690	PERF_PAPC_CLPRIM_STALLED = 0x0000005b,
20691	PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c,
20692	PERF_PAPC_CLIPSM_IDLE = 0x0000005d,
20693	PERF_PAPC_CLIPSM_BUSY = 0x0000005e,
20694	PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f,
20695	PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060,
20696	PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061,
20697	PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062,
20698	PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063,
20699	PERF_PAPC_CLIPGA_IDLE = 0x00000064,
20700	PERF_PAPC_CLIPGA_BUSY = 0x00000065,
20701	PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066,
20702	PERF_PAPC_CLIPGA_STALLED = 0x00000067,
20703	PERF_PAPC_CLIP_IDLE = 0x00000068,
20704	PERF_PAPC_CLIP_BUSY = 0x00000069,
20705	PERF_PAPC_SU_IDLE = 0x0000006a,
20706	PERF_PAPC_SU_BUSY = 0x0000006b,
20707	PERF_PAPC_SU_STARVED_CLIP = 0x0000006c,
20708	PERF_PAPC_SU_STALLED_SC = 0x0000006d,
20709	PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e,
20710	PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f,
20711	PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070,
20712	PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071,
20713	PERF_PAPC_PASX_SE0_REQ = 0x00000072,
20714	PERF_PAPC_PASX_SE1_REQ = 0x00000073,
20715	PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074,
20716	PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075,
20717	PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076,
20718	PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077,
20719	PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078,
20720	PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079,
20721	PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a,
20722	PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b,
20723	PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c,
20724	PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d,
20725	PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e,
20726	PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f,
20727	PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080,
20728	PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081,
20729	PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082,
20730	PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083,
20731	PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084,
20732	PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085,
20733	PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086,
20734	PERF_PAPC_SU_CULLED_PRIM = 0x00000087,
20735	PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088,
20736	PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089,
20737	PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a,
20738	PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b,
20739	PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c,
20740	PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d,
20741	PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e,
20742	PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f,
20743	PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090,
20744	PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091,
20745	PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092,
20746	PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093,
20747	PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094,
20748	PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095,
20749	PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096,
20750	PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097,
20751	PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098,
20752	} SU_PERFCNT_SEL;
20753
20754	/*
20755	* SC_PERFCNT_SEL enum
20756	*/
20757
20758	typedef enum SC_PERFCNT_SEL {
20759	SC_SRPS_WINDOW_VALID = 0x00000000,
20760	SC_PSSW_WINDOW_VALID = 0x00000001,
20761	SC_TPQZ_WINDOW_VALID = 0x00000002,
20762	SC_QZQP_WINDOW_VALID = 0x00000003,
20763	SC_TRPK_WINDOW_VALID = 0x00000004,
20764	SC_SRPS_WINDOW_VALID_BUSY = 0x00000005,
20765	SC_PSSW_WINDOW_VALID_BUSY = 0x00000006,
20766	SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007,
20767	SC_QZQP_WINDOW_VALID_BUSY = 0x00000008,
20768	SC_TRPK_WINDOW_VALID_BUSY = 0x00000009,
20769	SC_STARVED_BY_PA = 0x0000000a,
20770	SC_STALLED_BY_PRIMFIFO = 0x0000000b,
20771	SC_STALLED_BY_DB_TILE = 0x0000000c,
20772	SC_STARVED_BY_DB_TILE = 0x0000000d,
20773	SC_STALLED_BY_TILEORDERFIFO = 0x0000000e,
20774	SC_STALLED_BY_TILEFIFO = 0x0000000f,
20775	SC_STALLED_BY_DB_QUAD = 0x00000010,
20776	SC_STARVED_BY_DB_QUAD = 0x00000011,
20777	SC_STALLED_BY_QUADFIFO = 0x00000012,
20778	SC_STALLED_BY_BCI = 0x00000013,
20779	SC_STALLED_BY_SPI = 0x00000014,
20780	SC_SCISSOR_DISCARD = 0x00000015,
20781	SC_BB_DISCARD = 0x00000016,
20782	SC_SUPERTILE_COUNT = 0x00000017,
20783	SC_SUPERTILE_PER_PRIM_H0 = 0x00000018,
20784	SC_SUPERTILE_PER_PRIM_H1 = 0x00000019,
20785	SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a,
20786	SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b,
20787	SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c,
20788	SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d,
20789	SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e,
20790	SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f,
20791	SC_SUPERTILE_PER_PRIM_H8 = 0x00000020,
20792	SC_SUPERTILE_PER_PRIM_H9 = 0x00000021,
20793	SC_SUPERTILE_PER_PRIM_H10 = 0x00000022,
20794	SC_SUPERTILE_PER_PRIM_H11 = 0x00000023,
20795	SC_SUPERTILE_PER_PRIM_H12 = 0x00000024,
20796	SC_SUPERTILE_PER_PRIM_H13 = 0x00000025,
20797	SC_SUPERTILE_PER_PRIM_H14 = 0x00000026,
20798	SC_SUPERTILE_PER_PRIM_H15 = 0x00000027,
20799	SC_SUPERTILE_PER_PRIM_H16 = 0x00000028,
20800	SC_TILE_PER_PRIM_H0 = 0x00000029,
20801	SC_TILE_PER_PRIM_H1 = 0x0000002a,
20802	SC_TILE_PER_PRIM_H2 = 0x0000002b,
20803	SC_TILE_PER_PRIM_H3 = 0x0000002c,
20804	SC_TILE_PER_PRIM_H4 = 0x0000002d,
20805	SC_TILE_PER_PRIM_H5 = 0x0000002e,
20806	SC_TILE_PER_PRIM_H6 = 0x0000002f,
20807	SC_TILE_PER_PRIM_H7 = 0x00000030,
20808	SC_TILE_PER_PRIM_H8 = 0x00000031,
20809	SC_TILE_PER_PRIM_H9 = 0x00000032,
20810	SC_TILE_PER_PRIM_H10 = 0x00000033,
20811	SC_TILE_PER_PRIM_H11 = 0x00000034,
20812	SC_TILE_PER_PRIM_H12 = 0x00000035,
20813	SC_TILE_PER_PRIM_H13 = 0x00000036,
20814	SC_TILE_PER_PRIM_H14 = 0x00000037,
20815	SC_TILE_PER_PRIM_H15 = 0x00000038,
20816	SC_TILE_PER_PRIM_H16 = 0x00000039,
20817	SC_TILE_PER_SUPERTILE_H0 = 0x0000003a,
20818	SC_TILE_PER_SUPERTILE_H1 = 0x0000003b,
20819	SC_TILE_PER_SUPERTILE_H2 = 0x0000003c,
20820	SC_TILE_PER_SUPERTILE_H3 = 0x0000003d,
20821	SC_TILE_PER_SUPERTILE_H4 = 0x0000003e,
20822	SC_TILE_PER_SUPERTILE_H5 = 0x0000003f,
20823	SC_TILE_PER_SUPERTILE_H6 = 0x00000040,
20824	SC_TILE_PER_SUPERTILE_H7 = 0x00000041,
20825	SC_TILE_PER_SUPERTILE_H8 = 0x00000042,
20826	SC_TILE_PER_SUPERTILE_H9 = 0x00000043,
20827	SC_TILE_PER_SUPERTILE_H10 = 0x00000044,
20828	SC_TILE_PER_SUPERTILE_H11 = 0x00000045,
20829	SC_TILE_PER_SUPERTILE_H12 = 0x00000046,
20830	SC_TILE_PER_SUPERTILE_H13 = 0x00000047,
20831	SC_TILE_PER_SUPERTILE_H14 = 0x00000048,
20832	SC_TILE_PER_SUPERTILE_H15 = 0x00000049,
20833	SC_TILE_PER_SUPERTILE_H16 = 0x0000004a,
20834	SC_TILE_PICKED_H1 = 0x0000004b,
20835	SC_TILE_PICKED_H2 = 0x0000004c,
20836	SC_TILE_PICKED_H3 = 0x0000004d,
20837	SC_TILE_PICKED_H4 = 0x0000004e,
20838	SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x0000004f,
20839	SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x00000050,
20840	SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x00000051,
20841	SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x00000052,
20842	SC_QZ0_TILE_COUNT = 0x00000053,
20843	SC_QZ1_TILE_COUNT = 0x00000054,
20844	SC_QZ2_TILE_COUNT = 0x00000055,
20845	SC_QZ3_TILE_COUNT = 0x00000056,
20846	SC_QZ0_TILE_COVERED_COUNT = 0x00000057,
20847	SC_QZ1_TILE_COVERED_COUNT = 0x00000058,
20848	SC_QZ2_TILE_COVERED_COUNT = 0x00000059,
20849	SC_QZ3_TILE_COVERED_COUNT = 0x0000005a,
20850	SC_QZ0_TILE_NOT_COVERED_COUNT = 0x0000005b,
20851	SC_QZ1_TILE_NOT_COVERED_COUNT = 0x0000005c,
20852	SC_QZ2_TILE_NOT_COVERED_COUNT = 0x0000005d,
20853	SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005e,
20854	SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005f,
20855	SC_QZ0_QUAD_PER_TILE_H1 = 0x00000060,
20856	SC_QZ0_QUAD_PER_TILE_H2 = 0x00000061,
20857	SC_QZ0_QUAD_PER_TILE_H3 = 0x00000062,
20858	SC_QZ0_QUAD_PER_TILE_H4 = 0x00000063,
20859	SC_QZ0_QUAD_PER_TILE_H5 = 0x00000064,
20860	SC_QZ0_QUAD_PER_TILE_H6 = 0x00000065,
20861	SC_QZ0_QUAD_PER_TILE_H7 = 0x00000066,
20862	SC_QZ0_QUAD_PER_TILE_H8 = 0x00000067,
20863	SC_QZ0_QUAD_PER_TILE_H9 = 0x00000068,
20864	SC_QZ0_QUAD_PER_TILE_H10 = 0x00000069,
20865	SC_QZ0_QUAD_PER_TILE_H11 = 0x0000006a,
20866	SC_QZ0_QUAD_PER_TILE_H12 = 0x0000006b,
20867	SC_QZ0_QUAD_PER_TILE_H13 = 0x0000006c,
20868	SC_QZ0_QUAD_PER_TILE_H14 = 0x0000006d,
20869	SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006e,
20870	SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006f,
20871	SC_QZ1_QUAD_PER_TILE_H0 = 0x00000070,
20872	SC_QZ1_QUAD_PER_TILE_H1 = 0x00000071,
20873	SC_QZ1_QUAD_PER_TILE_H2 = 0x00000072,
20874	SC_QZ1_QUAD_PER_TILE_H3 = 0x00000073,
20875	SC_QZ1_QUAD_PER_TILE_H4 = 0x00000074,
20876	SC_QZ1_QUAD_PER_TILE_H5 = 0x00000075,
20877	SC_QZ1_QUAD_PER_TILE_H6 = 0x00000076,
20878	SC_QZ1_QUAD_PER_TILE_H7 = 0x00000077,
20879	SC_QZ1_QUAD_PER_TILE_H8 = 0x00000078,
20880	SC_QZ1_QUAD_PER_TILE_H9 = 0x00000079,
20881	SC_QZ1_QUAD_PER_TILE_H10 = 0x0000007a,
20882	SC_QZ1_QUAD_PER_TILE_H11 = 0x0000007b,
20883	SC_QZ1_QUAD_PER_TILE_H12 = 0x0000007c,
20884	SC_QZ1_QUAD_PER_TILE_H13 = 0x0000007d,
20885	SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007e,
20886	SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007f,
20887	SC_QZ1_QUAD_PER_TILE_H16 = 0x00000080,
20888	SC_QZ2_QUAD_PER_TILE_H0 = 0x00000081,
20889	SC_QZ2_QUAD_PER_TILE_H1 = 0x00000082,
20890	SC_QZ2_QUAD_PER_TILE_H2 = 0x00000083,
20891	SC_QZ2_QUAD_PER_TILE_H3 = 0x00000084,
20892	SC_QZ2_QUAD_PER_TILE_H4 = 0x00000085,
20893	SC_QZ2_QUAD_PER_TILE_H5 = 0x00000086,
20894	SC_QZ2_QUAD_PER_TILE_H6 = 0x00000087,
20895	SC_QZ2_QUAD_PER_TILE_H7 = 0x00000088,
20896	SC_QZ2_QUAD_PER_TILE_H8 = 0x00000089,
20897	SC_QZ2_QUAD_PER_TILE_H9 = 0x0000008a,
20898	SC_QZ2_QUAD_PER_TILE_H10 = 0x0000008b,
20899	SC_QZ2_QUAD_PER_TILE_H11 = 0x0000008c,
20900	SC_QZ2_QUAD_PER_TILE_H12 = 0x0000008d,
20901	SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008e,
20902	SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008f,
20903	SC_QZ2_QUAD_PER_TILE_H15 = 0x00000090,
20904	SC_QZ2_QUAD_PER_TILE_H16 = 0x00000091,
20905	SC_QZ3_QUAD_PER_TILE_H0 = 0x00000092,
20906	SC_QZ3_QUAD_PER_TILE_H1 = 0x00000093,
20907	SC_QZ3_QUAD_PER_TILE_H2 = 0x00000094,
20908	SC_QZ3_QUAD_PER_TILE_H3 = 0x00000095,
20909	SC_QZ3_QUAD_PER_TILE_H4 = 0x00000096,
20910	SC_QZ3_QUAD_PER_TILE_H5 = 0x00000097,
20911	SC_QZ3_QUAD_PER_TILE_H6 = 0x00000098,
20912	SC_QZ3_QUAD_PER_TILE_H7 = 0x00000099,
20913	SC_QZ3_QUAD_PER_TILE_H8 = 0x0000009a,
20914	SC_QZ3_QUAD_PER_TILE_H9 = 0x0000009b,
20915	SC_QZ3_QUAD_PER_TILE_H10 = 0x0000009c,
20916	SC_QZ3_QUAD_PER_TILE_H11 = 0x0000009d,
20917	SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009e,
20918	SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009f,
20919	SC_QZ3_QUAD_PER_TILE_H14 = 0x000000a0,
20920	SC_QZ3_QUAD_PER_TILE_H15 = 0x000000a1,
20921	SC_QZ3_QUAD_PER_TILE_H16 = 0x000000a2,
20922	SC_QZ0_QUAD_COUNT = 0x000000a3,
20923	SC_QZ1_QUAD_COUNT = 0x000000a4,
20924	SC_QZ2_QUAD_COUNT = 0x000000a5,
20925	SC_QZ3_QUAD_COUNT = 0x000000a6,
20926	SC_P0_HIZ_TILE_COUNT = 0x000000a7,
20927	SC_P1_HIZ_TILE_COUNT = 0x000000a8,
20928	SC_P2_HIZ_TILE_COUNT = 0x000000a9,
20929	SC_P3_HIZ_TILE_COUNT = 0x000000aa,
20930	SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000ab,
20931	SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000ac,
20932	SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000ad,
20933	SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000ae,
20934	SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000af,
20935	SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000b0,
20936	SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000b1,
20937	SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000b2,
20938	SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000b3,
20939	SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b4,
20940	SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b5,
20941	SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b6,
20942	SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b7,
20943	SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b8,
20944	SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b9,
20945	SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000ba,
20946	SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000bb,
20947	SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000bc,
20948	SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000bd,
20949	SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000be,
20950	SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bf,
20951	SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000c0,
20952	SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000c1,
20953	SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000c2,
20954	SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000c3,
20955	SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c4,
20956	SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c5,
20957	SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c6,
20958	SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c7,
20959	SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c8,
20960	SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c9,
20961	SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000ca,
20962	SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000cb,
20963	SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000cc,
20964	SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000cd,
20965	SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ce,
20966	SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cf,
20967	SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000d0,
20968	SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000d1,
20969	SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000d2,
20970	SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000d3,
20971	SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d4,
20972	SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d5,
20973	SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d6,
20974	SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d7,
20975	SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d8,
20976	SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d9,
20977	SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000da,
20978	SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000db,
20979	SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000dc,
20980	SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000dd,
20981	SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000de,
20982	SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000df,
20983	SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000e0,
20984	SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000e1,
20985	SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000e2,
20986	SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000e3,
20987	SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e4,
20988	SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e5,
20989	SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e6,
20990	SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e7,
20991	SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e8,
20992	SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e9,
20993	SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000ea,
20994	SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000eb,
20995	SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000ec,
20996	SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000ed,
20997	SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ee,
20998	SC_P0_HIZ_QUAD_COUNT = 0x000000ef,
20999	SC_P1_HIZ_QUAD_COUNT = 0x000000f0,
21000	SC_P2_HIZ_QUAD_COUNT = 0x000000f1,
21001	SC_P3_HIZ_QUAD_COUNT = 0x000000f2,
21002	SC_P0_DETAIL_QUAD_COUNT = 0x000000f3,
21003	SC_P1_DETAIL_QUAD_COUNT = 0x000000f4,
21004	SC_P2_DETAIL_QUAD_COUNT = 0x000000f5,
21005	SC_P3_DETAIL_QUAD_COUNT = 0x000000f6,
21006	SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f7,
21007	SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f8,
21008	SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f9,
21009	SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000fa,
21010	SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000fb,
21011	SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000fc,
21012	SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000fd,
21013	SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fe,
21014	SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000ff,
21015	SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x00000100,
21016	SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x00000101,
21017	SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x00000102,
21018	SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x00000103,
21019	SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000104,
21020	SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000105,
21021	SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000106,
21022	SC_EARLYZ_QUAD_COUNT = 0x00000107,
21023	SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000108,
21024	SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000109,
21025	SC_EARLYZ_QUAD_WITH_3_PIX = 0x0000010a,
21026	SC_EARLYZ_QUAD_WITH_4_PIX = 0x0000010b,
21027	SC_PKR_QUAD_PER_ROW_H1 = 0x0000010c,
21028	SC_PKR_QUAD_PER_ROW_H2 = 0x0000010d,
21029	SC_PKR_4X2_QUAD_SPLIT = 0x0000010e,
21030	SC_PKR_4X2_FILL_QUAD = 0x0000010f,
21031	SC_PKR_END_OF_VECTOR = 0x00000110,
21032	SC_PKR_CONTROL_XFER = 0x00000111,
21033	SC_PKR_DBHANG_FORCE_EOV = 0x00000112,
21034	SC_REG_SCLK_BUSY = 0x00000113,
21035	SC_GRP0_DYN_SCLK_BUSY = 0x00000114,
21036	SC_GRP1_DYN_SCLK_BUSY = 0x00000115,
21037	SC_GRP2_DYN_SCLK_BUSY = 0x00000116,
21038	SC_GRP3_DYN_SCLK_BUSY = 0x00000117,
21039	SC_GRP4_DYN_SCLK_BUSY = 0x00000118,
21040	SC_PA0_SC_DATA_FIFO_RD = 0x00000119,
21041	SC_PA0_SC_DATA_FIFO_WE = 0x0000011a,
21042	SC_PA1_SC_DATA_FIFO_RD = 0x0000011b,
21043	SC_PA1_SC_DATA_FIFO_WE = 0x0000011c,
21044	SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x0000011d,
21045	SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011e,
21046	SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011f,
21047	SC_PS_ARB_STALLED_FROM_BELOW = 0x00000120,
21048	SC_PS_ARB_STARVED_FROM_ABOVE = 0x00000121,
21049	SC_PS_ARB_SC_BUSY = 0x00000122,
21050	SC_PS_ARB_PA_SC_BUSY = 0x00000123,
21051	SC_PA2_SC_DATA_FIFO_RD = 0x00000124,
21052	SC_PA2_SC_DATA_FIFO_WE = 0x00000125,
21053	SC_PA3_SC_DATA_FIFO_RD = 0x00000126,
21054	SC_PA3_SC_DATA_FIFO_WE = 0x00000127,
21055	SC_PA_SC_DEALLOC_0_0_WE = 0x00000128,
21056	SC_PA_SC_DEALLOC_0_1_WE = 0x00000129,
21057	SC_PA_SC_DEALLOC_1_0_WE = 0x0000012a,
21058	SC_PA_SC_DEALLOC_1_1_WE = 0x0000012b,
21059	SC_PA_SC_DEALLOC_2_0_WE = 0x0000012c,
21060	SC_PA_SC_DEALLOC_2_1_WE = 0x0000012d,
21061	SC_PA_SC_DEALLOC_3_0_WE = 0x0000012e,
21062	SC_PA_SC_DEALLOC_3_1_WE = 0x0000012f,
21063	SC_PA0_SC_EOP_WE = 0x00000130,
21064	SC_PA0_SC_EOPG_WE = 0x00000131,
21065	SC_PA0_SC_EVENT_WE = 0x00000132,
21066	SC_PA1_SC_EOP_WE = 0x00000133,
21067	SC_PA1_SC_EOPG_WE = 0x00000134,
21068	SC_PA1_SC_EVENT_WE = 0x00000135,
21069	SC_PA2_SC_EOP_WE = 0x00000136,
21070	SC_PA2_SC_EOPG_WE = 0x00000137,
21071	SC_PA2_SC_EVENT_WE = 0x00000138,
21072	SC_PA3_SC_EOP_WE = 0x00000139,
21073	SC_PA3_SC_EOPG_WE = 0x0000013a,
21074	SC_PA3_SC_EVENT_WE = 0x0000013b,
21075	SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x0000013c,
21076	SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x0000013d,
21077	SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013e,
21078	SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013f,
21079	SC_PS_ARB_EVENT_SYNC_POP = 0x00000140,
21080	SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x00000141,
21081	SC_PA0_SC_FPOV_WE = 0x00000142,
21082	SC_PA1_SC_FPOV_WE = 0x00000143,
21083	SC_PA2_SC_FPOV_WE = 0x00000144,
21084	SC_PA3_SC_FPOV_WE = 0x00000145,
21085	SC_PA0_SC_LPOV_WE = 0x00000146,
21086	SC_PA1_SC_LPOV_WE = 0x00000147,
21087	SC_PA2_SC_LPOV_WE = 0x00000148,
21088	SC_PA3_SC_LPOV_WE = 0x00000149,
21089	SC_SC_SPI_DEALLOC_0_0 = 0x0000014a,
21090	SC_SC_SPI_DEALLOC_0_1 = 0x0000014b,
21091	SC_SC_SPI_DEALLOC_0_2 = 0x0000014c,
21092	SC_SC_SPI_DEALLOC_1_0 = 0x0000014d,
21093	SC_SC_SPI_DEALLOC_1_1 = 0x0000014e,
21094	SC_SC_SPI_DEALLOC_1_2 = 0x0000014f,
21095	SC_SC_SPI_DEALLOC_2_0 = 0x00000150,
21096	SC_SC_SPI_DEALLOC_2_1 = 0x00000151,
21097	SC_SC_SPI_DEALLOC_2_2 = 0x00000152,
21098	SC_SC_SPI_DEALLOC_3_0 = 0x00000153,
21099	SC_SC_SPI_DEALLOC_3_1 = 0x00000154,
21100	SC_SC_SPI_DEALLOC_3_2 = 0x00000155,
21101	SC_SC_SPI_FPOV_0 = 0x00000156,
21102	SC_SC_SPI_FPOV_1 = 0x00000157,
21103	SC_SC_SPI_FPOV_2 = 0x00000158,
21104	SC_SC_SPI_FPOV_3 = 0x00000159,
21105	SC_SC_SPI_EVENT = 0x0000015a,
21106	SC_PS_TS_EVENT_FIFO_PUSH = 0x0000015b,
21107	SC_PS_TS_EVENT_FIFO_POP = 0x0000015c,
21108	SC_PS_CTX_DONE_FIFO_PUSH = 0x0000015d,
21109	SC_PS_CTX_DONE_FIFO_POP = 0x0000015e,
21110	SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015f,
21111	SC_EOP_SYNC_WINDOW = 0x00000160,
21112	SC_PA0_SC_NULL_WE = 0x00000161,
21113	SC_PA0_SC_NULL_DEALLOC_WE = 0x00000162,
21114	SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x00000163,
21115	SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000164,
21116	SC_PA0_SC_DEALLOC_0_RD = 0x00000165,
21117	SC_PA0_SC_DEALLOC_1_RD = 0x00000166,
21118	SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000167,
21119	SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000168,
21120	SC_PA1_SC_DEALLOC_0_RD = 0x00000169,
21121	SC_PA1_SC_DEALLOC_1_RD = 0x0000016a,
21122	SC_PA1_SC_NULL_WE = 0x0000016b,
21123	SC_PA1_SC_NULL_DEALLOC_WE = 0x0000016c,
21124	SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x0000016d,
21125	SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016e,
21126	SC_PA2_SC_DEALLOC_0_RD = 0x0000016f,
21127	SC_PA2_SC_DEALLOC_1_RD = 0x00000170,
21128	SC_PA2_SC_NULL_WE = 0x00000171,
21129	SC_PA2_SC_NULL_DEALLOC_WE = 0x00000172,
21130	SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x00000173,
21131	SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000174,
21132	SC_PA3_SC_DEALLOC_0_RD = 0x00000175,
21133	SC_PA3_SC_DEALLOC_1_RD = 0x00000176,
21134	SC_PA3_SC_NULL_WE = 0x00000177,
21135	SC_PA3_SC_NULL_DEALLOC_WE = 0x00000178,
21136	SC_PS_PA0_SC_FIFO_EMPTY = 0x00000179,
21137	SC_PS_PA0_SC_FIFO_FULL = 0x0000017a,
21138	SC_PA0_PS_DATA_SEND = 0x0000017b,
21139	SC_PS_PA1_SC_FIFO_EMPTY = 0x0000017c,
21140	SC_PS_PA1_SC_FIFO_FULL = 0x0000017d,
21141	SC_PA1_PS_DATA_SEND = 0x0000017e,
21142	SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017f,
21143	SC_PS_PA2_SC_FIFO_FULL = 0x00000180,
21144	SC_PA2_PS_DATA_SEND = 0x00000181,
21145	SC_PS_PA3_SC_FIFO_EMPTY = 0x00000182,
21146	SC_PS_PA3_SC_FIFO_FULL = 0x00000183,
21147	SC_PA3_PS_DATA_SEND = 0x00000184,
21148	SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000185,
21149	SC_BUSY_CNT_NOT_ZERO = 0x00000186,
21150	SC_BM_BUSY = 0x00000187,
21151	SC_BACKEND_BUSY = 0x00000188,
21152	SC_SCF_SCB_INTERFACE_BUSY = 0x00000189,
21153	SC_SCB_BUSY = 0x0000018a,
21154	SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x0000018b,
21155	SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x0000018c,
21156	SC_PBB_BIN_HIST_NUM_PRIMS = 0x0000018d,
21157	SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018e,
21158	SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018f,
21159	SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x00000190,
21160	SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x00000191,
21161	SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x00000192,
21162	SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x00000193,
21163	SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000194,
21164	SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000195,
21165	SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000196,
21166	SC_PBB_BUSY = 0x00000197,
21167	SC_PBB_BUSY_AND_RTR = 0x00000198,
21168	SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000199,
21169	SC_PBB_NUM_BINS = 0x0000019a,
21170	SC_PBB_END_OF_BIN = 0x0000019b,
21171	SC_PBB_END_OF_BATCH = 0x0000019c,
21172	SC_PBB_PRIMBIN_PROCESSED = 0x0000019d,
21173	SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019e,
21174	SC_PBB_NONBINNED_PRIM = 0x0000019f,
21175	SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x000001a0,
21176	SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x000001a1,
21177	SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x000001a2,
21178	SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x000001a3,
21179	SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a4,
21180	SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a5,
21181	SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a6,
21182	SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a7,
21183	SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a8,
21184	SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a9,
21185	SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001aa,
21186	SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001ab,
21187	SC_POPS_FORCE_EOV = 0x000001ac,
21188	SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE = 0x000001ad,
21189	SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE = 0x000001ae,
21190	} SC_PERFCNT_SEL;
21191
21192	/*
21193	* SePairXsel enum
21194	*/
21195
21196	typedef enum SePairXsel {
21197	RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000,
21198	RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001,
21199	RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002,
21200	RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003,
21201	RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE = 0x00000004,
21202	} SePairXsel;
21203
21204	/*
21205	* SePairYsel enum
21206	*/
21207
21208	typedef enum SePairYsel {
21209	RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000,
21210	RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001,
21211	RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002,
21212	RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003,
21213	RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE = 0x00000004,
21214	} SePairYsel;
21215
21216	/*
21217	* SePairMap enum
21218	*/
21219
21220	typedef enum SePairMap {
21221	RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000,
21222	RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001,
21223	RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002,
21224	RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003,
21225	} SePairMap;
21226
21227	/*
21228	* SeXsel enum
21229	*/
21230
21231	typedef enum SeXsel {
21232	RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000,
21233	RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001,
21234	RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002,
21235	RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003,
21236	RASTER_CONFIG_SE_XSEL_128_WIDE_TILE = 0x00000004,
21237	} SeXsel;
21238
21239	/*
21240	* SeYsel enum
21241	*/
21242
21243	typedef enum SeYsel {
21244	RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000,
21245	RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001,
21246	RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002,
21247	RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003,
21248	RASTER_CONFIG_SE_YSEL_128_WIDE_TILE = 0x00000004,
21249	} SeYsel;
21250
21251	/*
21252	* SeMap enum
21253	*/
21254
21255	typedef enum SeMap {
21256	RASTER_CONFIG_SE_MAP_0 = 0x00000000,
21257	RASTER_CONFIG_SE_MAP_1 = 0x00000001,
21258	RASTER_CONFIG_SE_MAP_2 = 0x00000002,
21259	RASTER_CONFIG_SE_MAP_3 = 0x00000003,
21260	} SeMap;
21261
21262	/*
21263	* ScXsel enum
21264	*/
21265
21266	typedef enum ScXsel {
21267	RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000,
21268	RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001,
21269	RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002,
21270	RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003,
21271	} ScXsel;
21272
21273	/*
21274	* ScYsel enum
21275	*/
21276
21277	typedef enum ScYsel {
21278	RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000,
21279	RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001,
21280	RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002,
21281	RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003,
21282	} ScYsel;
21283
21284	/*
21285	* ScMap enum
21286	*/
21287
21288	typedef enum ScMap {
21289	RASTER_CONFIG_SC_MAP_0 = 0x00000000,
21290	RASTER_CONFIG_SC_MAP_1 = 0x00000001,
21291	RASTER_CONFIG_SC_MAP_2 = 0x00000002,
21292	RASTER_CONFIG_SC_MAP_3 = 0x00000003,
21293	} ScMap;
21294
21295	/*
21296	* PkrXsel2 enum
21297	*/
21298
21299	typedef enum PkrXsel2 {
21300	RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000,
21301	RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001,
21302	RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002,
21303	RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003,
21304	} PkrXsel2;
21305
21306	/*
21307	* PkrXsel enum
21308	*/
21309
21310	typedef enum PkrXsel {
21311	RASTER_CONFIG_PKR_XSEL_0 = 0x00000000,
21312	RASTER_CONFIG_PKR_XSEL_1 = 0x00000001,
21313	RASTER_CONFIG_PKR_XSEL_2 = 0x00000002,
21314	RASTER_CONFIG_PKR_XSEL_3 = 0x00000003,
21315	} PkrXsel;
21316
21317	/*
21318	* PkrYsel enum
21319	*/
21320
21321	typedef enum PkrYsel {
21322	RASTER_CONFIG_PKR_YSEL_0 = 0x00000000,
21323	RASTER_CONFIG_PKR_YSEL_1 = 0x00000001,
21324	RASTER_CONFIG_PKR_YSEL_2 = 0x00000002,
21325	RASTER_CONFIG_PKR_YSEL_3 = 0x00000003,
21326	} PkrYsel;
21327
21328	/*
21329	* PkrMap enum
21330	*/
21331
21332	typedef enum PkrMap {
21333	RASTER_CONFIG_PKR_MAP_0 = 0x00000000,
21334	RASTER_CONFIG_PKR_MAP_1 = 0x00000001,
21335	RASTER_CONFIG_PKR_MAP_2 = 0x00000002,
21336	RASTER_CONFIG_PKR_MAP_3 = 0x00000003,
21337	} PkrMap;
21338
21339	/*
21340	* RbXsel enum
21341	*/
21342
21343	typedef enum RbXsel {
21344	RASTER_CONFIG_RB_XSEL_0 = 0x00000000,
21345	RASTER_CONFIG_RB_XSEL_1 = 0x00000001,
21346	} RbXsel;
21347
21348	/*
21349	* RbYsel enum
21350	*/
21351
21352	typedef enum RbYsel {
21353	RASTER_CONFIG_RB_YSEL_0 = 0x00000000,
21354	RASTER_CONFIG_RB_YSEL_1 = 0x00000001,
21355	} RbYsel;
21356
21357	/*
21358	* RbXsel2 enum
21359	*/
21360
21361	typedef enum RbXsel2 {
21362	RASTER_CONFIG_RB_XSEL2_0 = 0x00000000,
21363	RASTER_CONFIG_RB_XSEL2_1 = 0x00000001,
21364	RASTER_CONFIG_RB_XSEL2_2 = 0x00000002,
21365	RASTER_CONFIG_RB_XSEL2_3 = 0x00000003,
21366	} RbXsel2;
21367
21368	/*
21369	* RbMap enum
21370	*/
21371
21372	typedef enum RbMap {
21373	RASTER_CONFIG_RB_MAP_0 = 0x00000000,
21374	RASTER_CONFIG_RB_MAP_1 = 0x00000001,
21375	RASTER_CONFIG_RB_MAP_2 = 0x00000002,
21376	RASTER_CONFIG_RB_MAP_3 = 0x00000003,
21377	} RbMap;
21378
21379	/*
21380	* BinningMode enum
21381	*/
21382
21383	typedef enum BinningMode {
21384	BINNING_ALLOWED = 0x00000000,
21385	FORCE_BINNING_ON = 0x00000001,
21386	DISABLE_BINNING_USE_NEW_SC = 0x00000002,
21387	DISABLE_BINNING_USE_LEGACY_SC = 0x00000003,
21388	} BinningMode;
21389
21390	/*
21391	* BinEventCntl enum
21392	*/
21393
21394	typedef enum BinEventCntl {
21395	BINNER_BREAK_BATCH = 0x00000000,
21396	BINNER_PIPELINE = 0x00000001,
21397	BINNER_DROP_ASSERT = 0x00000002,
21398	} BinEventCntl;
21399
21400	/*
21401	* CovToShaderSel enum
21402	*/
21403
21404	typedef enum CovToShaderSel {
21405	INPUT_COVERAGE = 0x00000000,
21406	INPUT_INNER_COVERAGE = 0x00000001,
21407	INPUT_DEPTH_COVERAGE = 0x00000002,
21408	RAW = 0x00000003,
21409	} CovToShaderSel;
21410
21411	/*******************************************************
21412	* RMI Enums
21413	*******************************************************/
21414
21415	/*
21416	* RMIPerfSel enum
21417	*/
21418
21419	typedef enum RMIPerfSel {
21420	RMI_PERF_SEL_NONE = 0x00000000,
21421	RMI_PERF_SEL_BUSY = 0x00000001,
21422	RMI_PERF_SEL_REG_CLK_VLD = 0x00000002,
21423	RMI_PERF_SEL_DYN_CLK_CMN_VLD = 0x00000003,
21424	RMI_PERF_SEL_DYN_CLK_RB_VLD = 0x00000004,
21425	RMI_PERF_SEL_DYN_CLK_PERF_VLD = 0x00000005,
21426	RMI_PERF_SEL_PERF_WINDOW = 0x00000006,
21427	RMI_PERF_SEL_EVENT_SEND = 0x00000007,
21428	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008,
21429	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009,
21430	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a,
21431	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b,
21432	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c,
21433	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d,
21434	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e,
21435	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f,
21436	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010,
21437	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011,
21438	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012,
21439	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013,
21440	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014,
21441	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015,
21442	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016,
21443	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017,
21444	RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018,
21445	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019,
21446	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a,
21447	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b,
21448	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c,
21449	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d,
21450	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e,
21451	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f,
21452	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020,
21453	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021,
21454	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022,
21455	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023,
21456	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024,
21457	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025,
21458	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026,
21459	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027,
21460	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028,
21461	RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029,
21462	RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x0000002a,
21463	RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 0x0000002b,
21464	RMI_PERF_SEL_UTCL1_REQUEST = 0x0000002c,
21465	RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x0000002d,
21466	RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x0000002e,
21467	RMI_PERF_SEL_UTCL1_LFIFO_FULL = 0x0000002f,
21468	RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x00000030,
21469	RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000031,
21470	RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x00000032,
21471	RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 0x00000033,
21472	RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 0x00000034,
21473	RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000035,
21474	RMI_PERF_SEL_RB_RMI_WRREQ_BUSY = 0x00000036,
21475	RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 0x00000037,
21476	RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 0x00000038,
21477	RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 0x00000039,
21478	RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 0x0000003a,
21479	RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 0x0000003b,
21480	RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 0x0000003c,
21481	RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 0x0000003d,
21482	RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 0x0000003e,
21483	RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 0x0000003f,
21484	RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000040,
21485	RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000041,
21486	RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 0x00000042,
21487	RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 0x00000043,
21488	RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 0x00000044,
21489	RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 0x00000045,
21490	RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 0x00000046,
21491	RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 0x00000047,
21492	RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 0x00000048,
21493	RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 0x00000049,
21494	RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 0x0000004a,
21495	RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 0x0000004b,
21496	RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 0x0000004c,
21497	RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 0x0000004d,
21498	RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 0x0000004e,
21499	RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 0x0000004f,
21500	RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 0x00000050,
21501	RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000051,
21502	RMI_PERF_SEL_RB_RMI_RDREQ_BUSY = 0x00000052,
21503	RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 0x00000053,
21504	RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 0x00000054,
21505	RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 0x00000055,
21506	RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 0x00000056,
21507	RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 0x00000057,
21508	RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 0x00000058,
21509	RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 0x00000059,
21510	RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 0x0000005a,
21511	RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 0x0000005b,
21512	RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 0x0000005c,
21513	RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 0x0000005d,
21514	RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 0x0000005e,
21515	RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 0x0000005f,
21516	RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 0x00000060,
21517	RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 0x00000061,
21518	RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 0x00000062,
21519	RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000063,
21520	RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000064,
21521	RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000065,
21522	RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 0x00000066,
21523	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000067,
21524	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 0x00000068,
21525	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 0x00000069,
21526	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 0x0000006a,
21527	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 0x0000006b,
21528	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 0x0000006c,
21529	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 0x0000006d,
21530	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 0x0000006e,
21531	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 0x0000006f,
21532	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000070,
21533	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000071,
21534	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000072,
21535	RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000073,
21536	RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 0x00000074,
21537	RMI_PERF_SEL_RMI_TC_REQ_BUSY = 0x00000075,
21538	RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 0x00000076,
21539	RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 0x00000077,
21540	RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 0x00000078,
21541	RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 0x00000079,
21542	RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 0x0000007a,
21543	RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 0x0000007b,
21544	RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 0x0000007c,
21545	RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 0x0000007d,
21546	RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000007e,
21547	RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 0x0000007f,
21548	RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 0x00000080,
21549	RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 0x00000081,
21550	RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 0x00000082,
21551	RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 0x00000083,
21552	RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 0x00000084,
21553	RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 0x00000085,
21554	RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 0x00000086,
21555	RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 0x00000087,
21556	RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 0x00000088,
21557	RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x00000089,
21558	RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 0x0000008a,
21559	RMI_PERF_SEL_UTCL1_BUSY = 0x0000008b,
21560	RMI_PERF_SEL_RMI_UTC_REQ = 0x0000008c,
21561	RMI_PERF_SEL_RMI_UTC_BUSY = 0x0000008d,
21562	RMI_PERF_SEL_UTCL1_UTCL2_REQ = 0x0000008e,
21563	RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 0x0000008f,
21564	RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 0x00000090,
21565	RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 0x00000091,
21566	RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x00000092,
21567	RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 0x00000093,
21568	RMI_PERF_SEL_LAT_FIFO_NUM_USED = 0x00000094,
21569	RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 0x00000095,
21570	RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 0x00000096,
21571	RMI_PERF_SEL_XNACK_FIFO_FULL = 0x00000097,
21572	RMI_PERF_SEL_XNACK_FIFO_BUSY = 0x00000098,
21573	RMI_PERF_SEL_LAT_FIFO_FULL = 0x00000099,
21574	RMI_PERF_SEL_SKID_FIFO_DEPTH = 0x0000009a,
21575	RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 0x0000009b,
21576	RMI_PERF_SEL_PRT_FIFO_NUM_USED = 0x0000009c,
21577	RMI_PERF_SEL_PRT_FIFO_REQ = 0x0000009d,
21578	RMI_PERF_SEL_PRT_FIFO_BUSY = 0x0000009e,
21579	RMI_PERF_SEL_TCIW_REQ = 0x0000009f,
21580	RMI_PERF_SEL_TCIW_BUSY = 0x000000a0,
21581	RMI_PERF_SEL_SKID_FIFO_REQ = 0x000000a1,
21582	RMI_PERF_SEL_SKID_FIFO_BUSY = 0x000000a2,
21583	RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 0x000000a3,
21584	RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 0x000000a4,
21585	RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 0x000000a5,
21586	RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 0x000000a6,
21587	RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 0x000000a7,
21588	RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 0x000000a8,
21589	RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 0x000000a9,
21590	RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 0x000000aa,
21591	RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000ab,
21592	RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000ac,
21593	RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000ad,
21594	RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000ae,
21595	RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000af,
21596	RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000b0,
21597	RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000b1,
21598	RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000b2,
21599	RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000b3,
21600	RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000b4,
21601	RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000b5,
21602	RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000b6,
21603	RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 0x000000b7,
21604	RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 0x000000b8,
21605	RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 0x000000b9,
21606	RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 0x000000ba,
21607	RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 0x000000bb,
21608	RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 0x000000bc,
21609	RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 0x000000bd,
21610	RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 0x000000be,
21611	RMI_PERF_SEL_UTC_POP_RTS_RTR = 0x000000bf,
21612	RMI_PERF_SEL_UTC_POP_RTSB_RTR = 0x000000c0,
21613	RMI_PERF_SEL_UTC_POP_RTS_RTRB = 0x000000c1,
21614	RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 0x000000c2,
21615	RMI_PERF_SEL_POP_XNACK_RTS_RTR = 0x000000c3,
21616	RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 0x000000c4,
21617	RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 0x000000c5,
21618	RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 0x000000c6,
21619	RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 0x000000c7,
21620	RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 0x000000c8,
21621	RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 0x000000c9,
21622	RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 0x000000ca,
21623	RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000cb,
21624	RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000cc,
21625	RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000cd,
21626	RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000ce,
21627	RMI_PERF_SEL_SKID_FIFO_IN_RTS = 0x000000cf,
21628	RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 0x000000d0,
21629	RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 0x000000d1,
21630	RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 0x000000d2,
21631	RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 0x000000d3,
21632	RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000d4,
21633	RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 0x000000d5,
21634	RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 0x000000d6,
21635	RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 0x000000d7,
21636	RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 0x000000d8,
21637	RMI_PERF_SEL_REORDER_FIFO_REQ = 0x000000d9,
21638	RMI_PERF_SEL_REORDER_FIFO_BUSY = 0x000000da,
21639	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 0x000000db,
21640	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 0x000000dc,
21641	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 0x000000dd,
21642	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 0x000000de,
21643	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 0x000000df,
21644	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 0x000000e0,
21645	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 0x000000e1,
21646	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 0x000000e2,
21647	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 0x000000e3,
21648	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 0x000000e4,
21649	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 0x000000e5,
21650	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 0x000000e6,
21651	RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 0x000000e7,
21652	} RMIPerfSel;
21653
21654	/*******************************************************
21655	* IH Enums
21656	*******************************************************/
21657
21658	/*
21659	* IH_PERF_SEL enum
21660	*/
21661
21662	typedef enum IH_PERF_SEL {
21663	IH_PERF_SEL_CYCLE = 0x00000000,
21664	IH_PERF_SEL_IDLE = 0x00000001,
21665	IH_PERF_SEL_INPUT_IDLE = 0x00000002,
21666	IH_PERF_SEL_BUFFER_IDLE = 0x00000003,
21667	IH_PERF_SEL_RB0_FULL = 0x00000004,
21668	IH_PERF_SEL_RB0_OVERFLOW = 0x00000005,
21669	IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006,
21670	IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007,
21671	IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008,
21672	IH_PERF_SEL_MC_WR_IDLE = 0x00000009,
21673	IH_PERF_SEL_MC_WR_COUNT = 0x0000000a,
21674	IH_PERF_SEL_MC_WR_STALL = 0x0000000b,
21675	IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c,
21676	IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d,
21677	IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e,
21678	IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f,
21679	IH_PERF_SEL_RB1_FULL = 0x00000010,
21680	IH_PERF_SEL_RB1_OVERFLOW = 0x00000011,
21681	Reserved18 = 0x00000012,
21682	IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013,
21683	IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014,
21684	IH_PERF_SEL_RB2_FULL = 0x00000015,
21685	IH_PERF_SEL_RB2_OVERFLOW = 0x00000016,
21686	Reserved23 = 0x00000017,
21687	IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018,
21688	IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019,
21689	Reserved26 = 0x0000001a,
21690	Reserved27 = 0x0000001b,
21691	Reserved28 = 0x0000001c,
21692	Reserved29 = 0x0000001d,
21693	IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001e,
21694	IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001f,
21695	IH_PERF_SEL_RB0_FULL_VF2 = 0x00000020,
21696	IH_PERF_SEL_RB0_FULL_VF3 = 0x00000021,
21697	IH_PERF_SEL_RB0_FULL_VF4 = 0x00000022,
21698	IH_PERF_SEL_RB0_FULL_VF5 = 0x00000023,
21699	IH_PERF_SEL_RB0_FULL_VF6 = 0x00000024,
21700	IH_PERF_SEL_RB0_FULL_VF7 = 0x00000025,
21701	IH_PERF_SEL_RB0_FULL_VF8 = 0x00000026,
21702	IH_PERF_SEL_RB0_FULL_VF9 = 0x00000027,
21703	IH_PERF_SEL_RB0_FULL_VF10 = 0x00000028,
21704	IH_PERF_SEL_RB0_FULL_VF11 = 0x00000029,
21705	IH_PERF_SEL_RB0_FULL_VF12 = 0x0000002a,
21706	IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002b,
21707	IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002c,
21708	IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002d,
21709	IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000002e,
21710	IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000002f,
21711	IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x00000030,
21712	IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x00000031,
21713	IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000032,
21714	IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000033,
21715	IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000034,
21716	IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000035,
21717	IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000036,
21718	IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000037,
21719	IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000038,
21720	IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000039,
21721	IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x0000003a,
21722	IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x0000003b,
21723	IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000003c,
21724	IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000003d,
21725	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000003e,
21726	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000003f,
21727	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x00000040,
21728	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x00000041,
21729	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x00000042,
21730	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000043,
21731	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000044,
21732	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000045,
21733	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000046,
21734	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000047,
21735	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000048,
21736	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000049,
21737	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x0000004a,
21738	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x0000004b,
21739	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x0000004c,
21740	IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000004d,
21741	IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000004e,
21742	IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000004f,
21743	IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x00000050,
21744	IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x00000051,
21745	IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x00000052,
21746	IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x00000053,
21747	IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000054,
21748	IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000055,
21749	IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000056,
21750	IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000057,
21751	IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000058,
21752	IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000059,
21753	IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x0000005a,
21754	IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x0000005b,
21755	IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x0000005c,
21756	IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x0000005d,
21757	IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x0000005e,
21758	IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000005f,
21759	IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x00000060,
21760	IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x00000061,
21761	IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x00000062,
21762	IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x00000063,
21763	IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x00000064,
21764	IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x00000065,
21765	IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x00000066,
21766	IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x00000067,
21767	IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x00000068,
21768	IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x00000069,
21769	IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x0000006a,
21770	IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x0000006b,
21771	IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x0000006c,
21772	IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x0000006d,
21773	IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x0000006e,
21774	IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x0000006f,
21775	IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x00000070,
21776	IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x00000071,
21777	IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x00000072,
21778	IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x00000073,
21779	IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x00000074,
21780	IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x00000075,
21781	IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x00000076,
21782	IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x00000077,
21783	IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x00000078,
21784	IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x00000079,
21785	IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x0000007a,
21786	IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x0000007b,
21787	IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x0000007c,
21788	IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x0000007d,
21789	IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x0000007e,
21790	IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x0000007f,
21791	IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x00000080,
21792	IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x00000081,
21793	IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x00000082,
21794	IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x00000083,
21795	IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x00000084,
21796	IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x00000085,
21797	IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x00000086,
21798	IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x00000087,
21799	IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x00000088,
21800	IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x00000089,
21801	IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x0000008a,
21802	IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x0000008b,
21803	IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x0000008c,
21804	IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x0000008d,
21805	Reserved142 = 0x0000008e,
21806	Reserved143 = 0x0000008f,
21807	Reserved144 = 0x00000090,
21808	Reserved145 = 0x00000091,
21809	Reserved146 = 0x00000092,
21810	Reserved147 = 0x00000093,
21811	Reserved148 = 0x00000094,
21812	Reserved149 = 0x00000095,
21813	IH_PERF_SEL_CLIENT0_INT = 0x00000096,
21814	IH_PERF_SEL_CLIENT1_INT = 0x00000097,
21815	IH_PERF_SEL_CLIENT2_INT = 0x00000098,
21816	IH_PERF_SEL_CLIENT3_INT = 0x00000099,
21817	IH_PERF_SEL_CLIENT4_INT = 0x0000009a,
21818	IH_PERF_SEL_CLIENT5_INT = 0x0000009b,
21819	IH_PERF_SEL_CLIENT6_INT = 0x0000009c,
21820	IH_PERF_SEL_CLIENT7_INT = 0x0000009d,
21821	IH_PERF_SEL_CLIENT8_INT = 0x0000009e,
21822	IH_PERF_SEL_CLIENT9_INT = 0x0000009f,
21823	IH_PERF_SEL_CLIENT10_INT = 0x000000a0,
21824	IH_PERF_SEL_CLIENT11_INT = 0x000000a1,
21825	IH_PERF_SEL_CLIENT12_INT = 0x000000a2,
21826	IH_PERF_SEL_CLIENT13_INT = 0x000000a3,
21827	IH_PERF_SEL_CLIENT14_INT = 0x000000a4,
21828	IH_PERF_SEL_CLIENT15_INT = 0x000000a5,
21829	IH_PERF_SEL_CLIENT16_INT = 0x000000a6,
21830	IH_PERF_SEL_CLIENT17_INT = 0x000000a7,
21831	IH_PERF_SEL_CLIENT18_INT = 0x000000a8,
21832	IH_PERF_SEL_CLIENT19_INT = 0x000000a9,
21833	IH_PERF_SEL_CLIENT20_INT = 0x000000aa,
21834	IH_PERF_SEL_CLIENT21_INT = 0x000000ab,
21835	IH_PERF_SEL_CLIENT22_INT = 0x000000ac,
21836	IH_PERF_SEL_CLIENT23_INT = 0x000000ad,
21837	IH_PERF_SEL_CLIENT24_INT = 0x000000ae,
21838	IH_PERF_SEL_CLIENT25_INT = 0x000000af,
21839	IH_PERF_SEL_CLIENT26_INT = 0x000000b0,
21840	IH_PERF_SEL_CLIENT27_INT = 0x000000b1,
21841	IH_PERF_SEL_CLIENT28_INT = 0x000000b2,
21842	IH_PERF_SEL_CLIENT29_INT = 0x000000b3,
21843	IH_PERF_SEL_CLIENT30_INT = 0x000000b4,
21844	IH_PERF_SEL_CLIENT31_INT = 0x000000b5,
21845	Reserved182 = 0x000000b6,
21846	Reserved183 = 0x000000b7,
21847	Reserved184 = 0x000000b8,
21848	Reserved185 = 0x000000b9,
21849	Reserved186 = 0x000000ba,
21850	Reserved187 = 0x000000bb,
21851	Reserved188 = 0x000000bc,
21852	Reserved189 = 0x000000bd,
21853	Reserved190 = 0x000000be,
21854	Reserved191 = 0x000000bf,
21855	Reserved192 = 0x000000c0,
21856	Reserved193 = 0x000000c1,
21857	Reserved194 = 0x000000c2,
21858	Reserved195 = 0x000000c3,
21859	Reserved196 = 0x000000c4,
21860	Reserved197 = 0x000000c5,
21861	Reserved198 = 0x000000c6,
21862	Reserved199 = 0x000000c7,
21863	Reserved200 = 0x000000c8,
21864	Reserved201 = 0x000000c9,
21865	Reserved202 = 0x000000ca,
21866	Reserved203 = 0x000000cb,
21867	Reserved204 = 0x000000cc,
21868	Reserved205 = 0x000000cd,
21869	Reserved206 = 0x000000ce,
21870	Reserved207 = 0x000000cf,
21871	Reserved208 = 0x000000d0,
21872	Reserved209 = 0x000000d1,
21873	Reserved210 = 0x000000d2,
21874	Reserved211 = 0x000000d3,
21875	Reserved212 = 0x000000d4,
21876	Reserved213 = 0x000000d5,
21877	Reserved214 = 0x000000d6,
21878	Reserved215 = 0x000000d7,
21879	Reserved216 = 0x000000d8,
21880	Reserved217 = 0x000000d9,
21881	Reserved218 = 0x000000da,
21882	Reserved219 = 0x000000db,
21883	IH_PERF_SEL_RB1_FULL_VF0 = 0x000000dc,
21884	IH_PERF_SEL_RB1_FULL_VF1 = 0x000000dd,
21885	IH_PERF_SEL_RB1_FULL_VF2 = 0x000000de,
21886	IH_PERF_SEL_RB1_FULL_VF3 = 0x000000df,
21887	IH_PERF_SEL_RB1_FULL_VF4 = 0x000000e0,
21888	IH_PERF_SEL_RB1_FULL_VF5 = 0x000000e1,
21889	IH_PERF_SEL_RB1_FULL_VF6 = 0x000000e2,
21890	IH_PERF_SEL_RB1_FULL_VF7 = 0x000000e3,
21891	IH_PERF_SEL_RB1_FULL_VF8 = 0x000000e4,
21892	IH_PERF_SEL_RB1_FULL_VF9 = 0x000000e5,
21893	IH_PERF_SEL_RB1_FULL_VF10 = 0x000000e6,
21894	IH_PERF_SEL_RB1_FULL_VF11 = 0x000000e7,
21895	IH_PERF_SEL_RB1_FULL_VF12 = 0x000000e8,
21896	IH_PERF_SEL_RB1_FULL_VF13 = 0x000000e9,
21897	IH_PERF_SEL_RB1_FULL_VF14 = 0x000000ea,
21898	IH_PERF_SEL_RB1_FULL_VF15 = 0x000000eb,
21899	IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x000000ec,
21900	IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x000000ed,
21901	IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x000000ee,
21902	IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x000000ef,
21903	IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x000000f0,
21904	IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x000000f1,
21905	IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x000000f2,
21906	IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x000000f3,
21907	IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x000000f4,
21908	IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x000000f5,
21909	IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x000000f6,
21910	IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x000000f7,
21911	IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x000000f8,
21912	IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x000000f9,
21913	IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x000000fa,
21914	IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x000000fb,
21915	Reserved252 = 0x000000fc,
21916	Reserved253 = 0x000000fd,
21917	Reserved254 = 0x000000fe,
21918	Reserved255 = 0x000000ff,
21919	Reserved256 = 0x00000100,
21920	Reserved257 = 0x00000101,
21921	Reserved258 = 0x00000102,
21922	Reserved259 = 0x00000103,
21923	Reserved260 = 0x00000104,
21924	Reserved261 = 0x00000105,
21925	Reserved262 = 0x00000106,
21926	Reserved263 = 0x00000107,
21927	Reserved264 = 0x00000108,
21928	Reserved265 = 0x00000109,
21929	Reserved266 = 0x0000010a,
21930	Reserved267 = 0x0000010b,
21931	IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x0000010c,
21932	IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x0000010d,
21933	IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x0000010e,
21934	IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x0000010f,
21935	IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x00000110,
21936	IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x00000111,
21937	IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x00000112,
21938	IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x00000113,
21939	IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x00000114,
21940	IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x00000115,
21941	IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x00000116,
21942	IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x00000117,
21943	IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x00000118,
21944	IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x00000119,
21945	IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x0000011a,
21946	IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x0000011b,
21947	IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x0000011c,
21948	IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x0000011d,
21949	IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x0000011e,
21950	IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x0000011f,
21951	IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x00000120,
21952	IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x00000121,
21953	IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x00000122,
21954	IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x00000123,
21955	IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x00000124,
21956	IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x00000125,
21957	IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x00000126,
21958	IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x00000127,
21959	IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x00000128,
21960	IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x00000129,
21961	IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x0000012a,
21962	IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x0000012b,
21963	Reserved300 = 0x0000012c,
21964	Reserved301 = 0x0000012d,
21965	Reserved302 = 0x0000012e,
21966	Reserved303 = 0x0000012f,
21967	Reserved304 = 0x00000130,
21968	Reserved305 = 0x00000131,
21969	Reserved306 = 0x00000132,
21970	Reserved307 = 0x00000133,
21971	Reserved308 = 0x00000134,
21972	Reserved309 = 0x00000135,
21973	Reserved310 = 0x00000136,
21974	Reserved311 = 0x00000137,
21975	Reserved312 = 0x00000138,
21976	Reserved313 = 0x00000139,
21977	Reserved314 = 0x0000013a,
21978	Reserved315 = 0x0000013b,
21979	Reserved316 = 0x0000013c,
21980	Reserved317 = 0x0000013d,
21981	Reserved318 = 0x0000013e,
21982	Reserved319 = 0x0000013f,
21983	Reserved320 = 0x00000140,
21984	Reserved321 = 0x00000141,
21985	Reserved322 = 0x00000142,
21986	Reserved323 = 0x00000143,
21987	Reserved324 = 0x00000144,
21988	Reserved325 = 0x00000145,
21989	Reserved326 = 0x00000146,
21990	Reserved327 = 0x00000147,
21991	Reserved328 = 0x00000148,
21992	Reserved329 = 0x00000149,
21993	Reserved330 = 0x0000014a,
21994	Reserved331 = 0x0000014b,
21995	IH_PERF_SEL_RB2_FULL_VF0 = 0x0000014c,
21996	IH_PERF_SEL_RB2_FULL_VF1 = 0x0000014d,
21997	IH_PERF_SEL_RB2_FULL_VF2 = 0x0000014e,
21998	IH_PERF_SEL_RB2_FULL_VF3 = 0x0000014f,
21999	IH_PERF_SEL_RB2_FULL_VF4 = 0x00000150,
22000	IH_PERF_SEL_RB2_FULL_VF5 = 0x00000151,
22001	IH_PERF_SEL_RB2_FULL_VF6 = 0x00000152,
22002	IH_PERF_SEL_RB2_FULL_VF7 = 0x00000153,
22003	IH_PERF_SEL_RB2_FULL_VF8 = 0x00000154,
22004	IH_PERF_SEL_RB2_FULL_VF9 = 0x00000155,
22005	IH_PERF_SEL_RB2_FULL_VF10 = 0x00000156,
22006	IH_PERF_SEL_RB2_FULL_VF11 = 0x00000157,
22007	IH_PERF_SEL_RB2_FULL_VF12 = 0x00000158,
22008	IH_PERF_SEL_RB2_FULL_VF13 = 0x00000159,
22009	IH_PERF_SEL_RB2_FULL_VF14 = 0x0000015a,
22010	IH_PERF_SEL_RB2_FULL_VF15 = 0x0000015b,
22011	IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x0000015c,
22012	IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x0000015d,
22013	IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x0000015e,
22014	IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x0000015f,
22015	IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x00000160,
22016	IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x00000161,
22017	IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x00000162,
22018	IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x00000163,
22019	IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x00000164,
22020	IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x00000165,
22021	IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x00000166,
22022	IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x00000167,
22023	IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x00000168,
22024	IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x00000169,
22025	IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x0000016a,
22026	IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x0000016b,
22027	Reserved364 = 0x0000016c,
22028	Reserved365 = 0x0000016d,
22029	Reserved366 = 0x0000016e,
22030	Reserved367 = 0x0000016f,
22031	Reserved368 = 0x00000170,
22032	Reserved369 = 0x00000171,
22033	Reserved370 = 0x00000172,
22034	Reserved371 = 0x00000173,
22035	Reserved372 = 0x00000174,
22036	Reserved373 = 0x00000175,
22037	Reserved374 = 0x00000176,
22038	Reserved375 = 0x00000177,
22039	Reserved376 = 0x00000178,
22040	Reserved377 = 0x00000179,
22041	Reserved378 = 0x0000017a,
22042	Reserved379 = 0x0000017b,
22043	IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x0000017c,
22044	IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x0000017d,
22045	IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x0000017e,
22046	IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x0000017f,
22047	IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x00000180,
22048	IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x00000181,
22049	IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x00000182,
22050	IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x00000183,
22051	IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x00000184,
22052	IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x00000185,
22053	IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x00000186,
22054	IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x00000187,
22055	IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x00000188,
22056	IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x00000189,
22057	IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x0000018a,
22058	IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x0000018b,
22059	IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x0000018c,
22060	IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x0000018d,
22061	IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x0000018e,
22062	IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x0000018f,
22063	IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x00000190,
22064	IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x00000191,
22065	IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x00000192,
22066	IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x00000193,
22067	IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x00000194,
22068	IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x00000195,
22069	IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x00000196,
22070	IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x00000197,
22071	IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x00000198,
22072	IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x00000199,
22073	IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x0000019a,
22074	IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x0000019b,
22075	Reserved412 = 0x0000019c,
22076	Reserved413 = 0x0000019d,
22077	Reserved414 = 0x0000019e,
22078	Reserved415 = 0x0000019f,
22079	Reserved416 = 0x000001a0,
22080	Reserved417 = 0x000001a1,
22081	Reserved418 = 0x000001a2,
22082	Reserved419 = 0x000001a3,
22083	Reserved420 = 0x000001a4,
22084	Reserved421 = 0x000001a5,
22085	Reserved422 = 0x000001a6,
22086	Reserved423 = 0x000001a7,
22087	Reserved424 = 0x000001a8,
22088	Reserved425 = 0x000001a9,
22089	Reserved426 = 0x000001aa,
22090	Reserved427 = 0x000001ab,
22091	Reserved428 = 0x000001ac,
22092	Reserved429 = 0x000001ad,
22093	Reserved430 = 0x000001ae,
22094	Reserved431 = 0x000001af,
22095	Reserved432 = 0x000001b0,
22096	Reserved433 = 0x000001b1,
22097	Reserved434 = 0x000001b2,
22098	Reserved435 = 0x000001b3,
22099	Reserved436 = 0x000001b4,
22100	Reserved437 = 0x000001b5,
22101	Reserved438 = 0x000001b6,
22102	Reserved439 = 0x000001b7,
22103	Reserved440 = 0x000001b8,
22104	Reserved441 = 0x000001b9,
22105	Reserved442 = 0x000001ba,
22106	Reserved443 = 0x000001bb,
22107	Reserved444 = 0x000001bc,
22108	Reserved445 = 0x000001bd,
22109	Reserved446 = 0x000001be,
22110	Reserved447 = 0x000001bf,
22111	Reserved448 = 0x000001c0,
22112	Reserved449 = 0x000001c1,
22113	Reserved450 = 0x000001c2,
22114	Reserved451 = 0x000001c3,
22115	Reserved452 = 0x000001c4,
22116	Reserved453 = 0x000001c5,
22117	Reserved454 = 0x000001c6,
22118	Reserved455 = 0x000001c7,
22119	Reserved456 = 0x000001c8,
22120	Reserved457 = 0x000001c9,
22121	Reserved458 = 0x000001ca,
22122	Reserved459 = 0x000001cb,
22123	Reserved460 = 0x000001cc,
22124	Reserved461 = 0x000001cd,
22125	Reserved462 = 0x000001ce,
22126	Reserved463 = 0x000001cf,
22127	Reserved464 = 0x000001d0,
22128	Reserved465 = 0x000001d1,
22129	Reserved466 = 0x000001d2,
22130	Reserved467 = 0x000001d3,
22131	Reserved468 = 0x000001d4,
22132	Reserved469 = 0x000001d5,
22133	Reserved470 = 0x000001d6,
22134	Reserved471 = 0x000001d7,
22135	Reserved472 = 0x000001d8,
22136	Reserved473 = 0x000001d9,
22137	Reserved474 = 0x000001da,
22138	Reserved475 = 0x000001db,
22139	Reserved476 = 0x000001dc,
22140	Reserved477 = 0x000001dd,
22141	Reserved478 = 0x000001de,
22142	Reserved479 = 0x000001df,
22143	Reserved480 = 0x000001e0,
22144	Reserved481 = 0x000001e1,
22145	Reserved482 = 0x000001e2,
22146	Reserved483 = 0x000001e3,
22147	Reserved484 = 0x000001e4,
22148	Reserved485 = 0x000001e5,
22149	Reserved486 = 0x000001e6,
22150	Reserved487 = 0x000001e7,
22151	Reserved488 = 0x000001e8,
22152	Reserved489 = 0x000001e9,
22153	Reserved490 = 0x000001ea,
22154	Reserved491 = 0x000001eb,
22155	Reserved492 = 0x000001ec,
22156	Reserved493 = 0x000001ed,
22157	Reserved494 = 0x000001ee,
22158	Reserved495 = 0x000001ef,
22159	Reserved496 = 0x000001f0,
22160	Reserved497 = 0x000001f1,
22161	Reserved498 = 0x000001f2,
22162	Reserved499 = 0x000001f3,
22163	Reserved500 = 0x000001f4,
22164	Reserved501 = 0x000001f5,
22165	Reserved502 = 0x000001f6,
22166	Reserved503 = 0x000001f7,
22167	Reserved504 = 0x000001f8,
22168	Reserved505 = 0x000001f9,
22169	Reserved506 = 0x000001fa,
22170	Reserved507 = 0x000001fb,
22171	Reserved508 = 0x000001fc,
22172	Reserved509 = 0x000001fd,
22173	Reserved510 = 0x000001fe,
22174	Reserved511 = 0x000001ff,
22175	} IH_PERF_SEL;
22176
22177	/*******************************************************
22178	* SEM Enums
22179	*******************************************************/
22180
22181	/*
22182	* SEM_PERF_SEL enum
22183	*/
22184
22185	typedef enum SEM_PERF_SEL {
22186	SEM_PERF_SEL_CYCLE = 0x00000000,
22187	SEM_PERF_SEL_IDLE = 0x00000001,
22188	SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002,
22189	SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003,
22190	SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000004,
22191	SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000005,
22192	SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000006,
22193	SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x00000007,
22194	SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x00000008,
22195	SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x00000009,
22196	SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000a,
22197	SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000b,
22198	SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000c,
22199	SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x0000000d,
22200	SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x0000000e,
22201	SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x0000000f,
22202	SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000010,
22203	SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000011,
22204	SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000012,
22205	SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000013,
22206	SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000014,
22207	SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000015,
22208	SEM_PERF_SEL_UVD_REQ_WAIT = 0x00000016,
22209	SEM_PERF_SEL_VCE0_REQ_WAIT = 0x00000017,
22210	SEM_PERF_SEL_ACP_REQ_WAIT = 0x00000018,
22211	SEM_PERF_SEL_ISP_REQ_WAIT = 0x00000019,
22212	SEM_PERF_SEL_VCE1_REQ_WAIT = 0x0000001a,
22213	SEM_PERF_SEL_VP8_REQ_WAIT = 0x0000001b,
22214	SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x0000001c,
22215	SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x0000001d,
22216	SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x0000001e,
22217	SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x0000001f,
22218	SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000020,
22219	SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000021,
22220	SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000022,
22221	SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000023,
22222	SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x00000024,
22223	SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x00000025,
22224	SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x00000026,
22225	SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x00000027,
22226	SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x00000028,
22227	SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x00000029,
22228	SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x0000002a,
22229	SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x0000002b,
22230	SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x0000002c,
22231	SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x0000002d,
22232	SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x0000002e,
22233	SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x0000002f,
22234	SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000030,
22235	SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000031,
22236	SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000032,
22237	SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000033,
22238	SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x00000034,
22239	SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x00000035,
22240	SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x00000036,
22241	SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x00000037,
22242	SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x00000038,
22243	SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x00000039,
22244	SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x0000003a,
22245	SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x0000003b,
22246	SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x0000003c,
22247	SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x0000003d,
22248	SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x0000003e,
22249	SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x0000003f,
22250	SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000040,
22251	SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000041,
22252	SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000042,
22253	SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000043,
22254	SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x00000044,
22255	SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x00000045,
22256	SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x00000046,
22257	SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x00000047,
22258	SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x00000048,
22259	SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x00000049,
22260	SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x0000004a,
22261	SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x0000004b,
22262	SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x0000004c,
22263	SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x0000004d,
22264	SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x0000004e,
22265	SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x0000004f,
22266	SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000050,
22267	SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000051,
22268	SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000052,
22269	SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000053,
22270	SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x00000054,
22271	SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x00000055,
22272	SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x00000056,
22273	SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x00000057,
22274	SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x00000058,
22275	SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x00000059,
22276	SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x0000005a,
22277	SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x0000005b,
22278	SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x0000005c,
22279	SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x0000005d,
22280	SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x0000005e,
22281	SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x0000005f,
22282	SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000060,
22283	SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000061,
22284	SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000062,
22285	SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000063,
22286	SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x00000064,
22287	SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x00000065,
22288	SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x00000066,
22289	SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x00000067,
22290	SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x00000068,
22291	SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x00000069,
22292	SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x0000006a,
22293	SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x0000006b,
22294	SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x0000006c,
22295	SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x0000006d,
22296	SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x0000006e,
22297	SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x0000006f,
22298	SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000070,
22299	SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000071,
22300	SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000072,
22301	SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000073,
22302	SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x00000074,
22303	SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x00000075,
22304	SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x00000076,
22305	SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x00000077,
22306	SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x00000078,
22307	SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x00000079,
22308	SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x0000007a,
22309	SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x0000007b,
22310	SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x0000007c,
22311	SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x0000007d,
22312	SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x0000007e,
22313	SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x0000007f,
22314	SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000080,
22315	SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000081,
22316	SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000082,
22317	SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000083,
22318	SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x00000084,
22319	SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x00000085,
22320	SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x00000086,
22321	SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x00000087,
22322	SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x00000088,
22323	SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x00000089,
22324	SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x0000008a,
22325	SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x0000008b,
22326	SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x0000008c,
22327	SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x0000008d,
22328	SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x0000008e,
22329	SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x0000008f,
22330	SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000090,
22331	SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000091,
22332	SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000092,
22333	SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000093,
22334	SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x00000094,
22335	SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x00000095,
22336	SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x00000096,
22337	SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x00000097,
22338	SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x00000098,
22339	SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x00000099,
22340	SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x0000009a,
22341	SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x0000009b,
22342	SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x0000009c,
22343	SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x0000009d,
22344	SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x0000009e,
22345	SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x0000009f,
22346	SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a0,
22347	SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a1,
22348	SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a2,
22349	SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a3,
22350	SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000a4,
22351	SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000a5,
22352	SEM_PERF_SEL_MC_RD_REQ = 0x000000a6,
22353	SEM_PERF_SEL_MC_RD_RET = 0x000000a7,
22354	SEM_PERF_SEL_MC_WR_REQ = 0x000000a8,
22355	SEM_PERF_SEL_MC_WR_RET = 0x000000a9,
22356	SEM_PERF_SEL_ATC_REQ = 0x000000aa,
22357	SEM_PERF_SEL_ATC_RET = 0x000000ab,
22358	SEM_PERF_SEL_ATC_XNACK = 0x000000ac,
22359	SEM_PERF_SEL_ATC_INVALIDATION = 0x000000ad,
22360	} SEM_PERF_SEL;
22361
22362	/*******************************************************
22363	* SDMA Enums
22364	*******************************************************/
22365
22366	/*
22367	* SDMA_PERF_SEL enum
22368	*/
22369
22370	typedef enum SDMA_PERF_SEL {
22371	SDMA_PERF_SEL_CYCLE = 0x00000000,
22372	SDMA_PERF_SEL_IDLE = 0x00000001,
22373	SDMA_PERF_SEL_REG_IDLE = 0x00000002,
22374	SDMA_PERF_SEL_RB_EMPTY = 0x00000003,
22375	SDMA_PERF_SEL_RB_FULL = 0x00000004,
22376	SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005,
22377	SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006,
22378	SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007,
22379	SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008,
22380	SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009,
22381	SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a,
22382	SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b,
22383	SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c,
22384	SDMA_PERF_SEL_EX_IDLE = 0x0000000d,
22385	SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e,
22386	SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
22387	SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010,
22388	SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011,
22389	SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012,
22390	SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013,
22391	SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014,
22392	SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015,
22393	SDMA_PERF_SEL_SEM_IDLE = 0x00000018,
22394	SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019,
22395	SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a,
22396	SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b,
22397	SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c,
22398	SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d,
22399	SDMA_PERF_SEL_INT_IDLE = 0x0000001e,
22400	SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f,
22401	SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020,
22402	SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021,
22403	SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022,
22404	SDMA_PERF_SEL_NUM_PACKET = 0x00000023,
22405	SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025,
22406	SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026,
22407	SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027,
22408	SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028,
22409	SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029,
22410	SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a,
22411	SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b,
22412	SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e,
22413	SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031,
22414	SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032,
22415	SDMA_PERF_SEL_CE_RD_STALL = 0x00000033,
22416	SDMA_PERF_SEL_CE_WR_STALL = 0x00000034,
22417	SDMA_PERF_SEL_GFX_SELECT = 0x00000035,
22418	SDMA_PERF_SEL_RLC0_SELECT = 0x00000036,
22419	SDMA_PERF_SEL_RLC1_SELECT = 0x00000037,
22420	SDMA_PERF_SEL_PAGE_SELECT = 0x00000038,
22421	SDMA_PERF_SEL_CTX_CHANGE = 0x00000039,
22422	SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a,
22423	SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b,
22424	SDMA_PERF_SEL_DOORBELL = 0x0000003c,
22425	SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d,
22426	SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e,
22427	SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f,
22428	SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040,
22429	SDMA_PERF_SEL_CE_L1_STALL = 0x00000041,
22430	SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042,
22431	SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043,
22432	SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044,
22433	SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045,
22434	SDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046,
22435	SDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047,
22436	SDMA_PERF_SEL_ATCL2_FREE = 0x00000048,
22437	SDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049,
22438	SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a,
22439	SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b,
22440	SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c,
22441	SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d,
22442	SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e,
22443	SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f,
22444	SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050,
22445	SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051,
22446	SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052,
22447	SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053,
22448	SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054,
22449	SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055,
22450	SDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056,
22451	SDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057,
22452	SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058,
22453	SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059,
22454	SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a,
22455	SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b,
22456	SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c,
22457	SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d,
22458	SDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e,
22459	SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 0x000000fe,
22460	SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 0x000000ff,
22461	} SDMA_PERF_SEL;
22462
22463	/*******************************************************
22464	* SMUIO Enums
22465	*******************************************************/
22466
22467	/*
22468	* ROM_SIGNATURE value
22469	*/
22470
22471	#define ROM_SIGNATURE 0x0000aa55
22472
22473	/*******************************************************
22474	* XDMA_CMN Enums
22475	*******************************************************/
22476
22477	/*
22478	* ENUM_XDMA_LOCAL_SW_MODE enum
22479	*/
22480
22481	typedef enum ENUM_XDMA_LOCAL_SW_MODE {
22482	XDMA_LOCAL_SW_MODE_SW_256B_D = 0x00000002,
22483	XDMA_LOCAL_SW_MODE_SW_64KB_D = 0x0000000a,
22484	XDMA_LOCAL_SW_MODE_SW_64KB_D_X = 0x0000001a,
22485	} ENUM_XDMA_LOCAL_SW_MODE;
22486
22487	/*******************************************************
22488	* XDMA_SLV Enums
22489	*******************************************************/
22490
22491	/*
22492	* ENUM_XDMA_SLV_ALPHA_POSITION enum
22493	*/
22494
22495	typedef enum ENUM_XDMA_SLV_ALPHA_POSITION {
22496	XDMA_SLV_ALPHA_POSITION_7_0 = 0x00000000,
22497	XDMA_SLV_ALPHA_POSITION_15_8 = 0x00000001,
22498	XDMA_SLV_ALPHA_POSITION_23_16 = 0x00000002,
22499	XDMA_SLV_ALPHA_POSITION_31_24 = 0x00000003,
22500	} ENUM_XDMA_SLV_ALPHA_POSITION;
22501
22502	/*******************************************************
22503	* XDMA_MSTR Enums
22504	*******************************************************/
22505
22506	/*
22507	* ENUM_XDMA_MSTR_ALPHA_POSITION enum
22508	*/
22509
22510	typedef enum ENUM_XDMA_MSTR_ALPHA_POSITION {
22511	XDMA_MSTR_ALPHA_POSITION_7_0 = 0x00000000,
22512	XDMA_MSTR_ALPHA_POSITION_15_8 = 0x00000001,
22513	XDMA_MSTR_ALPHA_POSITION_23_16 = 0x00000002,
22514	XDMA_MSTR_ALPHA_POSITION_31_24 = 0x00000003,
22515	} ENUM_XDMA_MSTR_ALPHA_POSITION;
22516
22517	/*
22518	* ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL enum
22519	*/
22520
22521	typedef enum ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL {
22522	XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0 = 0x00000000,
22523	XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1 = 0x00000001,
22524	XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2 = 0x00000002,
22525	XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3 = 0x00000003,
22526	XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4 = 0x00000004,
22527	XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5 = 0x00000005,
22528	} ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL;
22529
22530
22531	#endif /*_vega10_ENUM_HEADER*/
22532
22533