1	/*
2	* Copyright 2017 Advanced Micro Devices, Inc.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.
21	*
22	*/
23
24	#ifndef __KGD_PP_INTERFACE_H__
25	#define __KGD_PP_INTERFACE_H__
26
27	extern const struct amdgpu_ip_block_version pp_smu_ip_block;
28	extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
29	extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
30	extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
31	extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
32
33	enum smu_temp_metric_type {
34	SMU_TEMP_METRIC_BASEBOARD,
35	SMU_TEMP_METRIC_GPUBOARD,
36	SMU_TEMP_METRIC_MAX,
37	};
38
39	enum smu_event_type {
40	SMU_EVENT_RESET_COMPLETE = 0,
41	};
42
43	struct amd_vce_state {
44	/* vce clocks */
45	u32 evclk;
46	u32 ecclk;
47	/* gpu clocks */
48	u32 sclk;
49	u32 mclk;
50	u8 clk_idx;
51	u8 pstate;
52	};
53
54
55	enum amd_dpm_forced_level {
56	AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
57	AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
58	AMD_DPM_FORCED_LEVEL_LOW = 0x4,
59	AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
60	AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
61	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
62	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
63	AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
64	AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
65	AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
66	};
67
68	enum amd_pm_state_type {
69	/* not used for dpm */
70	POWER_STATE_TYPE_DEFAULT,
71	POWER_STATE_TYPE_POWERSAVE,
72	/* user selectable states */
73	POWER_STATE_TYPE_BATTERY,
74	POWER_STATE_TYPE_BALANCED,
75	POWER_STATE_TYPE_PERFORMANCE,
76	/* internal states */
77	POWER_STATE_TYPE_INTERNAL_UVD,
78	POWER_STATE_TYPE_INTERNAL_UVD_SD,
79	POWER_STATE_TYPE_INTERNAL_UVD_HD,
80	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
81	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
82	POWER_STATE_TYPE_INTERNAL_BOOT,
83	POWER_STATE_TYPE_INTERNAL_THERMAL,
84	POWER_STATE_TYPE_INTERNAL_ACPI,
85	POWER_STATE_TYPE_INTERNAL_ULV,
86	POWER_STATE_TYPE_INTERNAL_3DPERF,
87	};
88
89	#define AMD_MAX_VCE_LEVELS 6
90
91	enum amd_vce_level {
92	AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
93	AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
94	AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
95	AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
96	AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
97	AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
98	};
99
100	enum amd_fan_ctrl_mode {
101	AMD_FAN_CTRL_NONE = 0,
102	AMD_FAN_CTRL_MANUAL = 1,
103	AMD_FAN_CTRL_AUTO = 2,
104	};
105
106	enum pp_clock_type {
107	PP_SCLK,
108	PP_MCLK,
109	PP_PCIE,
110	PP_SOCCLK,
111	PP_FCLK,
112	PP_DCEFCLK,
113	PP_VCLK,
114	PP_VCLK1,
115	PP_DCLK,
116	PP_DCLK1,
117	PP_ISPICLK,
118	PP_ISPXCLK,
119	OD_SCLK,
120	OD_MCLK,
121	OD_VDDC_CURVE,
122	OD_RANGE,
123	OD_VDDGFX_OFFSET,
124	OD_CCLK,
125	OD_FAN_CURVE,
126	OD_ACOUSTIC_LIMIT,
127	OD_ACOUSTIC_TARGET,
128	OD_FAN_TARGET_TEMPERATURE,
129	OD_FAN_MINIMUM_PWM,
130	OD_FAN_ZERO_RPM_ENABLE,
131	OD_FAN_ZERO_RPM_STOP_TEMP,
132	};
133
134	enum amd_pp_sensors {
135	AMDGPU_PP_SENSOR_GFX_SCLK = 0,
136	AMDGPU_PP_SENSOR_CPU_CLK,
137	AMDGPU_PP_SENSOR_VDDNB,
138	AMDGPU_PP_SENSOR_VDDGFX,
139	AMDGPU_PP_SENSOR_VDDBOARD,
140	AMDGPU_PP_SENSOR_UVD_VCLK,
141	AMDGPU_PP_SENSOR_UVD_DCLK,
142	AMDGPU_PP_SENSOR_VCE_ECCLK,
143	AMDGPU_PP_SENSOR_GPU_LOAD,
144	AMDGPU_PP_SENSOR_MEM_LOAD,
145	AMDGPU_PP_SENSOR_GFX_MCLK,
146	AMDGPU_PP_SENSOR_GPU_TEMP,
147	AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
148	AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
149	AMDGPU_PP_SENSOR_MEM_TEMP,
150	AMDGPU_PP_SENSOR_VCE_POWER,
151	AMDGPU_PP_SENSOR_UVD_POWER,
152	AMDGPU_PP_SENSOR_GPU_AVG_POWER,
153	AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
154	AMDGPU_PP_SENSOR_SS_APU_SHARE,
155	AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
156	AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
157	AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
158	AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
159	AMDGPU_PP_SENSOR_MIN_FAN_RPM,
160	AMDGPU_PP_SENSOR_MAX_FAN_RPM,
161	AMDGPU_PP_SENSOR_VCN_POWER_STATE,
162	AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
163	AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
164	AMDGPU_PP_SENSOR_VCN_LOAD,
165	AMDGPU_PP_SENSOR_NODEPOWERLIMIT,
166	AMDGPU_PP_SENSOR_NODEPOWER,
167	AMDGPU_PP_SENSOR_GPPTRESIDENCY,
168	AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT,
169	};
170
171	enum amd_pp_task {
172	AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
173	AMD_PP_TASK_ENABLE_USER_STATE,
174	AMD_PP_TASK_READJUST_POWER_STATE,
175	AMD_PP_TASK_COMPLETE_INIT,
176	AMD_PP_TASK_MAX
177	};
178
179	enum PP_SMC_POWER_PROFILE {
180	PP_SMC_POWER_PROFILE_UNKNOWN = -1,
181	PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
182	PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
183	PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
184	PP_SMC_POWER_PROFILE_VIDEO = 0x3,
185	PP_SMC_POWER_PROFILE_VR = 0x4,
186	PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
187	PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
188	PP_SMC_POWER_PROFILE_WINDOW3D = 0x7,
189	PP_SMC_POWER_PROFILE_CAPPED = 0x8,
190	PP_SMC_POWER_PROFILE_UNCAPPED = 0x9,
191	PP_SMC_POWER_PROFILE_COUNT,
192	};
193
194	extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
195
196
197
198	enum {
199	PP_GROUP_UNKNOWN = 0,
200	PP_GROUP_GFX = 1,
201	PP_GROUP_SYS,
202	PP_GROUP_MAX
203	};
204
205	enum PP_OD_DPM_TABLE_COMMAND {
206	PP_OD_EDIT_SCLK_VDDC_TABLE,
207	PP_OD_EDIT_MCLK_VDDC_TABLE,
208	PP_OD_EDIT_CCLK_VDDC_TABLE,
209	PP_OD_EDIT_VDDC_CURVE,
210	PP_OD_RESTORE_DEFAULT_TABLE,
211	PP_OD_COMMIT_DPM_TABLE,
212	PP_OD_EDIT_VDDGFX_OFFSET,
213	PP_OD_EDIT_FAN_CURVE,
214	PP_OD_EDIT_ACOUSTIC_LIMIT,
215	PP_OD_EDIT_ACOUSTIC_TARGET,
216	PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
217	PP_OD_EDIT_FAN_MINIMUM_PWM,
218	PP_OD_EDIT_FAN_ZERO_RPM_ENABLE,
219	PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP,
220	};
221
222	struct pp_states_info {
223	uint32_t nums;
224	uint32_t states[16];
225	};
226
227	enum PP_HWMON_TEMP {
228	PP_TEMP_EDGE = 0,
229	PP_TEMP_JUNCTION,
230	PP_TEMP_MEM,
231	PP_TEMP_MAX
232	};
233
234	enum pp_mp1_state {
235	PP_MP1_STATE_NONE,
236	PP_MP1_STATE_SHUTDOWN,
237	PP_MP1_STATE_UNLOAD,
238	PP_MP1_STATE_RESET,
239	PP_MP1_STATE_FLR,
240	};
241
242	enum pp_df_cstate {
243	DF_CSTATE_DISALLOW = 0,
244	DF_CSTATE_ALLOW,
245	};
246
247	/**
248	* DOC: amdgpu_pp_power
249	*
250	* APU power is managed to system-level requirements through the PPT
251	* (package power tracking) feature. PPT is intended to limit power to the
252	* requirements of the power source and could be dynamically updated to
253	* maximize APU performance within the system power budget.
254	*
255	* Two types of power measurement can be requested, where supported, with
256	* :c:type:`enum pp_power_type <pp_power_type>`.
257	*/
258
259	/**
260	* enum pp_power_limit_level - Used to query the power limits
261	*
262	* @PP_PWR_LIMIT_MIN: Minimum Power Limit
263	* @PP_PWR_LIMIT_CURRENT: Current Power Limit
264	* @PP_PWR_LIMIT_DEFAULT: Default Power Limit
265	* @PP_PWR_LIMIT_MAX: Maximum Power Limit
266	*/
267	enum pp_power_limit_level {
268	PP_PWR_LIMIT_MIN = -1,
269	PP_PWR_LIMIT_CURRENT,
270	PP_PWR_LIMIT_DEFAULT,
271	PP_PWR_LIMIT_MAX,
272	};
273
274	/**
275	* enum pp_power_type - Used to specify the type of the requested power
276	*
277	* @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
278	* moving average of APU power (default ~5000 ms).
279	* @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
280	* where supported.
281	*/
282	enum pp_power_type {
283	PP_PWR_TYPE_SUSTAINED,
284	PP_PWR_TYPE_FAST,
285	};
286
287	enum pp_xgmi_plpd_mode {
288	XGMI_PLPD_NONE = -1,
289	XGMI_PLPD_DISALLOW,
290	XGMI_PLPD_DEFAULT,
291	XGMI_PLPD_OPTIMIZED,
292	XGMI_PLPD_COUNT,
293	};
294
295	enum pp_pm_policy {
296	PP_PM_POLICY_NONE = -1,
297	PP_PM_POLICY_SOC_PSTATE = 0,
298	PP_PM_POLICY_XGMI_PLPD,
299	PP_PM_POLICY_NUM,
300	};
301
302	enum pp_policy_soc_pstate {
303	SOC_PSTATE_DEFAULT = 0,
304	SOC_PSTATE_0,
305	SOC_PSTATE_1,
306	SOC_PSTATE_2,
307	SOC_PSTAT_COUNT,
308	};
309
310	#define PP_POLICY_MAX_LEVELS 5
311
312	#define PP_GROUP_MASK 0xF0000000
313	#define PP_GROUP_SHIFT 28
314
315	#define PP_BLOCK_MASK 0x0FFFFF00
316	#define PP_BLOCK_SHIFT 8
317
318	#define PP_BLOCK_GFX_CG 0x01
319	#define PP_BLOCK_GFX_MG 0x02
320	#define PP_BLOCK_GFX_3D 0x04
321	#define PP_BLOCK_GFX_RLC 0x08
322	#define PP_BLOCK_GFX_CP 0x10
323	#define PP_BLOCK_SYS_BIF 0x01
324	#define PP_BLOCK_SYS_MC 0x02
325	#define PP_BLOCK_SYS_ROM 0x04
326	#define PP_BLOCK_SYS_DRM 0x08
327	#define PP_BLOCK_SYS_HDP 0x10
328	#define PP_BLOCK_SYS_SDMA 0x20
329
330	#define PP_STATE_MASK 0x0000000F
331	#define PP_STATE_SHIFT 0
332	#define PP_STATE_SUPPORT_MASK 0x000000F0
333	#define PP_STATE_SUPPORT_SHIFT 0
334
335	#define PP_STATE_CG 0x01
336	#define PP_STATE_LS 0x02
337	#define PP_STATE_DS 0x04
338	#define PP_STATE_SD 0x08
339	#define PP_STATE_SUPPORT_CG 0x10
340	#define PP_STATE_SUPPORT_LS 0x20
341	#define PP_STATE_SUPPORT_DS 0x40
342	#define PP_STATE_SUPPORT_SD 0x80
343
344	#define PP_CG_MSG_ID(group, block, support, state) \
345	((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
346	(support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
347
348	#define XGMI_MODE_PSTATE_D3 0
349	#define XGMI_MODE_PSTATE_D0 1
350
351	#define NUM_HBM_INSTANCES 4
352	#define NUM_XGMI_LINKS 8
353	#define MAX_GFX_CLKS 8
354	#define MAX_CLKS 4
355	#define NUM_VCN 4
356	#define NUM_JPEG_ENG 32
357	#define NUM_JPEG_ENG_V1 40
358	#define MAX_XCC 8
359	#define NUM_XCP 8
360	struct seq_file;
361	enum amd_pp_clock_type;
362	struct amd_pp_simple_clock_info;
363	struct amd_pp_display_configuration;
364	struct amd_pp_clock_info;
365	struct pp_display_clock_request;
366	struct pp_clock_levels_with_voltage;
367	struct pp_clock_levels_with_latency;
368	struct amd_pp_clocks;
369	struct pp_smu_wm_range_sets;
370	struct pp_smu_nv_clock_table;
371	struct dpm_clocks;
372
373	struct amdgpu_xcp_metrics {
374	/* Utilization Instantaneous (%) */
375	uint32_t gfx_busy_inst[MAX_XCC];
376	uint16_t jpeg_busy[NUM_JPEG_ENG];
377	uint16_t vcn_busy[NUM_VCN];
378	/* Utilization Accumulated (%) */
379	uint64_t gfx_busy_acc[MAX_XCC];
380	};
381
382	struct amdgpu_xcp_metrics_v1_1 {
383	/* Utilization Instantaneous (%) */
384	uint32_t gfx_busy_inst[MAX_XCC];
385	uint16_t jpeg_busy[NUM_JPEG_ENG];
386	uint16_t vcn_busy[NUM_VCN];
387	/* Utilization Accumulated (%) */
388	uint64_t gfx_busy_acc[MAX_XCC];
389	/* Total App Clock Counter Accumulated */
390	uint64_t gfx_below_host_limit_acc[MAX_XCC];
391	};
392
393	struct amdgpu_xcp_metrics_v1_2 {
394	/* Utilization Instantaneous (%) */
395	uint32_t gfx_busy_inst[MAX_XCC];
396	uint16_t jpeg_busy[NUM_JPEG_ENG_V1];
397	uint16_t vcn_busy[NUM_VCN];
398	/* Utilization Accumulated (%) */
399	uint64_t gfx_busy_acc[MAX_XCC];
400	/* Total App Clock Counter Accumulated */
401	uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC];
402	uint64_t gfx_below_host_limit_thm_acc[MAX_XCC];
403	uint64_t gfx_low_utilization_acc[MAX_XCC];
404	uint64_t gfx_below_host_limit_total_acc[MAX_XCC];
405	};
406
407	struct amd_pm_funcs {
408	/* export for dpm on ci and si */
409	int (*pre_set_power_state)(void *handle);
410	int (*set_power_state)(void *handle);
411	void (*post_set_power_state)(void *handle);
412	void (*display_configuration_changed)(void *handle);
413	void (*print_power_state)(void *handle, void *ps);
414	bool (*vblank_too_short)(void *handle);
415	void (*enable_bapm)(void *handle, bool enable);
416	int (*check_state_equal)(void *handle,
417	void *cps,
418	void *rps,
419	bool *equal);
420	/* export for sysfs */
421	int (*set_fan_control_mode)(void *handle, u32 mode);
422	int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
423	int (*set_fan_speed_pwm)(void *handle, u32 speed);
424	int (*get_fan_speed_pwm)(void *handle, u32 *speed);
425	int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
426	int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
427	int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
428	int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
429	int (*get_sclk_od)(void *handle);
430	int (*set_sclk_od)(void *handle, uint32_t value);
431	int (*get_mclk_od)(void *handle);
432	int (*set_mclk_od)(void *handle, uint32_t value);
433	int (*read_sensor)(void *handle, int idx, void *value, int *size);
434	int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
435	int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
436	enum amd_dpm_forced_level (*get_performance_level)(void *handle);
437	enum amd_pm_state_type (*get_current_power_state)(void *handle);
438	int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
439	int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
440	int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
441	int (*get_pp_table)(void *handle, char **table);
442	int (*set_pp_table)(void *handle, const char *buf, size_t size);
443	void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
444	int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
445	int (*pause_power_profile)(void *handle, bool pause);
446	/* export to amdgpu */
447	struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
448	int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
449	enum amd_pm_state_type *user_state);
450	int (*load_firmware)(void *handle);
451	int (*wait_for_fw_loading_complete)(void *handle);
452	int (*set_powergating_by_smu)(void *handle,
453	uint32_t block_type,
454	bool gate,
455	int inst);
456	int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
457	int (*set_power_limit)(void *handle, uint32_t limit_type, uint32_t n);
458	int (*get_power_limit)(void *handle, uint32_t *limit,
459	enum pp_power_limit_level pp_limit_level,
460	enum pp_power_type power_type);
461	int (*get_power_profile_mode)(void *handle, char *buf);
462	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
463	int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
464	int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
465	long *input, uint32_t size);
466	int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
467	int (*smu_i2c_bus_access)(void *handle, bool acquire);
468	int (*gfx_state_change_set)(void *handle, uint32_t state);
469	/* export to DC */
470	u32 (*get_sclk)(void *handle, bool low);
471	u32 (*get_mclk)(void *handle, bool low);
472	int (*display_configuration_change)(void *handle,
473	const struct amd_pp_display_configuration *input);
474	int (*get_display_power_level)(void *handle,
475	struct amd_pp_simple_clock_info *output);
476	int (*get_current_clocks)(void *handle,
477	struct amd_pp_clock_info *clocks);
478	int (*get_clock_by_type)(void *handle,
479	enum amd_pp_clock_type type,
480	struct amd_pp_clocks *clocks);
481	int (*get_clock_by_type_with_latency)(void *handle,
482	enum amd_pp_clock_type type,
483	struct pp_clock_levels_with_latency *clocks);
484	int (*get_clock_by_type_with_voltage)(void *handle,
485	enum amd_pp_clock_type type,
486	struct pp_clock_levels_with_voltage *clocks);
487	int (*set_watermarks_for_clocks_ranges)(void *handle,
488	void *clock_ranges);
489	int (*display_clock_voltage_request)(void *handle,
490	struct pp_display_clock_request *clock);
491	int (*get_display_mode_validation_clocks)(void *handle,
492	struct amd_pp_simple_clock_info *clocks);
493	int (*notify_smu_enable_pwe)(void *handle);
494	int (*enable_mgpu_fan_boost)(void *handle);
495	int (*set_active_display_count)(void *handle, uint32_t count);
496	int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
497	int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
498	int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
499	int (*get_asic_baco_capability)(void *handle);
500	int (*get_asic_baco_state)(void *handle, int *state);
501	int (*set_asic_baco_state)(void *handle, int state);
502	int (*get_ppfeature_status)(void *handle, char *buf);
503	int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
504	int (*asic_reset_mode_2)(void *handle);
505	int (*asic_reset_enable_gfx_features)(void *handle);
506	int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
507	int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
508	ssize_t (*get_gpu_metrics)(void *handle, void **table);
509	ssize_t (*get_temp_metrics)(void *handle, enum smu_temp_metric_type type, void *table);
510	bool (*temp_metrics_is_supported)(void *handle, enum smu_temp_metric_type type);
511	ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table);
512	ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
513	int (*set_watermarks_for_clock_ranges)(void *handle,
514	struct pp_smu_wm_range_sets *ranges);
515	int (*display_disable_memory_clock_switch)(void *handle,
516	bool disable_memory_clock_switch);
517	int (*get_max_sustainable_clocks_by_dc)(void *handle,
518	struct pp_smu_nv_clock_table *max_clocks);
519	int (*get_uclk_dpm_states)(void *handle,
520	unsigned int *clock_values_in_khz,
521	unsigned int *num_states);
522	int (*get_dpm_clock_table)(void *handle,
523	struct dpm_clocks *clock_table);
524	int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
525	void (*pm_compute_clocks)(void *handle);
526	int (*notify_rlc_state)(void *handle, bool en);
527	};
528
529	struct metrics_table_header {
530	uint16_t structure_size;
531	uint8_t format_revision;
532	uint8_t content_revision;
533	};
534
535	enum amdgpu_metrics_attr_id {
536	AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HOTSPOT,
537	AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MEM,
538	AMDGPU_METRICS_ATTR_ID_TEMPERATURE_VRSOC,
539	AMDGPU_METRICS_ATTR_ID_CURR_SOCKET_POWER,
540	AMDGPU_METRICS_ATTR_ID_AVERAGE_GFX_ACTIVITY,
541	AMDGPU_METRICS_ATTR_ID_AVERAGE_UMC_ACTIVITY,
542	AMDGPU_METRICS_ATTR_ID_MEM_MAX_BANDWIDTH,
543	AMDGPU_METRICS_ATTR_ID_ENERGY_ACCUMULATOR,
544	AMDGPU_METRICS_ATTR_ID_SYSTEM_CLOCK_COUNTER,
545	AMDGPU_METRICS_ATTR_ID_ACCUMULATION_COUNTER,
546	AMDGPU_METRICS_ATTR_ID_PROCHOT_RESIDENCY_ACC,
547	AMDGPU_METRICS_ATTR_ID_PPT_RESIDENCY_ACC,
548	AMDGPU_METRICS_ATTR_ID_SOCKET_THM_RESIDENCY_ACC,
549	AMDGPU_METRICS_ATTR_ID_VR_THM_RESIDENCY_ACC,
550	AMDGPU_METRICS_ATTR_ID_HBM_THM_RESIDENCY_ACC,
551	AMDGPU_METRICS_ATTR_ID_GFXCLK_LOCK_STATUS,
552	AMDGPU_METRICS_ATTR_ID_PCIE_LINK_WIDTH,
553	AMDGPU_METRICS_ATTR_ID_PCIE_LINK_SPEED,
554	AMDGPU_METRICS_ATTR_ID_XGMI_LINK_WIDTH,
555	AMDGPU_METRICS_ATTR_ID_XGMI_LINK_SPEED,
556	AMDGPU_METRICS_ATTR_ID_GFX_ACTIVITY_ACC,
557	AMDGPU_METRICS_ATTR_ID_MEM_ACTIVITY_ACC,
558	AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_ACC,
559	AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_INST,
560	AMDGPU_METRICS_ATTR_ID_PCIE_L0_TO_RECOV_COUNT_ACC,
561	AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_COUNT_ACC,
562	AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_ROVER_COUNT_ACC,
563	AMDGPU_METRICS_ATTR_ID_PCIE_NAK_SENT_COUNT_ACC,
564	AMDGPU_METRICS_ATTR_ID_PCIE_NAK_RCVD_COUNT_ACC,
565	AMDGPU_METRICS_ATTR_ID_XGMI_READ_DATA_ACC,
566	AMDGPU_METRICS_ATTR_ID_XGMI_WRITE_DATA_ACC,
567	AMDGPU_METRICS_ATTR_ID_XGMI_LINK_STATUS,
568	AMDGPU_METRICS_ATTR_ID_FIRMWARE_TIMESTAMP,
569	AMDGPU_METRICS_ATTR_ID_CURRENT_GFXCLK,
570	AMDGPU_METRICS_ATTR_ID_CURRENT_SOCCLK,
571	AMDGPU_METRICS_ATTR_ID_CURRENT_VCLK0,
572	AMDGPU_METRICS_ATTR_ID_CURRENT_DCLK0,
573	AMDGPU_METRICS_ATTR_ID_CURRENT_UCLK,
574	AMDGPU_METRICS_ATTR_ID_NUM_PARTITION,
575	AMDGPU_METRICS_ATTR_ID_PCIE_LC_PERF_OTHER_END_RECOVERY,
576	AMDGPU_METRICS_ATTR_ID_GFX_BUSY_INST,
577	AMDGPU_METRICS_ATTR_ID_JPEG_BUSY,
578	AMDGPU_METRICS_ATTR_ID_VCN_BUSY,
579	AMDGPU_METRICS_ATTR_ID_GFX_BUSY_ACC,
580	AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_PPT_ACC,
581	AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_THM_ACC,
582	AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC,
583	AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC,
584	AMDGPU_METRICS_ATTR_ID_MAX,
585	};
586
587	enum amdgpu_metrics_attr_type {
588	AMDGPU_METRICS_TYPE_U8,
589	AMDGPU_METRICS_TYPE_S8,
590	AMDGPU_METRICS_TYPE_U16,
591	AMDGPU_METRICS_TYPE_S16,
592	AMDGPU_METRICS_TYPE_U32,
593	AMDGPU_METRICS_TYPE_S32,
594	AMDGPU_METRICS_TYPE_U64,
595	AMDGPU_METRICS_TYPE_S64,
596	AMDGPU_METRICS_TYPE_MAX,
597	};
598
599	enum amdgpu_metrics_attr_unit {
600	/* None */
601	AMDGPU_METRICS_UNIT_NONE,
602	/* MHz*/
603	AMDGPU_METRICS_UNIT_CLOCK_1,
604	/* Degree Celsius*/
605	AMDGPU_METRICS_UNIT_TEMP_1,
606	/* Watts*/
607	AMDGPU_METRICS_UNIT_POWER_1,
608	/* In nanoseconds*/
609	AMDGPU_METRICS_UNIT_TIME_1,
610	/* In 10 nanoseconds*/
611	AMDGPU_METRICS_UNIT_TIME_2,
612	/* Speed in GT/s */
613	AMDGPU_METRICS_UNIT_SPEED_1,
614	/* Speed in 0.1 GT/s */
615	AMDGPU_METRICS_UNIT_SPEED_2,
616	/* Bandwidth GB/s */
617	AMDGPU_METRICS_UNIT_BW_1,
618	/* Data in KB */
619	AMDGPU_METRICS_UNIT_DATA_1,
620	/* Percentage */
621	AMDGPU_METRICS_UNIT_PERCENT,
622	AMDGPU_METRICS_UNIT_MAX,
623	};
624
625	#define AMDGPU_METRICS_ATTR_UNIT_MASK 0xFF000000
626	#define AMDGPU_METRICS_ATTR_UNIT_SHIFT 24
627	#define AMDGPU_METRICS_ATTR_TYPE_MASK 0x00F00000
628	#define AMDGPU_METRICS_ATTR_TYPE_SHIFT 20
629	#define AMDGPU_METRICS_ATTR_ID_MASK 0x000FFC00
630	#define AMDGPU_METRICS_ATTR_ID_SHIFT 10
631	#define AMDGPU_METRICS_ATTR_INST_MASK 0x000003FF
632	#define AMDGPU_METRICS_ATTR_INST_SHIFT 0
633
634	#define AMDGPU_METRICS_ENC_ATTR(unit, type, id, inst) \
635	(((u64)(unit) << AMDGPU_METRICS_ATTR_UNIT_SHIFT) | \
636	((u64)(type) << AMDGPU_METRICS_ATTR_TYPE_SHIFT) | \
637	((u64)(id) << AMDGPU_METRICS_ATTR_ID_SHIFT) | (inst))
638
639	/*
640	* gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
641	* Use gpu_metrics_v1_1 or later instead.
642	*/
643	struct gpu_metrics_v1_0 {
644	struct metrics_table_header common_header;
645
646	/* Driver attached timestamp (in ns) */
647	uint64_t system_clock_counter;
648
649	/* Temperature */
650	uint16_t temperature_edge;
651	uint16_t temperature_hotspot;
652	uint16_t temperature_mem;
653	uint16_t temperature_vrgfx;
654	uint16_t temperature_vrsoc;
655	uint16_t temperature_vrmem;
656
657	/* Utilization */
658	uint16_t average_gfx_activity;
659	uint16_t average_umc_activity; // memory controller
660	uint16_t average_mm_activity; // UVD or VCN
661
662	/* Power/Energy */
663	uint16_t average_socket_power;
664	uint32_t energy_accumulator;
665
666	/* Average clocks */
667	uint16_t average_gfxclk_frequency;
668	uint16_t average_socclk_frequency;
669	uint16_t average_uclk_frequency;
670	uint16_t average_vclk0_frequency;
671	uint16_t average_dclk0_frequency;
672	uint16_t average_vclk1_frequency;
673	uint16_t average_dclk1_frequency;
674
675	/* Current clocks */
676	uint16_t current_gfxclk;
677	uint16_t current_socclk;
678	uint16_t current_uclk;
679	uint16_t current_vclk0;
680	uint16_t current_dclk0;
681	uint16_t current_vclk1;
682	uint16_t current_dclk1;
683
684	/* Throttle status */
685	uint32_t throttle_status;
686
687	/* Fans */
688	uint16_t current_fan_speed;
689
690	/* Link width/speed */
691	uint8_t pcie_link_width;
692	uint8_t pcie_link_speed; // in 0.1 GT/s
693	};
694
695	struct gpu_metrics_v1_1 {
696	struct metrics_table_header common_header;
697
698	/* Temperature */
699	uint16_t temperature_edge;
700	uint16_t temperature_hotspot;
701	uint16_t temperature_mem;
702	uint16_t temperature_vrgfx;
703	uint16_t temperature_vrsoc;
704	uint16_t temperature_vrmem;
705
706	/* Utilization */
707	uint16_t average_gfx_activity;
708	uint16_t average_umc_activity; // memory controller
709	uint16_t average_mm_activity; // UVD or VCN
710
711	/* Power/Energy */
712	uint16_t average_socket_power;
713	uint64_t energy_accumulator;
714
715	/* Driver attached timestamp (in ns) */
716	uint64_t system_clock_counter;
717
718	/* Average clocks */
719	uint16_t average_gfxclk_frequency;
720	uint16_t average_socclk_frequency;
721	uint16_t average_uclk_frequency;
722	uint16_t average_vclk0_frequency;
723	uint16_t average_dclk0_frequency;
724	uint16_t average_vclk1_frequency;
725	uint16_t average_dclk1_frequency;
726
727	/* Current clocks */
728	uint16_t current_gfxclk;
729	uint16_t current_socclk;
730	uint16_t current_uclk;
731	uint16_t current_vclk0;
732	uint16_t current_dclk0;
733	uint16_t current_vclk1;
734	uint16_t current_dclk1;
735
736	/* Throttle status */
737	uint32_t throttle_status;
738
739	/* Fans */
740	uint16_t current_fan_speed;
741
742	/* Link width/speed */
743	uint16_t pcie_link_width;
744	uint16_t pcie_link_speed; // in 0.1 GT/s
745
746	uint16_t padding;
747
748	uint32_t gfx_activity_acc;
749	uint32_t mem_activity_acc;
750
751	uint16_t temperature_hbm[NUM_HBM_INSTANCES];
752	};
753
754	struct gpu_metrics_v1_2 {
755	struct metrics_table_header common_header;
756
757	/* Temperature */
758	uint16_t temperature_edge;
759	uint16_t temperature_hotspot;
760	uint16_t temperature_mem;
761	uint16_t temperature_vrgfx;
762	uint16_t temperature_vrsoc;
763	uint16_t temperature_vrmem;
764
765	/* Utilization */
766	uint16_t average_gfx_activity;
767	uint16_t average_umc_activity; // memory controller
768	uint16_t average_mm_activity; // UVD or VCN
769
770	/* Power/Energy */
771	uint16_t average_socket_power;
772	uint64_t energy_accumulator;
773
774	/* Driver attached timestamp (in ns) */
775	uint64_t system_clock_counter;
776
777	/* Average clocks */
778	uint16_t average_gfxclk_frequency;
779	uint16_t average_socclk_frequency;
780	uint16_t average_uclk_frequency;
781	uint16_t average_vclk0_frequency;
782	uint16_t average_dclk0_frequency;
783	uint16_t average_vclk1_frequency;
784	uint16_t average_dclk1_frequency;
785
786	/* Current clocks */
787	uint16_t current_gfxclk;
788	uint16_t current_socclk;
789	uint16_t current_uclk;
790	uint16_t current_vclk0;
791	uint16_t current_dclk0;
792	uint16_t current_vclk1;
793	uint16_t current_dclk1;
794
795	/* Throttle status (ASIC dependent) */
796	uint32_t throttle_status;
797
798	/* Fans */
799	uint16_t current_fan_speed;
800
801	/* Link width/speed */
802	uint16_t pcie_link_width;
803	uint16_t pcie_link_speed; // in 0.1 GT/s
804
805	uint16_t padding;
806
807	uint32_t gfx_activity_acc;
808	uint32_t mem_activity_acc;
809
810	uint16_t temperature_hbm[NUM_HBM_INSTANCES];
811
812	/* PMFW attached timestamp (10ns resolution) */
813	uint64_t firmware_timestamp;
814	};
815
816	struct gpu_metrics_v1_3 {
817	struct metrics_table_header common_header;
818
819	/* Temperature */
820	uint16_t temperature_edge;
821	uint16_t temperature_hotspot;
822	uint16_t temperature_mem;
823	uint16_t temperature_vrgfx;
824	uint16_t temperature_vrsoc;
825	uint16_t temperature_vrmem;
826
827	/* Utilization */
828	uint16_t average_gfx_activity;
829	uint16_t average_umc_activity; // memory controller
830	uint16_t average_mm_activity; // UVD or VCN
831
832	/* Power/Energy */
833	uint16_t average_socket_power;
834	uint64_t energy_accumulator;
835
836	/* Driver attached timestamp (in ns) */
837	uint64_t system_clock_counter;
838
839	/* Average clocks */
840	uint16_t average_gfxclk_frequency;
841	uint16_t average_socclk_frequency;
842	uint16_t average_uclk_frequency;
843	uint16_t average_vclk0_frequency;
844	uint16_t average_dclk0_frequency;
845	uint16_t average_vclk1_frequency;
846	uint16_t average_dclk1_frequency;
847
848	/* Current clocks */
849	uint16_t current_gfxclk;
850	uint16_t current_socclk;
851	uint16_t current_uclk;
852	uint16_t current_vclk0;
853	uint16_t current_dclk0;
854	uint16_t current_vclk1;
855	uint16_t current_dclk1;
856
857	/* Throttle status */
858	uint32_t throttle_status;
859
860	/* Fans */
861	uint16_t current_fan_speed;
862
863	/* Link width/speed */
864	uint16_t pcie_link_width;
865	uint16_t pcie_link_speed; // in 0.1 GT/s
866
867	uint16_t padding;
868
869	uint32_t gfx_activity_acc;
870	uint32_t mem_activity_acc;
871
872	uint16_t temperature_hbm[NUM_HBM_INSTANCES];
873
874	/* PMFW attached timestamp (10ns resolution) */
875	uint64_t firmware_timestamp;
876
877	/* Voltage (mV) */
878	uint16_t voltage_soc;
879	uint16_t voltage_gfx;
880	uint16_t voltage_mem;
881
882	uint16_t padding1;
883
884	/* Throttle status (ASIC independent) */
885	uint64_t indep_throttle_status;
886	};
887
888	struct gpu_metrics_v1_4 {
889	struct metrics_table_header common_header;
890
891	/* Temperature (Celsius) */
892	uint16_t temperature_hotspot;
893	uint16_t temperature_mem;
894	uint16_t temperature_vrsoc;
895
896	/* Power (Watts) */
897	uint16_t curr_socket_power;
898
899	/* Utilization (%) */
900	uint16_t average_gfx_activity;
901	uint16_t average_umc_activity; // memory controller
902	uint16_t vcn_activity[NUM_VCN];
903
904	/* Energy (15.259uJ (2^-16) units) */
905	uint64_t energy_accumulator;
906
907	/* Driver attached timestamp (in ns) */
908	uint64_t system_clock_counter;
909
910	/* Throttle status */
911	uint32_t throttle_status;
912
913	/* Clock Lock Status. Each bit corresponds to clock instance */
914	uint32_t gfxclk_lock_status;
915
916	/* Link width (number of lanes) and speed (in 0.1 GT/s) */
917	uint16_t pcie_link_width;
918	uint16_t pcie_link_speed;
919
920	/* XGMI bus width and bitrate (in Gbps) */
921	uint16_t xgmi_link_width;
922	uint16_t xgmi_link_speed;
923
924	/* Utilization Accumulated (%) */
925	uint32_t gfx_activity_acc;
926	uint32_t mem_activity_acc;
927
928	/*PCIE accumulated bandwidth (GB/sec) */
929	uint64_t pcie_bandwidth_acc;
930
931	/*PCIE instantaneous bandwidth (GB/sec) */
932	uint64_t pcie_bandwidth_inst;
933
934	/* PCIE L0 to recovery state transition accumulated count */
935	uint64_t pcie_l0_to_recov_count_acc;
936
937	/* PCIE replay accumulated count */
938	uint64_t pcie_replay_count_acc;
939
940	/* PCIE replay rollover accumulated count */
941	uint64_t pcie_replay_rover_count_acc;
942
943	/* XGMI accumulated data transfer size(KiloBytes) */
944	uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
945	uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
946
947	/* PMFW attached timestamp (10ns resolution) */
948	uint64_t firmware_timestamp;
949
950	/* Current clocks (Mhz) */
951	uint16_t current_gfxclk[MAX_GFX_CLKS];
952	uint16_t current_socclk[MAX_CLKS];
953	uint16_t current_vclk0[MAX_CLKS];
954	uint16_t current_dclk0[MAX_CLKS];
955	uint16_t current_uclk;
956
957	uint16_t padding;
958	};
959
960	struct gpu_metrics_v1_5 {
961	struct metrics_table_header common_header;
962
963	/* Temperature (Celsius) */
964	uint16_t temperature_hotspot;
965	uint16_t temperature_mem;
966	uint16_t temperature_vrsoc;
967
968	/* Power (Watts) */
969	uint16_t curr_socket_power;
970
971	/* Utilization (%) */
972	uint16_t average_gfx_activity;
973	uint16_t average_umc_activity; // memory controller
974	uint16_t vcn_activity[NUM_VCN];
975	uint16_t jpeg_activity[NUM_JPEG_ENG];
976
977	/* Energy (15.259uJ (2^-16) units) */
978	uint64_t energy_accumulator;
979
980	/* Driver attached timestamp (in ns) */
981	uint64_t system_clock_counter;
982
983	/* Throttle status */
984	uint32_t throttle_status;
985
986	/* Clock Lock Status. Each bit corresponds to clock instance */
987	uint32_t gfxclk_lock_status;
988
989	/* Link width (number of lanes) and speed (in 0.1 GT/s) */
990	uint16_t pcie_link_width;
991	uint16_t pcie_link_speed;
992
993	/* XGMI bus width and bitrate (in Gbps) */
994	uint16_t xgmi_link_width;
995	uint16_t xgmi_link_speed;
996
997	/* Utilization Accumulated (%) */
998	uint32_t gfx_activity_acc;
999	uint32_t mem_activity_acc;
1000
1001	/*PCIE accumulated bandwidth (GB/sec) */
1002	uint64_t pcie_bandwidth_acc;
1003
1004	/*PCIE instantaneous bandwidth (GB/sec) */
1005	uint64_t pcie_bandwidth_inst;
1006
1007	/* PCIE L0 to recovery state transition accumulated count */
1008	uint64_t pcie_l0_to_recov_count_acc;
1009
1010	/* PCIE replay accumulated count */
1011	uint64_t pcie_replay_count_acc;
1012
1013	/* PCIE replay rollover accumulated count */
1014	uint64_t pcie_replay_rover_count_acc;
1015
1016	/* PCIE NAK sent accumulated count */
1017	uint32_t pcie_nak_sent_count_acc;
1018
1019	/* PCIE NAK received accumulated count */
1020	uint32_t pcie_nak_rcvd_count_acc;
1021
1022	/* XGMI accumulated data transfer size(KiloBytes) */
1023	uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1024	uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1025
1026	/* PMFW attached timestamp (10ns resolution) */
1027	uint64_t firmware_timestamp;
1028
1029	/* Current clocks (Mhz) */
1030	uint16_t current_gfxclk[MAX_GFX_CLKS];
1031	uint16_t current_socclk[MAX_CLKS];
1032	uint16_t current_vclk0[MAX_CLKS];
1033	uint16_t current_dclk0[MAX_CLKS];
1034	uint16_t current_uclk;
1035
1036	uint16_t padding;
1037	};
1038
1039	struct gpu_metrics_v1_6 {
1040	struct metrics_table_header common_header;
1041
1042	/* Temperature (Celsius) */
1043	uint16_t temperature_hotspot;
1044	uint16_t temperature_mem;
1045	uint16_t temperature_vrsoc;
1046
1047	/* Power (Watts) */
1048	uint16_t curr_socket_power;
1049
1050	/* Utilization (%) */
1051	uint16_t average_gfx_activity;
1052	uint16_t average_umc_activity; // memory controller
1053
1054	/* Energy (15.259uJ (2^-16) units) */
1055	uint64_t energy_accumulator;
1056
1057	/* Driver attached timestamp (in ns) */
1058	uint64_t system_clock_counter;
1059
1060	/* Accumulation cycle counter */
1061	uint32_t accumulation_counter;
1062
1063	/* Accumulated throttler residencies */
1064	uint32_t prochot_residency_acc;
1065	uint32_t ppt_residency_acc;
1066	uint32_t socket_thm_residency_acc;
1067	uint32_t vr_thm_residency_acc;
1068	uint32_t hbm_thm_residency_acc;
1069
1070	/* Clock Lock Status. Each bit corresponds to clock instance */
1071	uint32_t gfxclk_lock_status;
1072
1073	/* Link width (number of lanes) and speed (in 0.1 GT/s) */
1074	uint16_t pcie_link_width;
1075	uint16_t pcie_link_speed;
1076
1077	/* XGMI bus width and bitrate (in Gbps) */
1078	uint16_t xgmi_link_width;
1079	uint16_t xgmi_link_speed;
1080
1081	/* Utilization Accumulated (%) */
1082	uint32_t gfx_activity_acc;
1083	uint32_t mem_activity_acc;
1084
1085	/*PCIE accumulated bandwidth (GB/sec) */
1086	uint64_t pcie_bandwidth_acc;
1087
1088	/*PCIE instantaneous bandwidth (GB/sec) */
1089	uint64_t pcie_bandwidth_inst;
1090
1091	/* PCIE L0 to recovery state transition accumulated count */
1092	uint64_t pcie_l0_to_recov_count_acc;
1093
1094	/* PCIE replay accumulated count */
1095	uint64_t pcie_replay_count_acc;
1096
1097	/* PCIE replay rollover accumulated count */
1098	uint64_t pcie_replay_rover_count_acc;
1099
1100	/* PCIE NAK sent accumulated count */
1101	uint32_t pcie_nak_sent_count_acc;
1102
1103	/* PCIE NAK received accumulated count */
1104	uint32_t pcie_nak_rcvd_count_acc;
1105
1106	/* XGMI accumulated data transfer size(KiloBytes) */
1107	uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1108	uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1109
1110	/* PMFW attached timestamp (10ns resolution) */
1111	uint64_t firmware_timestamp;
1112
1113	/* Current clocks (Mhz) */
1114	uint16_t current_gfxclk[MAX_GFX_CLKS];
1115	uint16_t current_socclk[MAX_CLKS];
1116	uint16_t current_vclk0[MAX_CLKS];
1117	uint16_t current_dclk0[MAX_CLKS];
1118	uint16_t current_uclk;
1119
1120	/* Number of current partition */
1121	uint16_t num_partition;
1122
1123	/* XCP metrics stats */
1124	struct amdgpu_xcp_metrics xcp_stats[NUM_XCP];
1125
1126	/* PCIE other end recovery counter */
1127	uint32_t pcie_lc_perf_other_end_recovery;
1128	};
1129
1130	struct gpu_metrics_v1_7 {
1131	struct metrics_table_header common_header;
1132
1133	/* Temperature (Celsius) */
1134	uint16_t temperature_hotspot;
1135	uint16_t temperature_mem;
1136	uint16_t temperature_vrsoc;
1137
1138	/* Power (Watts) */
1139	uint16_t curr_socket_power;
1140
1141	/* Utilization (%) */
1142	uint16_t average_gfx_activity;
1143	uint16_t average_umc_activity; // memory controller
1144
1145	/* VRAM max bandwidthi (in GB/sec) at max memory clock */
1146	uint64_t mem_max_bandwidth;
1147
1148	/* Energy (15.259uJ (2^-16) units) */
1149	uint64_t energy_accumulator;
1150
1151	/* Driver attached timestamp (in ns) */
1152	uint64_t system_clock_counter;
1153
1154	/* Accumulation cycle counter */
1155	uint32_t accumulation_counter;
1156
1157	/* Accumulated throttler residencies */
1158	uint32_t prochot_residency_acc;
1159	uint32_t ppt_residency_acc;
1160	uint32_t socket_thm_residency_acc;
1161	uint32_t vr_thm_residency_acc;
1162	uint32_t hbm_thm_residency_acc;
1163
1164	/* Clock Lock Status. Each bit corresponds to clock instance */
1165	uint32_t gfxclk_lock_status;
1166
1167	/* Link width (number of lanes) and speed (in 0.1 GT/s) */
1168	uint16_t pcie_link_width;
1169	uint16_t pcie_link_speed;
1170
1171	/* XGMI bus width and bitrate (in Gbps) */
1172	uint16_t xgmi_link_width;
1173	uint16_t xgmi_link_speed;
1174
1175	/* Utilization Accumulated (%) */
1176	uint32_t gfx_activity_acc;
1177	uint32_t mem_activity_acc;
1178
1179	/*PCIE accumulated bandwidth (GB/sec) */
1180	uint64_t pcie_bandwidth_acc;
1181
1182	/*PCIE instantaneous bandwidth (GB/sec) */
1183	uint64_t pcie_bandwidth_inst;
1184
1185	/* PCIE L0 to recovery state transition accumulated count */
1186	uint64_t pcie_l0_to_recov_count_acc;
1187
1188	/* PCIE replay accumulated count */
1189	uint64_t pcie_replay_count_acc;
1190
1191	/* PCIE replay rollover accumulated count */
1192	uint64_t pcie_replay_rover_count_acc;
1193
1194	/* PCIE NAK sent accumulated count */
1195	uint32_t pcie_nak_sent_count_acc;
1196
1197	/* PCIE NAK received accumulated count */
1198	uint32_t pcie_nak_rcvd_count_acc;
1199
1200	/* XGMI accumulated data transfer size(KiloBytes) */
1201	uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1202	uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1203
1204	/* XGMI link status(active/inactive) */
1205	uint16_t xgmi_link_status[NUM_XGMI_LINKS];
1206
1207	uint16_t padding;
1208
1209	/* PMFW attached timestamp (10ns resolution) */
1210	uint64_t firmware_timestamp;
1211
1212	/* Current clocks (Mhz) */
1213	uint16_t current_gfxclk[MAX_GFX_CLKS];
1214	uint16_t current_socclk[MAX_CLKS];
1215	uint16_t current_vclk0[MAX_CLKS];
1216	uint16_t current_dclk0[MAX_CLKS];
1217	uint16_t current_uclk;
1218
1219	/* Number of current partition */
1220	uint16_t num_partition;
1221
1222	/* XCP metrics stats */
1223	struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP];
1224
1225	/* PCIE other end recovery counter */
1226	uint32_t pcie_lc_perf_other_end_recovery;
1227	};
1228
1229	struct gpu_metrics_v1_8 {
1230	struct metrics_table_header common_header;
1231
1232	/* Temperature (Celsius) */
1233	uint16_t temperature_hotspot;
1234	uint16_t temperature_mem;
1235	uint16_t temperature_vrsoc;
1236
1237	/* Power (Watts) */
1238	uint16_t curr_socket_power;
1239
1240	/* Utilization (%) */
1241	uint16_t average_gfx_activity;
1242	uint16_t average_umc_activity; // memory controller
1243
1244	/* VRAM max bandwidthi (in GB/sec) at max memory clock */
1245	uint64_t mem_max_bandwidth;
1246
1247	/* Energy (15.259uJ (2^-16) units) */
1248	uint64_t energy_accumulator;
1249
1250	/* Driver attached timestamp (in ns) */
1251	uint64_t system_clock_counter;
1252
1253	/* Accumulation cycle counter */
1254	uint32_t accumulation_counter;
1255
1256	/* Accumulated throttler residencies */
1257	uint32_t prochot_residency_acc;
1258	uint32_t ppt_residency_acc;
1259	uint32_t socket_thm_residency_acc;
1260	uint32_t vr_thm_residency_acc;
1261	uint32_t hbm_thm_residency_acc;
1262
1263	/* Clock Lock Status. Each bit corresponds to clock instance */
1264	uint32_t gfxclk_lock_status;
1265
1266	/* Link width (number of lanes) and speed (in 0.1 GT/s) */
1267	uint16_t pcie_link_width;
1268	uint16_t pcie_link_speed;
1269
1270	/* XGMI bus width and bitrate (in Gbps) */
1271	uint16_t xgmi_link_width;
1272	uint16_t xgmi_link_speed;
1273
1274	/* Utilization Accumulated (%) */
1275	uint32_t gfx_activity_acc;
1276	uint32_t mem_activity_acc;
1277
1278	/*PCIE accumulated bandwidth (GB/sec) */
1279	uint64_t pcie_bandwidth_acc;
1280
1281	/*PCIE instantaneous bandwidth (GB/sec) */
1282	uint64_t pcie_bandwidth_inst;
1283
1284	/* PCIE L0 to recovery state transition accumulated count */
1285	uint64_t pcie_l0_to_recov_count_acc;
1286
1287	/* PCIE replay accumulated count */
1288	uint64_t pcie_replay_count_acc;
1289
1290	/* PCIE replay rollover accumulated count */
1291	uint64_t pcie_replay_rover_count_acc;
1292
1293	/* PCIE NAK sent accumulated count */
1294	uint32_t pcie_nak_sent_count_acc;
1295
1296	/* PCIE NAK received accumulated count */
1297	uint32_t pcie_nak_rcvd_count_acc;
1298
1299	/* XGMI accumulated data transfer size(KiloBytes) */
1300	uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1301	uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1302
1303	/* XGMI link status(active/inactive) */
1304	uint16_t xgmi_link_status[NUM_XGMI_LINKS];
1305
1306	uint16_t padding;
1307
1308	/* PMFW attached timestamp (10ns resolution) */
1309	uint64_t firmware_timestamp;
1310
1311	/* Current clocks (Mhz) */
1312	uint16_t current_gfxclk[MAX_GFX_CLKS];
1313	uint16_t current_socclk[MAX_CLKS];
1314	uint16_t current_vclk0[MAX_CLKS];
1315	uint16_t current_dclk0[MAX_CLKS];
1316	uint16_t current_uclk;
1317
1318	/* Number of current partition */
1319	uint16_t num_partition;
1320
1321	/* XCP metrics stats */
1322	struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP];
1323
1324	/* PCIE other end recovery counter */
1325	uint32_t pcie_lc_perf_other_end_recovery;
1326	};
1327
1328	struct gpu_metrics_attr {
1329	/* Field type encoded with AMDGPU_METRICS_ENC_ATTR */
1330	uint64_t attr_encoding;
1331	/* Attribute value, depends on attr_encoding */
1332	void *attr_value;
1333	};
1334
1335	struct gpu_metrics_v1_9 {
1336	struct metrics_table_header common_header;
1337	int attr_count;
1338	struct gpu_metrics_attr metrics_attrs[];
1339	};
1340
1341	/*
1342	* gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
1343	* Use gpu_metrics_v2_1 or later instead.
1344	*/
1345	struct gpu_metrics_v2_0 {
1346	struct metrics_table_header common_header;
1347
1348	/* Driver attached timestamp (in ns) */
1349	uint64_t system_clock_counter;
1350
1351	/* Temperature */
1352	uint16_t temperature_gfx; // gfx temperature on APUs
1353	uint16_t temperature_soc; // soc temperature on APUs
1354	uint16_t temperature_core[8]; // CPU core temperature on APUs
1355	uint16_t temperature_l3[2];
1356
1357	/* Utilization */
1358	uint16_t average_gfx_activity;
1359	uint16_t average_mm_activity; // UVD or VCN
1360
1361	/* Power/Energy */
1362	uint16_t average_socket_power; // dGPU + APU power on A + A platform
1363	uint16_t average_cpu_power;
1364	uint16_t average_soc_power;
1365	uint16_t average_gfx_power;
1366	uint16_t average_core_power[8]; // CPU core power on APUs
1367
1368	/* Average clocks */
1369	uint16_t average_gfxclk_frequency;
1370	uint16_t average_socclk_frequency;
1371	uint16_t average_uclk_frequency;
1372	uint16_t average_fclk_frequency;
1373	uint16_t average_vclk_frequency;
1374	uint16_t average_dclk_frequency;
1375
1376	/* Current clocks */
1377	uint16_t current_gfxclk;
1378	uint16_t current_socclk;
1379	uint16_t current_uclk;
1380	uint16_t current_fclk;
1381	uint16_t current_vclk;
1382	uint16_t current_dclk;
1383	uint16_t current_coreclk[8]; // CPU core clocks
1384	uint16_t current_l3clk[2];
1385
1386	/* Throttle status */
1387	uint32_t throttle_status;
1388
1389	/* Fans */
1390	uint16_t fan_pwm;
1391
1392	uint16_t padding;
1393	};
1394
1395	struct gpu_metrics_v2_1 {
1396	struct metrics_table_header common_header;
1397
1398	/* Temperature */
1399	uint16_t temperature_gfx; // gfx temperature on APUs
1400	uint16_t temperature_soc; // soc temperature on APUs
1401	uint16_t temperature_core[8]; // CPU core temperature on APUs
1402	uint16_t temperature_l3[2];
1403
1404	/* Utilization */
1405	uint16_t average_gfx_activity;
1406	uint16_t average_mm_activity; // UVD or VCN
1407
1408	/* Driver attached timestamp (in ns) */
1409	uint64_t system_clock_counter;
1410
1411	/* Power/Energy */
1412	uint16_t average_socket_power; // dGPU + APU power on A + A platform
1413	uint16_t average_cpu_power;
1414	uint16_t average_soc_power;
1415	uint16_t average_gfx_power;
1416	uint16_t average_core_power[8]; // CPU core power on APUs
1417
1418	/* Average clocks */
1419	uint16_t average_gfxclk_frequency;
1420	uint16_t average_socclk_frequency;
1421	uint16_t average_uclk_frequency;
1422	uint16_t average_fclk_frequency;
1423	uint16_t average_vclk_frequency;
1424	uint16_t average_dclk_frequency;
1425
1426	/* Current clocks */
1427	uint16_t current_gfxclk;
1428	uint16_t current_socclk;
1429	uint16_t current_uclk;
1430	uint16_t current_fclk;
1431	uint16_t current_vclk;
1432	uint16_t current_dclk;
1433	uint16_t current_coreclk[8]; // CPU core clocks
1434	uint16_t current_l3clk[2];
1435
1436	/* Throttle status */
1437	uint32_t throttle_status;
1438
1439	/* Fans */
1440	uint16_t fan_pwm;
1441
1442	uint16_t padding[3];
1443	};
1444
1445	struct gpu_metrics_v2_2 {
1446	struct metrics_table_header common_header;
1447
1448	/* Temperature */
1449	uint16_t temperature_gfx; // gfx temperature on APUs
1450	uint16_t temperature_soc; // soc temperature on APUs
1451	uint16_t temperature_core[8]; // CPU core temperature on APUs
1452	uint16_t temperature_l3[2];
1453
1454	/* Utilization */
1455	uint16_t average_gfx_activity;
1456	uint16_t average_mm_activity; // UVD or VCN
1457
1458	/* Driver attached timestamp (in ns) */
1459	uint64_t system_clock_counter;
1460
1461	/* Power/Energy */
1462	uint16_t average_socket_power; // dGPU + APU power on A + A platform
1463	uint16_t average_cpu_power;
1464	uint16_t average_soc_power;
1465	uint16_t average_gfx_power;
1466	uint16_t average_core_power[8]; // CPU core power on APUs
1467
1468	/* Average clocks */
1469	uint16_t average_gfxclk_frequency;
1470	uint16_t average_socclk_frequency;
1471	uint16_t average_uclk_frequency;
1472	uint16_t average_fclk_frequency;
1473	uint16_t average_vclk_frequency;
1474	uint16_t average_dclk_frequency;
1475
1476	/* Current clocks */
1477	uint16_t current_gfxclk;
1478	uint16_t current_socclk;
1479	uint16_t current_uclk;
1480	uint16_t current_fclk;
1481	uint16_t current_vclk;
1482	uint16_t current_dclk;
1483	uint16_t current_coreclk[8]; // CPU core clocks
1484	uint16_t current_l3clk[2];
1485
1486	/* Throttle status (ASIC dependent) */
1487	uint32_t throttle_status;
1488
1489	/* Fans */
1490	uint16_t fan_pwm;
1491
1492	uint16_t padding[3];
1493
1494	/* Throttle status (ASIC independent) */
1495	uint64_t indep_throttle_status;
1496	};
1497
1498	struct gpu_metrics_v2_3 {
1499	struct metrics_table_header common_header;
1500
1501	/* Temperature */
1502	uint16_t temperature_gfx; // gfx temperature on APUs
1503	uint16_t temperature_soc; // soc temperature on APUs
1504	uint16_t temperature_core[8]; // CPU core temperature on APUs
1505	uint16_t temperature_l3[2];
1506
1507	/* Utilization */
1508	uint16_t average_gfx_activity;
1509	uint16_t average_mm_activity; // UVD or VCN
1510
1511	/* Driver attached timestamp (in ns) */
1512	uint64_t system_clock_counter;
1513
1514	/* Power/Energy */
1515	uint16_t average_socket_power; // dGPU + APU power on A + A platform
1516	uint16_t average_cpu_power;
1517	uint16_t average_soc_power;
1518	uint16_t average_gfx_power;
1519	uint16_t average_core_power[8]; // CPU core power on APUs
1520
1521	/* Average clocks */
1522	uint16_t average_gfxclk_frequency;
1523	uint16_t average_socclk_frequency;
1524	uint16_t average_uclk_frequency;
1525	uint16_t average_fclk_frequency;
1526	uint16_t average_vclk_frequency;
1527	uint16_t average_dclk_frequency;
1528
1529	/* Current clocks */
1530	uint16_t current_gfxclk;
1531	uint16_t current_socclk;
1532	uint16_t current_uclk;
1533	uint16_t current_fclk;
1534	uint16_t current_vclk;
1535	uint16_t current_dclk;
1536	uint16_t current_coreclk[8]; // CPU core clocks
1537	uint16_t current_l3clk[2];
1538
1539	/* Throttle status (ASIC dependent) */
1540	uint32_t throttle_status;
1541
1542	/* Fans */
1543	uint16_t fan_pwm;
1544
1545	uint16_t padding[3];
1546
1547	/* Throttle status (ASIC independent) */
1548	uint64_t indep_throttle_status;
1549
1550	/* Average Temperature */
1551	uint16_t average_temperature_gfx; // average gfx temperature on APUs
1552	uint16_t average_temperature_soc; // average soc temperature on APUs
1553	uint16_t average_temperature_core[8]; // average CPU core temperature on APUs
1554	uint16_t average_temperature_l3[2];
1555	};
1556
1557	struct gpu_metrics_v2_4 {
1558	struct metrics_table_header common_header;
1559
1560	/* Temperature (unit: centi-Celsius) */
1561	uint16_t temperature_gfx;
1562	uint16_t temperature_soc;
1563	uint16_t temperature_core[8];
1564	uint16_t temperature_l3[2];
1565
1566	/* Utilization (unit: centi) */
1567	uint16_t average_gfx_activity;
1568	uint16_t average_mm_activity;
1569
1570	/* Driver attached timestamp (in ns) */
1571	uint64_t system_clock_counter;
1572
1573	/* Power/Energy (unit: mW) */
1574	uint16_t average_socket_power;
1575	uint16_t average_cpu_power;
1576	uint16_t average_soc_power;
1577	uint16_t average_gfx_power;
1578	uint16_t average_core_power[8];
1579
1580	/* Average clocks (unit: MHz) */
1581	uint16_t average_gfxclk_frequency;
1582	uint16_t average_socclk_frequency;
1583	uint16_t average_uclk_frequency;
1584	uint16_t average_fclk_frequency;
1585	uint16_t average_vclk_frequency;
1586	uint16_t average_dclk_frequency;
1587
1588	/* Current clocks (unit: MHz) */
1589	uint16_t current_gfxclk;
1590	uint16_t current_socclk;
1591	uint16_t current_uclk;
1592	uint16_t current_fclk;
1593	uint16_t current_vclk;
1594	uint16_t current_dclk;
1595	uint16_t current_coreclk[8];
1596	uint16_t current_l3clk[2];
1597
1598	/* Throttle status (ASIC dependent) */
1599	uint32_t throttle_status;
1600
1601	/* Fans */
1602	uint16_t fan_pwm;
1603
1604	uint16_t padding[3];
1605
1606	/* Throttle status (ASIC independent) */
1607	uint64_t indep_throttle_status;
1608
1609	/* Average Temperature (unit: centi-Celsius) */
1610	uint16_t average_temperature_gfx;
1611	uint16_t average_temperature_soc;
1612	uint16_t average_temperature_core[8];
1613	uint16_t average_temperature_l3[2];
1614
1615	/* Power/Voltage (unit: mV) */
1616	uint16_t average_cpu_voltage;
1617	uint16_t average_soc_voltage;
1618	uint16_t average_gfx_voltage;
1619
1620	/* Power/Current (unit: mA) */
1621	uint16_t average_cpu_current;
1622	uint16_t average_soc_current;
1623	uint16_t average_gfx_current;
1624	};
1625
1626	struct gpu_metrics_v3_0 {
1627	struct metrics_table_header common_header;
1628
1629	/* Temperature */
1630	/* gfx temperature on APUs */
1631	uint16_t temperature_gfx;
1632	/* soc temperature on APUs */
1633	uint16_t temperature_soc;
1634	/* CPU core temperature on APUs */
1635	uint16_t temperature_core[16];
1636	/* skin temperature on APUs */
1637	uint16_t temperature_skin;
1638
1639	/* Utilization */
1640	/* time filtered GFX busy % [0-100] */
1641	uint16_t average_gfx_activity;
1642	/* time filtered VCN busy % [0-100] */
1643	uint16_t average_vcn_activity;
1644	/* time filtered IPU per-column busy % [0-100] */
1645	uint16_t average_ipu_activity[8];
1646	/* time filtered per-core C0 residency % [0-100]*/
1647	uint16_t average_core_c0_activity[16];
1648	/* time filtered DRAM read bandwidth [MB/sec] */
1649	uint16_t average_dram_reads;
1650	/* time filtered DRAM write bandwidth [MB/sec] */
1651	uint16_t average_dram_writes;
1652	/* time filtered IPU read bandwidth [MB/sec] */
1653	uint16_t average_ipu_reads;
1654	/* time filtered IPU write bandwidth [MB/sec] */
1655	uint16_t average_ipu_writes;
1656
1657	/* Driver attached timestamp (in ns) */
1658	uint64_t system_clock_counter;
1659
1660	/* Power/Energy */
1661	/* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1662	uint32_t average_socket_power;
1663	/* time filtered IPU power [mW] */
1664	uint16_t average_ipu_power;
1665	/* time filtered APU power [mW] */
1666	uint32_t average_apu_power;
1667	/* time filtered GFX power [mW] */
1668	uint32_t average_gfx_power;
1669	/* time filtered dGPU power [mW] */
1670	uint32_t average_dgpu_power;
1671	/* time filtered sum of core power across all cores in the socket [mW] */
1672	uint32_t average_all_core_power;
1673	/* calculated core power [mW] */
1674	uint16_t average_core_power[16];
1675	/* time filtered total system power [mW] */
1676	uint16_t average_sys_power;
1677	/* maximum IRM defined STAPM power limit [mW] */
1678	uint16_t stapm_power_limit;
1679	/* time filtered STAPM power limit [mW] */
1680	uint16_t current_stapm_power_limit;
1681
1682	/* time filtered clocks [MHz] */
1683	uint16_t average_gfxclk_frequency;
1684	uint16_t average_socclk_frequency;
1685	uint16_t average_vpeclk_frequency;
1686	uint16_t average_ipuclk_frequency;
1687	uint16_t average_fclk_frequency;
1688	uint16_t average_vclk_frequency;
1689	uint16_t average_uclk_frequency;
1690	uint16_t average_mpipu_frequency;
1691
1692	/* Current clocks */
1693	/* target core frequency [MHz] */
1694	uint16_t current_coreclk[16];
1695	/* CCLK frequency limit enforced on classic cores [MHz] */
1696	uint16_t current_core_maxfreq;
1697	/* GFXCLK frequency limit enforced on GFX [MHz] */
1698	uint16_t current_gfx_maxfreq;
1699
1700	/* Throttle Residency (ASIC dependent) */
1701	uint32_t throttle_residency_prochot;
1702	uint32_t throttle_residency_spl;
1703	uint32_t throttle_residency_fppt;
1704	uint32_t throttle_residency_sppt;
1705	uint32_t throttle_residency_thm_core;
1706	uint32_t throttle_residency_thm_gfx;
1707	uint32_t throttle_residency_thm_soc;
1708
1709	/* Metrics table alpha filter time constant [us] */
1710	uint32_t time_filter_alphavalue;
1711	};
1712
1713	struct amdgpu_pmmetrics_header {
1714	uint16_t structure_size;
1715	uint16_t pad;
1716	uint32_t mp1_ip_discovery_version;
1717	uint32_t pmfw_version;
1718	uint32_t pmmetrics_version;
1719	};
1720
1721	struct amdgpu_pm_metrics {
1722	struct amdgpu_pmmetrics_header common_header;
1723
1724	uint8_t data[];
1725	};
1726
1727	enum amdgpu_vr_temp {
1728	AMDGPU_VDDCR_VDD0_TEMP,
1729	AMDGPU_VDDCR_VDD1_TEMP,
1730	AMDGPU_VDDCR_VDD2_TEMP,
1731	AMDGPU_VDDCR_VDD3_TEMP,
1732	AMDGPU_VDDCR_SOC_A_TEMP,
1733	AMDGPU_VDDCR_SOC_C_TEMP,
1734	AMDGPU_VDDCR_SOCIO_A_TEMP,
1735	AMDGPU_VDDCR_SOCIO_C_TEMP,
1736	AMDGPU_VDD_085_HBM_TEMP,
1737	AMDGPU_VDDCR_11_HBM_B_TEMP,
1738	AMDGPU_VDDCR_11_HBM_D_TEMP,
1739	AMDGPU_VDD_USR_TEMP,
1740	AMDGPU_VDDIO_11_E32_TEMP,
1741	AMDGPU_VR_MAX_TEMP_ENTRIES,
1742	};
1743
1744	enum amdgpu_system_temp {
1745	AMDGPU_UBB_FPGA_TEMP,
1746	AMDGPU_UBB_FRONT_TEMP,
1747	AMDGPU_UBB_BACK_TEMP,
1748	AMDGPU_UBB_OAM7_TEMP,
1749	AMDGPU_UBB_IBC_TEMP,
1750	AMDGPU_UBB_UFPGA_TEMP,
1751	AMDGPU_UBB_OAM1_TEMP,
1752	AMDGPU_OAM_0_1_HSC_TEMP,
1753	AMDGPU_OAM_2_3_HSC_TEMP,
1754	AMDGPU_OAM_4_5_HSC_TEMP,
1755	AMDGPU_OAM_6_7_HSC_TEMP,
1756	AMDGPU_UBB_FPGA_0V72_VR_TEMP,
1757	AMDGPU_UBB_FPGA_3V3_VR_TEMP,
1758	AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP,
1759	AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP,
1760	AMDGPU_RETIMER_0_1_0V9_VR_TEMP,
1761	AMDGPU_RETIMER_4_5_0V9_VR_TEMP,
1762	AMDGPU_RETIMER_2_3_0V9_VR_TEMP,
1763	AMDGPU_RETIMER_6_7_0V9_VR_TEMP,
1764	AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP,
1765	AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP,
1766	AMDGPU_IBC_HSC_TEMP,
1767	AMDGPU_IBC_TEMP,
1768	AMDGPU_SYSTEM_MAX_TEMP_ENTRIES = 32,
1769	};
1770
1771	enum amdgpu_node_temp {
1772	AMDGPU_RETIMER_X_TEMP,
1773	AMDGPU_OAM_X_IBC_TEMP,
1774	AMDGPU_OAM_X_IBC_2_TEMP,
1775	AMDGPU_OAM_X_VDD18_VR_TEMP,
1776	AMDGPU_OAM_X_04_HBM_B_VR_TEMP,
1777	AMDGPU_OAM_X_04_HBM_D_VR_TEMP,
1778	AMDGPU_NODE_MAX_TEMP_ENTRIES = 12,
1779	};
1780
1781	struct amdgpu_gpuboard_temp_metrics_v1_0 {
1782	struct metrics_table_header common_header;
1783	uint16_t label_version;
1784	uint16_t node_id;
1785	uint64_t accumulation_counter;
1786	/* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */
1787	uint32_t node_temp[AMDGPU_NODE_MAX_TEMP_ENTRIES];
1788	uint32_t vr_temp[AMDGPU_VR_MAX_TEMP_ENTRIES];
1789	};
1790
1791	struct amdgpu_baseboard_temp_metrics_v1_0 {
1792	struct metrics_table_header common_header;
1793	uint16_t label_version;
1794	uint16_t node_id;
1795	uint64_t accumulation_counter;
1796	/* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */
1797	uint32_t system_temp[AMDGPU_SYSTEM_MAX_TEMP_ENTRIES];
1798	};
1799
1800	struct amdgpu_partition_metrics_v1_0 {
1801	struct metrics_table_header common_header;
1802	/* Current clocks (Mhz) */
1803	uint16_t current_gfxclk[MAX_XCC];
1804	uint16_t current_socclk[MAX_CLKS];
1805	uint16_t current_vclk0[MAX_CLKS];
1806	uint16_t current_dclk0[MAX_CLKS];
1807	uint16_t current_uclk;
1808	uint16_t padding;
1809
1810	/* Utilization Instantaneous (%) */
1811	uint32_t gfx_busy_inst[MAX_XCC];
1812	uint16_t jpeg_busy[NUM_JPEG_ENG_V1];
1813	uint16_t vcn_busy[NUM_VCN];
1814	/* Utilization Accumulated (%) */
1815	uint64_t gfx_busy_acc[MAX_XCC];
1816	/* Total App Clock Counter Accumulated */
1817	uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC];
1818	uint64_t gfx_below_host_limit_thm_acc[MAX_XCC];
1819	uint64_t gfx_low_utilization_acc[MAX_XCC];
1820	uint64_t gfx_below_host_limit_total_acc[MAX_XCC];
1821	};
1822
1823	struct amdgpu_partition_metrics_v1_1 {
1824	struct metrics_table_header common_header;
1825	int attr_count;
1826	struct gpu_metrics_attr metrics_attrs[];
1827	};
1828
1829	#endif
1830