1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _CGS_COMMON_H
25#define _CGS_COMMON_H
26
27#include "amd_shared.h"
28
29struct cgs_device;
30
31/**
32 * enum cgs_ind_reg - Indirect register spaces
33 */
34enum cgs_ind_reg {
35 CGS_IND_REG__PCIE,
36 CGS_IND_REG__SMC,
37 CGS_IND_REG__UVD_CTX,
38 CGS_IND_REG__DIDT,
39 CGS_IND_REG_GC_CAC,
40 CGS_IND_REG_SE_CAC,
41 CGS_IND_REG__AUDIO_ENDPT
42};
43
44/*
45 * enum cgs_ucode_id - Firmware types for different IPs
46 */
47enum cgs_ucode_id {
48 CGS_UCODE_ID_SMU = 0,
49 CGS_UCODE_ID_SMU_SK,
50 CGS_UCODE_ID_SDMA0,
51 CGS_UCODE_ID_SDMA1,
52 CGS_UCODE_ID_CP_CE,
53 CGS_UCODE_ID_CP_PFP,
54 CGS_UCODE_ID_CP_ME,
55 CGS_UCODE_ID_CP_MEC,
56 CGS_UCODE_ID_CP_MEC_JT1,
57 CGS_UCODE_ID_CP_MEC_JT2,
58 CGS_UCODE_ID_GMCON_RENG,
59 CGS_UCODE_ID_RLC_G,
60 CGS_UCODE_ID_STORAGE,
61 CGS_UCODE_ID_MAXIMUM,
62};
63
64/**
65 * struct cgs_firmware_info - Firmware information
66 */
67struct cgs_firmware_info {
68 uint16_t version;
69 uint16_t fw_version;
70 uint16_t feature_version;
71 uint32_t image_size;
72 uint64_t mc_addr;
73
74 /* only for smc firmware */
75 uint32_t ucode_start_address;
76
77 void *kptr;
78 bool is_kicker;
79};
80
81typedef unsigned long cgs_handle_t;
82
83/**
84 * cgs_read_register() - Read an MMIO register
85 * @cgs_device: opaque device handle
86 * @offset: register offset
87 *
88 * Return: register value
89 */
90typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
91
92/**
93 * cgs_write_register() - Write an MMIO register
94 * @cgs_device: opaque device handle
95 * @offset: register offset
96 * @value: register value
97 */
98typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
99 uint32_t value);
100
101/**
102 * cgs_read_ind_register() - Read an indirect register
103 * @cgs_device: opaque device handle
104 * @offset: register offset
105 *
106 * Return: register value
107 */
108typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
109 unsigned index);
110
111/**
112 * cgs_write_ind_register() - Write an indirect register
113 * @cgs_device: opaque device handle
114 * @offset: register offset
115 * @value: register value
116 */
117typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
118 unsigned index, uint32_t value);
119
120#define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
121#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK
122
123#define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \
124 (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \
125 (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
126
127#define CGS_REG_GET_FIELD(value, reg, field) \
128 (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))
129
130#define CGS_WREG32_FIELD(device, reg, field, val) \
131 cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
132
133#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \
134 cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
135
136typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
137 enum cgs_ucode_id type,
138 struct cgs_firmware_info *info);
139
140struct cgs_ops {
141 /* MMIO access */
142 cgs_read_register_t read_register;
143 cgs_write_register_t write_register;
144 cgs_read_ind_register_t read_ind_register;
145 cgs_write_ind_register_t write_ind_register;
146 /* Firmware Info */
147 cgs_get_firmware_info get_firmware_info;
148};
149
150struct cgs_os_ops; /* To be define in OS-specific CGS header */
151
152struct cgs_device {
153 const struct cgs_ops *ops;
154 /* to be embedded at the start of driver private structure */
155};
156
157/* Convenience macros that make CGS indirect function calls look like
158 * normal function calls */
159#define CGS_CALL(func, dev, ...) \
160 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
161#define CGS_OS_CALL(func, dev, ...) \
162 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
163
164#define cgs_read_register(dev, offset) \
165 CGS_CALL(read_register, dev, offset)
166#define cgs_write_register(dev, offset, value) \
167 CGS_CALL(write_register, dev, offset, value)
168#define cgs_read_ind_register(dev, space, index) \
169 CGS_CALL(read_ind_register, dev, space, index)
170#define cgs_write_ind_register(dev, space, index, value) \
171 CGS_CALL(write_ind_register, dev, space, index, value)
172
173#define cgs_get_firmware_info(dev, type, info) \
174 CGS_CALL(get_firmware_info, dev, type, info)
175
176#endif /* _CGS_COMMON_H */
177

source code of linux/drivers/gpu/drm/amd/include/cgs_common.h